VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 72907

Last change on this file since 72907 was 72907, checked in by vboxsync, 6 years ago

VMM/HMR0: Naming, cleanup nits.
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1/* $Id: HM.cpp 72907 2018-07-05 03:55:29Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/pdmapi.h>
45#include <VBox/vmm/pgm.h>
46#include <VBox/vmm/ssm.h>
47#include <VBox/vmm/trpm.h>
48#include <VBox/vmm/dbgf.h>
49#include <VBox/vmm/iom.h>
50#include <VBox/vmm/iem.h>
51#include <VBox/vmm/patm.h>
52#include <VBox/vmm/csam.h>
53#include <VBox/vmm/selm.h>
54#include <VBox/vmm/nem.h>
55#ifdef VBOX_WITH_REM
56# include <VBox/vmm/rem.h>
57#endif
58#include <VBox/vmm/hm_vmx.h>
59#include <VBox/vmm/hm_svm.h>
60#include "HMInternal.h"
61#include <VBox/vmm/vm.h>
62#include <VBox/vmm/uvm.h>
63#include <VBox/err.h>
64#include <VBox/param.h>
65
66#include <iprt/assert.h>
67#include <VBox/log.h>
68#include <iprt/asm.h>
69#include <iprt/asm-amd64-x86.h>
70#include <iprt/env.h>
71#include <iprt/thread.h>
72
73
74/*********************************************************************************************************************************
75* Global Variables *
76*********************************************************************************************************************************/
77#define EXIT_REASON(def, val, str) #def " - " #val " - " str
78#define EXIT_REASON_NIL() NULL
79/** Exit reason descriptions for VT-x, used to describe statistics. */
80static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
81{
82 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
83 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
84 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
85 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
86 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
87 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
88 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
89 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
90 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
91 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
92 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
93 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
94 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
95 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
96 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
97 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
98 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
99 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
100 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
101 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
102 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
103 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
104 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
105 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
106 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
107 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
108 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
109 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
110 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
111 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
112 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
113 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
114 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
115 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
116 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
117 EXIT_REASON_NIL(),
118 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
119 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
122 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
123 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
124 EXIT_REASON_NIL(),
125 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
126 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
127 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
128 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
129 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
130 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
131 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
132 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
133 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
134 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
135 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
136 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
137 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
138 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
139 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
140 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
141 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
142 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
143 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
144 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
145 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
146 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
147};
148/** Array index of the last valid VT-x exit reason. */
149#define MAX_EXITREASON_VTX 64
150
151/** A partial list of Exit reason descriptions for AMD-V, used to describe
152 * statistics.
153 *
154 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
155 * this array doesn't contain the entire set of exit reasons, we
156 * handle them via hmSvmGetSpecialExitReasonDesc(). */
157static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
158{
159 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
160 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
161 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
162 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
163 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
164 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
165 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
166 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
167 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
168 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
169 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
170 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
171 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
172 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
173 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
174 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
190 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
191 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
192 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
193 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
194 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
195 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
196 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
197 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
198 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
199 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
200 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
201 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
202 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
203 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
204 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
205 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
206 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
222 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
223 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
224 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
225 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
226 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
227 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
228 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
229 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
230 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
231 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
232 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
233 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
234 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
235 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
236 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
237 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
238 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
239 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
240 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
241 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
242 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
243 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
244 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
245 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
246 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
247 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
248 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
249 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1A)."),
250 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1B)."),
251 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1C)."),
252 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1D)."),
253 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
254 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
255 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
256 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
257 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
258 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
259 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
260 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
261 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
262 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
263 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
264 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
265 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
266 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
267 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
268 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
269 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
270 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
271 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
272 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
273 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
274 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
275 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
276 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
277 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
278 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
279 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
280 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
281 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
282 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
283 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
284 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
285 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
286 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
287 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
288 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
289 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
290 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
291 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
292 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
293 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
294 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
295 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
296 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
297 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
298 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
299 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
300 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
301};
302/** Array index of the last valid AMD-V exit reason. */
303#define MAX_EXITREASON_AMDV 141
304
305/** Special exit reasons not covered in the array above. */
306#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
307#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
308#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
309
310/**
311 * Gets the SVM exit reason if it's one of the reasons not present in the @c
312 * g_apszAmdVExitReasons array.
313 *
314 * @returns The exit reason or NULL if unknown.
315 * @param uExit The exit.
316 */
317DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
318{
319 switch (uExit)
320 {
321 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
322 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
323 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
324 }
325 return EXIT_REASON_NIL();
326}
327#undef EXIT_REASON_NIL
328#undef EXIT_REASON
329
330/** @def HMVMX_REPORT_FEATURE
331 * Reports VT-x feature to the release log.
332 *
333 * @param allowed1 Mask of allowed feature bits.
334 * @param disallowed0 Mask of disallowed feature bits.
335 * @param strdesc The description string to report.
336 * @param featflag Mask of the feature to report.
337 */
338#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
339 do { \
340 if ((allowed1) & (featflag)) \
341 { \
342 if ((disallowed0) & (featflag)) \
343 LogRel(("HM: " strdesc " (must be set)\n")); \
344 else \
345 LogRel(("HM: " strdesc "\n")); \
346 } \
347 else \
348 LogRel(("HM: " strdesc " (must be cleared)\n")); \
349 } while (0)
350
351/** @def HMVMX_REPORT_ALLOWED_FEATURE
352 * Reports an allowed VT-x feature to the release log.
353 *
354 * @param allowed1 Mask of allowed feature bits.
355 * @param strdesc The description string to report.
356 * @param featflag Mask of the feature to report.
357 */
358#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
359 do { \
360 if ((allowed1) & (featflag)) \
361 LogRel(("HM: " strdesc "\n")); \
362 else \
363 LogRel(("HM: " strdesc " not supported\n")); \
364 } while (0)
365
366/** @def HMVMX_REPORT_MSR_CAPABILITY
367 * Reports MSR feature capability.
368 *
369 * @param msrcaps Mask of MSR feature bits.
370 * @param strdesc The description string to report.
371 * @param cap Mask of the feature to report.
372 */
373#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
374 do { \
375 if ((msrcaps) & (cap)) \
376 LogRel(("HM: " strdesc "\n")); \
377 } while (0)
378
379/** @def HMVMX_LOGREL_FEAT
380 * Dumps a feature flag from a bitmap of features to the release log.
381 *
382 * @param a_fVal The value of all the features.
383 * @param a_fMask The specific bitmask of the feature.
384 */
385#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
386 do { \
387 if ((a_fVal) & (a_fMask)) \
388 LogRel(("HM: %s\n", #a_fMask)); \
389 } while (0)
390
391
392/*********************************************************************************************************************************
393* Internal Functions *
394*********************************************************************************************************************************/
395static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
396static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
397static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
398static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
399static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
400static int hmR3InitCPU(PVM pVM);
401static int hmR3InitFinalizeR0(PVM pVM);
402static int hmR3InitFinalizeR0Intel(PVM pVM);
403static int hmR3InitFinalizeR0Amd(PVM pVM);
404static int hmR3TermCPU(PVM pVM);
405
406
407
408/**
409 * Initializes the HM.
410 *
411 * This is the very first component to really do init after CFGM so that we can
412 * establish the predominat execution engine for the VM prior to initializing
413 * other modules. It takes care of NEM initialization if needed (HM disabled or
414 * not available in HW).
415 *
416 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
417 * hypervisor API via NEM, and then back on raw-mode if that isn't available
418 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
419 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
420 * X, OS/2 and others).
421 *
422 * Note that a lot of the set up work is done in ring-0 and thus postponed till
423 * the ring-3 and ring-0 callback to HMR3InitCompleted.
424 *
425 * @returns VBox status code.
426 * @param pVM The cross context VM structure.
427 *
428 * @remarks Be careful with what we call here, since most of the VMM components
429 * are uninitialized.
430 */
431VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
432{
433 LogFlow(("HMR3Init\n"));
434
435 /*
436 * Assert alignment and sizes.
437 */
438 AssertCompileMemberAlignment(VM, hm.s, 32);
439 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
440
441 /*
442 * Register the saved state data unit.
443 */
444 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
445 NULL, NULL, NULL,
446 NULL, hmR3Save, NULL,
447 NULL, hmR3Load, NULL);
448 if (RT_FAILURE(rc))
449 return rc;
450
451 /*
452 * Register info handlers.
453 */
454 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
455 AssertRCReturn(rc, rc);
456
457 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
458 DBGFINFO_FLAGS_ALL_EMTS);
459 AssertRCReturn(rc, rc);
460
461 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
462 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
463 AssertRCReturn(rc, rc);
464
465 /*
466 * Read configuration.
467 */
468 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
469
470 /*
471 * Validate the HM settings.
472 */
473 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
474 "HMForced"
475 "|UseNEMInstead"
476 "|FallbackToNEM"
477 "|EnableNestedPaging"
478 "|EnableUX"
479 "|EnableLargePages"
480 "|EnableVPID"
481 "|IBPBOnVMExit"
482 "|IBPBOnVMEntry"
483 "|SpecCtrlByHost"
484 "|TPRPatchingEnabled"
485 "|64bitEnabled"
486 "|Exclusive"
487 "|MaxResumeLoops"
488 "|VmxPleGap"
489 "|VmxPleWindow"
490 "|UseVmxPreemptTimer"
491 "|SvmPauseFilter"
492 "|SvmPauseFilterThreshold"
493 "|SvmVirtVmsaveVmload"
494 "|SvmVGif",
495 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
496 if (RT_FAILURE(rc))
497 return rc;
498
499 /** @cfgm{/HM/HMForced, bool, false}
500 * Forces hardware virtualization, no falling back on raw-mode. HM must be
501 * enabled, i.e. /HMEnabled must be true. */
502 bool fHMForced;
503#ifdef VBOX_WITH_RAW_MODE
504 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
505 AssertRCReturn(rc, rc);
506 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
507 VERR_INVALID_PARAMETER);
508# if defined(RT_OS_DARWIN)
509 if (pVM->fHMEnabled)
510 fHMForced = true;
511# endif
512 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
513 VERR_INVALID_PARAMETER);
514 if (pVM->cCpus > 1)
515 fHMForced = true;
516#else /* !VBOX_WITH_RAW_MODE */
517 AssertRelease(pVM->fHMEnabled);
518 fHMForced = true;
519#endif /* !VBOX_WITH_RAW_MODE */
520
521 /** @cfgm{/HM/UseNEMInstead, bool, true}
522 * Don't use HM, use NEM instead. */
523 bool fUseNEMInstead = false;
524 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
525 AssertRCReturn(rc, rc);
526 if (fUseNEMInstead && pVM->fHMEnabled)
527 {
528 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
529 pVM->fHMEnabled = false;
530 }
531
532 /** @cfgm{/HM/FallbackToNEM, bool, true}
533 * Enables fallback on NEM. */
534 bool fFallbackToNEM = true;
535 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
536 AssertRCReturn(rc, rc);
537
538 /** @cfgm{/HM/EnableNestedPaging, bool, false}
539 * Enables nested paging (aka extended page tables). */
540 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
541 AssertRCReturn(rc, rc);
542
543 /** @cfgm{/HM/EnableUX, bool, true}
544 * Enables the VT-x unrestricted execution feature. */
545 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
546 AssertRCReturn(rc, rc);
547
548 /** @cfgm{/HM/EnableLargePages, bool, false}
549 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
550 * page table walking and maybe better TLB hit rate in some cases. */
551 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
552 AssertRCReturn(rc, rc);
553
554 /** @cfgm{/HM/EnableVPID, bool, false}
555 * Enables the VT-x VPID feature. */
556 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
557 AssertRCReturn(rc, rc);
558
559 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
560 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
561 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
562 AssertRCReturn(rc, rc);
563
564 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
565 * Enables AMD64 cpu features.
566 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
567 * already have the support. */
568#ifdef VBOX_ENABLE_64_BITS_GUESTS
569 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
570 AssertLogRelRCReturn(rc, rc);
571#else
572 pVM->hm.s.fAllow64BitGuests = false;
573#endif
574
575 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
576 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
577 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
578 * latest PAUSE instruction to be start of a new PAUSE loop.
579 */
580 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
581 AssertRCReturn(rc, rc);
582
583 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
584 * The pause-filter exiting window in TSC ticks. When the number of ticks
585 * between the current PAUSE instruction and first PAUSE of a loop exceeds
586 * VmxPleWindow, a VM-exit is triggered.
587 *
588 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
589 */
590 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
591 AssertRCReturn(rc, rc);
592
593 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
594 * A counter that is decrement each time a PAUSE instruction is executed by the
595 * guest. When the counter is 0, a \#VMEXIT is triggered.
596 *
597 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
598 */
599 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
600 AssertRCReturn(rc, rc);
601
602 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
603 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
604 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
605 * PauseFilter count is reset to its initial value. However, if PAUSE is
606 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
607 * be triggered.
608 *
609 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
610 * activated.
611 */
612 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
613 AssertRCReturn(rc, rc);
614
615 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
616 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
617 * available. */
618 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
619 AssertRCReturn(rc, rc);
620
621 /** @cfgm{/HM/SvmVGif, bool, true}
622 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
623 * if it's available. */
624 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
625 AssertRCReturn(rc, rc);
626
627 /** @cfgm{/HM/Exclusive, bool}
628 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
629 * global init for each host CPU. If false, we do local init each time we wish
630 * to execute guest code.
631 *
632 * On Windows, default is false due to the higher risk of conflicts with other
633 * hypervisors.
634 *
635 * On Mac OS X, this setting is ignored since the code does not handle local
636 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
637 */
638#if defined(RT_OS_DARWIN)
639 pVM->hm.s.fGlobalInit = true;
640#else
641 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
642# if defined(RT_OS_WINDOWS)
643 false
644# else
645 true
646# endif
647 );
648 AssertLogRelRCReturn(rc, rc);
649#endif
650
651 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
652 * The number of times to resume guest execution before we forcibly return to
653 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
654 * determines the default value. */
655 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
656 AssertLogRelRCReturn(rc, rc);
657
658 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
659 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
660 * available. */
661 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
662 AssertLogRelRCReturn(rc, rc);
663
664 /** @cfgm{/HM/IBPBOnVMExit, bool}
665 * Costly paranoia setting. */
666 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
667 AssertLogRelRCReturn(rc, rc);
668
669 /** @cfgm{/HM/IBPBOnVMEntry, bool}
670 * Costly paranoia setting. */
671 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
672 AssertLogRelRCReturn(rc, rc);
673
674 /** @cfgm{/HM/SpecCtrlByHost, bool}
675 * Another expensive paranoia setting. */
676 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
677 AssertLogRelRCReturn(rc, rc);
678
679 /*
680 * Check if VT-x or AMD-v support according to the users wishes.
681 */
682 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
683 * VERR_SVM_IN_USE. */
684 if (pVM->fHMEnabled)
685 {
686 uint32_t fCaps;
687 rc = SUPR3QueryVTCaps(&fCaps);
688 if (RT_SUCCESS(rc))
689 {
690 if (fCaps & SUPVTCAPS_AMD_V)
691 {
692 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
693 pVM->hm.s.svm.fSupported = true;
694 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
695 }
696 else if (fCaps & SUPVTCAPS_VT_X)
697 {
698 const char *pszWhy;
699 rc = SUPR3QueryVTxSupported(&pszWhy);
700 if (RT_SUCCESS(rc))
701 {
702 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
703 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
704 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
705 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
706 pVM->hm.s.vmx.fSupported = true;
707 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
708 }
709 else
710 {
711 /*
712 * Before failing, try fallback to NEM if we're allowed to do that.
713 */
714 pVM->fHMEnabled = false;
715 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
716 if (fFallbackToNEM)
717 {
718 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
719 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
720
721 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
722 if ( RT_SUCCESS(rc2)
723 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
724 rc = VINF_SUCCESS;
725 }
726 if (RT_FAILURE(rc))
727 {
728 if (fHMForced)
729 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
730
731 /* Fall back to raw-mode. */
732 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
733 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
734 }
735 }
736 }
737 else
738 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
739 VERR_INTERNAL_ERROR_5);
740
741 /*
742 * Do we require a little bit or raw-mode for 64-bit guest execution?
743 */
744 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
745 && pVM->fHMEnabled
746 && pVM->hm.s.fAllow64BitGuests;
747
748 /*
749 * Disable nested paging and unrestricted guest execution now if they're
750 * configured so that CPUM can make decisions based on our configuration.
751 */
752 Assert(!pVM->hm.s.fNestedPaging);
753 if (pVM->hm.s.fAllowNestedPaging)
754 {
755 if (fCaps & SUPVTCAPS_NESTED_PAGING)
756 pVM->hm.s.fNestedPaging = true;
757 else
758 pVM->hm.s.fAllowNestedPaging = false;
759 }
760
761 if (fCaps & SUPVTCAPS_VT_X)
762 {
763 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
764 if (pVM->hm.s.vmx.fAllowUnrestricted)
765 {
766 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
767 && pVM->hm.s.fNestedPaging)
768 pVM->hm.s.vmx.fUnrestrictedGuest = true;
769 else
770 pVM->hm.s.vmx.fAllowUnrestricted = false;
771 }
772 }
773 }
774 else
775 {
776 const char *pszMsg;
777 switch (rc)
778 {
779 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
780 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
781 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
782 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
783 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
784 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
785 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
786 default:
787 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
788 }
789
790 /*
791 * Before failing, try fallback to NEM if we're allowed to do that.
792 */
793 pVM->fHMEnabled = false;
794 if (fFallbackToNEM)
795 {
796 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
797 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
798 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
799 if ( RT_SUCCESS(rc2)
800 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
801 rc = VINF_SUCCESS;
802 }
803 if (RT_FAILURE(rc))
804 {
805 if (fHMForced)
806 return VM_SET_ERROR(pVM, rc, pszMsg);
807
808 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
809 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
810 }
811 }
812 }
813 else
814 {
815 /*
816 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
817 */
818 if (!fUseNEMInstead)
819 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
820 else
821 {
822 rc = NEMR3Init(pVM, false /*fFallback*/, true);
823 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
824 if (RT_FAILURE(rc))
825 return rc;
826 }
827 }
828
829 return VINF_SUCCESS;
830}
831
832
833/**
834 * Initializes the per-VCPU HM.
835 *
836 * @returns VBox status code.
837 * @param pVM The cross context VM structure.
838 */
839static int hmR3InitCPU(PVM pVM)
840{
841 LogFlow(("HMR3InitCPU\n"));
842
843 if (!HMIsEnabled(pVM))
844 return VINF_SUCCESS;
845
846 for (VMCPUID i = 0; i < pVM->cCpus; i++)
847 {
848 PVMCPU pVCpu = &pVM->aCpus[i];
849 pVCpu->hm.s.fActive = false;
850 }
851
852#ifdef VBOX_WITH_STATISTICS
853 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
854 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
855 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
856 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
857 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
858#endif
859
860 /*
861 * Statistics.
862 */
863 for (VMCPUID i = 0; i < pVM->cCpus; i++)
864 {
865 PVMCPU pVCpu = &pVM->aCpus[i];
866 int rc;
867
868#ifdef VBOX_WITH_STATISTICS
869 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
870 "Profiling of RTMpPokeCpu",
871 "/PROF/CPU%d/HM/Poke", i);
872 AssertRC(rc);
873 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
874 "Profiling of poke wait",
875 "/PROF/CPU%d/HM/PokeWait", i);
876 AssertRC(rc);
877 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
878 "Profiling of poke wait when RTMpPokeCpu fails",
879 "/PROF/CPU%d/HM/PokeWaitFailed", i);
880 AssertRC(rc);
881 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
882 "Profiling of VMXR0RunGuestCode entry",
883 "/PROF/CPU%d/HM/StatEntry", i);
884 AssertRC(rc);
885 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
886 "Profiling of pre-exit processing after returning from GC",
887 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
888 AssertRC(rc);
889 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
890 "Profiling of exit handling (longjmps not included!)",
891 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
892 AssertRC(rc);
893
894 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
895 "I/O",
896 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
897 AssertRC(rc);
898 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
899 "MOV CRx",
900 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
901 AssertRC(rc);
902 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
903 "Exceptions, NMIs",
904 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
905 AssertRC(rc);
906
907 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
908 "Profiling of hmR0VmxImportGuestState or hmR0SvmImportGuestState",
909 "/PROF/CPU%d/HM/StatImportGuestState", i);
910 AssertRC(rc);
911 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
912 "Profiling of hmR0VmxExportGuestState or hmR0SvmExportGuestState",
913 "/PROF/CPU%d/HM/StatExportGuestState", i);
914 AssertRC(rc);
915 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
916 "Profiling of CPUMR0LoadGuestFPU",
917 "/PROF/CPU%d/HM/StatLoadGuestFpuState", i);
918 AssertRC(rc);
919 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
920 "Profiling of VMLAUNCH/VMRESUME.",
921 "/PROF/CPU%d/HM/InGC", i);
922 AssertRC(rc);
923
924# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
925 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
926 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
927 "/PROF/CPU%d/HM/Switcher3264", i);
928 AssertRC(rc);
929# endif
930
931# ifdef HM_PROFILE_EXIT_DISPATCH
932 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
933 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
934 "/PROF/CPU%d/HM/ExitDispatch", i);
935 AssertRC(rc);
936# endif
937
938#endif
939# define HM_REG_COUNTER(a, b, desc) \
940 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
941 AssertRC(rc);
942
943#ifdef VBOX_WITH_STATISTICS
944 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
945 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
946 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
948 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
949 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
950 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
951 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
952 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
953 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
954 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
955 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
956 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
957 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
968 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
970 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
972 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
974 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
976 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
977 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
980 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
981 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
986 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
987 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
988 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
989 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
990 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
991 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
992#endif
993 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
994#ifdef VBOX_WITH_STATISTICS
995 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
996 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
997 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
999 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
1000
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
1002 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
1004 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
1006 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
1008 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
1010#endif
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
1012#ifdef VBOX_WITH_STATISTICS
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptExportHostState, "/HM/CPU%d/Switch/ExportHostState", "Preemption caused us to re-export the host state.");
1014
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
1016 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
1018 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
1019
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
1021 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
1022 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1024 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1026 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1028 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1030 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1031 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1033 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1034
1035 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1036 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1037 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1038
1039 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1040 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1041 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1042
1043 HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry exporting minimal guest-state.");
1044 HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Load/Full", "VM-entry exporting the full guest-state.");
1045 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Load/GuestFpu", "VM-entry loading the guest-FPU state.");
1046
1047 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1048 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1049 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1050 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1051 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1052 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
1053 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
1054 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1055
1056#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1057 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1058 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1059#endif
1060
1061#undef HM_REG_COUNTER
1062
1063 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVTxExitReasons[0]
1064 : &g_apszAmdVExitReasons[0];
1065
1066 /*
1067 * Guest Exit reason stats.
1068 */
1069 pVCpu->hm.s.paStatExitReason = NULL;
1070 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1071 (void **)&pVCpu->hm.s.paStatExitReason);
1072 AssertRCReturn(rc, rc);
1073 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1074 {
1075 if (papszDesc[j])
1076 {
1077 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1078 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1079 AssertRCReturn(rc, rc);
1080 }
1081 }
1082 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1083 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1084 AssertRCReturn(rc, rc);
1085 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1086# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1087 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1088# else
1089 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1090# endif
1091
1092#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1093 /*
1094 * Nested-guest Exit reason stats.
1095 */
1096 pVCpu->hm.s.paStatNestedExitReason = NULL;
1097 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1098 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1099 AssertRCReturn(rc, rc);
1100 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1101 {
1102 if (papszDesc[j])
1103 {
1104 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1105 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1106 AssertRC(rc);
1107 }
1108 }
1109 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1110 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1111 AssertRCReturn(rc, rc);
1112 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1113# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1114 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1115# else
1116 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1117# endif
1118#endif
1119
1120 /*
1121 * Injected events stats.
1122 */
1123 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1124 AssertRCReturn(rc, rc);
1125 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1126# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1127 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1128# else
1129 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1130# endif
1131 for (unsigned j = 0; j < 255; j++)
1132 {
1133 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1134 "Injected event.",
1135 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1136 }
1137
1138#endif /* VBOX_WITH_STATISTICS */
1139 }
1140
1141#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1142 /*
1143 * Magic marker for searching in crash dumps.
1144 */
1145 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1146 {
1147 PVMCPU pVCpu = &pVM->aCpus[i];
1148
1149 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1150 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1151 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1152 }
1153#endif
1154
1155 return VINF_SUCCESS;
1156}
1157
1158
1159/**
1160 * Called when a init phase has completed.
1161 *
1162 * @returns VBox status code.
1163 * @param pVM The cross context VM structure.
1164 * @param enmWhat The phase that completed.
1165 */
1166VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1167{
1168 switch (enmWhat)
1169 {
1170 case VMINITCOMPLETED_RING3:
1171 return hmR3InitCPU(pVM);
1172 case VMINITCOMPLETED_RING0:
1173 return hmR3InitFinalizeR0(pVM);
1174 default:
1175 return VINF_SUCCESS;
1176 }
1177}
1178
1179
1180/**
1181 * Turns off normal raw mode features.
1182 *
1183 * @param pVM The cross context VM structure.
1184 */
1185static void hmR3DisableRawMode(PVM pVM)
1186{
1187 /* Reinit the paging mode to force the new shadow mode. */
1188 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1189 {
1190 PVMCPU pVCpu = &pVM->aCpus[i];
1191
1192 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1193 }
1194}
1195
1196
1197/**
1198 * Initialize VT-x or AMD-V.
1199 *
1200 * @returns VBox status code.
1201 * @param pVM The cross context VM structure.
1202 */
1203static int hmR3InitFinalizeR0(PVM pVM)
1204{
1205 int rc;
1206
1207 if (!HMIsEnabled(pVM))
1208 return VINF_SUCCESS;
1209
1210 /*
1211 * Hack to allow users to work around broken BIOSes that incorrectly set
1212 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1213 */
1214 if ( !pVM->hm.s.vmx.fSupported
1215 && !pVM->hm.s.svm.fSupported
1216 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1217 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1218 {
1219 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1220 pVM->hm.s.svm.fSupported = true;
1221 pVM->hm.s.svm.fIgnoreInUseError = true;
1222 pVM->hm.s.rcInit = VINF_SUCCESS;
1223 }
1224
1225 /*
1226 * Report ring-0 init errors.
1227 */
1228 if ( !pVM->hm.s.vmx.fSupported
1229 && !pVM->hm.s.svm.fSupported)
1230 {
1231 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1232 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1233 switch (pVM->hm.s.rcInit)
1234 {
1235 case VERR_VMX_IN_VMX_ROOT_MODE:
1236 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1237 case VERR_VMX_NO_VMX:
1238 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1239 case VERR_VMX_MSR_VMX_DISABLED:
1240 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1241 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1242 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1243 case VERR_VMX_MSR_LOCKING_FAILED:
1244 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1245 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1246 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1247 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1248 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1249
1250 case VERR_SVM_IN_USE:
1251 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1252 case VERR_SVM_NO_SVM:
1253 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1254 case VERR_SVM_DISABLED:
1255 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1256 }
1257 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1258 }
1259
1260 /*
1261 * Enable VT-x or AMD-V on all host CPUs.
1262 */
1263 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1264 if (RT_FAILURE(rc))
1265 {
1266 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1267 HMR3CheckError(pVM, rc);
1268 return rc;
1269 }
1270
1271 /*
1272 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1273 * (Main should have taken care of this already)
1274 */
1275 if (!PDMHasIoApic(pVM))
1276 {
1277 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1278 pVM->hm.s.fTprPatchingAllowed = false;
1279 }
1280
1281 /*
1282 * Sync options.
1283 */
1284 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1285 * That will require a little bit of work, of course. */
1286 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1287 {
1288 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1289 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1290 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1291 if (pVM->cpum.ro.HostFeatures.fIbpb)
1292 {
1293 if (pVM->hm.s.fIbpbOnVmExit)
1294 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1295 if (pVM->hm.s.fIbpbOnVmEntry)
1296 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1297 }
1298 if (iCpu == 0)
1299 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1300 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1301 }
1302
1303 /*
1304 * Do the vendor specific initialization
1305 *
1306 * Note! We disable release log buffering here since we're doing relatively
1307 * lot of logging and doesn't want to hit the disk with each LogRel
1308 * statement.
1309 */
1310 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1311 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1312 if (pVM->hm.s.vmx.fSupported)
1313 rc = hmR3InitFinalizeR0Intel(pVM);
1314 else
1315 rc = hmR3InitFinalizeR0Amd(pVM);
1316 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1317 RTLogRelSetBuffering(fOldBuffered);
1318 pVM->hm.s.fInitialized = true;
1319
1320 return rc;
1321}
1322
1323
1324/**
1325 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1326 */
1327static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1328{
1329 NOREF(pVM);
1330 NOREF(pvAllocation);
1331 NOREF(GCPhysAllocation);
1332}
1333
1334
1335/**
1336 * Finish VT-x initialization (after ring-0 init).
1337 *
1338 * @returns VBox status code.
1339 * @param pVM The cross context VM structure.
1340 */
1341static int hmR3InitFinalizeR0Intel(PVM pVM)
1342{
1343 int rc;
1344
1345 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1346 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1347
1348 uint64_t val;
1349 uint64_t zap;
1350
1351 LogRel(("HM: Using VT-x implementation 2.0\n"));
1352 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1353 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1354 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1355 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1356 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1357 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1358 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1359 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1360 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1361 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1362 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1363 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1364 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1365 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1366 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1367
1368 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1369 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1370 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1371 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1372 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1373 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1374 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1375 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1376
1377 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1378 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1379 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1380 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1381 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1382 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1383 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1384 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1385 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1386 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1387 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1388 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1389 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1390 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1391 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1392 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1393 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1394 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1395 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1396 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1397 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1398 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1399 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1400 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1401 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1402 {
1403 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1404 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1405 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1406 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1407 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1408 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1409 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1410 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1411 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1412 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1413 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1414 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1415 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1416 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1417 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1418 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1419 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1420 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1421 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1422 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1423 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1424 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1425 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1426 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1427 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1428 }
1429
1430 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1431 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1432 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1433 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1434 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1435 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1436 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1437 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1438 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1439 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1440
1441 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1442 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1443 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1444 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1445 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1446 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1447 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1448 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1449 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1450 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1451 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1452 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1453
1454 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1455 {
1456 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1457 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1458 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1459 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1460 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1461 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1462 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1463 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1464 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1465 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1466 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1467 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1468 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1469 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1470 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1471 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1472 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1473 }
1474
1475 val = pVM->hm.s.vmx.Msrs.u64Misc;
1476 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1477 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1478 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1479 else
1480 {
1481 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1482 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1483 }
1484
1485 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1486 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1487 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1488 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1489 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1490 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1491 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1492 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1493
1494 /* Paranoia */
1495 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1496
1497 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1498 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1499 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1500 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1501
1502 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1503 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1504 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1505
1506 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1507 if (val)
1508 {
1509 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1510 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1511 }
1512
1513 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1514
1515 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1516 {
1517 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1518 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1519 }
1520
1521 /*
1522 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1523 */
1524 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1525 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1526 VERR_HM_IPE_1);
1527 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1528 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1529 && pVM->hm.s.fNestedPaging),
1530 VERR_HM_IPE_1);
1531
1532 /*
1533 * Enable VPID if configured and supported.
1534 */
1535 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1536 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1537
1538#if 0
1539 /*
1540 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1541 */
1542 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1543 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1544 pVM->hm.s.fVirtApicRegs = true;
1545
1546 /*
1547 * Enable posted-interrupt processing if supported.
1548 */
1549 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1550 * here. */
1551 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1552 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1553 pVM->hm.s.fPostedIntrs = true;
1554#endif
1555
1556 /*
1557 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1558 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1559 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1560 */
1561 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1562 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1563 {
1564 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1565 LogRel(("HM: Disabled RDTSCP\n"));
1566 }
1567
1568 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1569 {
1570 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1571 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1572 if (RT_SUCCESS(rc))
1573 {
1574 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1575 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1576 esp. Figure 20-5.*/
1577 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1578 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1579
1580 /* Bit set to 0 means software interrupts are redirected to the
1581 8086 program interrupt handler rather than switching to
1582 protected-mode handler. */
1583 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1584
1585 /* Allow all port IO, so that port IO instructions do not cause
1586 exceptions and would instead cause a VM-exit (based on VT-x's
1587 IO bitmap which we currently configure to always cause an exit). */
1588 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1589 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1590
1591 /*
1592 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1593 * page table used in real and protected mode without paging with EPT.
1594 */
1595 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1596 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1597 {
1598 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1599 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1600 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1601 | X86_PDE4M_G;
1602 }
1603
1604 /* We convert it here every time as PCI regions could be reconfigured. */
1605 if (PDMVmmDevHeapIsEnabled(pVM))
1606 {
1607 RTGCPHYS GCPhys;
1608 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1609 AssertRCReturn(rc, rc);
1610 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1611
1612 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1613 AssertRCReturn(rc, rc);
1614 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1615 }
1616 }
1617 else
1618 {
1619 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1620 pVM->hm.s.vmx.pRealModeTSS = NULL;
1621 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1622 return VMSetError(pVM, rc, RT_SRC_POS,
1623 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1624 }
1625 }
1626
1627 LogRel((pVM->hm.s.fAllow64BitGuests
1628 ? "HM: Guest support: 32-bit and 64-bit\n"
1629 : "HM: Guest support: 32-bit only\n"));
1630
1631 /*
1632 * Call ring-0 to set up the VM.
1633 */
1634 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1635 if (rc != VINF_SUCCESS)
1636 {
1637 AssertMsgFailed(("%Rrc\n", rc));
1638 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1639 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1640 {
1641 PVMCPU pVCpu = &pVM->aCpus[i];
1642 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1643 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1644 }
1645 HMR3CheckError(pVM, rc);
1646 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1647 }
1648
1649 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1650 LogRel(("HM: Enabled VMX\n"));
1651 pVM->hm.s.vmx.fEnabled = true;
1652
1653 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1654
1655 /*
1656 * Change the CPU features.
1657 */
1658 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1659 if (pVM->hm.s.fAllow64BitGuests)
1660 {
1661 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1662 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1663 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1664 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1665 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1666 }
1667 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1668 (we reuse the host EFER in the switcher). */
1669 /** @todo this needs to be fixed properly!! */
1670 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1671 {
1672 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1673 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1674 else
1675 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1676 }
1677
1678 /*
1679 * Log configuration details.
1680 */
1681 if (pVM->hm.s.fNestedPaging)
1682 {
1683 LogRel(("HM: Enabled nested paging\n"));
1684 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1685 LogRel(("HM: EPT flush type = Single context\n"));
1686 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1687 LogRel(("HM: EPT flush type = All contexts\n"));
1688 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1689 LogRel(("HM: EPT flush type = Not supported\n"));
1690 else
1691 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1692
1693 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1694 LogRel(("HM: Enabled unrestricted guest execution\n"));
1695
1696#if HC_ARCH_BITS == 64
1697 if (pVM->hm.s.fLargePages)
1698 {
1699 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1700 PGMSetLargePageUsage(pVM, true);
1701 LogRel(("HM: Enabled large page support\n"));
1702 }
1703#endif
1704 }
1705 else
1706 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1707
1708 if (pVM->hm.s.fVirtApicRegs)
1709 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1710
1711 if (pVM->hm.s.fPostedIntrs)
1712 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1713
1714 if (pVM->hm.s.vmx.fVpid)
1715 {
1716 LogRel(("HM: Enabled VPID\n"));
1717 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1718 LogRel(("HM: VPID flush type = Individual addresses\n"));
1719 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1720 LogRel(("HM: VPID flush type = Single context\n"));
1721 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1722 LogRel(("HM: VPID flush type = All contexts\n"));
1723 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1724 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1725 else
1726 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1727 }
1728 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1729 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1730
1731 if (pVM->hm.s.vmx.fUsePreemptTimer)
1732 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1733 else
1734 LogRel(("HM: Disabled VMX-preemption timer\n"));
1735
1736 return VINF_SUCCESS;
1737}
1738
1739
1740/**
1741 * Finish AMD-V initialization (after ring-0 init).
1742 *
1743 * @returns VBox status code.
1744 * @param pVM The cross context VM structure.
1745 */
1746static int hmR3InitFinalizeR0Amd(PVM pVM)
1747{
1748 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1749
1750 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1751
1752 uint32_t u32Family;
1753 uint32_t u32Model;
1754 uint32_t u32Stepping;
1755 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1756 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1757 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1758 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1759 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1760 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1761 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1762 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1763 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1764
1765 /*
1766 * Enumerate AMD-V features.
1767 */
1768 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1769 {
1770#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1771 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1772 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1773 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1774 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1775 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1776 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1777 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1778 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1779 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1780 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1781 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1782 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1783 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1784#undef HMSVM_REPORT_FEATURE
1785 };
1786
1787 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1788 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1789 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1790 {
1791 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1792 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1793 }
1794 if (fSvmFeatures)
1795 for (unsigned iBit = 0; iBit < 32; iBit++)
1796 if (RT_BIT_32(iBit) & fSvmFeatures)
1797 LogRel(("HM: Reserved bit %u\n", iBit));
1798
1799 /*
1800 * Nested paging is determined in HMR3Init, verify the sanity of that.
1801 */
1802 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1803 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1804 VERR_HM_IPE_1);
1805
1806#if 0
1807 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1808 * here. */
1809 if (RTR0IsPostIpiSupport())
1810 pVM->hm.s.fPostedIntrs = true;
1811#endif
1812
1813 /*
1814 * Call ring-0 to set up the VM.
1815 */
1816 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1817 if (rc != VINF_SUCCESS)
1818 {
1819 AssertMsgFailed(("%Rrc\n", rc));
1820 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1821 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1822 }
1823
1824 LogRel(("HM: Enabled SVM\n"));
1825 pVM->hm.s.svm.fEnabled = true;
1826
1827 if (pVM->hm.s.fNestedPaging)
1828 {
1829 LogRel(("HM: Enabled nested paging\n"));
1830
1831 /*
1832 * Enable large pages (2 MB) if applicable.
1833 */
1834#if HC_ARCH_BITS == 64
1835 if (pVM->hm.s.fLargePages)
1836 {
1837 PGMSetLargePageUsage(pVM, true);
1838 LogRel(("HM: Enabled large page support\n"));
1839 }
1840#endif
1841 }
1842
1843 if (pVM->hm.s.fVirtApicRegs)
1844 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1845
1846 if (pVM->hm.s.fPostedIntrs)
1847 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1848
1849 hmR3DisableRawMode(pVM);
1850
1851 /*
1852 * Change the CPU features.
1853 */
1854 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1855 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1856 if (pVM->hm.s.fAllow64BitGuests)
1857 {
1858 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1859 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1860 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1861 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1862 }
1863 /* Turn on NXE if PAE has been enabled. */
1864 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1865 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1866
1867 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1868
1869 LogRel((pVM->hm.s.fAllow64BitGuests
1870 ? "HM: Guest support: 32-bit and 64-bit\n"
1871 : "HM: Guest support: 32-bit only\n"));
1872
1873 return VINF_SUCCESS;
1874}
1875
1876
1877/**
1878 * Applies relocations to data and code managed by this
1879 * component. This function will be called at init and
1880 * whenever the VMM need to relocate it self inside the GC.
1881 *
1882 * @param pVM The cross context VM structure.
1883 */
1884VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1885{
1886 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1887
1888 /* Fetch the current paging mode during the relocate callback during state loading. */
1889 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1890 {
1891 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1892 {
1893 PVMCPU pVCpu = &pVM->aCpus[i];
1894 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1895 }
1896 }
1897#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1898 if (HMIsEnabled(pVM))
1899 {
1900 switch (PGMGetHostMode(pVM))
1901 {
1902 case PGMMODE_32_BIT:
1903 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1904 break;
1905
1906 case PGMMODE_PAE:
1907 case PGMMODE_PAE_NX:
1908 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1909 break;
1910
1911 default:
1912 AssertFailed();
1913 break;
1914 }
1915 }
1916#endif
1917 return;
1918}
1919
1920
1921/**
1922 * Notification callback which is called whenever there is a chance that a CR3
1923 * value might have changed.
1924 *
1925 * This is called by PGM.
1926 *
1927 * @param pVM The cross context VM structure.
1928 * @param pVCpu The cross context virtual CPU structure.
1929 * @param enmShadowMode New shadow paging mode.
1930 * @param enmGuestMode New guest paging mode.
1931 */
1932VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1933{
1934 RT_NOREF_PV(pVM);
1935
1936 /* Ignore page mode changes during state loading. */
1937 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1938 return;
1939
1940 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1941
1942 /*
1943 * If the guest left protected mode VMX execution, we'll have to be
1944 * extra careful if/when the guest switches back to protected mode.
1945 */
1946 if (enmGuestMode == PGMMODE_REAL)
1947 pVCpu->hm.s.vmx.fWasInRealMode = true;
1948
1949 Log4(("HMR3PagingModeChanged: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
1950 PGMGetModeName(enmShadowMode)));
1951}
1952
1953
1954/**
1955 * Terminates the HM.
1956 *
1957 * Termination means cleaning up and freeing all resources,
1958 * the VM itself is, at this point, powered off or suspended.
1959 *
1960 * @returns VBox status code.
1961 * @param pVM The cross context VM structure.
1962 */
1963VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1964{
1965 if (pVM->hm.s.vmx.pRealModeTSS)
1966 {
1967 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1968 pVM->hm.s.vmx.pRealModeTSS = 0;
1969 }
1970 hmR3TermCPU(pVM);
1971 return 0;
1972}
1973
1974
1975/**
1976 * Terminates the per-VCPU HM.
1977 *
1978 * @returns VBox status code.
1979 * @param pVM The cross context VM structure.
1980 */
1981static int hmR3TermCPU(PVM pVM)
1982{
1983 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1984 {
1985 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1986
1987#ifdef VBOX_WITH_STATISTICS
1988 if (pVCpu->hm.s.paStatExitReason)
1989 {
1990 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1991 pVCpu->hm.s.paStatExitReason = NULL;
1992 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1993 }
1994 if (pVCpu->hm.s.paStatInjectedIrqs)
1995 {
1996 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1997 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1998 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1999 }
2000#endif
2001
2002#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2003 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
2004 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
2005 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
2006#endif
2007 }
2008 return 0;
2009}
2010
2011
2012/**
2013 * Resets a virtual CPU.
2014 *
2015 * Used by HMR3Reset and CPU hot plugging.
2016 *
2017 * @param pVCpu The cross context virtual CPU structure to reset.
2018 */
2019VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2020{
2021 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2022 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2023 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2024
2025 pVCpu->hm.s.fActive = false;
2026 pVCpu->hm.s.Event.fPending = false;
2027 pVCpu->hm.s.vmx.fWasInRealMode = true;
2028 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2029 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2030
2031 /* Reset the contents of the read cache. */
2032 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2033 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2034 pCache->Read.aFieldVal[j] = 0;
2035
2036#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2037 /* Magic marker for searching in crash dumps. */
2038 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2039 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2040#endif
2041}
2042
2043
2044/**
2045 * The VM is being reset.
2046 *
2047 * For the HM component this means that any GDT/LDT/TSS monitors
2048 * needs to be removed.
2049 *
2050 * @param pVM The cross context VM structure.
2051 */
2052VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2053{
2054 LogFlow(("HMR3Reset:\n"));
2055
2056 if (HMIsEnabled(pVM))
2057 hmR3DisableRawMode(pVM);
2058
2059 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2060 {
2061 PVMCPU pVCpu = &pVM->aCpus[i];
2062
2063 HMR3ResetCpu(pVCpu);
2064 }
2065
2066 /* Clear all patch information. */
2067 pVM->hm.s.pGuestPatchMem = 0;
2068 pVM->hm.s.pFreeGuestPatchMem = 0;
2069 pVM->hm.s.cbGuestPatchMem = 0;
2070 pVM->hm.s.cPatches = 0;
2071 pVM->hm.s.PatchTree = 0;
2072 pVM->hm.s.fTPRPatchingActive = false;
2073 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2074}
2075
2076
2077/**
2078 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2079 *
2080 * @returns VBox strict status code.
2081 * @param pVM The cross context VM structure.
2082 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2083 * @param pvUser Unused.
2084 */
2085static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2086{
2087 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2088
2089 /* Only execute the handler on the VCPU the original patch request was issued. */
2090 if (pVCpu->idCpu != idCpu)
2091 return VINF_SUCCESS;
2092
2093 Log(("hmR3RemovePatches\n"));
2094 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2095 {
2096 uint8_t abInstr[15];
2097 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2098 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2099 int rc;
2100
2101#ifdef LOG_ENABLED
2102 char szOutput[256];
2103 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2104 szOutput, sizeof(szOutput), NULL);
2105 if (RT_SUCCESS(rc))
2106 Log(("Patched instr: %s\n", szOutput));
2107#endif
2108
2109 /* Check if the instruction is still the same. */
2110 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2111 if (rc != VINF_SUCCESS)
2112 {
2113 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2114 continue; /* swapped out or otherwise removed; skip it. */
2115 }
2116
2117 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2118 {
2119 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2120 continue; /* skip it. */
2121 }
2122
2123 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2124 AssertRC(rc);
2125
2126#ifdef LOG_ENABLED
2127 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2128 szOutput, sizeof(szOutput), NULL);
2129 if (RT_SUCCESS(rc))
2130 Log(("Original instr: %s\n", szOutput));
2131#endif
2132 }
2133 pVM->hm.s.cPatches = 0;
2134 pVM->hm.s.PatchTree = 0;
2135 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2136 pVM->hm.s.fTPRPatchingActive = false;
2137 return VINF_SUCCESS;
2138}
2139
2140
2141/**
2142 * Worker for enabling patching in a VT-x/AMD-V guest.
2143 *
2144 * @returns VBox status code.
2145 * @param pVM The cross context VM structure.
2146 * @param idCpu VCPU to execute hmR3RemovePatches on.
2147 * @param pPatchMem Patch memory range.
2148 * @param cbPatchMem Size of the memory range.
2149 */
2150static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2151{
2152 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2153 AssertRC(rc);
2154
2155 pVM->hm.s.pGuestPatchMem = pPatchMem;
2156 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2157 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2158 return VINF_SUCCESS;
2159}
2160
2161
2162/**
2163 * Enable patching in a VT-x/AMD-V guest
2164 *
2165 * @returns VBox status code.
2166 * @param pVM The cross context VM structure.
2167 * @param pPatchMem Patch memory range.
2168 * @param cbPatchMem Size of the memory range.
2169 */
2170VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2171{
2172 VM_ASSERT_EMT(pVM);
2173 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2174 if (pVM->cCpus > 1)
2175 {
2176 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2177 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2178 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2179 AssertRC(rc);
2180 return rc;
2181 }
2182 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2183}
2184
2185
2186/**
2187 * Disable patching in a VT-x/AMD-V guest.
2188 *
2189 * @returns VBox status code.
2190 * @param pVM The cross context VM structure.
2191 * @param pPatchMem Patch memory range.
2192 * @param cbPatchMem Size of the memory range.
2193 */
2194VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2195{
2196 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2197 RT_NOREF2(pPatchMem, cbPatchMem);
2198
2199 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2200 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2201
2202 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2203 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2204 (void *)(uintptr_t)VMMGetCpuId(pVM));
2205 AssertRC(rc);
2206
2207 pVM->hm.s.pGuestPatchMem = 0;
2208 pVM->hm.s.pFreeGuestPatchMem = 0;
2209 pVM->hm.s.cbGuestPatchMem = 0;
2210 pVM->hm.s.fTPRPatchingActive = false;
2211 return VINF_SUCCESS;
2212}
2213
2214
2215/**
2216 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2217 *
2218 * @returns VBox strict status code.
2219 * @param pVM The cross context VM structure.
2220 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2221 * @param pvUser User specified CPU context.
2222 *
2223 */
2224static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2225{
2226 /*
2227 * Only execute the handler on the VCPU the original patch request was
2228 * issued. (The other CPU(s) might not yet have switched to protected
2229 * mode, nor have the correct memory context.)
2230 */
2231 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2232 if (pVCpu->idCpu != idCpu)
2233 return VINF_SUCCESS;
2234
2235 /*
2236 * We're racing other VCPUs here, so don't try patch the instruction twice
2237 * and make sure there is still room for our patch record.
2238 */
2239 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2240 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2241 if (pPatch)
2242 {
2243 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2244 return VINF_SUCCESS;
2245 }
2246 uint32_t const idx = pVM->hm.s.cPatches;
2247 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2248 {
2249 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2250 return VINF_SUCCESS;
2251 }
2252 pPatch = &pVM->hm.s.aPatches[idx];
2253
2254 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2255
2256 /*
2257 * Disassembler the instruction and get cracking.
2258 */
2259 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2260 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2261 uint32_t cbOp;
2262 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2263 AssertRC(rc);
2264 if ( rc == VINF_SUCCESS
2265 && pDis->pCurInstr->uOpcode == OP_MOV
2266 && cbOp >= 3)
2267 {
2268 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2269
2270 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2271 AssertRC(rc);
2272
2273 pPatch->cbOp = cbOp;
2274
2275 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2276 {
2277 /* write. */
2278 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2279 {
2280 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2281 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2282 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2283 }
2284 else
2285 {
2286 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2287 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2288 pPatch->uSrcOperand = pDis->Param2.uValue;
2289 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2290 }
2291 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2292 AssertRC(rc);
2293
2294 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2295 pPatch->cbNewOp = sizeof(s_abVMMCall);
2296 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2297 }
2298 else
2299 {
2300 /*
2301 * TPR Read.
2302 *
2303 * Found:
2304 * mov eax, dword [fffe0080] (5 bytes)
2305 * Check if next instruction is:
2306 * shr eax, 4
2307 */
2308 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2309
2310 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2311 uint8_t const cbOpMmio = cbOp;
2312 uint64_t const uSavedRip = pCtx->rip;
2313
2314 pCtx->rip += cbOp;
2315 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2316 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2317 pCtx->rip = uSavedRip;
2318
2319 if ( rc == VINF_SUCCESS
2320 && pDis->pCurInstr->uOpcode == OP_SHR
2321 && pDis->Param1.fUse == DISUSE_REG_GEN32
2322 && pDis->Param1.Base.idxGenReg == idxMmioReg
2323 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2324 && pDis->Param2.uValue == 4
2325 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2326 {
2327 uint8_t abInstr[15];
2328
2329 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2330 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2331 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2332 AssertRC(rc);
2333
2334 pPatch->cbOp = cbOpMmio + cbOp;
2335
2336 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2337 abInstr[0] = 0xF0;
2338 abInstr[1] = 0x0F;
2339 abInstr[2] = 0x20;
2340 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2341 for (unsigned i = 4; i < pPatch->cbOp; i++)
2342 abInstr[i] = 0x90; /* nop */
2343
2344 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2345 AssertRC(rc);
2346
2347 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2348 pPatch->cbNewOp = pPatch->cbOp;
2349 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2350
2351 Log(("Acceptable read/shr candidate!\n"));
2352 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2353 }
2354 else
2355 {
2356 pPatch->enmType = HMTPRINSTR_READ;
2357 pPatch->uDstOperand = idxMmioReg;
2358
2359 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2360 AssertRC(rc);
2361
2362 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2363 pPatch->cbNewOp = sizeof(s_abVMMCall);
2364 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2365 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2366 }
2367 }
2368
2369 pPatch->Core.Key = pCtx->eip;
2370 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2371 AssertRC(rc);
2372
2373 pVM->hm.s.cPatches++;
2374 return VINF_SUCCESS;
2375 }
2376
2377 /*
2378 * Save invalid patch, so we will not try again.
2379 */
2380 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2381 pPatch->Core.Key = pCtx->eip;
2382 pPatch->enmType = HMTPRINSTR_INVALID;
2383 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2384 AssertRC(rc);
2385 pVM->hm.s.cPatches++;
2386 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2387 return VINF_SUCCESS;
2388}
2389
2390
2391/**
2392 * Callback to patch a TPR instruction (jump to generated code).
2393 *
2394 * @returns VBox strict status code.
2395 * @param pVM The cross context VM structure.
2396 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2397 * @param pvUser User specified CPU context.
2398 *
2399 */
2400static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2401{
2402 /*
2403 * Only execute the handler on the VCPU the original patch request was
2404 * issued. (The other CPU(s) might not yet have switched to protected
2405 * mode, nor have the correct memory context.)
2406 */
2407 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2408 if (pVCpu->idCpu != idCpu)
2409 return VINF_SUCCESS;
2410
2411 /*
2412 * We're racing other VCPUs here, so don't try patch the instruction twice
2413 * and make sure there is still room for our patch record.
2414 */
2415 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2416 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2417 if (pPatch)
2418 {
2419 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2420 return VINF_SUCCESS;
2421 }
2422 uint32_t const idx = pVM->hm.s.cPatches;
2423 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2424 {
2425 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2426 return VINF_SUCCESS;
2427 }
2428 pPatch = &pVM->hm.s.aPatches[idx];
2429
2430 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2431 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2432
2433 /*
2434 * Disassemble the instruction and get cracking.
2435 */
2436 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2437 uint32_t cbOp;
2438 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2439 AssertRC(rc);
2440 if ( rc == VINF_SUCCESS
2441 && pDis->pCurInstr->uOpcode == OP_MOV
2442 && cbOp >= 5)
2443 {
2444 uint8_t aPatch[64];
2445 uint32_t off = 0;
2446
2447 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2448 AssertRC(rc);
2449
2450 pPatch->cbOp = cbOp;
2451 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2452
2453 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2454 {
2455 /*
2456 * TPR write:
2457 *
2458 * push ECX [51]
2459 * push EDX [52]
2460 * push EAX [50]
2461 * xor EDX,EDX [31 D2]
2462 * mov EAX,EAX [89 C0]
2463 * or
2464 * mov EAX,0000000CCh [B8 CC 00 00 00]
2465 * mov ECX,0C0000082h [B9 82 00 00 C0]
2466 * wrmsr [0F 30]
2467 * pop EAX [58]
2468 * pop EDX [5A]
2469 * pop ECX [59]
2470 * jmp return_address [E9 return_address]
2471 */
2472 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2473
2474 aPatch[off++] = 0x51; /* push ecx */
2475 aPatch[off++] = 0x52; /* push edx */
2476 if (!fUsesEax)
2477 aPatch[off++] = 0x50; /* push eax */
2478 aPatch[off++] = 0x31; /* xor edx, edx */
2479 aPatch[off++] = 0xD2;
2480 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2481 {
2482 if (!fUsesEax)
2483 {
2484 aPatch[off++] = 0x89; /* mov eax, src_reg */
2485 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2486 }
2487 }
2488 else
2489 {
2490 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2491 aPatch[off++] = 0xB8; /* mov eax, immediate */
2492 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2493 off += sizeof(uint32_t);
2494 }
2495 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2496 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2497 off += sizeof(uint32_t);
2498
2499 aPatch[off++] = 0x0F; /* wrmsr */
2500 aPatch[off++] = 0x30;
2501 if (!fUsesEax)
2502 aPatch[off++] = 0x58; /* pop eax */
2503 aPatch[off++] = 0x5A; /* pop edx */
2504 aPatch[off++] = 0x59; /* pop ecx */
2505 }
2506 else
2507 {
2508 /*
2509 * TPR read:
2510 *
2511 * push ECX [51]
2512 * push EDX [52]
2513 * push EAX [50]
2514 * mov ECX,0C0000082h [B9 82 00 00 C0]
2515 * rdmsr [0F 32]
2516 * mov EAX,EAX [89 C0]
2517 * pop EAX [58]
2518 * pop EDX [5A]
2519 * pop ECX [59]
2520 * jmp return_address [E9 return_address]
2521 */
2522 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2523
2524 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2525 aPatch[off++] = 0x51; /* push ecx */
2526 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2527 aPatch[off++] = 0x52; /* push edx */
2528 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2529 aPatch[off++] = 0x50; /* push eax */
2530
2531 aPatch[off++] = 0x31; /* xor edx, edx */
2532 aPatch[off++] = 0xD2;
2533
2534 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2535 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2536 off += sizeof(uint32_t);
2537
2538 aPatch[off++] = 0x0F; /* rdmsr */
2539 aPatch[off++] = 0x32;
2540
2541 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2542 {
2543 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2544 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2545 }
2546
2547 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2548 aPatch[off++] = 0x58; /* pop eax */
2549 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2550 aPatch[off++] = 0x5A; /* pop edx */
2551 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2552 aPatch[off++] = 0x59; /* pop ecx */
2553 }
2554 aPatch[off++] = 0xE9; /* jmp return_address */
2555 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2556 off += sizeof(RTRCUINTPTR);
2557
2558 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2559 {
2560 /* Write new code to the patch buffer. */
2561 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2562 AssertRC(rc);
2563
2564#ifdef LOG_ENABLED
2565 uint32_t cbCurInstr;
2566 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2567 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2568 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2569 {
2570 char szOutput[256];
2571 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2572 szOutput, sizeof(szOutput), &cbCurInstr);
2573 if (RT_SUCCESS(rc))
2574 Log(("Patch instr %s\n", szOutput));
2575 else
2576 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2577 }
2578#endif
2579
2580 pPatch->aNewOpcode[0] = 0xE9;
2581 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2582
2583 /* Overwrite the TPR instruction with a jump. */
2584 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2585 AssertRC(rc);
2586
2587 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2588
2589 pVM->hm.s.pFreeGuestPatchMem += off;
2590 pPatch->cbNewOp = 5;
2591
2592 pPatch->Core.Key = pCtx->eip;
2593 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2594 AssertRC(rc);
2595
2596 pVM->hm.s.cPatches++;
2597 pVM->hm.s.fTPRPatchingActive = true;
2598 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2599 return VINF_SUCCESS;
2600 }
2601
2602 Log(("Ran out of space in our patch buffer!\n"));
2603 }
2604 else
2605 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2606
2607
2608 /*
2609 * Save invalid patch, so we will not try again.
2610 */
2611 pPatch = &pVM->hm.s.aPatches[idx];
2612 pPatch->Core.Key = pCtx->eip;
2613 pPatch->enmType = HMTPRINSTR_INVALID;
2614 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2615 AssertRC(rc);
2616 pVM->hm.s.cPatches++;
2617 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2618 return VINF_SUCCESS;
2619}
2620
2621
2622/**
2623 * Attempt to patch TPR mmio instructions.
2624 *
2625 * @returns VBox status code.
2626 * @param pVM The cross context VM structure.
2627 * @param pVCpu The cross context virtual CPU structure.
2628 * @param pCtx Pointer to the guest CPU context.
2629 */
2630VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2631{
2632 NOREF(pCtx);
2633 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2634 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2635 (void *)(uintptr_t)pVCpu->idCpu);
2636 AssertRC(rc);
2637 return rc;
2638}
2639
2640
2641/**
2642 * Checks if a code selector (CS) is suitable for execution
2643 * within VMX when unrestricted execution isn't available.
2644 *
2645 * @returns true if selector is suitable for VMX, otherwise
2646 * false.
2647 * @param pSel Pointer to the selector to check (CS).
2648 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2649 */
2650static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2651{
2652 /*
2653 * Segment must be an accessed code segment, it must be present and it must
2654 * be usable.
2655 * Note! These are all standard requirements and if CS holds anything else
2656 * we've got buggy code somewhere!
2657 */
2658 AssertCompile(X86DESCATTR_TYPE == 0xf);
2659 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2660 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2661 ("%#x\n", pSel->Attr.u),
2662 false);
2663
2664 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2665 must equal SS.DPL for non-confroming segments.
2666 Note! This is also a hard requirement like above. */
2667 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2668 ? pSel->Attr.n.u2Dpl <= uStackDpl
2669 : pSel->Attr.n.u2Dpl == uStackDpl,
2670 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2671 false);
2672
2673 /*
2674 * The following two requirements are VT-x specific:
2675 * - G bit must be set if any high limit bits are set.
2676 * - G bit must be clear if any low limit bits are clear.
2677 */
2678 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2679 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity))
2680 return true;
2681 return false;
2682}
2683
2684
2685/**
2686 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2687 * execution within VMX when unrestricted execution isn't
2688 * available.
2689 *
2690 * @returns true if selector is suitable for VMX, otherwise
2691 * false.
2692 * @param pSel Pointer to the selector to check
2693 * (DS/ES/FS/GS).
2694 */
2695static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2696{
2697 /*
2698 * Unusable segments are OK. These days they should be marked as such, as
2699 * but as an alternative we for old saved states and AMD<->VT-x migration
2700 * we also treat segments with all the attributes cleared as unusable.
2701 */
2702 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2703 return true;
2704
2705 /** @todo tighten these checks. Will require CPUM load adjusting. */
2706
2707 /* Segment must be accessed. */
2708 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2709 {
2710 /* Code segments must also be readable. */
2711 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2712 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2713 {
2714 /* The S bit must be set. */
2715 if (pSel->Attr.n.u1DescType)
2716 {
2717 /* Except for conforming segments, DPL >= RPL. */
2718 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2719 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2720 {
2721 /* Segment must be present. */
2722 if (pSel->Attr.n.u1Present)
2723 {
2724 /*
2725 * The following two requirements are VT-x specific:
2726 * - G bit must be set if any high limit bits are set.
2727 * - G bit must be clear if any low limit bits are clear.
2728 */
2729 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2730 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity))
2731 return true;
2732 }
2733 }
2734 }
2735 }
2736 }
2737
2738 return false;
2739}
2740
2741
2742/**
2743 * Checks if the stack selector (SS) is suitable for execution
2744 * within VMX when unrestricted execution isn't available.
2745 *
2746 * @returns true if selector is suitable for VMX, otherwise
2747 * false.
2748 * @param pSel Pointer to the selector to check (SS).
2749 */
2750static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2751{
2752 /*
2753 * Unusable segments are OK. These days they should be marked as such, as
2754 * but as an alternative we for old saved states and AMD<->VT-x migration
2755 * we also treat segments with all the attributes cleared as unusable.
2756 */
2757 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2758 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2759 return true;
2760
2761 /*
2762 * Segment must be an accessed writable segment, it must be present.
2763 * Note! These are all standard requirements and if SS holds anything else
2764 * we've got buggy code somewhere!
2765 */
2766 AssertCompile(X86DESCATTR_TYPE == 0xf);
2767 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2768 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2769 ("%#x\n", pSel->Attr.u), false);
2770
2771 /* DPL must equal RPL.
2772 Note! This is also a hard requirement like above. */
2773 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2774 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel), false);
2775
2776 /*
2777 * The following two requirements are VT-x specific:
2778 * - G bit must be set if any high limit bits are set.
2779 * - G bit must be clear if any low limit bits are clear.
2780 */
2781 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2782 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity))
2783 return true;
2784 return false;
2785}
2786
2787
2788/**
2789 * Force execution of the current IO code in the recompiler.
2790 *
2791 * @returns VBox status code.
2792 * @param pVM The cross context VM structure.
2793 * @param pCtx Partial VM execution context.
2794 */
2795VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2796{
2797 PVMCPU pVCpu = VMMGetCpu(pVM);
2798
2799 Assert(HMIsEnabled(pVM));
2800 Log(("HMR3EmulateIoBlock\n"));
2801
2802 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2803 if (HMCanEmulateIoBlockEx(pCtx))
2804 {
2805 Log(("HMR3EmulateIoBlock -> enabled\n"));
2806 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2807 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2808 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2809 return VINF_EM_RESCHEDULE_REM;
2810 }
2811 return VINF_SUCCESS;
2812}
2813
2814
2815/**
2816 * Checks if we can currently use hardware accelerated raw mode.
2817 *
2818 * @returns true if we can currently use hardware acceleration, otherwise false.
2819 * @param pVM The cross context VM structure.
2820 * @param pCtx Partial VM execution context.
2821 */
2822VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2823{
2824 PVMCPU pVCpu = VMMGetCpu(pVM);
2825
2826 Assert(HMIsEnabled(pVM));
2827
2828#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
2829 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
2830 {
2831 Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
2832 return false;
2833 }
2834#endif
2835
2836 /* If we're still executing the IO code, then return false. */
2837 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2838 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2839 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2840 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2841 return false;
2842
2843 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2844
2845 /* AMD-V supports real & protected mode with or without paging. */
2846 if (pVM->hm.s.svm.fEnabled)
2847 {
2848 pVCpu->hm.s.fActive = true;
2849 return true;
2850 }
2851
2852 pVCpu->hm.s.fActive = false;
2853
2854 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2855 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2856 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2857
2858 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2859 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2860 {
2861 /*
2862 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2863 * guest execution feature is missing (VT-x only).
2864 */
2865 if (fSupportsRealMode)
2866 {
2867 if (CPUMIsGuestInRealModeEx(pCtx))
2868 {
2869 /*
2870 * In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2871 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2872 * If this is not true, we cannot execute real mode as V86 and have to fall
2873 * back to emulation.
2874 */
2875 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2876 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2877 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2878 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2879 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2880 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2881 {
2882 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2883 return false;
2884 }
2885 if ( (pCtx->cs.u32Limit != 0xffff)
2886 || (pCtx->ds.u32Limit != 0xffff)
2887 || (pCtx->es.u32Limit != 0xffff)
2888 || (pCtx->ss.u32Limit != 0xffff)
2889 || (pCtx->fs.u32Limit != 0xffff)
2890 || (pCtx->gs.u32Limit != 0xffff))
2891 {
2892 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2893 return false;
2894 }
2895 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2896 }
2897 else
2898 {
2899 /*
2900 * Verify the requirements for executing code in protected mode. VT-x can't
2901 * handle the CPU state right after a switch from real to protected mode
2902 * (all sorts of RPL & DPL assumptions).
2903 */
2904 if (pVCpu->hm.s.vmx.fWasInRealMode)
2905 {
2906 /** @todo If guest is in V86 mode, these checks should be different! */
2907 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2908 {
2909 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2910 return false;
2911 }
2912 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2913 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2914 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2915 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2916 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2917 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2918 {
2919 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2920 return false;
2921 }
2922 }
2923 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2924 if (pCtx->gdtr.cbGdt)
2925 {
2926 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2927 {
2928 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2929 return false;
2930 }
2931 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2932 {
2933 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2934 return false;
2935 }
2936 }
2937 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2938 }
2939 }
2940 else
2941 {
2942 if ( !CPUMIsGuestInLongModeEx(pCtx)
2943 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2944 {
2945 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2946 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2947 return false;
2948
2949 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2950 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2951 return false;
2952
2953 /*
2954 * The guest is about to complete the switch to protected mode. Wait a bit longer.
2955 * Windows XP; switch to protected mode; all selectors are marked not present
2956 * in the hidden registers (possible recompiler bug; see load_seg_vm).
2957 */
2958 /** @todo Is this supposed recompiler bug still relevant with IEM? */
2959 if (pCtx->cs.Attr.n.u1Present == 0)
2960 return false;
2961 if (pCtx->ss.Attr.n.u1Present == 0)
2962 return false;
2963
2964 /*
2965 * Windows XP: possible same as above, but new recompiler requires new
2966 * heuristics? VT-x doesn't seem to like something about the guest state and
2967 * this stuff avoids it.
2968 */
2969 /** @todo This check is actually wrong, it doesn't take the direction of the
2970 * stack segment into account. But, it does the job for now. */
2971 if (pCtx->rsp >= pCtx->ss.u32Limit)
2972 return false;
2973 }
2974 }
2975 }
2976
2977 if (pVM->hm.s.vmx.fEnabled)
2978 {
2979 uint32_t uCR0Mask;
2980
2981 /* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2982 uCR0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2983
2984 /* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
2985 uCR0Mask &= ~X86_CR0_NE;
2986
2987 if (fSupportsRealMode)
2988 {
2989 /* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2990 uCR0Mask &= ~(X86_CR0_PG|X86_CR0_PE);
2991 }
2992 else
2993 {
2994 /* We support protected mode without paging using identity mapping. */
2995 uCR0Mask &= ~X86_CR0_PG;
2996 }
2997 if ((pCtx->cr0 & uCR0Mask) != uCR0Mask)
2998 return false;
2999
3000 /* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
3001 uCR0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
3002 if ((pCtx->cr0 & uCR0Mask) != 0)
3003 return false;
3004
3005 /* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
3006 uCR0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
3007 uCR0Mask &= ~X86_CR4_VMXE;
3008 if ((pCtx->cr4 & uCR0Mask) != uCR0Mask)
3009 return false;
3010
3011 /* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
3012 uCR0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
3013 if ((pCtx->cr4 & uCR0Mask) != 0)
3014 return false;
3015
3016 pVCpu->hm.s.fActive = true;
3017 return true;
3018 }
3019
3020 return false;
3021}
3022
3023
3024/**
3025 * Checks if we need to reschedule due to VMM device heap changes.
3026 *
3027 * @returns true if a reschedule is required, otherwise false.
3028 * @param pVM The cross context VM structure.
3029 * @param pCtx VM execution context.
3030 */
3031VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
3032{
3033 /*
3034 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
3035 * when the unrestricted guest execution feature is missing (VT-x only).
3036 */
3037 if ( pVM->hm.s.vmx.fEnabled
3038 && !pVM->hm.s.vmx.fUnrestrictedGuest
3039 && CPUMIsGuestInRealModeEx(pCtx)
3040 && !PDMVmmDevHeapIsEnabled(pVM))
3041 {
3042 return true;
3043 }
3044
3045 return false;
3046}
3047
3048
3049/**
3050 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
3051 * event settings changes.
3052 *
3053 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
3054 * function is just updating the VM globals.
3055 *
3056 * @param pVM The VM cross context VM structure.
3057 * @thread EMT(0)
3058 */
3059VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
3060{
3061 /* Interrupts. */
3062 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
3063 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
3064
3065 /* CPU Exceptions. */
3066 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
3067 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
3068 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3069 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3070
3071 /* Common VM exits. */
3072 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
3073 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
3074 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3075 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3076
3077 /* Vendor specific VM exits. */
3078 if (HMR3IsVmxEnabled(pVM->pUVM))
3079 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
3080 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
3081 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3082 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3083 else
3084 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
3085 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
3086 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3087 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3088
3089 /* Done. */
3090 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
3091}
3092
3093
3094/**
3095 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
3096 *
3097 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
3098 * per CPU settings.
3099 *
3100 * @param pVM The VM cross context VM structure.
3101 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3102 */
3103VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
3104{
3105 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
3106}
3107
3108
3109/**
3110 * Checks if we are currently using hardware acceleration.
3111 *
3112 * @returns true if hardware acceleration is being used, otherwise false.
3113 * @param pVCpu The cross context virtual CPU structure.
3114 */
3115VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
3116{
3117 return pVCpu->hm.s.fActive;
3118}
3119
3120
3121/**
3122 * External interface for querying whether hardware acceleration is enabled.
3123 *
3124 * @returns true if VT-x or AMD-V is being used, otherwise false.
3125 * @param pUVM The user mode VM handle.
3126 * @sa HMIsEnabled, HMIsEnabledNotMacro.
3127 */
3128VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
3129{
3130 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3131 PVM pVM = pUVM->pVM;
3132 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3133 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
3134}
3135
3136
3137/**
3138 * External interface for querying whether VT-x is being used.
3139 *
3140 * @returns true if VT-x is being used, otherwise false.
3141 * @param pUVM The user mode VM handle.
3142 * @sa HMR3IsSvmEnabled, HMIsEnabled
3143 */
3144VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3145{
3146 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3147 PVM pVM = pUVM->pVM;
3148 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3149 return pVM->hm.s.vmx.fEnabled
3150 && pVM->hm.s.vmx.fSupported
3151 && pVM->fHMEnabled;
3152}
3153
3154
3155/**
3156 * External interface for querying whether AMD-V is being used.
3157 *
3158 * @returns true if VT-x is being used, otherwise false.
3159 * @param pUVM The user mode VM handle.
3160 * @sa HMR3IsVmxEnabled, HMIsEnabled
3161 */
3162VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3163{
3164 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3165 PVM pVM = pUVM->pVM;
3166 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3167 return pVM->hm.s.svm.fEnabled
3168 && pVM->hm.s.svm.fSupported
3169 && pVM->fHMEnabled;
3170}
3171
3172
3173/**
3174 * Checks if we are currently using nested paging.
3175 *
3176 * @returns true if nested paging is being used, otherwise false.
3177 * @param pUVM The user mode VM handle.
3178 */
3179VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3180{
3181 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3182 PVM pVM = pUVM->pVM;
3183 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3184 return pVM->hm.s.fNestedPaging;
3185}
3186
3187
3188/**
3189 * Checks if virtualized APIC registers is enabled.
3190 *
3191 * When enabled this feature allows the hardware to access most of the
3192 * APIC registers in the virtual-APIC page without causing VM-exits. See
3193 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3194 *
3195 * @returns true if virtualized APIC registers is enabled, otherwise
3196 * false.
3197 * @param pUVM The user mode VM handle.
3198 */
3199VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3200{
3201 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3202 PVM pVM = pUVM->pVM;
3203 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3204 return pVM->hm.s.fVirtApicRegs;
3205}
3206
3207
3208/**
3209 * Checks if APIC posted-interrupt processing is enabled.
3210 *
3211 * This returns whether we can deliver interrupts to the guest without
3212 * leaving guest-context by updating APIC state from host-context.
3213 *
3214 * @returns true if APIC posted-interrupt processing is enabled,
3215 * otherwise false.
3216 * @param pUVM The user mode VM handle.
3217 */
3218VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3219{
3220 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3221 PVM pVM = pUVM->pVM;
3222 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3223 return pVM->hm.s.fPostedIntrs;
3224}
3225
3226
3227/**
3228 * Checks if we are currently using VPID in VT-x mode.
3229 *
3230 * @returns true if VPID is being used, otherwise false.
3231 * @param pUVM The user mode VM handle.
3232 */
3233VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3234{
3235 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3236 PVM pVM = pUVM->pVM;
3237 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3238 return pVM->hm.s.vmx.fVpid;
3239}
3240
3241
3242/**
3243 * Checks if we are currently using VT-x unrestricted execution,
3244 * aka UX.
3245 *
3246 * @returns true if UX is being used, otherwise false.
3247 * @param pUVM The user mode VM handle.
3248 */
3249VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3250{
3251 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3252 PVM pVM = pUVM->pVM;
3253 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3254 return pVM->hm.s.vmx.fUnrestrictedGuest;
3255}
3256
3257
3258/**
3259 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3260 *
3261 * @returns true if an internal event is pending, otherwise false.
3262 * @param pVCpu The cross context virtual CPU structure.
3263 */
3264VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3265{
3266 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3267}
3268
3269
3270/**
3271 * Checks if the VMX-preemption timer is being used.
3272 *
3273 * @returns true if the VMX-preemption timer is being used, otherwise false.
3274 * @param pVM The cross context VM structure.
3275 */
3276VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3277{
3278 return HMIsEnabled(pVM)
3279 && pVM->hm.s.vmx.fEnabled
3280 && pVM->hm.s.vmx.fUsePreemptTimer;
3281}
3282
3283
3284/**
3285 * Checks if there is an I/O instruction pending.
3286 *
3287 * @returns true if pending, false if not.
3288 * @param pVCpu The cross context virtual CPU structure.
3289 */
3290VMMR3_INT_DECL(bool) HMR3HasPendingIOInstr(PVMCPU pVCpu)
3291{
3292 return pVCpu->hm.s.PendingIO.enmType != HMPENDINGIO_INVALID
3293 && pVCpu->hm.s.PendingIO.GCPtrRip == pVCpu->cpum.GstCtx.rip;
3294}
3295
3296
3297/**
3298 * Restart an I/O instruction that was refused in ring-0
3299 *
3300 * @returns Strict VBox status code. Informational status codes other than the one documented
3301 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3302 * @retval VINF_SUCCESS Success.
3303 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3304 * status code must be passed on to EM.
3305 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3306 *
3307 * @param pVM The cross context VM structure.
3308 * @param pVCpu The cross context virtual CPU structure.
3309 * @param pCtx Pointer to the guest CPU context.
3310 */
3311VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3312{
3313 /*
3314 * Check if we've got relevant data pending.
3315 */
3316 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3317 if (enmType == HMPENDINGIO_INVALID)
3318 return VERR_NOT_FOUND;
3319 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3320 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3321 return VERR_NOT_FOUND;
3322
3323 /*
3324 * Execute pending I/O.
3325 */
3326 VBOXSTRICTRC rcStrict;
3327 switch (enmType)
3328 {
3329 case HMPENDINGIO_PORT_READ:
3330 {
3331 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3332 uint32_t u32Val = 0;
3333
3334 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3335 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3336 if (IOM_SUCCESS(rcStrict))
3337 {
3338 /* Write back to the EAX register. */
3339 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3340 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3341 }
3342 break;
3343 }
3344
3345 default:
3346 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3347 }
3348
3349 if (IOM_SUCCESS(rcStrict))
3350 {
3351 /*
3352 * Check for I/O breakpoints.
3353 */
3354 uint32_t const uDr7 = pCtx->dr[7];
3355 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3356 && X86_DR7_ANY_RW_IO(uDr7)
3357 && (pCtx->cr4 & X86_CR4_DE))
3358 || DBGFBpIsHwIoArmed(pVM))
3359 {
3360 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3361 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3362 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3363 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3364 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3365 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3366 rcStrict = rcStrict2;
3367 }
3368 }
3369 return rcStrict;
3370}
3371
3372
3373/**
3374 * Check fatal VT-x/AMD-V error and produce some meaningful
3375 * log release message.
3376 *
3377 * @param pVM The cross context VM structure.
3378 * @param iStatusCode VBox status code.
3379 */
3380VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3381{
3382 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3383 {
3384 PVMCPU pVCpu = &pVM->aCpus[i];
3385 switch (iStatusCode)
3386 {
3387 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3388 * might be getting inaccurate values for non-guru'ing EMTs. */
3389 case VERR_VMX_INVALID_VMCS_FIELD:
3390 break;
3391
3392 case VERR_VMX_INVALID_VMCS_PTR:
3393 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3394 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3395 pVCpu->hm.s.vmx.HCPhysVmcs));
3396 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3397 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3398 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3399 break;
3400
3401 case VERR_VMX_UNABLE_TO_START_VM:
3402 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3403 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3404 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3405
3406 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3407 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3408 {
3409 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3410 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3411 }
3412 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3413 {
3414 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3415 {
3416 uint32_t const u32Val = pVCpu->hm.s.vmx.u32PinCtls;
3417 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT );
3418 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT );
3419 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI );
3420 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
3421 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR );
3422 }
3423 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3424 {
3425 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls;
3426 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT );
3427 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
3428 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT );
3429 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT );
3430 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT );
3431 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT );
3432 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT );
3433 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT );
3434 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT );
3435 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT );
3436 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT );
3437 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW );
3438 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT );
3439 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT );
3440 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT );
3441 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS );
3442 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG );
3443 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS );
3444 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT );
3445 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT );
3446 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
3447 }
3448 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3449 {
3450 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls2;
3451 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC );
3452 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_EPT );
3453 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
3454 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP );
3455 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC );
3456 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VPID );
3457 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT );
3458 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST );
3459 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT );
3460 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY );
3461 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT );
3462 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT );
3463 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID );
3464 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC );
3465 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING );
3466 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT );
3467 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT );
3468 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_PML );
3469 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE );
3470 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT );
3471 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS );
3472 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING );
3473 }
3474 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3475 {
3476 uint32_t const u32Val = pVCpu->hm.s.vmx.u32EntryCtls;
3477 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG );
3478 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST );
3479 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM );
3480 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON );
3481 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
3482 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR );
3483 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
3484 }
3485 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3486 {
3487 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ExitCtls;
3488 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG );
3489 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE );
3490 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR );
3491 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT );
3492 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR );
3493 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR );
3494 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR );
3495 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR );
3496 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
3497 }
3498 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3499 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3500 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3501 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3502 }
3503 /** @todo Log VM-entry event injection control fields
3504 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3505 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3506 break;
3507
3508 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3509 case VERR_VMX_INVALID_VMXON_PTR:
3510 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3511 case VERR_VMX_INVALID_GUEST_STATE:
3512 case VERR_VMX_UNEXPECTED_EXIT:
3513 case VERR_SVM_UNKNOWN_EXIT:
3514 case VERR_SVM_UNEXPECTED_EXIT:
3515 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3516 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3517 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3518 break;
3519 }
3520 }
3521
3522 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3523 {
3524 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3525 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3526 }
3527 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3528 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3529}
3530
3531
3532/**
3533 * Execute state save operation.
3534 *
3535 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3536 * is because we always save the VM state from ring-3 and thus most HM state
3537 * will be re-synced dynamically at runtime and don't need to be part of the VM
3538 * saved state.
3539 *
3540 * @returns VBox status code.
3541 * @param pVM The cross context VM structure.
3542 * @param pSSM SSM operation handle.
3543 */
3544static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3545{
3546 int rc;
3547
3548 Log(("hmR3Save:\n"));
3549
3550 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3551 {
3552 Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3553 if (pVM->cpum.ro.GuestFeatures.fSvm)
3554 {
3555 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3556 rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3557 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3558 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3559 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3560 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3561 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3562 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3563 rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3564 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3565 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3566 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3567 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3568 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3569 AssertRCReturn(rc, rc);
3570 }
3571 }
3572
3573 /* Save the guest patch data. */
3574 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3575 rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3576 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3577
3578 /* Store all the guest patch records too. */
3579 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3580 AssertRCReturn(rc, rc);
3581
3582 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3583 {
3584 AssertCompileSize(HMTPRINSTR, 4);
3585 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3586 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3587 rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3588 rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
3589 rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3590 rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3591 rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3592 rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3593 rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3594 rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3595 rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
3596 AssertRCReturn(rc, rc);
3597 }
3598
3599 return VINF_SUCCESS;
3600}
3601
3602
3603/**
3604 * Execute state load operation.
3605 *
3606 * @returns VBox status code.
3607 * @param pVM The cross context VM structure.
3608 * @param pSSM SSM operation handle.
3609 * @param uVersion Data layout version.
3610 * @param uPass The data pass.
3611 */
3612static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3613{
3614 int rc;
3615
3616 LogFlowFunc(("uVersion=%u\n", uVersion));
3617 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3618
3619 /*
3620 * Validate version.
3621 */
3622 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3623 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3624 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3625 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3626 {
3627 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3628 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3629 }
3630
3631 /*
3632 * Load per-VCPU state.
3633 */
3634 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3635 {
3636 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3637 {
3638 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3639 if (pVM->cpum.ro.GuestFeatures.fSvm)
3640 {
3641 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3642 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3643 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3644 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3645 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3646 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3647 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3648 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3649 rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3650 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3651 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3652 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3653 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3654 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3655 AssertRCReturn(rc, rc);
3656 }
3657 }
3658 else
3659 {
3660 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3661 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3662 rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3663 rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3664
3665 /* VMX fWasInRealMode related data. */
3666 uint32_t uDummy;
3667 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3668 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3669 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3670 AssertRCReturn(rc, rc);
3671 }
3672 }
3673
3674 /*
3675 * Load TPR patching data.
3676 */
3677 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3678 {
3679 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3680 rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3681 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3682
3683 /* Fetch all TPR patch records. */
3684 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3685 AssertRCReturn(rc, rc);
3686 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3687 {
3688 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3689 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3690 rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3691 rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
3692 rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3693 rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3694 rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3695
3696 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3697 pVM->hm.s.fTPRPatchingActive = true;
3698 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3699
3700 rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3701 rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3702 rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
3703 rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3704 AssertRCReturn(rc, rc);
3705
3706 LogFlow(("hmR3Load: patch %d\n", i));
3707 LogFlow(("Key = %x\n", pPatch->Core.Key));
3708 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3709 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3710 LogFlow(("type = %d\n", pPatch->enmType));
3711 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3712 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3713 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3714 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3715
3716 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3717 AssertRCReturn(rc, rc);
3718 }
3719 }
3720
3721 return VINF_SUCCESS;
3722}
3723
3724
3725/**
3726 * Gets the name of a VT-x exit code.
3727 *
3728 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3729 * @param uExit The VT-x exit to name.
3730 */
3731VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
3732{
3733 if (uExit < RT_ELEMENTS(g_apszVTxExitReasons))
3734 return g_apszVTxExitReasons[uExit];
3735 return NULL;
3736}
3737
3738
3739/**
3740 * Gets the name of an AMD-V exit code.
3741 *
3742 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3743 * @param uExit The AMD-V exit to name.
3744 */
3745VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
3746{
3747 if (uExit < RT_ELEMENTS(g_apszAmdVExitReasons))
3748 return g_apszAmdVExitReasons[uExit];
3749 return hmSvmGetSpecialExitReasonDesc(uExit);
3750}
3751
3752
3753/**
3754 * Displays HM info.
3755 *
3756 * @param pVM The cross context VM structure.
3757 * @param pHlp The info helper functions.
3758 * @param pszArgs Arguments, ignored.
3759 */
3760static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3761{
3762 NOREF(pszArgs);
3763 PVMCPU pVCpu = VMMGetCpu(pVM);
3764 if (!pVCpu)
3765 pVCpu = &pVM->aCpus[0];
3766
3767 if (HMIsEnabled(pVM))
3768 {
3769 if (pVM->hm.s.vmx.fSupported)
3770 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3771 else
3772 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3773 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3774 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3775 }
3776 else
3777 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3778}
3779
3780
3781/**
3782 * Displays the HM pending event.
3783 *
3784 * @param pVM The cross context VM structure.
3785 * @param pHlp The info helper functions.
3786 * @param pszArgs Arguments, ignored.
3787 */
3788static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3789{
3790 NOREF(pszArgs);
3791 PVMCPU pVCpu = VMMGetCpu(pVM);
3792 if (!pVCpu)
3793 pVCpu = &pVM->aCpus[0];
3794
3795 if (HMIsEnabled(pVM))
3796 {
3797 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3798 if (pVCpu->hm.s.Event.fPending)
3799 {
3800 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3801 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3802 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3803 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3804 }
3805 }
3806 else
3807 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3808}
3809
3810
3811/**
3812 * Displays the SVM nested-guest VMCB cache.
3813 *
3814 * @param pVM The cross context VM structure.
3815 * @param pHlp The info helper functions.
3816 * @param pszArgs Arguments, ignored.
3817 */
3818static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3819{
3820 NOREF(pszArgs);
3821 PVMCPU pVCpu = VMMGetCpu(pVM);
3822 if (!pVCpu)
3823 pVCpu = &pVM->aCpus[0];
3824
3825 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3826 if ( fSvmEnabled
3827 && pVM->cpum.ro.GuestFeatures.fSvm)
3828 {
3829 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3830 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3831 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3832 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3833 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3834 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3835 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3836 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3837 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3838 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3839 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3840 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3841 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3842 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3843 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3844 }
3845 else
3846 {
3847 if (!fSvmEnabled)
3848 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3849 else
3850 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3851 }
3852}
3853
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