VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 73293

Last change on this file since 73293 was 73293, checked in by vboxsync, 7 years ago

VMM, SUPDrv: Nested VMX: bugref:9180 Read VMX true control MSRs, dump them. Remove pVM->hm.cpuid as we for a long time now
have cpum.ro.HostFeatures available. Related cleanups and simplifications.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 173.6 KB
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1/* $Id: HM.cpp 73293 2018-07-21 15:11:53Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/pdmapi.h>
45#include <VBox/vmm/pgm.h>
46#include <VBox/vmm/ssm.h>
47#include <VBox/vmm/trpm.h>
48#include <VBox/vmm/dbgf.h>
49#include <VBox/vmm/iom.h>
50#include <VBox/vmm/iem.h>
51#include <VBox/vmm/patm.h>
52#include <VBox/vmm/csam.h>
53#include <VBox/vmm/selm.h>
54#include <VBox/vmm/nem.h>
55#ifdef VBOX_WITH_REM
56# include <VBox/vmm/rem.h>
57#endif
58#include <VBox/vmm/hm_vmx.h>
59#include <VBox/vmm/hm_svm.h>
60#include "HMInternal.h"
61#include <VBox/vmm/vm.h>
62#include <VBox/vmm/uvm.h>
63#include <VBox/err.h>
64#include <VBox/param.h>
65
66#include <iprt/assert.h>
67#include <VBox/log.h>
68#include <iprt/asm.h>
69#include <iprt/asm-amd64-x86.h>
70#include <iprt/env.h>
71#include <iprt/thread.h>
72
73
74/*********************************************************************************************************************************
75* Global Variables *
76*********************************************************************************************************************************/
77#define EXIT_REASON(def, val, str) #def " - " #val " - " str
78#define EXIT_REASON_NIL() NULL
79/** Exit reason descriptions for VT-x, used to describe statistics. */
80static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
81{
82 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
83 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
84 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
85 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
86 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
87 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
88 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
89 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
90 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
91 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
92 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
93 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
94 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
95 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
96 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
97 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
98 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
99 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
100 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
101 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
102 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
103 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
104 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
105 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
106 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
107 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
108 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
109 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
110 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
111 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
112 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
113 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
114 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
115 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
116 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
117 EXIT_REASON_NIL(),
118 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
119 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
122 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
123 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
124 EXIT_REASON_NIL(),
125 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
126 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
127 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
128 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
129 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
130 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
131 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
132 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
133 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
134 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
135 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
136 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
137 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
138 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
139 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
140 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
141 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
142 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
143 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
144 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
145 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
146 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
147};
148/** Array index of the last valid VT-x exit reason. */
149#define MAX_EXITREASON_VTX 64
150
151/** A partial list of Exit reason descriptions for AMD-V, used to describe
152 * statistics.
153 *
154 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
155 * this array doesn't contain the entire set of exit reasons, we
156 * handle them via hmSvmGetSpecialExitReasonDesc(). */
157static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
158{
159 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
160 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
161 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
162 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
163 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
164 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
165 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
166 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
167 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
168 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
169 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
170 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
171 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
172 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
173 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
174 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
190 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
191 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
192 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
193 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
194 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
195 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
196 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
197 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
198 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
199 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
200 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
201 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
202 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
203 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
204 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
205 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
206 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
222 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
223 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
224 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
225 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
226 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
227 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
228 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
229 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
230 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
231 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
232 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
233 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
234 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
235 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
236 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
237 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
238 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
239 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
240 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
241 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
242 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
243 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
244 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
245 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
246 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
247 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
248 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
249 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
250 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
251 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
252 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
253 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
254 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
255 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
256 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
257 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
258 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
259 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
260 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
261 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
262 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
263 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
264 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
265 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
266 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
267 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
268 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
269 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
270 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
271 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
272 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
273 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
274 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
275 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
276 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
277 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
278 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
279 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
280 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
281 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
282 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
283 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
284 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
285 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
286 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
287 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
288 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
289 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
290 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
291 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
292 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
293 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
294 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
295 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
296 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
297 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
298 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
299 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
300 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
301};
302/** Array index of the last valid AMD-V exit reason. */
303#define MAX_EXITREASON_AMDV 141
304
305/** Special exit reasons not covered in the array above. */
306#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
307#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
308#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
309
310/**
311 * Gets the SVM exit reason if it's one of the reasons not present in the @c
312 * g_apszAmdVExitReasons array.
313 *
314 * @returns The exit reason or NULL if unknown.
315 * @param uExit The exit.
316 */
317DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
318{
319 switch (uExit)
320 {
321 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
322 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
323 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
324 }
325 return EXIT_REASON_NIL();
326}
327#undef EXIT_REASON_NIL
328#undef EXIT_REASON
329
330/** @def HMVMX_REPORT_FEAT
331 * Reports VT-x feature to the release log.
332 *
333 * @param allowed1 Mask of allowed feature bits.
334 * @param disallowed0 Mask of disallowed feature bits.
335 * @param strdesc The description string to report.
336 * @param featflag Mask of the feature to report.
337 */
338#define HMVMX_REPORT_FEAT(allowed1, disallowed0, strdesc, featflag) \
339 do { \
340 if ((allowed1) & (featflag)) \
341 { \
342 if ((disallowed0) & (featflag)) \
343 LogRel(("HM: " strdesc " (must be set)\n")); \
344 else \
345 LogRel(("HM: " strdesc "\n")); \
346 } \
347 else \
348 LogRel(("HM: " strdesc " (must be cleared)\n")); \
349 } while (0)
350
351/** @def HMVMX_REPORT_ALLOWED_FEAT
352 * Reports an allowed VT-x feature to the release log.
353 *
354 * @param allowed1 Mask of allowed feature bits.
355 * @param strdesc The description string to report.
356 * @param featflag Mask of the feature to report.
357 */
358#define HMVMX_REPORT_ALLOWED_FEAT(allowed1, strdesc, featflag) \
359 do { \
360 if ((allowed1) & (featflag)) \
361 LogRel(("HM: " strdesc "\n")); \
362 else \
363 LogRel(("HM: " strdesc " not supported\n")); \
364 } while (0)
365
366/** @def HMVMX_REPORT_MSR_CAP
367 * Reports MSR feature capability.
368 *
369 * @param msrcaps Mask of MSR feature bits.
370 * @param strdesc The description string to report.
371 * @param cap Mask of the feature to report.
372 */
373#define HMVMX_REPORT_MSR_CAP(msrcaps, strdesc, cap) \
374 do { \
375 if ((msrcaps) & (cap)) \
376 LogRel(("HM: " strdesc "\n")); \
377 } while (0)
378
379/** @def HMVMX_LOGREL_FEAT
380 * Dumps a feature flag from a bitmap of features to the release log.
381 *
382 * @param a_fVal The value of all the features.
383 * @param a_fMask The specific bitmask of the feature.
384 */
385#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
386 do { \
387 if ((a_fVal) & (a_fMask)) \
388 LogRel(("HM: %s\n", #a_fMask)); \
389 } while (0)
390
391
392/*********************************************************************************************************************************
393* Internal Functions *
394*********************************************************************************************************************************/
395static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
396static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
397static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
398static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
399static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
400static int hmR3InitCPU(PVM pVM);
401static int hmR3InitFinalizeR0(PVM pVM);
402static int hmR3InitFinalizeR0Intel(PVM pVM);
403static int hmR3InitFinalizeR0Amd(PVM pVM);
404static int hmR3TermCPU(PVM pVM);
405
406
407
408/**
409 * Initializes the HM.
410 *
411 * This is the very first component to really do init after CFGM so that we can
412 * establish the predominat execution engine for the VM prior to initializing
413 * other modules. It takes care of NEM initialization if needed (HM disabled or
414 * not available in HW).
415 *
416 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
417 * hypervisor API via NEM, and then back on raw-mode if that isn't available
418 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
419 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
420 * X, OS/2 and others).
421 *
422 * Note that a lot of the set up work is done in ring-0 and thus postponed till
423 * the ring-3 and ring-0 callback to HMR3InitCompleted.
424 *
425 * @returns VBox status code.
426 * @param pVM The cross context VM structure.
427 *
428 * @remarks Be careful with what we call here, since most of the VMM components
429 * are uninitialized.
430 */
431VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
432{
433 LogFlow(("HMR3Init\n"));
434
435 /*
436 * Assert alignment and sizes.
437 */
438 AssertCompileMemberAlignment(VM, hm.s, 32);
439 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
440
441 /*
442 * Register the saved state data unit.
443 */
444 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
445 NULL, NULL, NULL,
446 NULL, hmR3Save, NULL,
447 NULL, hmR3Load, NULL);
448 if (RT_FAILURE(rc))
449 return rc;
450
451 /*
452 * Register info handlers.
453 */
454 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
455 AssertRCReturn(rc, rc);
456
457 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
458 DBGFINFO_FLAGS_ALL_EMTS);
459 AssertRCReturn(rc, rc);
460
461 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
462 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
463 AssertRCReturn(rc, rc);
464
465 /*
466 * Read configuration.
467 */
468 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
469
470 /*
471 * Validate the HM settings.
472 */
473 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
474 "HMForced"
475 "|UseNEMInstead"
476 "|FallbackToNEM"
477 "|EnableNestedPaging"
478 "|EnableUX"
479 "|EnableLargePages"
480 "|EnableVPID"
481 "|IBPBOnVMExit"
482 "|IBPBOnVMEntry"
483 "|SpecCtrlByHost"
484 "|TPRPatchingEnabled"
485 "|64bitEnabled"
486 "|Exclusive"
487 "|MaxResumeLoops"
488 "|VmxPleGap"
489 "|VmxPleWindow"
490 "|UseVmxPreemptTimer"
491 "|SvmPauseFilter"
492 "|SvmPauseFilterThreshold"
493 "|SvmVirtVmsaveVmload"
494 "|SvmVGif",
495 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
496 if (RT_FAILURE(rc))
497 return rc;
498
499 /** @cfgm{/HM/HMForced, bool, false}
500 * Forces hardware virtualization, no falling back on raw-mode. HM must be
501 * enabled, i.e. /HMEnabled must be true. */
502 bool fHMForced;
503#ifdef VBOX_WITH_RAW_MODE
504 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
505 AssertRCReturn(rc, rc);
506 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
507 VERR_INVALID_PARAMETER);
508# if defined(RT_OS_DARWIN)
509 if (pVM->fHMEnabled)
510 fHMForced = true;
511# endif
512 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
513 VERR_INVALID_PARAMETER);
514 if (pVM->cCpus > 1)
515 fHMForced = true;
516#else /* !VBOX_WITH_RAW_MODE */
517 AssertRelease(pVM->fHMEnabled);
518 fHMForced = true;
519#endif /* !VBOX_WITH_RAW_MODE */
520
521 /** @cfgm{/HM/UseNEMInstead, bool, true}
522 * Don't use HM, use NEM instead. */
523 bool fUseNEMInstead = false;
524 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
525 AssertRCReturn(rc, rc);
526 if (fUseNEMInstead && pVM->fHMEnabled)
527 {
528 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
529 pVM->fHMEnabled = false;
530 }
531
532 /** @cfgm{/HM/FallbackToNEM, bool, true}
533 * Enables fallback on NEM. */
534 bool fFallbackToNEM = true;
535 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
536 AssertRCReturn(rc, rc);
537
538 /** @cfgm{/HM/EnableNestedPaging, bool, false}
539 * Enables nested paging (aka extended page tables). */
540 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
541 AssertRCReturn(rc, rc);
542
543 /** @cfgm{/HM/EnableUX, bool, true}
544 * Enables the VT-x unrestricted execution feature. */
545 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
546 AssertRCReturn(rc, rc);
547
548 /** @cfgm{/HM/EnableLargePages, bool, false}
549 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
550 * page table walking and maybe better TLB hit rate in some cases. */
551 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
552 AssertRCReturn(rc, rc);
553
554 /** @cfgm{/HM/EnableVPID, bool, false}
555 * Enables the VT-x VPID feature. */
556 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
557 AssertRCReturn(rc, rc);
558
559 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
560 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
561 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
562 AssertRCReturn(rc, rc);
563
564 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
565 * Enables AMD64 cpu features.
566 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
567 * already have the support. */
568#ifdef VBOX_ENABLE_64_BITS_GUESTS
569 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
570 AssertLogRelRCReturn(rc, rc);
571#else
572 pVM->hm.s.fAllow64BitGuests = false;
573#endif
574
575 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
576 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
577 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
578 * latest PAUSE instruction to be start of a new PAUSE loop.
579 */
580 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
581 AssertRCReturn(rc, rc);
582
583 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
584 * The pause-filter exiting window in TSC ticks. When the number of ticks
585 * between the current PAUSE instruction and first PAUSE of a loop exceeds
586 * VmxPleWindow, a VM-exit is triggered.
587 *
588 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
589 */
590 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
591 AssertRCReturn(rc, rc);
592
593 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
594 * A counter that is decrement each time a PAUSE instruction is executed by the
595 * guest. When the counter is 0, a \#VMEXIT is triggered.
596 *
597 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
598 */
599 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
600 AssertRCReturn(rc, rc);
601
602 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
603 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
604 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
605 * PauseFilter count is reset to its initial value. However, if PAUSE is
606 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
607 * be triggered.
608 *
609 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
610 * activated.
611 */
612 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
613 AssertRCReturn(rc, rc);
614
615 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
616 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
617 * available. */
618 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
619 AssertRCReturn(rc, rc);
620
621 /** @cfgm{/HM/SvmVGif, bool, true}
622 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
623 * if it's available. */
624 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
625 AssertRCReturn(rc, rc);
626
627 /** @cfgm{/HM/Exclusive, bool}
628 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
629 * global init for each host CPU. If false, we do local init each time we wish
630 * to execute guest code.
631 *
632 * On Windows, default is false due to the higher risk of conflicts with other
633 * hypervisors.
634 *
635 * On Mac OS X, this setting is ignored since the code does not handle local
636 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
637 */
638#if defined(RT_OS_DARWIN)
639 pVM->hm.s.fGlobalInit = true;
640#else
641 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
642# if defined(RT_OS_WINDOWS)
643 false
644# else
645 true
646# endif
647 );
648 AssertLogRelRCReturn(rc, rc);
649#endif
650
651 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
652 * The number of times to resume guest execution before we forcibly return to
653 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
654 * determines the default value. */
655 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
656 AssertLogRelRCReturn(rc, rc);
657
658 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
659 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
660 * available. */
661 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
662 AssertLogRelRCReturn(rc, rc);
663
664 /** @cfgm{/HM/IBPBOnVMExit, bool}
665 * Costly paranoia setting. */
666 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
667 AssertLogRelRCReturn(rc, rc);
668
669 /** @cfgm{/HM/IBPBOnVMEntry, bool}
670 * Costly paranoia setting. */
671 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
672 AssertLogRelRCReturn(rc, rc);
673
674 /** @cfgm{/HM/SpecCtrlByHost, bool}
675 * Another expensive paranoia setting. */
676 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
677 AssertLogRelRCReturn(rc, rc);
678
679 /*
680 * Check if VT-x or AMD-v support according to the users wishes.
681 */
682 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
683 * VERR_SVM_IN_USE. */
684 if (pVM->fHMEnabled)
685 {
686 uint32_t fCaps;
687 rc = SUPR3QueryVTCaps(&fCaps);
688 if (RT_SUCCESS(rc))
689 {
690 if (fCaps & SUPVTCAPS_AMD_V)
691 {
692 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
693 pVM->hm.s.svm.fSupported = true;
694 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
695 }
696 else if (fCaps & SUPVTCAPS_VT_X)
697 {
698 const char *pszWhy;
699 rc = SUPR3QueryVTxSupported(&pszWhy);
700 if (RT_SUCCESS(rc))
701 {
702 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
703 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
704 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
705 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
706 pVM->hm.s.vmx.fSupported = true;
707 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
708 }
709 else
710 {
711 /*
712 * Before failing, try fallback to NEM if we're allowed to do that.
713 */
714 pVM->fHMEnabled = false;
715 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
716 if (fFallbackToNEM)
717 {
718 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
719 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
720
721 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
722 if ( RT_SUCCESS(rc2)
723 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
724 rc = VINF_SUCCESS;
725 }
726 if (RT_FAILURE(rc))
727 {
728 if (fHMForced)
729 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
730
731 /* Fall back to raw-mode. */
732 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
733 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
734 }
735 }
736 }
737 else
738 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
739 VERR_INTERNAL_ERROR_5);
740
741 /*
742 * Do we require a little bit or raw-mode for 64-bit guest execution?
743 */
744 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
745 && pVM->fHMEnabled
746 && pVM->hm.s.fAllow64BitGuests;
747
748 /*
749 * Disable nested paging and unrestricted guest execution now if they're
750 * configured so that CPUM can make decisions based on our configuration.
751 */
752 Assert(!pVM->hm.s.fNestedPaging);
753 if (pVM->hm.s.fAllowNestedPaging)
754 {
755 if (fCaps & SUPVTCAPS_NESTED_PAGING)
756 pVM->hm.s.fNestedPaging = true;
757 else
758 pVM->hm.s.fAllowNestedPaging = false;
759 }
760
761 if (fCaps & SUPVTCAPS_VT_X)
762 {
763 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
764 if (pVM->hm.s.vmx.fAllowUnrestricted)
765 {
766 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
767 && pVM->hm.s.fNestedPaging)
768 pVM->hm.s.vmx.fUnrestrictedGuest = true;
769 else
770 pVM->hm.s.vmx.fAllowUnrestricted = false;
771 }
772 }
773 }
774 else
775 {
776 const char *pszMsg;
777 switch (rc)
778 {
779 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
780 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
781 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
782 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
783 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
784 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
785 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
786 default:
787 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
788 }
789
790 /*
791 * Before failing, try fallback to NEM if we're allowed to do that.
792 */
793 pVM->fHMEnabled = false;
794 if (fFallbackToNEM)
795 {
796 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
797 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
798 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
799 if ( RT_SUCCESS(rc2)
800 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
801 rc = VINF_SUCCESS;
802 }
803 if (RT_FAILURE(rc))
804 {
805 if (fHMForced)
806 return VM_SET_ERROR(pVM, rc, pszMsg);
807
808 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
809 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
810 }
811 }
812 }
813 else
814 {
815 /*
816 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
817 */
818 if (!fUseNEMInstead)
819 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
820 else
821 {
822 rc = NEMR3Init(pVM, false /*fFallback*/, true);
823 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
824 if (RT_FAILURE(rc))
825 return rc;
826 }
827 }
828
829 return VINF_SUCCESS;
830}
831
832
833/**
834 * Initializes the per-VCPU HM.
835 *
836 * @returns VBox status code.
837 * @param pVM The cross context VM structure.
838 */
839static int hmR3InitCPU(PVM pVM)
840{
841 LogFlow(("HMR3InitCPU\n"));
842
843 if (!HMIsEnabled(pVM))
844 return VINF_SUCCESS;
845
846 for (VMCPUID i = 0; i < pVM->cCpus; i++)
847 {
848 PVMCPU pVCpu = &pVM->aCpus[i];
849 pVCpu->hm.s.fActive = false;
850 }
851
852#ifdef VBOX_WITH_STATISTICS
853 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
854 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
855 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
856 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
857 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
858#endif
859
860 /*
861 * Statistics.
862 */
863 for (VMCPUID i = 0; i < pVM->cCpus; i++)
864 {
865 PVMCPU pVCpu = &pVM->aCpus[i];
866 int rc;
867
868#ifdef VBOX_WITH_STATISTICS
869 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
870 "Profiling of RTMpPokeCpu.",
871 "/PROF/CPU%d/HM/Poke", i);
872 AssertRC(rc);
873 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
874 "Profiling of poke wait.",
875 "/PROF/CPU%d/HM/PokeWait", i);
876 AssertRC(rc);
877 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
878 "Profiling of poke wait when RTMpPokeCpu fails.",
879 "/PROF/CPU%d/HM/PokeWaitFailed", i);
880 AssertRC(rc);
881 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
882 "Profiling of entry until entering GC.",
883 "/PROF/CPU%d/HM/Entry", i);
884 AssertRC(rc);
885 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
886 "Profiling of pre-exit processing after returning from GC.",
887 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
888 AssertRC(rc);
889 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
890 "Profiling of exit handling (longjmps not included!)",
891 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
892 AssertRC(rc);
893
894 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
895 "I/O.",
896 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
897 AssertRC(rc);
898 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
899 "MOV CRx.",
900 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
901 AssertRC(rc);
902 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
903 "Exceptions, NMIs.",
904 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
905 AssertRC(rc);
906
907 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
908 "Profiling of importing guest state from hardware after VM-exit.",
909 "/PROF/CPU%d/HM/ImportGuestState", i);
910 AssertRC(rc);
911 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
912 "Profiling of exporting guest state to hardware before VM-entry.",
913 "/PROF/CPU%d/HM/ExportGuestState", i);
914 AssertRC(rc);
915 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
916 "Profiling of CPUMR0LoadGuestFPU.",
917 "/PROF/CPU%d/HM/LoadGuestFpuState", i);
918 AssertRC(rc);
919 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
920 "Profiling of execution of guest-code in hardware.",
921 "/PROF/CPU%d/HM/InGC", i);
922 AssertRC(rc);
923
924# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
925 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
926 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
927 "/PROF/CPU%d/HM/Switcher3264", i);
928 AssertRC(rc);
929# endif
930
931# ifdef HM_PROFILE_EXIT_DISPATCH
932 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
933 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
934 "/PROF/CPU%d/HM/ExitDispatch", i);
935 AssertRC(rc);
936# endif
937
938#endif
939# define HM_REG_COUNTER(a, b, desc) \
940 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
941 AssertRC(rc);
942
943#ifdef VBOX_WITH_STATISTICS
944 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
945 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
946 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
948 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
949 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
950 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
951 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
952 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
953 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
954 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
955 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
956 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
957 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
968 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
970 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
972 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
974 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
976 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
977 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
980 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
981 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
986 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
987 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
988 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
989 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
990 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
991 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
992#endif
993 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
994#ifdef VBOX_WITH_STATISTICS
995 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
996 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
997 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
999 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
1000
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
1002 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
1004 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
1006 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
1008 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
1010#endif
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
1012#ifdef VBOX_WITH_STATISTICS
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptExportHostState, "/HM/CPU%d/Switch/ExportHostState", "Preemption caused us to re-export the host state.");
1014
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
1016 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
1018 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
1019
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
1021 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
1022 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1024 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1026 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1028 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1030 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1031 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1033 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1034
1035 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1036 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1037 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1038
1039 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1040 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1041 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1042
1043 HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
1044 HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
1045 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
1046
1047 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1048 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1049 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1050 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1051 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1052 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
1053 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
1054 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1055
1056#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1057 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1058 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1059#endif
1060
1061#undef HM_REG_COUNTER
1062
1063 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVTxExitReasons[0]
1064 : &g_apszAmdVExitReasons[0];
1065
1066 /*
1067 * Guest Exit reason stats.
1068 */
1069 pVCpu->hm.s.paStatExitReason = NULL;
1070 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1071 (void **)&pVCpu->hm.s.paStatExitReason);
1072 AssertRCReturn(rc, rc);
1073 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1074 {
1075 if (papszDesc[j])
1076 {
1077 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1078 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1079 AssertRCReturn(rc, rc);
1080 }
1081 }
1082 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1083 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1084 AssertRCReturn(rc, rc);
1085 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1086# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1087 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1088# else
1089 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1090# endif
1091
1092#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1093 /*
1094 * Nested-guest Exit reason stats.
1095 */
1096 pVCpu->hm.s.paStatNestedExitReason = NULL;
1097 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1098 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1099 AssertRCReturn(rc, rc);
1100 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1101 {
1102 if (papszDesc[j])
1103 {
1104 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1105 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1106 AssertRC(rc);
1107 }
1108 }
1109 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1110 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1111 AssertRCReturn(rc, rc);
1112 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1113# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1114 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1115# else
1116 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1117# endif
1118#endif
1119
1120 /*
1121 * Injected events stats.
1122 */
1123 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1124 AssertRCReturn(rc, rc);
1125 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1126# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1127 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1128# else
1129 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1130# endif
1131 for (unsigned j = 0; j < 255; j++)
1132 {
1133 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1134 "Injected event.",
1135 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1136 }
1137
1138#endif /* VBOX_WITH_STATISTICS */
1139 }
1140
1141#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1142 /*
1143 * Magic marker for searching in crash dumps.
1144 */
1145 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1146 {
1147 PVMCPU pVCpu = &pVM->aCpus[i];
1148
1149 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1150 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1151 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
1152 }
1153#endif
1154
1155 return VINF_SUCCESS;
1156}
1157
1158
1159/**
1160 * Called when a init phase has completed.
1161 *
1162 * @returns VBox status code.
1163 * @param pVM The cross context VM structure.
1164 * @param enmWhat The phase that completed.
1165 */
1166VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1167{
1168 switch (enmWhat)
1169 {
1170 case VMINITCOMPLETED_RING3:
1171 return hmR3InitCPU(pVM);
1172 case VMINITCOMPLETED_RING0:
1173 return hmR3InitFinalizeR0(pVM);
1174 default:
1175 return VINF_SUCCESS;
1176 }
1177}
1178
1179
1180/**
1181 * Turns off normal raw mode features.
1182 *
1183 * @param pVM The cross context VM structure.
1184 */
1185static void hmR3DisableRawMode(PVM pVM)
1186{
1187/** @todo r=bird: HM shouldn't be doing this crap. */
1188 /* Reinit the paging mode to force the new shadow mode. */
1189 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1190 {
1191 PVMCPU pVCpu = &pVM->aCpus[i];
1192 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1193 }
1194}
1195
1196
1197/**
1198 * Initialize VT-x or AMD-V.
1199 *
1200 * @returns VBox status code.
1201 * @param pVM The cross context VM structure.
1202 */
1203static int hmR3InitFinalizeR0(PVM pVM)
1204{
1205 int rc;
1206
1207 if (!HMIsEnabled(pVM))
1208 return VINF_SUCCESS;
1209
1210 /*
1211 * Hack to allow users to work around broken BIOSes that incorrectly set
1212 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1213 */
1214 if ( !pVM->hm.s.vmx.fSupported
1215 && !pVM->hm.s.svm.fSupported
1216 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1217 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1218 {
1219 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1220 pVM->hm.s.svm.fSupported = true;
1221 pVM->hm.s.svm.fIgnoreInUseError = true;
1222 pVM->hm.s.rcInit = VINF_SUCCESS;
1223 }
1224
1225 /*
1226 * Report ring-0 init errors.
1227 */
1228 if ( !pVM->hm.s.vmx.fSupported
1229 && !pVM->hm.s.svm.fSupported)
1230 {
1231 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1232 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1233 switch (pVM->hm.s.rcInit)
1234 {
1235 case VERR_VMX_IN_VMX_ROOT_MODE:
1236 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1237 case VERR_VMX_NO_VMX:
1238 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1239 case VERR_VMX_MSR_VMX_DISABLED:
1240 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1241 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1242 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1243 case VERR_VMX_MSR_LOCKING_FAILED:
1244 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1245 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1246 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1247 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1248 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1249
1250 case VERR_SVM_IN_USE:
1251 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1252 case VERR_SVM_NO_SVM:
1253 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1254 case VERR_SVM_DISABLED:
1255 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1256 }
1257 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1258 }
1259
1260 /*
1261 * Enable VT-x or AMD-V on all host CPUs.
1262 */
1263 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1264 if (RT_FAILURE(rc))
1265 {
1266 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1267 HMR3CheckError(pVM, rc);
1268 return rc;
1269 }
1270
1271 /*
1272 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1273 * (Main should have taken care of this already)
1274 */
1275 if (!PDMHasIoApic(pVM))
1276 {
1277 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1278 pVM->hm.s.fTprPatchingAllowed = false;
1279 }
1280
1281 /*
1282 * Sync options.
1283 */
1284 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1285 * That will require a little bit of work, of course. */
1286 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1287 {
1288 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1289 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1290 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1291 if (pVM->cpum.ro.HostFeatures.fIbpb)
1292 {
1293 if (pVM->hm.s.fIbpbOnVmExit)
1294 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1295 if (pVM->hm.s.fIbpbOnVmEntry)
1296 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1297 }
1298 if (iCpu == 0)
1299 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1300 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1301 }
1302
1303 /*
1304 * Do the vendor specific initialization
1305 *
1306 * Note! We disable release log buffering here since we're doing relatively
1307 * lot of logging and doesn't want to hit the disk with each LogRel
1308 * statement.
1309 */
1310 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1311 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1312 if (pVM->hm.s.vmx.fSupported)
1313 rc = hmR3InitFinalizeR0Intel(pVM);
1314 else
1315 rc = hmR3InitFinalizeR0Amd(pVM);
1316 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1317 RTLogRelSetBuffering(fOldBuffered);
1318 pVM->hm.s.fInitialized = true;
1319
1320 return rc;
1321}
1322
1323
1324/**
1325 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1326 */
1327static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1328{
1329 NOREF(pVM);
1330 NOREF(pvAllocation);
1331 NOREF(GCPhysAllocation);
1332}
1333
1334
1335/**
1336 * Returns the VMCS (and associated regions') memory type given the IA32_VMX_BASIC
1337 * MSR.
1338 *
1339 * @returns The descriptive memory type.
1340 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1341 */
1342static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1343{
1344 uint8_t const uMemType = MSR_IA32_VMX_BASIC_VMCS_MEM_TYPE(uMsrVmxBasic);
1345 switch (uMemType)
1346 {
1347 case VMX_VMCS_MEM_TYPE_WB: return "Write Back (WB)";
1348 case VMX_VMCS_MEM_TYPE_UC: return "Uncacheable (UC)";
1349 }
1350 return "Unknown";
1351}
1352
1353
1354/**
1355 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1356 *
1357 * @param fFeatMsr The feature control MSR value.
1358 */
1359static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1360{
1361 uint64_t const val = fFeatMsr;
1362 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1363 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1364 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1365 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1366 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1367 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1368 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1369 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1370 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1371 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1372 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1373 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1374 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1375 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1376 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1377 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1378 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1379}
1380
1381
1382/**
1383 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1384 *
1385 * @param uBasicMsr The VMX basic MSR value.
1386 */
1387static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1388{
1389 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1390 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_VMCS_ID(uBasicMsr)));
1391 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_VMCS_SIZE(uBasicMsr)));
1392 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_VMCS_PHYS_WIDTH(uBasicMsr) ? "< 4 GB"
1393 : "None"));
1394 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1395 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_DUAL_MON(uBasicMsr)));
1396 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_VMCS_INS_OUTS(uBasicMsr)));
1397 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_TRUE_CONTROLS(uBasicMsr)));
1398}
1399
1400
1401/**
1402 * Reports MSR_IA32_PINBASED_CTLS to the log.
1403 *
1404 * @param pVmxMsr Pointer to the VMX MSR.
1405 */
1406static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1407{
1408 uint64_t const val = pVmxMsr->n.allowed1;
1409 uint64_t const zap = pVmxMsr->n.disallowed0;
1410 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1411 HMVMX_REPORT_FEAT(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1412 HMVMX_REPORT_FEAT(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1413 HMVMX_REPORT_FEAT(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1414 HMVMX_REPORT_FEAT(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1415 HMVMX_REPORT_FEAT(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1416}
1417
1418
1419/**
1420 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1421 *
1422 * @param pVmxMsr Pointer to the VMX MSR.
1423 */
1424static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1425{
1426 uint64_t const val = pVmxMsr->n.allowed1;
1427 uint64_t const zap = pVmxMsr->n.disallowed0;
1428 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1429 HMVMX_REPORT_FEAT(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1430 HMVMX_REPORT_FEAT(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1431 HMVMX_REPORT_FEAT(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1432 HMVMX_REPORT_FEAT(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1433 HMVMX_REPORT_FEAT(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1434 HMVMX_REPORT_FEAT(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1435 HMVMX_REPORT_FEAT(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1436 HMVMX_REPORT_FEAT(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1437 HMVMX_REPORT_FEAT(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1438 HMVMX_REPORT_FEAT(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1439 HMVMX_REPORT_FEAT(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1440 HMVMX_REPORT_FEAT(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1441 HMVMX_REPORT_FEAT(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1442 HMVMX_REPORT_FEAT(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1443 HMVMX_REPORT_FEAT(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1444 HMVMX_REPORT_FEAT(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1445 HMVMX_REPORT_FEAT(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1446 HMVMX_REPORT_FEAT(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1447 HMVMX_REPORT_FEAT(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1448 HMVMX_REPORT_FEAT(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1449 HMVMX_REPORT_FEAT(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1450}
1451
1452
1453/**
1454 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1455 *
1456 * @param pVmxMsr Pointer to the VMX MSR.
1457 */
1458static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1459{
1460 uint64_t const val = pVmxMsr->n.allowed1;
1461 uint64_t const zap = pVmxMsr->n.disallowed0;
1462 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1463 HMVMX_REPORT_FEAT(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1464 HMVMX_REPORT_FEAT(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1465 HMVMX_REPORT_FEAT(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1466 HMVMX_REPORT_FEAT(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1467 HMVMX_REPORT_FEAT(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1468 HMVMX_REPORT_FEAT(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1469 HMVMX_REPORT_FEAT(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1470 HMVMX_REPORT_FEAT(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1471 HMVMX_REPORT_FEAT(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1472 HMVMX_REPORT_FEAT(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1473 HMVMX_REPORT_FEAT(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1474 HMVMX_REPORT_FEAT(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1475 HMVMX_REPORT_FEAT(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1476 HMVMX_REPORT_FEAT(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1477 HMVMX_REPORT_FEAT(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1478 HMVMX_REPORT_FEAT(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1479 HMVMX_REPORT_FEAT(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1480 HMVMX_REPORT_FEAT(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1481 HMVMX_REPORT_FEAT(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1482 HMVMX_REPORT_FEAT(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1483 HMVMX_REPORT_FEAT(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1484 HMVMX_REPORT_FEAT(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1485}
1486
1487
1488/**
1489 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1490 *
1491 * @param pVmxMsr Pointer to the VMX MSR.
1492 */
1493static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1494{
1495 uint64_t const val = pVmxMsr->n.allowed1;
1496 uint64_t const zap = pVmxMsr->n.disallowed0;
1497 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1498 HMVMX_REPORT_FEAT(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1499 HMVMX_REPORT_FEAT(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1500 HMVMX_REPORT_FEAT(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1501 HMVMX_REPORT_FEAT(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1502 HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1503 HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1504 HMVMX_REPORT_FEAT(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1505}
1506
1507
1508/**
1509 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1510 *
1511 * @param pVmxMsr Pointer to the VMX MSR.
1512 */
1513static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1514{
1515 uint64_t const val = pVmxMsr->n.allowed1;
1516 uint64_t const zap = pVmxMsr->n.disallowed0;
1517 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1518 HMVMX_REPORT_FEAT(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1519 HMVMX_REPORT_FEAT(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1520 HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1521 HMVMX_REPORT_FEAT(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1522 HMVMX_REPORT_FEAT(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1523 HMVMX_REPORT_FEAT(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1524 HMVMX_REPORT_FEAT(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1525 HMVMX_REPORT_FEAT(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1526 HMVMX_REPORT_FEAT(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1527}
1528
1529
1530/**
1531 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1532 *
1533 * @param fCaps The VMX EPT/VPID capability MSR value.
1534 */
1535static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1536{
1537 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1538 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1539 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1540 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1541 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1542 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1543 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1544 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1545 HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1546 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1547 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1548 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1549 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1550 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1551 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1552 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1553}
1554
1555
1556/**
1557 * Reports MSR_IA32_VMX_MISC MSR to the log.
1558 *
1559 * @param fMisc The VMX misc. MSR value.
1560 */
1561static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1562{
1563 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1564 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(fMisc) == pVM->hm.s.vmx.cPreemptTimerShift)
1565 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(fMisc)));
1566 else
1567 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1568 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(fMisc), pVM->hm.s.vmx.cPreemptTimerShift));
1569 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(fMisc)));
1570 uint8_t const fActivityState = MSR_IA32_VMX_MISC_ACTIVITY_STATES(fMisc);
1571 LogRel(("HM: ACTIVITY_STATES = %#x\n", fActivityState));
1572 HMVMX_REPORT_MSR_CAP(fActivityState, " HLT", VMX_VMCS_GUEST_ACTIVITY_HLT);
1573 HMVMX_REPORT_MSR_CAP(fActivityState, " SHUTDOWN", VMX_VMCS_GUEST_ACTIVITY_SHUTDOWN);
1574 HMVMX_REPORT_MSR_CAP(fActivityState, " SIPI_WAIT", VMX_VMCS_GUEST_ACTIVITY_SIPI_WAIT);
1575 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(fMisc)));
1576 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(fMisc)));
1577 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(fMisc)));
1578 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(fMisc)));
1579 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(fMisc)));
1580 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(fMisc)));
1581}
1582
1583
1584/**
1585 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1586 *
1587 * @param uVmcsEnum The VMX VMCS enum MSR value.
1588 */
1589static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1590{
1591 uint64_t const val = uVmcsEnum;
1592 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1593 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1594}
1595
1596
1597/**
1598 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1599 *
1600 * @param uVmFunc The VMX VMFUNC MSR value.
1601 */
1602static void hmR3VmxReportVmfuncMsr(uint64_t uVmFunc)
1603{
1604 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1605 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1606}
1607
1608
1609/**
1610 * Reports VMX CR0, CR4 fixed MSRs.
1611 *
1612 * @param pMsrs Pointer to the VMX MSRs.
1613 */
1614static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1615{
1616 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1617 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1618 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1619 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1620}
1621
1622
1623/**
1624 * Finish VT-x initialization (after ring-0 init).
1625 *
1626 * @returns VBox status code.
1627 * @param pVM The cross context VM structure.
1628 */
1629static int hmR3InitFinalizeR0Intel(PVM pVM)
1630{
1631 int rc;
1632
1633 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1634 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1635
1636 LogRel(("HM: Using VT-x implementation 2.0\n"));
1637 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1638 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1639 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1640 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1641
1642 hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1643 hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1644
1645 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1646 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1647 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1648 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1649
1650 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1651 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1652
1653 if (MSR_IA32_VMX_BASIC_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64Basic))
1654 {
1655 /* We don't do extensive dumping of the true capability MSRs as we don't use them yet. */
1656 /** @todo Consider using true capability MSRs and dumping them extensively. */
1657 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1658 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1659 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1660 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1661 }
1662
1663 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1664 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1665 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1666 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1667 if (pVM->hm.s.vmx.Msrs.u64Vmfunc)
1668 hmR3VmxReportVmfuncMsr(pVM->hm.s.vmx.Msrs.u64Vmfunc);
1669 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1670
1671 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1672 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1673 {
1674 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1675 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1676 }
1677
1678 /*
1679 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1680 */
1681 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1682 || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1683 VERR_HM_IPE_1);
1684 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1685 || ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1686 && pVM->hm.s.fNestedPaging),
1687 VERR_HM_IPE_1);
1688
1689 /*
1690 * Enable VPID if configured and supported.
1691 */
1692 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1693 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1694
1695#if 0
1696 /*
1697 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1698 */
1699 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1700 && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1701 pVM->hm.s.fVirtApicRegs = true;
1702
1703 /*
1704 * Enable posted-interrupt processing if supported.
1705 */
1706 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1707 * here. */
1708 if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1709 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1710 pVM->hm.s.fPostedIntrs = true;
1711#endif
1712
1713 /*
1714 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1715 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1716 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1717 */
1718 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1719 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1720 {
1721 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1722 LogRel(("HM: Disabled RDTSCP\n"));
1723 }
1724
1725 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1726 {
1727 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1728 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1729 if (RT_SUCCESS(rc))
1730 {
1731 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1732 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1733 esp. Figure 20-5.*/
1734 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1735 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1736
1737 /* Bit set to 0 means software interrupts are redirected to the
1738 8086 program interrupt handler rather than switching to
1739 protected-mode handler. */
1740 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1741
1742 /* Allow all port IO, so that port IO instructions do not cause
1743 exceptions and would instead cause a VM-exit (based on VT-x's
1744 IO bitmap which we currently configure to always cause an exit). */
1745 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1746 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1747
1748 /*
1749 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1750 * page table used in real and protected mode without paging with EPT.
1751 */
1752 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1753 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1754 {
1755 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1756 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1757 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1758 | X86_PDE4M_G;
1759 }
1760
1761 /* We convert it here every time as PCI regions could be reconfigured. */
1762 if (PDMVmmDevHeapIsEnabled(pVM))
1763 {
1764 RTGCPHYS GCPhys;
1765 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1766 AssertRCReturn(rc, rc);
1767 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1768
1769 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1770 AssertRCReturn(rc, rc);
1771 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1772 }
1773 }
1774 else
1775 {
1776 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1777 pVM->hm.s.vmx.pRealModeTSS = NULL;
1778 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1779 return VMSetError(pVM, rc, RT_SRC_POS,
1780 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1781 }
1782 }
1783
1784 LogRel((pVM->hm.s.fAllow64BitGuests
1785 ? "HM: Guest support: 32-bit and 64-bit\n"
1786 : "HM: Guest support: 32-bit only\n"));
1787
1788 /*
1789 * Call ring-0 to set up the VM.
1790 */
1791 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1792 if (rc != VINF_SUCCESS)
1793 {
1794 AssertMsgFailed(("%Rrc\n", rc));
1795 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1796 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1797 {
1798 PVMCPU pVCpu = &pVM->aCpus[i];
1799 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1800 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1801 }
1802 HMR3CheckError(pVM, rc);
1803 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1804 }
1805
1806 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1807 LogRel(("HM: Enabled VMX\n"));
1808 pVM->hm.s.vmx.fEnabled = true;
1809
1810 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1811
1812 /*
1813 * Change the CPU features.
1814 */
1815 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1816 if (pVM->hm.s.fAllow64BitGuests)
1817 {
1818 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1819 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1820 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1821 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1822 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1823 }
1824 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1825 (we reuse the host EFER in the switcher). */
1826 /** @todo this needs to be fixed properly!! */
1827 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1828 {
1829 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1830 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1831 else
1832 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1833 }
1834
1835 /*
1836 * Log configuration details.
1837 */
1838 if (pVM->hm.s.fNestedPaging)
1839 {
1840 LogRel(("HM: Enabled nested paging\n"));
1841 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1842 LogRel(("HM: EPT flush type = Single context\n"));
1843 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1844 LogRel(("HM: EPT flush type = All contexts\n"));
1845 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1846 LogRel(("HM: EPT flush type = Not supported\n"));
1847 else
1848 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1849
1850 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1851 LogRel(("HM: Enabled unrestricted guest execution\n"));
1852
1853#if HC_ARCH_BITS == 64
1854 if (pVM->hm.s.fLargePages)
1855 {
1856 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1857 PGMSetLargePageUsage(pVM, true);
1858 LogRel(("HM: Enabled large page support\n"));
1859 }
1860#endif
1861 }
1862 else
1863 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1864
1865 if (pVM->hm.s.fVirtApicRegs)
1866 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1867
1868 if (pVM->hm.s.fPostedIntrs)
1869 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1870
1871 if (pVM->hm.s.vmx.fVpid)
1872 {
1873 LogRel(("HM: Enabled VPID\n"));
1874 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1875 LogRel(("HM: VPID flush type = Individual addresses\n"));
1876 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1877 LogRel(("HM: VPID flush type = Single context\n"));
1878 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1879 LogRel(("HM: VPID flush type = All contexts\n"));
1880 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1881 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1882 else
1883 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1884 }
1885 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1886 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1887
1888 if (pVM->hm.s.vmx.fUsePreemptTimer)
1889 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1890 else
1891 LogRel(("HM: Disabled VMX-preemption timer\n"));
1892
1893 return VINF_SUCCESS;
1894}
1895
1896
1897/**
1898 * Finish AMD-V initialization (after ring-0 init).
1899 *
1900 * @returns VBox status code.
1901 * @param pVM The cross context VM structure.
1902 */
1903static int hmR3InitFinalizeR0Amd(PVM pVM)
1904{
1905 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1906
1907 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1908
1909 uint32_t u32Family;
1910 uint32_t u32Model;
1911 uint32_t u32Stepping;
1912 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1913 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1914 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1915 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1916 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1917 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1918 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1919
1920 /*
1921 * Enumerate AMD-V features.
1922 */
1923 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1924 {
1925#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1926 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1927 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1928 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1929 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1930 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1931 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1932 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1933 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1934 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1935 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1936 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1937 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1938 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1939#undef HMSVM_REPORT_FEATURE
1940 };
1941
1942 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1943 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1944 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1945 {
1946 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1947 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1948 }
1949 if (fSvmFeatures)
1950 for (unsigned iBit = 0; iBit < 32; iBit++)
1951 if (RT_BIT_32(iBit) & fSvmFeatures)
1952 LogRel(("HM: Reserved bit %u\n", iBit));
1953
1954 /*
1955 * Nested paging is determined in HMR3Init, verify the sanity of that.
1956 */
1957 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1958 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1959 VERR_HM_IPE_1);
1960
1961#if 0
1962 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1963 * here. */
1964 if (RTR0IsPostIpiSupport())
1965 pVM->hm.s.fPostedIntrs = true;
1966#endif
1967
1968 /*
1969 * Call ring-0 to set up the VM.
1970 */
1971 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1972 if (rc != VINF_SUCCESS)
1973 {
1974 AssertMsgFailed(("%Rrc\n", rc));
1975 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1976 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1977 }
1978
1979 LogRel(("HM: Enabled SVM\n"));
1980 pVM->hm.s.svm.fEnabled = true;
1981
1982 if (pVM->hm.s.fNestedPaging)
1983 {
1984 LogRel(("HM: Enabled nested paging\n"));
1985
1986 /*
1987 * Enable large pages (2 MB) if applicable.
1988 */
1989#if HC_ARCH_BITS == 64
1990 if (pVM->hm.s.fLargePages)
1991 {
1992 PGMSetLargePageUsage(pVM, true);
1993 LogRel(("HM: Enabled large page support\n"));
1994 }
1995#endif
1996 }
1997
1998 if (pVM->hm.s.fVirtApicRegs)
1999 LogRel(("HM: Enabled APIC-register virtualization support\n"));
2000
2001 if (pVM->hm.s.fPostedIntrs)
2002 LogRel(("HM: Enabled posted-interrupt processing support\n"));
2003
2004 hmR3DisableRawMode(pVM);
2005
2006 /*
2007 * Change the CPU features.
2008 */
2009 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
2010 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
2011 if (pVM->hm.s.fAllow64BitGuests)
2012 {
2013 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
2014 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
2015 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2016 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
2017 }
2018 /* Turn on NXE if PAE has been enabled. */
2019 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
2020 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2021
2022 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
2023
2024 LogRel((pVM->hm.s.fAllow64BitGuests
2025 ? "HM: Guest support: 32-bit and 64-bit\n"
2026 : "HM: Guest support: 32-bit only\n"));
2027
2028 return VINF_SUCCESS;
2029}
2030
2031
2032/**
2033 * Applies relocations to data and code managed by this
2034 * component. This function will be called at init and
2035 * whenever the VMM need to relocate it self inside the GC.
2036 *
2037 * @param pVM The cross context VM structure.
2038 */
2039VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2040{
2041 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
2042
2043 /* Fetch the current paging mode during the relocate callback during state loading. */
2044 if (VMR3GetState(pVM) == VMSTATE_LOADING)
2045 {
2046 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2047 {
2048 PVMCPU pVCpu = &pVM->aCpus[i];
2049 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2050 }
2051 }
2052#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
2053 if (HMIsEnabled(pVM))
2054 {
2055 switch (PGMGetHostMode(pVM))
2056 {
2057 case PGMMODE_32_BIT:
2058 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
2059 break;
2060
2061 case PGMMODE_PAE:
2062 case PGMMODE_PAE_NX:
2063 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
2064 break;
2065
2066 default:
2067 AssertFailed();
2068 break;
2069 }
2070 }
2071#endif
2072 return;
2073}
2074
2075
2076/**
2077 * Terminates the HM.
2078 *
2079 * Termination means cleaning up and freeing all resources,
2080 * the VM itself is, at this point, powered off or suspended.
2081 *
2082 * @returns VBox status code.
2083 * @param pVM The cross context VM structure.
2084 */
2085VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2086{
2087 if (pVM->hm.s.vmx.pRealModeTSS)
2088 {
2089 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2090 pVM->hm.s.vmx.pRealModeTSS = 0;
2091 }
2092 hmR3TermCPU(pVM);
2093 return 0;
2094}
2095
2096
2097/**
2098 * Terminates the per-VCPU HM.
2099 *
2100 * @returns VBox status code.
2101 * @param pVM The cross context VM structure.
2102 */
2103static int hmR3TermCPU(PVM pVM)
2104{
2105 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2106 {
2107 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2108
2109#ifdef VBOX_WITH_STATISTICS
2110 if (pVCpu->hm.s.paStatExitReason)
2111 {
2112 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2113 pVCpu->hm.s.paStatExitReason = NULL;
2114 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2115 }
2116 if (pVCpu->hm.s.paStatInjectedIrqs)
2117 {
2118 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2119 pVCpu->hm.s.paStatInjectedIrqs = NULL;
2120 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2121 }
2122#endif
2123
2124#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2125 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
2126 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
2127 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
2128#endif
2129 }
2130 return 0;
2131}
2132
2133
2134/**
2135 * Resets a virtual CPU.
2136 *
2137 * Used by HMR3Reset and CPU hot plugging.
2138 *
2139 * @param pVCpu The cross context virtual CPU structure to reset.
2140 */
2141VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2142{
2143 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2144 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2145 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2146
2147 pVCpu->hm.s.fActive = false;
2148 pVCpu->hm.s.Event.fPending = false;
2149 pVCpu->hm.s.vmx.fWasInRealMode = true;
2150 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2151 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2152
2153 /* Reset the contents of the read cache. */
2154 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2155 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2156 pCache->Read.aFieldVal[j] = 0;
2157
2158#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2159 /* Magic marker for searching in crash dumps. */
2160 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2161 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2162#endif
2163}
2164
2165
2166/**
2167 * The VM is being reset.
2168 *
2169 * For the HM component this means that any GDT/LDT/TSS monitors
2170 * needs to be removed.
2171 *
2172 * @param pVM The cross context VM structure.
2173 */
2174VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2175{
2176 LogFlow(("HMR3Reset:\n"));
2177
2178 if (HMIsEnabled(pVM))
2179 hmR3DisableRawMode(pVM);
2180
2181 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2182 {
2183 PVMCPU pVCpu = &pVM->aCpus[i];
2184
2185 HMR3ResetCpu(pVCpu);
2186 }
2187
2188 /* Clear all patch information. */
2189 pVM->hm.s.pGuestPatchMem = 0;
2190 pVM->hm.s.pFreeGuestPatchMem = 0;
2191 pVM->hm.s.cbGuestPatchMem = 0;
2192 pVM->hm.s.cPatches = 0;
2193 pVM->hm.s.PatchTree = 0;
2194 pVM->hm.s.fTPRPatchingActive = false;
2195 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2196}
2197
2198
2199/**
2200 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2201 *
2202 * @returns VBox strict status code.
2203 * @param pVM The cross context VM structure.
2204 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2205 * @param pvUser Unused.
2206 */
2207static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2208{
2209 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2210
2211 /* Only execute the handler on the VCPU the original patch request was issued. */
2212 if (pVCpu->idCpu != idCpu)
2213 return VINF_SUCCESS;
2214
2215 Log(("hmR3RemovePatches\n"));
2216 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2217 {
2218 uint8_t abInstr[15];
2219 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2220 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2221 int rc;
2222
2223#ifdef LOG_ENABLED
2224 char szOutput[256];
2225 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2226 szOutput, sizeof(szOutput), NULL);
2227 if (RT_SUCCESS(rc))
2228 Log(("Patched instr: %s\n", szOutput));
2229#endif
2230
2231 /* Check if the instruction is still the same. */
2232 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2233 if (rc != VINF_SUCCESS)
2234 {
2235 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2236 continue; /* swapped out or otherwise removed; skip it. */
2237 }
2238
2239 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2240 {
2241 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2242 continue; /* skip it. */
2243 }
2244
2245 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2246 AssertRC(rc);
2247
2248#ifdef LOG_ENABLED
2249 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2250 szOutput, sizeof(szOutput), NULL);
2251 if (RT_SUCCESS(rc))
2252 Log(("Original instr: %s\n", szOutput));
2253#endif
2254 }
2255 pVM->hm.s.cPatches = 0;
2256 pVM->hm.s.PatchTree = 0;
2257 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2258 pVM->hm.s.fTPRPatchingActive = false;
2259 return VINF_SUCCESS;
2260}
2261
2262
2263/**
2264 * Worker for enabling patching in a VT-x/AMD-V guest.
2265 *
2266 * @returns VBox status code.
2267 * @param pVM The cross context VM structure.
2268 * @param idCpu VCPU to execute hmR3RemovePatches on.
2269 * @param pPatchMem Patch memory range.
2270 * @param cbPatchMem Size of the memory range.
2271 */
2272static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2273{
2274 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2275 AssertRC(rc);
2276
2277 pVM->hm.s.pGuestPatchMem = pPatchMem;
2278 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2279 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2280 return VINF_SUCCESS;
2281}
2282
2283
2284/**
2285 * Enable patching in a VT-x/AMD-V guest
2286 *
2287 * @returns VBox status code.
2288 * @param pVM The cross context VM structure.
2289 * @param pPatchMem Patch memory range.
2290 * @param cbPatchMem Size of the memory range.
2291 */
2292VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2293{
2294 VM_ASSERT_EMT(pVM);
2295 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2296 if (pVM->cCpus > 1)
2297 {
2298 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2299 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2300 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2301 AssertRC(rc);
2302 return rc;
2303 }
2304 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2305}
2306
2307
2308/**
2309 * Disable patching in a VT-x/AMD-V guest.
2310 *
2311 * @returns VBox status code.
2312 * @param pVM The cross context VM structure.
2313 * @param pPatchMem Patch memory range.
2314 * @param cbPatchMem Size of the memory range.
2315 */
2316VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2317{
2318 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2319 RT_NOREF2(pPatchMem, cbPatchMem);
2320
2321 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2322 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2323
2324 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2325 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2326 (void *)(uintptr_t)VMMGetCpuId(pVM));
2327 AssertRC(rc);
2328
2329 pVM->hm.s.pGuestPatchMem = 0;
2330 pVM->hm.s.pFreeGuestPatchMem = 0;
2331 pVM->hm.s.cbGuestPatchMem = 0;
2332 pVM->hm.s.fTPRPatchingActive = false;
2333 return VINF_SUCCESS;
2334}
2335
2336
2337/**
2338 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2339 *
2340 * @returns VBox strict status code.
2341 * @param pVM The cross context VM structure.
2342 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2343 * @param pvUser User specified CPU context.
2344 *
2345 */
2346static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2347{
2348 /*
2349 * Only execute the handler on the VCPU the original patch request was
2350 * issued. (The other CPU(s) might not yet have switched to protected
2351 * mode, nor have the correct memory context.)
2352 */
2353 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2354 if (pVCpu->idCpu != idCpu)
2355 return VINF_SUCCESS;
2356
2357 /*
2358 * We're racing other VCPUs here, so don't try patch the instruction twice
2359 * and make sure there is still room for our patch record.
2360 */
2361 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2362 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2363 if (pPatch)
2364 {
2365 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2366 return VINF_SUCCESS;
2367 }
2368 uint32_t const idx = pVM->hm.s.cPatches;
2369 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2370 {
2371 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2372 return VINF_SUCCESS;
2373 }
2374 pPatch = &pVM->hm.s.aPatches[idx];
2375
2376 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2377
2378 /*
2379 * Disassembler the instruction and get cracking.
2380 */
2381 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2382 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2383 uint32_t cbOp;
2384 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2385 AssertRC(rc);
2386 if ( rc == VINF_SUCCESS
2387 && pDis->pCurInstr->uOpcode == OP_MOV
2388 && cbOp >= 3)
2389 {
2390 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2391
2392 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2393 AssertRC(rc);
2394
2395 pPatch->cbOp = cbOp;
2396
2397 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2398 {
2399 /* write. */
2400 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2401 {
2402 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2403 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2404 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2405 }
2406 else
2407 {
2408 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2409 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2410 pPatch->uSrcOperand = pDis->Param2.uValue;
2411 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2412 }
2413 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2414 AssertRC(rc);
2415
2416 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2417 pPatch->cbNewOp = sizeof(s_abVMMCall);
2418 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2419 }
2420 else
2421 {
2422 /*
2423 * TPR Read.
2424 *
2425 * Found:
2426 * mov eax, dword [fffe0080] (5 bytes)
2427 * Check if next instruction is:
2428 * shr eax, 4
2429 */
2430 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2431
2432 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2433 uint8_t const cbOpMmio = cbOp;
2434 uint64_t const uSavedRip = pCtx->rip;
2435
2436 pCtx->rip += cbOp;
2437 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2438 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2439 pCtx->rip = uSavedRip;
2440
2441 if ( rc == VINF_SUCCESS
2442 && pDis->pCurInstr->uOpcode == OP_SHR
2443 && pDis->Param1.fUse == DISUSE_REG_GEN32
2444 && pDis->Param1.Base.idxGenReg == idxMmioReg
2445 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2446 && pDis->Param2.uValue == 4
2447 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2448 {
2449 uint8_t abInstr[15];
2450
2451 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2452 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2453 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2454 AssertRC(rc);
2455
2456 pPatch->cbOp = cbOpMmio + cbOp;
2457
2458 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2459 abInstr[0] = 0xf0;
2460 abInstr[1] = 0x0f;
2461 abInstr[2] = 0x20;
2462 abInstr[3] = 0xc0 | pDis->Param1.Base.idxGenReg;
2463 for (unsigned i = 4; i < pPatch->cbOp; i++)
2464 abInstr[i] = 0x90; /* nop */
2465
2466 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2467 AssertRC(rc);
2468
2469 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2470 pPatch->cbNewOp = pPatch->cbOp;
2471 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2472
2473 Log(("Acceptable read/shr candidate!\n"));
2474 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2475 }
2476 else
2477 {
2478 pPatch->enmType = HMTPRINSTR_READ;
2479 pPatch->uDstOperand = idxMmioReg;
2480
2481 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2482 AssertRC(rc);
2483
2484 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2485 pPatch->cbNewOp = sizeof(s_abVMMCall);
2486 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2487 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2488 }
2489 }
2490
2491 pPatch->Core.Key = pCtx->eip;
2492 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2493 AssertRC(rc);
2494
2495 pVM->hm.s.cPatches++;
2496 return VINF_SUCCESS;
2497 }
2498
2499 /*
2500 * Save invalid patch, so we will not try again.
2501 */
2502 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2503 pPatch->Core.Key = pCtx->eip;
2504 pPatch->enmType = HMTPRINSTR_INVALID;
2505 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2506 AssertRC(rc);
2507 pVM->hm.s.cPatches++;
2508 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2509 return VINF_SUCCESS;
2510}
2511
2512
2513/**
2514 * Callback to patch a TPR instruction (jump to generated code).
2515 *
2516 * @returns VBox strict status code.
2517 * @param pVM The cross context VM structure.
2518 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2519 * @param pvUser User specified CPU context.
2520 *
2521 */
2522static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2523{
2524 /*
2525 * Only execute the handler on the VCPU the original patch request was
2526 * issued. (The other CPU(s) might not yet have switched to protected
2527 * mode, nor have the correct memory context.)
2528 */
2529 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2530 if (pVCpu->idCpu != idCpu)
2531 return VINF_SUCCESS;
2532
2533 /*
2534 * We're racing other VCPUs here, so don't try patch the instruction twice
2535 * and make sure there is still room for our patch record.
2536 */
2537 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2538 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2539 if (pPatch)
2540 {
2541 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2542 return VINF_SUCCESS;
2543 }
2544 uint32_t const idx = pVM->hm.s.cPatches;
2545 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2546 {
2547 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2548 return VINF_SUCCESS;
2549 }
2550 pPatch = &pVM->hm.s.aPatches[idx];
2551
2552 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2553 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2554
2555 /*
2556 * Disassemble the instruction and get cracking.
2557 */
2558 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2559 uint32_t cbOp;
2560 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2561 AssertRC(rc);
2562 if ( rc == VINF_SUCCESS
2563 && pDis->pCurInstr->uOpcode == OP_MOV
2564 && cbOp >= 5)
2565 {
2566 uint8_t aPatch[64];
2567 uint32_t off = 0;
2568
2569 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2570 AssertRC(rc);
2571
2572 pPatch->cbOp = cbOp;
2573 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2574
2575 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2576 {
2577 /*
2578 * TPR write:
2579 *
2580 * push ECX [51]
2581 * push EDX [52]
2582 * push EAX [50]
2583 * xor EDX,EDX [31 D2]
2584 * mov EAX,EAX [89 C0]
2585 * or
2586 * mov EAX,0000000CCh [B8 CC 00 00 00]
2587 * mov ECX,0C0000082h [B9 82 00 00 C0]
2588 * wrmsr [0F 30]
2589 * pop EAX [58]
2590 * pop EDX [5A]
2591 * pop ECX [59]
2592 * jmp return_address [E9 return_address]
2593 */
2594 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2595
2596 aPatch[off++] = 0x51; /* push ecx */
2597 aPatch[off++] = 0x52; /* push edx */
2598 if (!fUsesEax)
2599 aPatch[off++] = 0x50; /* push eax */
2600 aPatch[off++] = 0x31; /* xor edx, edx */
2601 aPatch[off++] = 0xd2;
2602 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2603 {
2604 if (!fUsesEax)
2605 {
2606 aPatch[off++] = 0x89; /* mov eax, src_reg */
2607 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2608 }
2609 }
2610 else
2611 {
2612 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2613 aPatch[off++] = 0xb8; /* mov eax, immediate */
2614 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2615 off += sizeof(uint32_t);
2616 }
2617 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2618 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2619 off += sizeof(uint32_t);
2620
2621 aPatch[off++] = 0x0f; /* wrmsr */
2622 aPatch[off++] = 0x30;
2623 if (!fUsesEax)
2624 aPatch[off++] = 0x58; /* pop eax */
2625 aPatch[off++] = 0x5a; /* pop edx */
2626 aPatch[off++] = 0x59; /* pop ecx */
2627 }
2628 else
2629 {
2630 /*
2631 * TPR read:
2632 *
2633 * push ECX [51]
2634 * push EDX [52]
2635 * push EAX [50]
2636 * mov ECX,0C0000082h [B9 82 00 00 C0]
2637 * rdmsr [0F 32]
2638 * mov EAX,EAX [89 C0]
2639 * pop EAX [58]
2640 * pop EDX [5A]
2641 * pop ECX [59]
2642 * jmp return_address [E9 return_address]
2643 */
2644 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2645
2646 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2647 aPatch[off++] = 0x51; /* push ecx */
2648 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2649 aPatch[off++] = 0x52; /* push edx */
2650 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2651 aPatch[off++] = 0x50; /* push eax */
2652
2653 aPatch[off++] = 0x31; /* xor edx, edx */
2654 aPatch[off++] = 0xd2;
2655
2656 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2657 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2658 off += sizeof(uint32_t);
2659
2660 aPatch[off++] = 0x0f; /* rdmsr */
2661 aPatch[off++] = 0x32;
2662
2663 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2664 {
2665 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2666 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2667 }
2668
2669 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2670 aPatch[off++] = 0x58; /* pop eax */
2671 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2672 aPatch[off++] = 0x5a; /* pop edx */
2673 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2674 aPatch[off++] = 0x59; /* pop ecx */
2675 }
2676 aPatch[off++] = 0xe9; /* jmp return_address */
2677 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2678 off += sizeof(RTRCUINTPTR);
2679
2680 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2681 {
2682 /* Write new code to the patch buffer. */
2683 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2684 AssertRC(rc);
2685
2686#ifdef LOG_ENABLED
2687 uint32_t cbCurInstr;
2688 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2689 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2690 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2691 {
2692 char szOutput[256];
2693 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2694 szOutput, sizeof(szOutput), &cbCurInstr);
2695 if (RT_SUCCESS(rc))
2696 Log(("Patch instr %s\n", szOutput));
2697 else
2698 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2699 }
2700#endif
2701
2702 pPatch->aNewOpcode[0] = 0xE9;
2703 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2704
2705 /* Overwrite the TPR instruction with a jump. */
2706 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2707 AssertRC(rc);
2708
2709 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2710
2711 pVM->hm.s.pFreeGuestPatchMem += off;
2712 pPatch->cbNewOp = 5;
2713
2714 pPatch->Core.Key = pCtx->eip;
2715 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2716 AssertRC(rc);
2717
2718 pVM->hm.s.cPatches++;
2719 pVM->hm.s.fTPRPatchingActive = true;
2720 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2721 return VINF_SUCCESS;
2722 }
2723
2724 Log(("Ran out of space in our patch buffer!\n"));
2725 }
2726 else
2727 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2728
2729
2730 /*
2731 * Save invalid patch, so we will not try again.
2732 */
2733 pPatch = &pVM->hm.s.aPatches[idx];
2734 pPatch->Core.Key = pCtx->eip;
2735 pPatch->enmType = HMTPRINSTR_INVALID;
2736 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2737 AssertRC(rc);
2738 pVM->hm.s.cPatches++;
2739 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2740 return VINF_SUCCESS;
2741}
2742
2743
2744/**
2745 * Attempt to patch TPR mmio instructions.
2746 *
2747 * @returns VBox status code.
2748 * @param pVM The cross context VM structure.
2749 * @param pVCpu The cross context virtual CPU structure.
2750 */
2751VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2752{
2753 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2754 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2755 (void *)(uintptr_t)pVCpu->idCpu);
2756 AssertRC(rc);
2757 return rc;
2758}
2759
2760
2761/**
2762 * Checks if a code selector (CS) is suitable for execution
2763 * within VMX when unrestricted execution isn't available.
2764 *
2765 * @returns true if selector is suitable for VMX, otherwise
2766 * false.
2767 * @param pSel Pointer to the selector to check (CS).
2768 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2769 */
2770static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2771{
2772 /*
2773 * Segment must be an accessed code segment, it must be present and it must
2774 * be usable.
2775 * Note! These are all standard requirements and if CS holds anything else
2776 * we've got buggy code somewhere!
2777 */
2778 AssertCompile(X86DESCATTR_TYPE == 0xf);
2779 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2780 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2781 ("%#x\n", pSel->Attr.u),
2782 false);
2783
2784 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2785 must equal SS.DPL for non-confroming segments.
2786 Note! This is also a hard requirement like above. */
2787 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2788 ? pSel->Attr.n.u2Dpl <= uStackDpl
2789 : pSel->Attr.n.u2Dpl == uStackDpl,
2790 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2791 false);
2792
2793 /*
2794 * The following two requirements are VT-x specific:
2795 * - G bit must be set if any high limit bits are set.
2796 * - G bit must be clear if any low limit bits are clear.
2797 */
2798 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2799 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity))
2800 return true;
2801 return false;
2802}
2803
2804
2805/**
2806 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2807 * execution within VMX when unrestricted execution isn't
2808 * available.
2809 *
2810 * @returns true if selector is suitable for VMX, otherwise
2811 * false.
2812 * @param pSel Pointer to the selector to check
2813 * (DS/ES/FS/GS).
2814 */
2815static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2816{
2817 /*
2818 * Unusable segments are OK. These days they should be marked as such, as
2819 * but as an alternative we for old saved states and AMD<->VT-x migration
2820 * we also treat segments with all the attributes cleared as unusable.
2821 */
2822 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2823 return true;
2824
2825 /** @todo tighten these checks. Will require CPUM load adjusting. */
2826
2827 /* Segment must be accessed. */
2828 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2829 {
2830 /* Code segments must also be readable. */
2831 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2832 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2833 {
2834 /* The S bit must be set. */
2835 if (pSel->Attr.n.u1DescType)
2836 {
2837 /* Except for conforming segments, DPL >= RPL. */
2838 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2839 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2840 {
2841 /* Segment must be present. */
2842 if (pSel->Attr.n.u1Present)
2843 {
2844 /*
2845 * The following two requirements are VT-x specific:
2846 * - G bit must be set if any high limit bits are set.
2847 * - G bit must be clear if any low limit bits are clear.
2848 */
2849 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2850 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity))
2851 return true;
2852 }
2853 }
2854 }
2855 }
2856 }
2857
2858 return false;
2859}
2860
2861
2862/**
2863 * Checks if the stack selector (SS) is suitable for execution
2864 * within VMX when unrestricted execution isn't available.
2865 *
2866 * @returns true if selector is suitable for VMX, otherwise
2867 * false.
2868 * @param pSel Pointer to the selector to check (SS).
2869 */
2870static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2871{
2872 /*
2873 * Unusable segments are OK. These days they should be marked as such, as
2874 * but as an alternative we for old saved states and AMD<->VT-x migration
2875 * we also treat segments with all the attributes cleared as unusable.
2876 */
2877 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2878 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2879 return true;
2880
2881 /*
2882 * Segment must be an accessed writable segment, it must be present.
2883 * Note! These are all standard requirements and if SS holds anything else
2884 * we've got buggy code somewhere!
2885 */
2886 AssertCompile(X86DESCATTR_TYPE == 0xf);
2887 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2888 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2889 ("%#x\n", pSel->Attr.u), false);
2890
2891 /* DPL must equal RPL.
2892 Note! This is also a hard requirement like above. */
2893 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2894 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel), false);
2895
2896 /*
2897 * The following two requirements are VT-x specific:
2898 * - G bit must be set if any high limit bits are set.
2899 * - G bit must be clear if any low limit bits are clear.
2900 */
2901 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2902 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity))
2903 return true;
2904 return false;
2905}
2906
2907
2908/**
2909 * Checks if we can currently use hardware accelerated raw mode.
2910 *
2911 * @returns true if we can currently use hardware acceleration, otherwise false.
2912 * @param pVM The cross context VM structure.
2913 * @param pCtx Partial VM execution context.
2914 */
2915VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2916{
2917 PVMCPU pVCpu = VMMGetCpu(pVM);
2918
2919 Assert(HMIsEnabled(pVM));
2920
2921#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
2922 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
2923 {
2924 Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
2925 return false;
2926 }
2927#endif
2928
2929 /* AMD-V supports real & protected mode with or without paging. */
2930 if (pVM->hm.s.svm.fEnabled)
2931 {
2932 pVCpu->hm.s.fActive = true;
2933 return true;
2934 }
2935
2936 pVCpu->hm.s.fActive = false;
2937
2938 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2939 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2940 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2941
2942 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2943 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2944 {
2945 /*
2946 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2947 * guest execution feature is missing (VT-x only).
2948 */
2949 if (fSupportsRealMode)
2950 {
2951 if (CPUMIsGuestInRealModeEx(pCtx))
2952 {
2953 /*
2954 * In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2955 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2956 * If this is not true, we cannot execute real mode as V86 and have to fall
2957 * back to emulation.
2958 */
2959 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2960 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2961 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2962 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2963 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2964 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2965 {
2966 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2967 return false;
2968 }
2969 if ( (pCtx->cs.u32Limit != 0xffff)
2970 || (pCtx->ds.u32Limit != 0xffff)
2971 || (pCtx->es.u32Limit != 0xffff)
2972 || (pCtx->ss.u32Limit != 0xffff)
2973 || (pCtx->fs.u32Limit != 0xffff)
2974 || (pCtx->gs.u32Limit != 0xffff))
2975 {
2976 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2977 return false;
2978 }
2979 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2980 }
2981 else
2982 {
2983 /*
2984 * Verify the requirements for executing code in protected mode. VT-x can't
2985 * handle the CPU state right after a switch from real to protected mode
2986 * (all sorts of RPL & DPL assumptions).
2987 */
2988 if (pVCpu->hm.s.vmx.fWasInRealMode)
2989 {
2990 /** @todo If guest is in V86 mode, these checks should be different! */
2991 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2992 {
2993 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2994 return false;
2995 }
2996 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2997 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2998 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2999 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
3000 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
3001 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
3002 {
3003 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
3004 return false;
3005 }
3006 }
3007 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
3008 if (pCtx->gdtr.cbGdt)
3009 {
3010 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
3011 {
3012 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
3013 return false;
3014 }
3015 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
3016 {
3017 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
3018 return false;
3019 }
3020 }
3021 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
3022 }
3023 }
3024 else
3025 {
3026 if ( !CPUMIsGuestInLongModeEx(pCtx)
3027 && !pVM->hm.s.vmx.fUnrestrictedGuest)
3028 {
3029 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
3030 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
3031 return false;
3032
3033 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
3034 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
3035 return false;
3036
3037 /*
3038 * The guest is about to complete the switch to protected mode. Wait a bit longer.
3039 * Windows XP; switch to protected mode; all selectors are marked not present
3040 * in the hidden registers (possible recompiler bug; see load_seg_vm).
3041 */
3042 /** @todo Is this supposed recompiler bug still relevant with IEM? */
3043 if (pCtx->cs.Attr.n.u1Present == 0)
3044 return false;
3045 if (pCtx->ss.Attr.n.u1Present == 0)
3046 return false;
3047
3048 /*
3049 * Windows XP: possible same as above, but new recompiler requires new
3050 * heuristics? VT-x doesn't seem to like something about the guest state and
3051 * this stuff avoids it.
3052 */
3053 /** @todo This check is actually wrong, it doesn't take the direction of the
3054 * stack segment into account. But, it does the job for now. */
3055 if (pCtx->rsp >= pCtx->ss.u32Limit)
3056 return false;
3057 }
3058 }
3059 }
3060
3061 if (pVM->hm.s.vmx.fEnabled)
3062 {
3063 uint32_t uCR0Mask;
3064
3065 /* If bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
3066 uCR0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
3067
3068 /* We ignore the NE bit here on purpose; see HMR0.cpp for details. */
3069 uCR0Mask &= ~X86_CR0_NE;
3070
3071 if (fSupportsRealMode)
3072 {
3073 /* We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
3074 uCR0Mask &= ~(X86_CR0_PG|X86_CR0_PE);
3075 }
3076 else
3077 {
3078 /* We support protected mode without paging using identity mapping. */
3079 uCR0Mask &= ~X86_CR0_PG;
3080 }
3081 if ((pCtx->cr0 & uCR0Mask) != uCR0Mask)
3082 return false;
3083
3084 /* If bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
3085 uCR0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
3086 if ((pCtx->cr0 & uCR0Mask) != 0)
3087 return false;
3088
3089 /* If bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
3090 uCR0Mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
3091 uCR0Mask &= ~X86_CR4_VMXE;
3092 if ((pCtx->cr4 & uCR0Mask) != uCR0Mask)
3093 return false;
3094
3095 /* If bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
3096 uCR0Mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
3097 if ((pCtx->cr4 & uCR0Mask) != 0)
3098 return false;
3099
3100 pVCpu->hm.s.fActive = true;
3101 return true;
3102 }
3103
3104 return false;
3105}
3106
3107
3108/**
3109 * Checks if we need to reschedule due to VMM device heap changes.
3110 *
3111 * @returns true if a reschedule is required, otherwise false.
3112 * @param pVM The cross context VM structure.
3113 * @param pCtx VM execution context.
3114 */
3115VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
3116{
3117 /*
3118 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
3119 * when the unrestricted guest execution feature is missing (VT-x only).
3120 */
3121 if ( pVM->hm.s.vmx.fEnabled
3122 && !pVM->hm.s.vmx.fUnrestrictedGuest
3123 && CPUMIsGuestInRealModeEx(pCtx)
3124 && !PDMVmmDevHeapIsEnabled(pVM))
3125 {
3126 return true;
3127 }
3128
3129 return false;
3130}
3131
3132
3133/**
3134 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
3135 * event settings changes.
3136 *
3137 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
3138 * function is just updating the VM globals.
3139 *
3140 * @param pVM The VM cross context VM structure.
3141 * @thread EMT(0)
3142 */
3143VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
3144{
3145 /* Interrupts. */
3146 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
3147 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
3148
3149 /* CPU Exceptions. */
3150 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
3151 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
3152 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3153 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3154
3155 /* Common VM exits. */
3156 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
3157 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
3158 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3159 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3160
3161 /* Vendor specific VM exits. */
3162 if (HMR3IsVmxEnabled(pVM->pUVM))
3163 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
3164 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
3165 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3166 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3167 else
3168 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
3169 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
3170 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3171 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3172
3173 /* Done. */
3174 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
3175}
3176
3177
3178/**
3179 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
3180 *
3181 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
3182 * per CPU settings.
3183 *
3184 * @param pVM The VM cross context VM structure.
3185 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3186 */
3187VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
3188{
3189 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
3190}
3191
3192
3193/**
3194 * Checks if we are currently using hardware acceleration.
3195 *
3196 * @returns true if hardware acceleration is being used, otherwise false.
3197 * @param pVCpu The cross context virtual CPU structure.
3198 */
3199VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
3200{
3201 return pVCpu->hm.s.fActive;
3202}
3203
3204
3205/**
3206 * External interface for querying whether hardware acceleration is enabled.
3207 *
3208 * @returns true if VT-x or AMD-V is being used, otherwise false.
3209 * @param pUVM The user mode VM handle.
3210 * @sa HMIsEnabled, HMIsEnabledNotMacro.
3211 */
3212VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
3213{
3214 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3215 PVM pVM = pUVM->pVM;
3216 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3217 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
3218}
3219
3220
3221/**
3222 * External interface for querying whether VT-x is being used.
3223 *
3224 * @returns true if VT-x is being used, otherwise false.
3225 * @param pUVM The user mode VM handle.
3226 * @sa HMR3IsSvmEnabled, HMIsEnabled
3227 */
3228VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3229{
3230 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3231 PVM pVM = pUVM->pVM;
3232 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3233 return pVM->hm.s.vmx.fEnabled
3234 && pVM->hm.s.vmx.fSupported
3235 && pVM->fHMEnabled;
3236}
3237
3238
3239/**
3240 * External interface for querying whether AMD-V is being used.
3241 *
3242 * @returns true if VT-x is being used, otherwise false.
3243 * @param pUVM The user mode VM handle.
3244 * @sa HMR3IsVmxEnabled, HMIsEnabled
3245 */
3246VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3247{
3248 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3249 PVM pVM = pUVM->pVM;
3250 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3251 return pVM->hm.s.svm.fEnabled
3252 && pVM->hm.s.svm.fSupported
3253 && pVM->fHMEnabled;
3254}
3255
3256
3257/**
3258 * Checks if we are currently using nested paging.
3259 *
3260 * @returns true if nested paging is being used, otherwise false.
3261 * @param pUVM The user mode VM handle.
3262 */
3263VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3264{
3265 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3266 PVM pVM = pUVM->pVM;
3267 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3268 return pVM->hm.s.fNestedPaging;
3269}
3270
3271
3272/**
3273 * Checks if virtualized APIC registers is enabled.
3274 *
3275 * When enabled this feature allows the hardware to access most of the
3276 * APIC registers in the virtual-APIC page without causing VM-exits. See
3277 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3278 *
3279 * @returns true if virtualized APIC registers is enabled, otherwise
3280 * false.
3281 * @param pUVM The user mode VM handle.
3282 */
3283VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3284{
3285 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3286 PVM pVM = pUVM->pVM;
3287 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3288 return pVM->hm.s.fVirtApicRegs;
3289}
3290
3291
3292/**
3293 * Checks if APIC posted-interrupt processing is enabled.
3294 *
3295 * This returns whether we can deliver interrupts to the guest without
3296 * leaving guest-context by updating APIC state from host-context.
3297 *
3298 * @returns true if APIC posted-interrupt processing is enabled,
3299 * otherwise false.
3300 * @param pUVM The user mode VM handle.
3301 */
3302VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3303{
3304 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3305 PVM pVM = pUVM->pVM;
3306 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3307 return pVM->hm.s.fPostedIntrs;
3308}
3309
3310
3311/**
3312 * Checks if we are currently using VPID in VT-x mode.
3313 *
3314 * @returns true if VPID is being used, otherwise false.
3315 * @param pUVM The user mode VM handle.
3316 */
3317VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3318{
3319 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3320 PVM pVM = pUVM->pVM;
3321 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3322 return pVM->hm.s.vmx.fVpid;
3323}
3324
3325
3326/**
3327 * Checks if we are currently using VT-x unrestricted execution,
3328 * aka UX.
3329 *
3330 * @returns true if UX is being used, otherwise false.
3331 * @param pUVM The user mode VM handle.
3332 */
3333VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3334{
3335 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3336 PVM pVM = pUVM->pVM;
3337 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3338 return pVM->hm.s.vmx.fUnrestrictedGuest
3339 || pVM->hm.s.svm.fSupported;
3340}
3341
3342
3343/**
3344 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3345 *
3346 * @returns true if an internal event is pending, otherwise false.
3347 * @param pVCpu The cross context virtual CPU structure.
3348 */
3349VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3350{
3351 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3352}
3353
3354
3355/**
3356 * Checks if the VMX-preemption timer is being used.
3357 *
3358 * @returns true if the VMX-preemption timer is being used, otherwise false.
3359 * @param pVM The cross context VM structure.
3360 */
3361VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3362{
3363 return HMIsEnabled(pVM)
3364 && pVM->hm.s.vmx.fEnabled
3365 && pVM->hm.s.vmx.fUsePreemptTimer;
3366}
3367
3368
3369/**
3370 * Check fatal VT-x/AMD-V error and produce some meaningful
3371 * log release message.
3372 *
3373 * @param pVM The cross context VM structure.
3374 * @param iStatusCode VBox status code.
3375 */
3376VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3377{
3378 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3379 {
3380 PVMCPU pVCpu = &pVM->aCpus[i];
3381 switch (iStatusCode)
3382 {
3383 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3384 * might be getting inaccurate values for non-guru'ing EMTs. */
3385 case VERR_VMX_INVALID_VMCS_FIELD:
3386 break;
3387
3388 case VERR_VMX_INVALID_VMCS_PTR:
3389 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3390 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3391 pVCpu->hm.s.vmx.HCPhysVmcs));
3392 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3393 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3394 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3395 break;
3396
3397 case VERR_VMX_UNABLE_TO_START_VM:
3398 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3399 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3400 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3401
3402 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3403 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3404 {
3405 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3406 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3407 }
3408 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3409 {
3410 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3411 {
3412 uint32_t const u32Val = pVCpu->hm.s.vmx.u32PinCtls;
3413 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT );
3414 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT );
3415 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI );
3416 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
3417 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR );
3418 }
3419 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3420 {
3421 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls;
3422 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT );
3423 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
3424 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT );
3425 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT );
3426 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT );
3427 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT );
3428 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT );
3429 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT );
3430 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT );
3431 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT );
3432 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT );
3433 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW );
3434 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT );
3435 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT );
3436 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT );
3437 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS );
3438 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG );
3439 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS );
3440 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT );
3441 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT );
3442 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
3443 }
3444 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3445 {
3446 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls2;
3447 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC );
3448 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_EPT );
3449 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
3450 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP );
3451 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC );
3452 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VPID );
3453 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT );
3454 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST );
3455 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT );
3456 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY );
3457 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT );
3458 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT );
3459 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID );
3460 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC );
3461 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING );
3462 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT );
3463 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT );
3464 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_PML );
3465 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE );
3466 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT );
3467 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS );
3468 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING );
3469 }
3470 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3471 {
3472 uint32_t const u32Val = pVCpu->hm.s.vmx.u32EntryCtls;
3473 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG );
3474 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST );
3475 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM );
3476 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON );
3477 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
3478 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR );
3479 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
3480 }
3481 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3482 {
3483 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ExitCtls;
3484 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG );
3485 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE );
3486 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR );
3487 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT );
3488 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR );
3489 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR );
3490 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR );
3491 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR );
3492 HMVMX_LOGREL_FEAT(u32Val, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
3493 }
3494 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3495 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3496 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3497 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3498 }
3499 /** @todo Log VM-entry event injection control fields
3500 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3501 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3502 break;
3503
3504 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3505 case VERR_VMX_INVALID_VMXON_PTR:
3506 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3507 case VERR_VMX_INVALID_GUEST_STATE:
3508 case VERR_VMX_UNEXPECTED_EXIT:
3509 case VERR_SVM_UNKNOWN_EXIT:
3510 case VERR_SVM_UNEXPECTED_EXIT:
3511 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3512 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3513 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3514 break;
3515 }
3516 }
3517
3518 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3519 {
3520 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3521 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.disallowed0));
3522 }
3523 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3524 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3525}
3526
3527
3528/**
3529 * Execute state save operation.
3530 *
3531 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3532 * is because we always save the VM state from ring-3 and thus most HM state
3533 * will be re-synced dynamically at runtime and don't need to be part of the VM
3534 * saved state.
3535 *
3536 * @returns VBox status code.
3537 * @param pVM The cross context VM structure.
3538 * @param pSSM SSM operation handle.
3539 */
3540static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3541{
3542 int rc;
3543
3544 Log(("hmR3Save:\n"));
3545
3546 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3547 {
3548 Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3549 if (pVM->cpum.ro.GuestFeatures.fSvm)
3550 {
3551 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3552 rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3553 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3554 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3555 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3556 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3557 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3558 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3559 rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3560 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3561 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3562 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3563 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3564 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3565 AssertRCReturn(rc, rc);
3566 }
3567 }
3568
3569 /* Save the guest patch data. */
3570 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3571 rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3572 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3573
3574 /* Store all the guest patch records too. */
3575 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3576 AssertRCReturn(rc, rc);
3577
3578 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3579 {
3580 AssertCompileSize(HMTPRINSTR, 4);
3581 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3582 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3583 rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3584 rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
3585 rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3586 rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3587 rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3588 rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3589 rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3590 rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3591 rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
3592 AssertRCReturn(rc, rc);
3593 }
3594
3595 return VINF_SUCCESS;
3596}
3597
3598
3599/**
3600 * Execute state load operation.
3601 *
3602 * @returns VBox status code.
3603 * @param pVM The cross context VM structure.
3604 * @param pSSM SSM operation handle.
3605 * @param uVersion Data layout version.
3606 * @param uPass The data pass.
3607 */
3608static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3609{
3610 int rc;
3611
3612 LogFlowFunc(("uVersion=%u\n", uVersion));
3613 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3614
3615 /*
3616 * Validate version.
3617 */
3618 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3619 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3620 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3621 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3622 {
3623 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3624 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3625 }
3626
3627 /*
3628 * Load per-VCPU state.
3629 */
3630 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3631 {
3632 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3633 {
3634 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3635 if (pVM->cpum.ro.GuestFeatures.fSvm)
3636 {
3637 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3638 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3639 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3640 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3641 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3642 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3643 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3644 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3645 rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3646 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3647 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3648 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3649 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3650 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3651 AssertRCReturn(rc, rc);
3652 }
3653 }
3654 else
3655 {
3656 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3657 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3658 rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3659 rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3660
3661 /* VMX fWasInRealMode related data. */
3662 uint32_t uDummy;
3663 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3664 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3665 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3666 AssertRCReturn(rc, rc);
3667 }
3668 }
3669
3670 /*
3671 * Load TPR patching data.
3672 */
3673 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3674 {
3675 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3676 rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3677 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3678
3679 /* Fetch all TPR patch records. */
3680 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3681 AssertRCReturn(rc, rc);
3682 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3683 {
3684 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3685 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3686 rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3687 rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
3688 rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3689 rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3690 rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3691
3692 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3693 pVM->hm.s.fTPRPatchingActive = true;
3694 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3695
3696 rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3697 rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3698 rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
3699 rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3700 AssertRCReturn(rc, rc);
3701
3702 LogFlow(("hmR3Load: patch %d\n", i));
3703 LogFlow(("Key = %x\n", pPatch->Core.Key));
3704 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3705 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3706 LogFlow(("type = %d\n", pPatch->enmType));
3707 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3708 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3709 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3710 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3711
3712 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3713 AssertRCReturn(rc, rc);
3714 }
3715 }
3716
3717 return VINF_SUCCESS;
3718}
3719
3720
3721/**
3722 * Gets the name of a VT-x exit code.
3723 *
3724 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3725 * @param uExit The VT-x exit to name.
3726 */
3727VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
3728{
3729 if (uExit < RT_ELEMENTS(g_apszVTxExitReasons))
3730 return g_apszVTxExitReasons[uExit];
3731 return NULL;
3732}
3733
3734
3735/**
3736 * Gets the name of an AMD-V exit code.
3737 *
3738 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3739 * @param uExit The AMD-V exit to name.
3740 */
3741VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
3742{
3743 if (uExit < RT_ELEMENTS(g_apszAmdVExitReasons))
3744 return g_apszAmdVExitReasons[uExit];
3745 return hmSvmGetSpecialExitReasonDesc(uExit);
3746}
3747
3748
3749/**
3750 * Displays HM info.
3751 *
3752 * @param pVM The cross context VM structure.
3753 * @param pHlp The info helper functions.
3754 * @param pszArgs Arguments, ignored.
3755 */
3756static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3757{
3758 NOREF(pszArgs);
3759 PVMCPU pVCpu = VMMGetCpu(pVM);
3760 if (!pVCpu)
3761 pVCpu = &pVM->aCpus[0];
3762
3763 if (HMIsEnabled(pVM))
3764 {
3765 if (pVM->hm.s.vmx.fSupported)
3766 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3767 else
3768 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3769 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3770 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3771 }
3772 else
3773 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3774}
3775
3776
3777/**
3778 * Displays the HM pending event.
3779 *
3780 * @param pVM The cross context VM structure.
3781 * @param pHlp The info helper functions.
3782 * @param pszArgs Arguments, ignored.
3783 */
3784static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3785{
3786 NOREF(pszArgs);
3787 PVMCPU pVCpu = VMMGetCpu(pVM);
3788 if (!pVCpu)
3789 pVCpu = &pVM->aCpus[0];
3790
3791 if (HMIsEnabled(pVM))
3792 {
3793 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3794 if (pVCpu->hm.s.Event.fPending)
3795 {
3796 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3797 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3798 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3799 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3800 }
3801 }
3802 else
3803 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3804}
3805
3806
3807/**
3808 * Displays the SVM nested-guest VMCB cache.
3809 *
3810 * @param pVM The cross context VM structure.
3811 * @param pHlp The info helper functions.
3812 * @param pszArgs Arguments, ignored.
3813 */
3814static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3815{
3816 NOREF(pszArgs);
3817 PVMCPU pVCpu = VMMGetCpu(pVM);
3818 if (!pVCpu)
3819 pVCpu = &pVM->aCpus[0];
3820
3821 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3822 if ( fSvmEnabled
3823 && pVM->cpum.ro.GuestFeatures.fSvm)
3824 {
3825 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3826 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3827 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3828 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3829 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3830 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3831 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3832 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3833 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3834 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3835 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3836 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3837 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3838 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3839 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3840 }
3841 else
3842 {
3843 if (!fSvmEnabled)
3844 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3845 else
3846 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3847 }
3848}
3849
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