VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 74113

Last change on this file since 74113 was 74061, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 vmlaunch/vmresume bits.
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File size: 159.2 KB
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1/* $Id: HM.cpp 74061 2018-09-04 09:43:57Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/pdmapi.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/ssm.h>
48#include <VBox/vmm/trpm.h>
49#include <VBox/vmm/dbgf.h>
50#include <VBox/vmm/iom.h>
51#include <VBox/vmm/iem.h>
52#include <VBox/vmm/patm.h>
53#include <VBox/vmm/csam.h>
54#include <VBox/vmm/selm.h>
55#include <VBox/vmm/nem.h>
56#ifdef VBOX_WITH_REM
57# include <VBox/vmm/rem.h>
58#endif
59#include <VBox/vmm/hm_vmx.h>
60#include <VBox/vmm/hm_svm.h>
61#include "HMInternal.h"
62#include <VBox/vmm/vm.h>
63#include <VBox/vmm/uvm.h>
64#include <VBox/err.h>
65#include <VBox/param.h>
66
67#include <iprt/assert.h>
68#include <VBox/log.h>
69#include <iprt/asm.h>
70#include <iprt/asm-amd64-x86.h>
71#include <iprt/env.h>
72#include <iprt/thread.h>
73
74
75/*********************************************************************************************************************************
76* Global Variables *
77*********************************************************************************************************************************/
78#define EXIT_REASON(def, val, str) #def " - " #val " - " str
79#define EXIT_REASON_NIL() NULL
80/** Exit reason descriptions for VT-x, used to describe statistics and exit
81 * history. */
82static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
83{
84 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
85 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
86 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
87 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
88 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
89 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
90 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
91 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
92 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
93 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
94 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
95 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
96 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
97 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
98 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
99 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
100 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
101 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
102 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
103 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
104 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
105 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
106 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
107 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
108 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
109 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
110 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
111 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
112 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
113 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
114 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
115 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
116 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
117 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
118 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
119 EXIT_REASON_NIL(),
120 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
121 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
122 EXIT_REASON_NIL(),
123 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
124 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
125 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
126 EXIT_REASON_NIL(),
127 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
128 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
129 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
130 EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
131 EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
132 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
133 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
134 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
135 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
136 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
137 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
138 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
139 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
140 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
141 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
142 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
143 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
144 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
145 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
146 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
147 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
148 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
149};
150/** Array index of the last valid VT-x exit reason. */
151#define MAX_EXITREASON_VTX 64
152
153/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
154 * statistics and exit history.
155 *
156 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
157 * this array doesn't contain the entire set of exit reasons, we
158 * handle them via hmSvmGetSpecialExitReasonDesc(). */
159static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
160{
161 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
162 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
163 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
164 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
165 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
166 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
167 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
168 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
169 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
170 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
171 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
172 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
173 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
174 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
175 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
176 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
190 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
191 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
192 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
193 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
194 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
195 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
196 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
197 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
198 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
199 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
200 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
201 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
202 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
203 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
204 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
205 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
206 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
207 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
208 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
222 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
223 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
224 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
225 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
226 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
227 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
228 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
229 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
230 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
231 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
232 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
233 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
234 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
235 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
236 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
237 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
238 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
239 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
240 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
241 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
242 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
243 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
244 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
245 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
246 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
247 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
248 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
249 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
250 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
251 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
252 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
253 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
254 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
255 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
256 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
257 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
258 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
259 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
260 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
261 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
262 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
263 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
264 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
265 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
266 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
267 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
268 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
269 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
270 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
271 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
272 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
273 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
274 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
275 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
276 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
277 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
278 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
279 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
280 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
281 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
282 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
283 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
284 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
285 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
286 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
287 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
288 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
289 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
290 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
291 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
292 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
293 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
294 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
295 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
296 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
297 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
298 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
299 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
300 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
301 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
302 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
303};
304/** Array index of the last valid AMD-V exit reason. */
305#define MAX_EXITREASON_AMDV 141
306
307/** Special exit reasons not covered in the array above. */
308#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
309#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
310#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
311
312/**
313 * Gets the SVM exit reason if it's one of the reasons not present in the @c
314 * g_apszSvmExitReasons array.
315 *
316 * @returns The exit reason or NULL if unknown.
317 * @param uExit The exit.
318 */
319DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
320{
321 switch (uExit)
322 {
323 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
324 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
325 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
326 }
327 return EXIT_REASON_NIL();
328}
329#undef EXIT_REASON_NIL
330#undef EXIT_REASON
331
332/** @def HMVMX_REPORT_FEAT
333 * Reports VT-x feature to the release log.
334 *
335 * @param allowed1 Mask of allowed feature bits.
336 * @param disallowed0 Mask of disallowed feature bits.
337 * @param strdesc The description string to report.
338 * @param featflag Mask of the feature to report.
339 */
340#define HMVMX_REPORT_FEAT(allowed1, disallowed0, strdesc, featflag) \
341 do { \
342 if ((allowed1) & (featflag)) \
343 { \
344 if ((disallowed0) & (featflag)) \
345 LogRel(("HM: " strdesc " (must be set)\n")); \
346 else \
347 LogRel(("HM: " strdesc "\n")); \
348 } \
349 else \
350 LogRel(("HM: " strdesc " (must be cleared)\n")); \
351 } while (0)
352
353/** @def HMVMX_REPORT_ALLOWED_FEAT
354 * Reports an allowed VT-x feature to the release log.
355 *
356 * @param allowed1 Mask of allowed feature bits.
357 * @param strdesc The description string to report.
358 * @param featflag Mask of the feature to report.
359 */
360#define HMVMX_REPORT_ALLOWED_FEAT(allowed1, strdesc, featflag) \
361 do { \
362 if ((allowed1) & (featflag)) \
363 LogRel(("HM: " strdesc "\n")); \
364 else \
365 LogRel(("HM: " strdesc " not supported\n")); \
366 } while (0)
367
368/** @def HMVMX_REPORT_MSR_CAP
369 * Reports MSR feature capability.
370 *
371 * @param msrcaps Mask of MSR feature bits.
372 * @param strdesc The description string to report.
373 * @param cap Mask of the feature to report.
374 */
375#define HMVMX_REPORT_MSR_CAP(msrcaps, strdesc, cap) \
376 do { \
377 if ((msrcaps) & (cap)) \
378 LogRel(("HM: " strdesc "\n")); \
379 } while (0)
380
381/** @def HMVMX_LOGREL_FEAT
382 * Dumps a feature flag from a bitmap of features to the release log.
383 *
384 * @param a_fVal The value of all the features.
385 * @param a_fMask The specific bitmask of the feature.
386 */
387#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
388 do { \
389 if ((a_fVal) & (a_fMask)) \
390 LogRel(("HM: %s\n", #a_fMask)); \
391 } while (0)
392
393
394/*********************************************************************************************************************************
395* Internal Functions *
396*********************************************************************************************************************************/
397static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
398static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
399static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
400static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
401static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
402static int hmR3InitCPU(PVM pVM);
403static int hmR3InitFinalizeR0(PVM pVM);
404static int hmR3InitFinalizeR0Intel(PVM pVM);
405static int hmR3InitFinalizeR0Amd(PVM pVM);
406static int hmR3TermCPU(PVM pVM);
407
408
409
410/**
411 * Initializes the HM.
412 *
413 * This is the very first component to really do init after CFGM so that we can
414 * establish the predominat execution engine for the VM prior to initializing
415 * other modules. It takes care of NEM initialization if needed (HM disabled or
416 * not available in HW).
417 *
418 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
419 * hypervisor API via NEM, and then back on raw-mode if that isn't available
420 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
421 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
422 * X, OS/2 and others).
423 *
424 * Note that a lot of the set up work is done in ring-0 and thus postponed till
425 * the ring-3 and ring-0 callback to HMR3InitCompleted.
426 *
427 * @returns VBox status code.
428 * @param pVM The cross context VM structure.
429 *
430 * @remarks Be careful with what we call here, since most of the VMM components
431 * are uninitialized.
432 */
433VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
434{
435 LogFlow(("HMR3Init\n"));
436
437 /*
438 * Assert alignment and sizes.
439 */
440 AssertCompileMemberAlignment(VM, hm.s, 32);
441 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
442
443 /*
444 * Register the saved state data unit.
445 */
446 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
447 NULL, NULL, NULL,
448 NULL, hmR3Save, NULL,
449 NULL, hmR3Load, NULL);
450 if (RT_FAILURE(rc))
451 return rc;
452
453 /*
454 * Register info handlers.
455 */
456 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
457 AssertRCReturn(rc, rc);
458
459 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
460 DBGFINFO_FLAGS_ALL_EMTS);
461 AssertRCReturn(rc, rc);
462
463 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
464 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
465 AssertRCReturn(rc, rc);
466
467 /*
468 * Read configuration.
469 */
470 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
471
472 /*
473 * Validate the HM settings.
474 */
475 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
476 "HMForced"
477 "|UseNEMInstead"
478 "|FallbackToNEM"
479 "|EnableNestedPaging"
480 "|EnableUX"
481 "|EnableLargePages"
482 "|EnableVPID"
483 "|IBPBOnVMExit"
484 "|IBPBOnVMEntry"
485 "|SpecCtrlByHost"
486 "|TPRPatchingEnabled"
487 "|64bitEnabled"
488 "|Exclusive"
489 "|MaxResumeLoops"
490 "|VmxPleGap"
491 "|VmxPleWindow"
492 "|UseVmxPreemptTimer"
493 "|SvmPauseFilter"
494 "|SvmPauseFilterThreshold"
495 "|SvmVirtVmsaveVmload"
496 "|SvmVGif",
497 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
498 if (RT_FAILURE(rc))
499 return rc;
500
501 /** @cfgm{/HM/HMForced, bool, false}
502 * Forces hardware virtualization, no falling back on raw-mode. HM must be
503 * enabled, i.e. /HMEnabled must be true. */
504 bool fHMForced;
505#ifdef VBOX_WITH_RAW_MODE
506 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
507 AssertRCReturn(rc, rc);
508 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
509 VERR_INVALID_PARAMETER);
510# if defined(RT_OS_DARWIN)
511 if (pVM->fHMEnabled)
512 fHMForced = true;
513# endif
514 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
515 VERR_INVALID_PARAMETER);
516 if (pVM->cCpus > 1)
517 fHMForced = true;
518#else /* !VBOX_WITH_RAW_MODE */
519 AssertRelease(pVM->fHMEnabled);
520 fHMForced = true;
521#endif /* !VBOX_WITH_RAW_MODE */
522
523 /** @cfgm{/HM/UseNEMInstead, bool, true}
524 * Don't use HM, use NEM instead. */
525 bool fUseNEMInstead = false;
526 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
527 AssertRCReturn(rc, rc);
528 if (fUseNEMInstead && pVM->fHMEnabled)
529 {
530 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
531 pVM->fHMEnabled = false;
532 }
533
534 /** @cfgm{/HM/FallbackToNEM, bool, true}
535 * Enables fallback on NEM. */
536 bool fFallbackToNEM = true;
537 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
538 AssertRCReturn(rc, rc);
539
540 /** @cfgm{/HM/EnableNestedPaging, bool, false}
541 * Enables nested paging (aka extended page tables). */
542 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
543 AssertRCReturn(rc, rc);
544
545 /** @cfgm{/HM/EnableUX, bool, true}
546 * Enables the VT-x unrestricted execution feature. */
547 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
548 AssertRCReturn(rc, rc);
549
550 /** @cfgm{/HM/EnableLargePages, bool, false}
551 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
552 * page table walking and maybe better TLB hit rate in some cases. */
553 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
554 AssertRCReturn(rc, rc);
555
556 /** @cfgm{/HM/EnableVPID, bool, false}
557 * Enables the VT-x VPID feature. */
558 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
559 AssertRCReturn(rc, rc);
560
561 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
562 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
563 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
564 AssertRCReturn(rc, rc);
565
566 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
567 * Enables AMD64 cpu features.
568 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
569 * already have the support. */
570#ifdef VBOX_ENABLE_64_BITS_GUESTS
571 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
572 AssertLogRelRCReturn(rc, rc);
573#else
574 pVM->hm.s.fAllow64BitGuests = false;
575#endif
576
577 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
578 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
579 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
580 * latest PAUSE instruction to be start of a new PAUSE loop.
581 */
582 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
583 AssertRCReturn(rc, rc);
584
585 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
586 * The pause-filter exiting window in TSC ticks. When the number of ticks
587 * between the current PAUSE instruction and first PAUSE of a loop exceeds
588 * VmxPleWindow, a VM-exit is triggered.
589 *
590 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
591 */
592 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
593 AssertRCReturn(rc, rc);
594
595 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
596 * A counter that is decrement each time a PAUSE instruction is executed by the
597 * guest. When the counter is 0, a \#VMEXIT is triggered.
598 *
599 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
600 */
601 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
602 AssertRCReturn(rc, rc);
603
604 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
605 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
606 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
607 * PauseFilter count is reset to its initial value. However, if PAUSE is
608 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
609 * be triggered.
610 *
611 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
612 * activated.
613 */
614 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
615 AssertRCReturn(rc, rc);
616
617 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
618 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
619 * available. */
620 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
621 AssertRCReturn(rc, rc);
622
623 /** @cfgm{/HM/SvmVGif, bool, true}
624 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
625 * if it's available. */
626 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
627 AssertRCReturn(rc, rc);
628
629 /** @cfgm{/HM/Exclusive, bool}
630 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
631 * global init for each host CPU. If false, we do local init each time we wish
632 * to execute guest code.
633 *
634 * On Windows, default is false due to the higher risk of conflicts with other
635 * hypervisors.
636 *
637 * On Mac OS X, this setting is ignored since the code does not handle local
638 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
639 */
640#if defined(RT_OS_DARWIN)
641 pVM->hm.s.fGlobalInit = true;
642#else
643 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
644# if defined(RT_OS_WINDOWS)
645 false
646# else
647 true
648# endif
649 );
650 AssertLogRelRCReturn(rc, rc);
651#endif
652
653 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
654 * The number of times to resume guest execution before we forcibly return to
655 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
656 * determines the default value. */
657 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
658 AssertLogRelRCReturn(rc, rc);
659
660 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
661 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
662 * available. */
663 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
664 AssertLogRelRCReturn(rc, rc);
665
666 /** @cfgm{/HM/IBPBOnVMExit, bool}
667 * Costly paranoia setting. */
668 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
669 AssertLogRelRCReturn(rc, rc);
670
671 /** @cfgm{/HM/IBPBOnVMEntry, bool}
672 * Costly paranoia setting. */
673 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
674 AssertLogRelRCReturn(rc, rc);
675
676 /** @cfgm{/HM/SpecCtrlByHost, bool}
677 * Another expensive paranoia setting. */
678 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
679 AssertLogRelRCReturn(rc, rc);
680
681 /*
682 * Check if VT-x or AMD-v support according to the users wishes.
683 */
684 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
685 * VERR_SVM_IN_USE. */
686 if (pVM->fHMEnabled)
687 {
688 uint32_t fCaps;
689 rc = SUPR3QueryVTCaps(&fCaps);
690 if (RT_SUCCESS(rc))
691 {
692 if (fCaps & SUPVTCAPS_AMD_V)
693 {
694 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
695 pVM->hm.s.svm.fSupported = true;
696 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
697 }
698 else if (fCaps & SUPVTCAPS_VT_X)
699 {
700 const char *pszWhy;
701 rc = SUPR3QueryVTxSupported(&pszWhy);
702 if (RT_SUCCESS(rc))
703 {
704 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
705 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
706 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
707 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
708 pVM->hm.s.vmx.fSupported = true;
709 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
710 }
711 else
712 {
713 /*
714 * Before failing, try fallback to NEM if we're allowed to do that.
715 */
716 pVM->fHMEnabled = false;
717 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
718 if (fFallbackToNEM)
719 {
720 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
721 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
722
723 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
724 if ( RT_SUCCESS(rc2)
725 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
726 rc = VINF_SUCCESS;
727 }
728 if (RT_FAILURE(rc))
729 {
730 if (fHMForced)
731 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
732
733 /* Fall back to raw-mode. */
734 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
735 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
736 }
737 }
738 }
739 else
740 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
741 VERR_INTERNAL_ERROR_5);
742
743 /*
744 * Do we require a little bit or raw-mode for 64-bit guest execution?
745 */
746 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
747 && pVM->fHMEnabled
748 && pVM->hm.s.fAllow64BitGuests;
749
750 /*
751 * Disable nested paging and unrestricted guest execution now if they're
752 * configured so that CPUM can make decisions based on our configuration.
753 */
754 Assert(!pVM->hm.s.fNestedPaging);
755 if (pVM->hm.s.fAllowNestedPaging)
756 {
757 if (fCaps & SUPVTCAPS_NESTED_PAGING)
758 pVM->hm.s.fNestedPaging = true;
759 else
760 pVM->hm.s.fAllowNestedPaging = false;
761 }
762
763 if (fCaps & SUPVTCAPS_VT_X)
764 {
765 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
766 if (pVM->hm.s.vmx.fAllowUnrestricted)
767 {
768 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
769 && pVM->hm.s.fNestedPaging)
770 pVM->hm.s.vmx.fUnrestrictedGuest = true;
771 else
772 pVM->hm.s.vmx.fAllowUnrestricted = false;
773 }
774 }
775 }
776 else
777 {
778 const char *pszMsg;
779 switch (rc)
780 {
781 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
782 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
783 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
784 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
785 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
786 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
787 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
788 default:
789 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
790 }
791
792 /*
793 * Before failing, try fallback to NEM if we're allowed to do that.
794 */
795 pVM->fHMEnabled = false;
796 if (fFallbackToNEM)
797 {
798 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
799 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
800 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
801 if ( RT_SUCCESS(rc2)
802 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
803 rc = VINF_SUCCESS;
804 }
805 if (RT_FAILURE(rc))
806 {
807 if (fHMForced)
808 return VM_SET_ERROR(pVM, rc, pszMsg);
809
810 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
811 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
812 }
813 }
814 }
815 else
816 {
817 /*
818 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
819 */
820 if (!fUseNEMInstead)
821 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
822 else
823 {
824 rc = NEMR3Init(pVM, false /*fFallback*/, true);
825 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
826 if (RT_FAILURE(rc))
827 return rc;
828 }
829 }
830
831 return VINF_SUCCESS;
832}
833
834
835/**
836 * Initializes the per-VCPU HM.
837 *
838 * @returns VBox status code.
839 * @param pVM The cross context VM structure.
840 */
841static int hmR3InitCPU(PVM pVM)
842{
843 LogFlow(("HMR3InitCPU\n"));
844
845 if (!HMIsEnabled(pVM))
846 return VINF_SUCCESS;
847
848 for (VMCPUID i = 0; i < pVM->cCpus; i++)
849 {
850 PVMCPU pVCpu = &pVM->aCpus[i];
851 pVCpu->hm.s.fActive = false;
852 }
853
854#ifdef VBOX_WITH_STATISTICS
855 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
856 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
857 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
858 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
859 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
860#endif
861
862 /*
863 * Statistics.
864 */
865 for (VMCPUID i = 0; i < pVM->cCpus; i++)
866 {
867 PVMCPU pVCpu = &pVM->aCpus[i];
868 int rc;
869
870#ifdef VBOX_WITH_STATISTICS
871 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
872 "Profiling of RTMpPokeCpu.",
873 "/PROF/CPU%d/HM/Poke", i);
874 AssertRC(rc);
875 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
876 "Profiling of poke wait.",
877 "/PROF/CPU%d/HM/PokeWait", i);
878 AssertRC(rc);
879 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
880 "Profiling of poke wait when RTMpPokeCpu fails.",
881 "/PROF/CPU%d/HM/PokeWaitFailed", i);
882 AssertRC(rc);
883 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
884 "Profiling of entry until entering GC.",
885 "/PROF/CPU%d/HM/Entry", i);
886 AssertRC(rc);
887 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
888 "Profiling of pre-exit processing after returning from GC.",
889 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
890 AssertRC(rc);
891 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
892 "Profiling of exit handling (longjmps not included!)",
893 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
894 AssertRC(rc);
895
896 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
897 "I/O.",
898 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
899 AssertRC(rc);
900 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
901 "MOV CRx.",
902 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
903 AssertRC(rc);
904 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
905 "Exceptions, NMIs.",
906 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
907 AssertRC(rc);
908
909 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
910 "Profiling of importing guest state from hardware after VM-exit.",
911 "/PROF/CPU%d/HM/ImportGuestState", i);
912 AssertRC(rc);
913 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
914 "Profiling of exporting guest state to hardware before VM-entry.",
915 "/PROF/CPU%d/HM/ExportGuestState", i);
916 AssertRC(rc);
917 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
918 "Profiling of CPUMR0LoadGuestFPU.",
919 "/PROF/CPU%d/HM/LoadGuestFpuState", i);
920 AssertRC(rc);
921 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
922 "Profiling of execution of guest-code in hardware.",
923 "/PROF/CPU%d/HM/InGC", i);
924 AssertRC(rc);
925
926# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
927 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
928 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
929 "/PROF/CPU%d/HM/Switcher3264", i);
930 AssertRC(rc);
931# endif
932
933# ifdef HM_PROFILE_EXIT_DISPATCH
934 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
935 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
936 "/PROF/CPU%d/HM/ExitDispatch", i);
937 AssertRC(rc);
938# endif
939
940#endif
941# define HM_REG_COUNTER(a, b, desc) \
942 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
943 AssertRC(rc);
944
945#ifdef VBOX_WITH_STATISTICS
946 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
948 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
949 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
950 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
951 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
952 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
953 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
954 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
955 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
956 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
957 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
968 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
970 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
972 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
974 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
976 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
977 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
980 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
981 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
986 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
987 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
988 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
989 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
990 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
991 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
992 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
993 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
994#endif
995 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
996#ifdef VBOX_WITH_STATISTICS
997 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
999 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
1000 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
1002
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
1004 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
1006 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
1008 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
1010 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
1012#endif
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
1014#ifdef VBOX_WITH_STATISTICS
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptExportHostState, "/HM/CPU%d/Switch/ExportHostState", "Preemption caused us to re-export the host state.");
1016
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
1018 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
1019 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
1021
1022 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
1024 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1026 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1028 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1030 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1031 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1033 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1034 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1035 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1036
1037 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1038 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1039 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1040
1041 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1042 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1043 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1044
1045 HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
1046 HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
1047 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
1048
1049 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1050 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1051 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1052 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1053 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1054 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
1055 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
1056 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1057
1058#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1059 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1060 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1061#endif
1062
1063#undef HM_REG_COUNTER
1064
1065 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVmxExitReasons[0]
1066 : &g_apszSvmExitReasons[0];
1067
1068 /*
1069 * Guest Exit reason stats.
1070 */
1071 pVCpu->hm.s.paStatExitReason = NULL;
1072 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1073 (void **)&pVCpu->hm.s.paStatExitReason);
1074 AssertRCReturn(rc, rc);
1075 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1076 {
1077 if (papszDesc[j])
1078 {
1079 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1080 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1081 AssertRCReturn(rc, rc);
1082 }
1083 }
1084 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1085 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1086 AssertRCReturn(rc, rc);
1087 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1088# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1089 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1090# else
1091 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1092# endif
1093
1094#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1095 /*
1096 * Nested-guest Exit reason stats.
1097 */
1098 pVCpu->hm.s.paStatNestedExitReason = NULL;
1099 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1100 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1101 AssertRCReturn(rc, rc);
1102 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1103 {
1104 if (papszDesc[j])
1105 {
1106 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1107 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1108 AssertRC(rc);
1109 }
1110 }
1111 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1112 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1113 AssertRCReturn(rc, rc);
1114 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1115# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1116 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1117# else
1118 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1119# endif
1120#endif
1121
1122 /*
1123 * Injected events stats.
1124 */
1125 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1126 AssertRCReturn(rc, rc);
1127 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1128# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1129 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1130# else
1131 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1132# endif
1133 for (unsigned j = 0; j < 255; j++)
1134 {
1135 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1136 "Injected event.",
1137 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1138 }
1139
1140#endif /* VBOX_WITH_STATISTICS */
1141 }
1142
1143#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1144 /*
1145 * Magic marker for searching in crash dumps.
1146 */
1147 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1148 {
1149 PVMCPU pVCpu = &pVM->aCpus[i];
1150
1151 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1152 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1153 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
1154 }
1155#endif
1156
1157 return VINF_SUCCESS;
1158}
1159
1160
1161/**
1162 * Called when a init phase has completed.
1163 *
1164 * @returns VBox status code.
1165 * @param pVM The cross context VM structure.
1166 * @param enmWhat The phase that completed.
1167 */
1168VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1169{
1170 switch (enmWhat)
1171 {
1172 case VMINITCOMPLETED_RING3:
1173 return hmR3InitCPU(pVM);
1174 case VMINITCOMPLETED_RING0:
1175 return hmR3InitFinalizeR0(pVM);
1176 default:
1177 return VINF_SUCCESS;
1178 }
1179}
1180
1181
1182/**
1183 * Turns off normal raw mode features.
1184 *
1185 * @param pVM The cross context VM structure.
1186 */
1187static void hmR3DisableRawMode(PVM pVM)
1188{
1189/** @todo r=bird: HM shouldn't be doing this crap. */
1190 /* Reinit the paging mode to force the new shadow mode. */
1191 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1192 {
1193 PVMCPU pVCpu = &pVM->aCpus[i];
1194 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1195 }
1196}
1197
1198
1199/**
1200 * Initialize VT-x or AMD-V.
1201 *
1202 * @returns VBox status code.
1203 * @param pVM The cross context VM structure.
1204 */
1205static int hmR3InitFinalizeR0(PVM pVM)
1206{
1207 int rc;
1208
1209 if (!HMIsEnabled(pVM))
1210 return VINF_SUCCESS;
1211
1212 /*
1213 * Hack to allow users to work around broken BIOSes that incorrectly set
1214 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1215 */
1216 if ( !pVM->hm.s.vmx.fSupported
1217 && !pVM->hm.s.svm.fSupported
1218 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1219 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1220 {
1221 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1222 pVM->hm.s.svm.fSupported = true;
1223 pVM->hm.s.svm.fIgnoreInUseError = true;
1224 pVM->hm.s.rcInit = VINF_SUCCESS;
1225 }
1226
1227 /*
1228 * Report ring-0 init errors.
1229 */
1230 if ( !pVM->hm.s.vmx.fSupported
1231 && !pVM->hm.s.svm.fSupported)
1232 {
1233 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1234 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1235 switch (pVM->hm.s.rcInit)
1236 {
1237 case VERR_VMX_IN_VMX_ROOT_MODE:
1238 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1239 case VERR_VMX_NO_VMX:
1240 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1241 case VERR_VMX_MSR_VMX_DISABLED:
1242 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1243 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1244 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1245 case VERR_VMX_MSR_LOCKING_FAILED:
1246 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1247 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1248 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1249 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1250 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1251
1252 case VERR_SVM_IN_USE:
1253 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1254 case VERR_SVM_NO_SVM:
1255 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1256 case VERR_SVM_DISABLED:
1257 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1258 }
1259 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1260 }
1261
1262 /*
1263 * Enable VT-x or AMD-V on all host CPUs.
1264 */
1265 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1266 if (RT_FAILURE(rc))
1267 {
1268 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1269 HMR3CheckError(pVM, rc);
1270 return rc;
1271 }
1272
1273 /*
1274 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1275 * (Main should have taken care of this already)
1276 */
1277 if (!PDMHasIoApic(pVM))
1278 {
1279 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1280 pVM->hm.s.fTprPatchingAllowed = false;
1281 }
1282
1283 /*
1284 * Sync options.
1285 */
1286 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1287 * That will require a little bit of work, of course. */
1288 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1289 {
1290 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1291 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1292 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1293 if (pVM->cpum.ro.HostFeatures.fIbpb)
1294 {
1295 if (pVM->hm.s.fIbpbOnVmExit)
1296 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1297 if (pVM->hm.s.fIbpbOnVmEntry)
1298 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1299 }
1300 if (iCpu == 0)
1301 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1302 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1303 }
1304
1305 /*
1306 * Do the vendor specific initialization
1307 *
1308 * Note! We disable release log buffering here since we're doing relatively
1309 * lot of logging and doesn't want to hit the disk with each LogRel
1310 * statement.
1311 */
1312 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1313 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1314 if (pVM->hm.s.vmx.fSupported)
1315 rc = hmR3InitFinalizeR0Intel(pVM);
1316 else
1317 rc = hmR3InitFinalizeR0Amd(pVM);
1318 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1319 RTLogRelSetBuffering(fOldBuffered);
1320 pVM->hm.s.fInitialized = true;
1321
1322 return rc;
1323}
1324
1325
1326/**
1327 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1328 */
1329static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1330{
1331 NOREF(pVM);
1332 NOREF(pvAllocation);
1333 NOREF(GCPhysAllocation);
1334}
1335
1336
1337/**
1338 * Returns a description of the VMCS (and associated regions') memory type given the
1339 * IA32_VMX_BASIC MSR.
1340 *
1341 * @returns The descriptive memory type.
1342 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1343 */
1344static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1345{
1346 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1347 switch (uMemType)
1348 {
1349 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1350 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1351 }
1352 return "Unknown";
1353}
1354
1355
1356/**
1357 * Returns a single-line description of all the activity-states supported by the CPU
1358 * given the IA32_VMX_MISC MSR.
1359 *
1360 * @returns All supported activity states.
1361 * @param uMsrMisc IA32_VMX_MISC MSR value.
1362 */
1363static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1364{
1365 static const char * const s_apszActStates[] =
1366 {
1367 "",
1368 " ( HLT )",
1369 " ( SHUTDOWN )",
1370 " ( HLT SHUTDOWN )",
1371 " ( SIPI_WAIT )",
1372 " ( HLT SIPI_WAIT )",
1373 " ( SHUTDOWN SIPI_WAIT )",
1374 " ( HLT SHUTDOWN SIPI_WAIT )"
1375 };
1376 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1377 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1378 return s_apszActStates[idxActStates];
1379}
1380
1381
1382/**
1383 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1384 *
1385 * @param fFeatMsr The feature control MSR value.
1386 */
1387static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1388{
1389 uint64_t const val = fFeatMsr;
1390 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1391 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1392 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1393 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1394 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1395 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1396 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1397 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1398 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1399 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1400 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1401 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1402 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1403 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1404 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1405 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1406 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1407}
1408
1409
1410/**
1411 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1412 *
1413 * @param uBasicMsr The VMX basic MSR value.
1414 */
1415static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1416{
1417 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1418 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1419 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1420 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1421 "< 4 GB" : "None"));
1422 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1423 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1424 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1425 LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1426}
1427
1428
1429/**
1430 * Reports MSR_IA32_PINBASED_CTLS to the log.
1431 *
1432 * @param pVmxMsr Pointer to the VMX MSR.
1433 */
1434static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1435{
1436 uint64_t const val = pVmxMsr->n.allowed1;
1437 uint64_t const zap = pVmxMsr->n.disallowed0;
1438 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1439 HMVMX_REPORT_FEAT(val, zap, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1440 HMVMX_REPORT_FEAT(val, zap, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1441 HMVMX_REPORT_FEAT(val, zap, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1442 HMVMX_REPORT_FEAT(val, zap, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1443 HMVMX_REPORT_FEAT(val, zap, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1444}
1445
1446
1447/**
1448 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1449 *
1450 * @param pVmxMsr Pointer to the VMX MSR.
1451 */
1452static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1453{
1454 uint64_t const val = pVmxMsr->n.allowed1;
1455 uint64_t const zap = pVmxMsr->n.disallowed0;
1456 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1457 HMVMX_REPORT_FEAT(val, zap, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1458 HMVMX_REPORT_FEAT(val, zap, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1459 HMVMX_REPORT_FEAT(val, zap, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1460 HMVMX_REPORT_FEAT(val, zap, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1461 HMVMX_REPORT_FEAT(val, zap, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1462 HMVMX_REPORT_FEAT(val, zap, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1463 HMVMX_REPORT_FEAT(val, zap, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1464 HMVMX_REPORT_FEAT(val, zap, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1465 HMVMX_REPORT_FEAT(val, zap, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1466 HMVMX_REPORT_FEAT(val, zap, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1467 HMVMX_REPORT_FEAT(val, zap, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1468 HMVMX_REPORT_FEAT(val, zap, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1469 HMVMX_REPORT_FEAT(val, zap, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1470 HMVMX_REPORT_FEAT(val, zap, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1471 HMVMX_REPORT_FEAT(val, zap, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1472 HMVMX_REPORT_FEAT(val, zap, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1473 HMVMX_REPORT_FEAT(val, zap, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1474 HMVMX_REPORT_FEAT(val, zap, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1475 HMVMX_REPORT_FEAT(val, zap, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1476 HMVMX_REPORT_FEAT(val, zap, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1477 HMVMX_REPORT_FEAT(val, zap, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1478}
1479
1480
1481/**
1482 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1483 *
1484 * @param pVmxMsr Pointer to the VMX MSR.
1485 */
1486static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1487{
1488 uint64_t const val = pVmxMsr->n.allowed1;
1489 uint64_t const zap = pVmxMsr->n.disallowed0;
1490 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1491 HMVMX_REPORT_FEAT(val, zap, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1492 HMVMX_REPORT_FEAT(val, zap, "EPT", VMX_PROC_CTLS2_EPT);
1493 HMVMX_REPORT_FEAT(val, zap, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1494 HMVMX_REPORT_FEAT(val, zap, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1495 HMVMX_REPORT_FEAT(val, zap, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1496 HMVMX_REPORT_FEAT(val, zap, "VPID", VMX_PROC_CTLS2_VPID);
1497 HMVMX_REPORT_FEAT(val, zap, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1498 HMVMX_REPORT_FEAT(val, zap, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1499 HMVMX_REPORT_FEAT(val, zap, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1500 HMVMX_REPORT_FEAT(val, zap, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1501 HMVMX_REPORT_FEAT(val, zap, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1502 HMVMX_REPORT_FEAT(val, zap, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1503 HMVMX_REPORT_FEAT(val, zap, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1504 HMVMX_REPORT_FEAT(val, zap, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1505 HMVMX_REPORT_FEAT(val, zap, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1506 HMVMX_REPORT_FEAT(val, zap, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1507 HMVMX_REPORT_FEAT(val, zap, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1508 HMVMX_REPORT_FEAT(val, zap, "PML", VMX_PROC_CTLS2_PML);
1509 HMVMX_REPORT_FEAT(val, zap, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1510 HMVMX_REPORT_FEAT(val, zap, "CONCEAL_FROM_PT", VMX_PROC_CTLS2_CONCEAL_FROM_PT);
1511 HMVMX_REPORT_FEAT(val, zap, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1512 HMVMX_REPORT_FEAT(val, zap, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1513}
1514
1515
1516/**
1517 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1518 *
1519 * @param pVmxMsr Pointer to the VMX MSR.
1520 */
1521static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1522{
1523 uint64_t const val = pVmxMsr->n.allowed1;
1524 uint64_t const zap = pVmxMsr->n.disallowed0;
1525 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1526 HMVMX_REPORT_FEAT(val, zap, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1527 HMVMX_REPORT_FEAT(val, zap, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1528 HMVMX_REPORT_FEAT(val, zap, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1529 HMVMX_REPORT_FEAT(val, zap, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1530 HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1531 HMVMX_REPORT_FEAT(val, zap, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1532 HMVMX_REPORT_FEAT(val, zap, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1533}
1534
1535
1536/**
1537 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1538 *
1539 * @param pVmxMsr Pointer to the VMX MSR.
1540 */
1541static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1542{
1543 uint64_t const val = pVmxMsr->n.allowed1;
1544 uint64_t const zap = pVmxMsr->n.disallowed0;
1545 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1546 HMVMX_REPORT_FEAT(val, zap, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1547 HMVMX_REPORT_FEAT(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1548 HMVMX_REPORT_FEAT(val, zap, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1549 HMVMX_REPORT_FEAT(val, zap, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1550 HMVMX_REPORT_FEAT(val, zap, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1551 HMVMX_REPORT_FEAT(val, zap, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1552 HMVMX_REPORT_FEAT(val, zap, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1553 HMVMX_REPORT_FEAT(val, zap, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1554 HMVMX_REPORT_FEAT(val, zap, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1555}
1556
1557
1558/**
1559 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1560 *
1561 * @param fCaps The VMX EPT/VPID capability MSR value.
1562 */
1563static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1564{
1565 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1566 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1567 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1568 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1569 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1570 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1571 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1572 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1573 HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1574 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1575 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1576 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1577 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1578 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1579 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1580 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1581}
1582
1583
1584/**
1585 * Reports MSR_IA32_VMX_MISC MSR to the log.
1586 *
1587 * @param pVM Pointer to the VM.
1588 * @param fMisc The VMX misc. MSR value.
1589 */
1590static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1591{
1592 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1593 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1594 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1595 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1596 else
1597 {
1598 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1599 pVM->hm.s.vmx.cPreemptTimerShift));
1600 }
1601 LogRel(("HM: EXIT_STORE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_STORE_EFER_LMA)));
1602 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1603 hmR3VmxGetActivityStateAllDesc(fMisc)));
1604 LogRel(("HM: PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_PT)));
1605 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1606 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1607 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1608 VMX_MISC_MAX_MSRS(fMisc)));
1609 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1610 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1611 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1612 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1613}
1614
1615
1616/**
1617 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1618 *
1619 * @param uVmcsEnum The VMX VMCS enum MSR value.
1620 */
1621static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1622{
1623 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1624 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1625}
1626
1627
1628/**
1629 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1630 *
1631 * @param uVmFunc The VMX VMFUNC MSR value.
1632 */
1633static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1634{
1635 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1636 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1637}
1638
1639
1640/**
1641 * Reports VMX CR0, CR4 fixed MSRs.
1642 *
1643 * @param pMsrs Pointer to the VMX MSRs.
1644 */
1645static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1646{
1647 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1648 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1649 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1650 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1651}
1652
1653
1654/**
1655 * Finish VT-x initialization (after ring-0 init).
1656 *
1657 * @returns VBox status code.
1658 * @param pVM The cross context VM structure.
1659 */
1660static int hmR3InitFinalizeR0Intel(PVM pVM)
1661{
1662 int rc;
1663
1664 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1665 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1666
1667 LogRel(("HM: Using VT-x implementation 2.0\n"));
1668 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1669 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1670 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1671 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1672
1673 hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1674 hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1675
1676 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1677 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1678 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1679 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1680
1681 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1682 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1683
1684 if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1685 {
1686 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1687 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1688 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1689 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1690 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1691 }
1692
1693 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1694 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1695 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1696 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1697 if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1698 hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1699 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1700
1701 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1702 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1703 {
1704 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1705 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1706 }
1707
1708 /*
1709 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1710 */
1711 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1712 || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1713 VERR_HM_IPE_1);
1714 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1715 || ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1716 && pVM->hm.s.fNestedPaging),
1717 VERR_HM_IPE_1);
1718
1719 /*
1720 * Enable VPID if configured and supported.
1721 */
1722 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1723 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1724
1725#if 0
1726 /*
1727 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1728 */
1729 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1730 && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1731 pVM->hm.s.fVirtApicRegs = true;
1732
1733 /*
1734 * Enable posted-interrupt processing if supported.
1735 */
1736 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1737 * here. */
1738 if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1739 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1740 pVM->hm.s.fPostedIntrs = true;
1741#endif
1742
1743 /*
1744 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1745 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1746 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1747 */
1748 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1749 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1750 {
1751 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1752 LogRel(("HM: Disabled RDTSCP\n"));
1753 }
1754
1755 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1756 {
1757 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1758 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1759 if (RT_SUCCESS(rc))
1760 {
1761 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1762 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1763 esp. Figure 20-5.*/
1764 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1765 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1766
1767 /* Bit set to 0 means software interrupts are redirected to the
1768 8086 program interrupt handler rather than switching to
1769 protected-mode handler. */
1770 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1771
1772 /* Allow all port IO, so that port IO instructions do not cause
1773 exceptions and would instead cause a VM-exit (based on VT-x's
1774 IO bitmap which we currently configure to always cause an exit). */
1775 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1776 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1777
1778 /*
1779 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1780 * page table used in real and protected mode without paging with EPT.
1781 */
1782 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1783 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1784 {
1785 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1786 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1787 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1788 | X86_PDE4M_G;
1789 }
1790
1791 /* We convert it here every time as PCI regions could be reconfigured. */
1792 if (PDMVmmDevHeapIsEnabled(pVM))
1793 {
1794 RTGCPHYS GCPhys;
1795 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1796 AssertRCReturn(rc, rc);
1797 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1798
1799 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1800 AssertRCReturn(rc, rc);
1801 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1802 }
1803 }
1804 else
1805 {
1806 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1807 pVM->hm.s.vmx.pRealModeTSS = NULL;
1808 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1809 return VMSetError(pVM, rc, RT_SRC_POS,
1810 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1811 }
1812 }
1813
1814 LogRel((pVM->hm.s.fAllow64BitGuests
1815 ? "HM: Guest support: 32-bit and 64-bit\n"
1816 : "HM: Guest support: 32-bit only\n"));
1817
1818 /*
1819 * Call ring-0 to set up the VM.
1820 */
1821 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1822 if (rc != VINF_SUCCESS)
1823 {
1824 AssertMsgFailed(("%Rrc\n", rc));
1825 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1826 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1827 {
1828 PVMCPU pVCpu = &pVM->aCpus[i];
1829 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1830 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1831 }
1832 HMR3CheckError(pVM, rc);
1833 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1834 }
1835
1836 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1837 LogRel(("HM: Enabled VMX\n"));
1838 pVM->hm.s.vmx.fEnabled = true;
1839
1840 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1841
1842 /*
1843 * Change the CPU features.
1844 */
1845 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1846 if (pVM->hm.s.fAllow64BitGuests)
1847 {
1848 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1849 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1850 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1851 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1852 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1853 }
1854 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1855 (we reuse the host EFER in the switcher). */
1856 /** @todo this needs to be fixed properly!! */
1857 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1858 {
1859 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1860 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1861 else
1862 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1863 }
1864
1865 /*
1866 * Log configuration details.
1867 */
1868 if (pVM->hm.s.fNestedPaging)
1869 {
1870 LogRel(("HM: Enabled nested paging\n"));
1871 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1872 LogRel(("HM: EPT flush type = Single context\n"));
1873 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1874 LogRel(("HM: EPT flush type = All contexts\n"));
1875 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1876 LogRel(("HM: EPT flush type = Not supported\n"));
1877 else
1878 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1879
1880 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1881 LogRel(("HM: Enabled unrestricted guest execution\n"));
1882
1883#if HC_ARCH_BITS == 64
1884 if (pVM->hm.s.fLargePages)
1885 {
1886 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1887 PGMSetLargePageUsage(pVM, true);
1888 LogRel(("HM: Enabled large page support\n"));
1889 }
1890#endif
1891 }
1892 else
1893 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1894
1895 if (pVM->hm.s.fVirtApicRegs)
1896 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1897
1898 if (pVM->hm.s.fPostedIntrs)
1899 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1900
1901 if (pVM->hm.s.vmx.fVpid)
1902 {
1903 LogRel(("HM: Enabled VPID\n"));
1904 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1905 LogRel(("HM: VPID flush type = Individual addresses\n"));
1906 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1907 LogRel(("HM: VPID flush type = Single context\n"));
1908 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1909 LogRel(("HM: VPID flush type = All contexts\n"));
1910 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1911 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1912 else
1913 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1914 }
1915 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1916 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1917
1918 if (pVM->hm.s.vmx.fUsePreemptTimer)
1919 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1920 else
1921 LogRel(("HM: Disabled VMX-preemption timer\n"));
1922
1923 return VINF_SUCCESS;
1924}
1925
1926
1927/**
1928 * Finish AMD-V initialization (after ring-0 init).
1929 *
1930 * @returns VBox status code.
1931 * @param pVM The cross context VM structure.
1932 */
1933static int hmR3InitFinalizeR0Amd(PVM pVM)
1934{
1935 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1936
1937 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1938
1939 uint32_t u32Family;
1940 uint32_t u32Model;
1941 uint32_t u32Stepping;
1942 if (HMSvmIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1943 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1944 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1945 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1946 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1947 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1948 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1949
1950 /*
1951 * Enumerate AMD-V features.
1952 */
1953 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1954 {
1955#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1956 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1957 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1958 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1959 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1960 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1961 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1962 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1963 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1964 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1965 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1966 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1967 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1968 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1969#undef HMSVM_REPORT_FEATURE
1970 };
1971
1972 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1973 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1974 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1975 {
1976 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1977 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1978 }
1979 if (fSvmFeatures)
1980 for (unsigned iBit = 0; iBit < 32; iBit++)
1981 if (RT_BIT_32(iBit) & fSvmFeatures)
1982 LogRel(("HM: Reserved bit %u\n", iBit));
1983
1984 /*
1985 * Nested paging is determined in HMR3Init, verify the sanity of that.
1986 */
1987 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1988 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1989 VERR_HM_IPE_1);
1990
1991#if 0
1992 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1993 * here. */
1994 if (RTR0IsPostIpiSupport())
1995 pVM->hm.s.fPostedIntrs = true;
1996#endif
1997
1998 /*
1999 * Call ring-0 to set up the VM.
2000 */
2001 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
2002 if (rc != VINF_SUCCESS)
2003 {
2004 AssertMsgFailed(("%Rrc\n", rc));
2005 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
2006 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
2007 }
2008
2009 LogRel(("HM: Enabled SVM\n"));
2010 pVM->hm.s.svm.fEnabled = true;
2011
2012 if (pVM->hm.s.fNestedPaging)
2013 {
2014 LogRel(("HM: Enabled nested paging\n"));
2015
2016 /*
2017 * Enable large pages (2 MB) if applicable.
2018 */
2019#if HC_ARCH_BITS == 64
2020 if (pVM->hm.s.fLargePages)
2021 {
2022 PGMSetLargePageUsage(pVM, true);
2023 LogRel(("HM: Enabled large page support\n"));
2024 }
2025#endif
2026 }
2027
2028 if (pVM->hm.s.fVirtApicRegs)
2029 LogRel(("HM: Enabled APIC-register virtualization support\n"));
2030
2031 if (pVM->hm.s.fPostedIntrs)
2032 LogRel(("HM: Enabled posted-interrupt processing support\n"));
2033
2034 hmR3DisableRawMode(pVM);
2035
2036 /*
2037 * Change the CPU features.
2038 */
2039 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
2040 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
2041 if (pVM->hm.s.fAllow64BitGuests)
2042 {
2043 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
2044 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
2045 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2046 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
2047 }
2048 /* Turn on NXE if PAE has been enabled. */
2049 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
2050 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2051
2052 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
2053
2054 LogRel((pVM->hm.s.fAllow64BitGuests
2055 ? "HM: Guest support: 32-bit and 64-bit\n"
2056 : "HM: Guest support: 32-bit only\n"));
2057
2058 return VINF_SUCCESS;
2059}
2060
2061
2062/**
2063 * Applies relocations to data and code managed by this
2064 * component. This function will be called at init and
2065 * whenever the VMM need to relocate it self inside the GC.
2066 *
2067 * @param pVM The cross context VM structure.
2068 */
2069VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2070{
2071 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
2072
2073 /* Fetch the current paging mode during the relocate callback during state loading. */
2074 if (VMR3GetState(pVM) == VMSTATE_LOADING)
2075 {
2076 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2077 {
2078 PVMCPU pVCpu = &pVM->aCpus[i];
2079 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2080 }
2081 }
2082#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
2083 if (HMIsEnabled(pVM))
2084 {
2085 switch (PGMGetHostMode(pVM))
2086 {
2087 case PGMMODE_32_BIT:
2088 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
2089 break;
2090
2091 case PGMMODE_PAE:
2092 case PGMMODE_PAE_NX:
2093 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
2094 break;
2095
2096 default:
2097 AssertFailed();
2098 break;
2099 }
2100 }
2101#endif
2102 return;
2103}
2104
2105
2106/**
2107 * Terminates the HM.
2108 *
2109 * Termination means cleaning up and freeing all resources,
2110 * the VM itself is, at this point, powered off or suspended.
2111 *
2112 * @returns VBox status code.
2113 * @param pVM The cross context VM structure.
2114 */
2115VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2116{
2117 if (pVM->hm.s.vmx.pRealModeTSS)
2118 {
2119 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2120 pVM->hm.s.vmx.pRealModeTSS = 0;
2121 }
2122 hmR3TermCPU(pVM);
2123 return 0;
2124}
2125
2126
2127/**
2128 * Terminates the per-VCPU HM.
2129 *
2130 * @returns VBox status code.
2131 * @param pVM The cross context VM structure.
2132 */
2133static int hmR3TermCPU(PVM pVM)
2134{
2135 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2136 {
2137 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2138
2139#ifdef VBOX_WITH_STATISTICS
2140 if (pVCpu->hm.s.paStatExitReason)
2141 {
2142 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2143 pVCpu->hm.s.paStatExitReason = NULL;
2144 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2145 }
2146 if (pVCpu->hm.s.paStatInjectedIrqs)
2147 {
2148 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2149 pVCpu->hm.s.paStatInjectedIrqs = NULL;
2150 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2151 }
2152#endif
2153
2154#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2155 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
2156 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
2157 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
2158#endif
2159 }
2160 return 0;
2161}
2162
2163
2164/**
2165 * Resets a virtual CPU.
2166 *
2167 * Used by HMR3Reset and CPU hot plugging.
2168 *
2169 * @param pVCpu The cross context virtual CPU structure to reset.
2170 */
2171VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2172{
2173 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2174 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2175 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2176
2177 pVCpu->hm.s.fActive = false;
2178 pVCpu->hm.s.Event.fPending = false;
2179 pVCpu->hm.s.vmx.fWasInRealMode = true;
2180 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2181 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2182
2183 /* Reset the contents of the read cache. */
2184 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2185 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2186 pCache->Read.aFieldVal[j] = 0;
2187
2188#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2189 /* Magic marker for searching in crash dumps. */
2190 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2191 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2192#endif
2193}
2194
2195
2196/**
2197 * The VM is being reset.
2198 *
2199 * For the HM component this means that any GDT/LDT/TSS monitors
2200 * needs to be removed.
2201 *
2202 * @param pVM The cross context VM structure.
2203 */
2204VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2205{
2206 LogFlow(("HMR3Reset:\n"));
2207
2208 if (HMIsEnabled(pVM))
2209 hmR3DisableRawMode(pVM);
2210
2211 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2212 {
2213 PVMCPU pVCpu = &pVM->aCpus[i];
2214
2215 HMR3ResetCpu(pVCpu);
2216 }
2217
2218 /* Clear all patch information. */
2219 pVM->hm.s.pGuestPatchMem = 0;
2220 pVM->hm.s.pFreeGuestPatchMem = 0;
2221 pVM->hm.s.cbGuestPatchMem = 0;
2222 pVM->hm.s.cPatches = 0;
2223 pVM->hm.s.PatchTree = 0;
2224 pVM->hm.s.fTPRPatchingActive = false;
2225 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2226}
2227
2228
2229/**
2230 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2231 *
2232 * @returns VBox strict status code.
2233 * @param pVM The cross context VM structure.
2234 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2235 * @param pvUser Unused.
2236 */
2237static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2238{
2239 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2240
2241 /* Only execute the handler on the VCPU the original patch request was issued. */
2242 if (pVCpu->idCpu != idCpu)
2243 return VINF_SUCCESS;
2244
2245 Log(("hmR3RemovePatches\n"));
2246 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2247 {
2248 uint8_t abInstr[15];
2249 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2250 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2251 int rc;
2252
2253#ifdef LOG_ENABLED
2254 char szOutput[256];
2255 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2256 szOutput, sizeof(szOutput), NULL);
2257 if (RT_SUCCESS(rc))
2258 Log(("Patched instr: %s\n", szOutput));
2259#endif
2260
2261 /* Check if the instruction is still the same. */
2262 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2263 if (rc != VINF_SUCCESS)
2264 {
2265 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2266 continue; /* swapped out or otherwise removed; skip it. */
2267 }
2268
2269 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2270 {
2271 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2272 continue; /* skip it. */
2273 }
2274
2275 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2276 AssertRC(rc);
2277
2278#ifdef LOG_ENABLED
2279 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2280 szOutput, sizeof(szOutput), NULL);
2281 if (RT_SUCCESS(rc))
2282 Log(("Original instr: %s\n", szOutput));
2283#endif
2284 }
2285 pVM->hm.s.cPatches = 0;
2286 pVM->hm.s.PatchTree = 0;
2287 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2288 pVM->hm.s.fTPRPatchingActive = false;
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/**
2294 * Worker for enabling patching in a VT-x/AMD-V guest.
2295 *
2296 * @returns VBox status code.
2297 * @param pVM The cross context VM structure.
2298 * @param idCpu VCPU to execute hmR3RemovePatches on.
2299 * @param pPatchMem Patch memory range.
2300 * @param cbPatchMem Size of the memory range.
2301 */
2302static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2303{
2304 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2305 AssertRC(rc);
2306
2307 pVM->hm.s.pGuestPatchMem = pPatchMem;
2308 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2309 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2310 return VINF_SUCCESS;
2311}
2312
2313
2314/**
2315 * Enable patching in a VT-x/AMD-V guest
2316 *
2317 * @returns VBox status code.
2318 * @param pVM The cross context VM structure.
2319 * @param pPatchMem Patch memory range.
2320 * @param cbPatchMem Size of the memory range.
2321 */
2322VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2323{
2324 VM_ASSERT_EMT(pVM);
2325 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2326 if (pVM->cCpus > 1)
2327 {
2328 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2329 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2330 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2331 AssertRC(rc);
2332 return rc;
2333 }
2334 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2335}
2336
2337
2338/**
2339 * Disable patching in a VT-x/AMD-V guest.
2340 *
2341 * @returns VBox status code.
2342 * @param pVM The cross context VM structure.
2343 * @param pPatchMem Patch memory range.
2344 * @param cbPatchMem Size of the memory range.
2345 */
2346VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2347{
2348 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2349 RT_NOREF2(pPatchMem, cbPatchMem);
2350
2351 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2352 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2353
2354 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2355 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2356 (void *)(uintptr_t)VMMGetCpuId(pVM));
2357 AssertRC(rc);
2358
2359 pVM->hm.s.pGuestPatchMem = 0;
2360 pVM->hm.s.pFreeGuestPatchMem = 0;
2361 pVM->hm.s.cbGuestPatchMem = 0;
2362 pVM->hm.s.fTPRPatchingActive = false;
2363 return VINF_SUCCESS;
2364}
2365
2366
2367/**
2368 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2369 *
2370 * @returns VBox strict status code.
2371 * @param pVM The cross context VM structure.
2372 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2373 * @param pvUser User specified CPU context.
2374 *
2375 */
2376static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2377{
2378 /*
2379 * Only execute the handler on the VCPU the original patch request was
2380 * issued. (The other CPU(s) might not yet have switched to protected
2381 * mode, nor have the correct memory context.)
2382 */
2383 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2384 if (pVCpu->idCpu != idCpu)
2385 return VINF_SUCCESS;
2386
2387 /*
2388 * We're racing other VCPUs here, so don't try patch the instruction twice
2389 * and make sure there is still room for our patch record.
2390 */
2391 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2392 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2393 if (pPatch)
2394 {
2395 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2396 return VINF_SUCCESS;
2397 }
2398 uint32_t const idx = pVM->hm.s.cPatches;
2399 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2400 {
2401 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2402 return VINF_SUCCESS;
2403 }
2404 pPatch = &pVM->hm.s.aPatches[idx];
2405
2406 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2407
2408 /*
2409 * Disassembler the instruction and get cracking.
2410 */
2411 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2412 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2413 uint32_t cbOp;
2414 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2415 AssertRC(rc);
2416 if ( rc == VINF_SUCCESS
2417 && pDis->pCurInstr->uOpcode == OP_MOV
2418 && cbOp >= 3)
2419 {
2420 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2421
2422 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2423 AssertRC(rc);
2424
2425 pPatch->cbOp = cbOp;
2426
2427 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2428 {
2429 /* write. */
2430 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2431 {
2432 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2433 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2434 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2435 }
2436 else
2437 {
2438 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2439 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2440 pPatch->uSrcOperand = pDis->Param2.uValue;
2441 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2442 }
2443 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2444 AssertRC(rc);
2445
2446 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2447 pPatch->cbNewOp = sizeof(s_abVMMCall);
2448 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2449 }
2450 else
2451 {
2452 /*
2453 * TPR Read.
2454 *
2455 * Found:
2456 * mov eax, dword [fffe0080] (5 bytes)
2457 * Check if next instruction is:
2458 * shr eax, 4
2459 */
2460 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2461
2462 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2463 uint8_t const cbOpMmio = cbOp;
2464 uint64_t const uSavedRip = pCtx->rip;
2465
2466 pCtx->rip += cbOp;
2467 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2468 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2469 pCtx->rip = uSavedRip;
2470
2471 if ( rc == VINF_SUCCESS
2472 && pDis->pCurInstr->uOpcode == OP_SHR
2473 && pDis->Param1.fUse == DISUSE_REG_GEN32
2474 && pDis->Param1.Base.idxGenReg == idxMmioReg
2475 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2476 && pDis->Param2.uValue == 4
2477 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2478 {
2479 uint8_t abInstr[15];
2480
2481 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2482 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2483 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2484 AssertRC(rc);
2485
2486 pPatch->cbOp = cbOpMmio + cbOp;
2487
2488 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2489 abInstr[0] = 0xf0;
2490 abInstr[1] = 0x0f;
2491 abInstr[2] = 0x20;
2492 abInstr[3] = 0xc0 | pDis->Param1.Base.idxGenReg;
2493 for (unsigned i = 4; i < pPatch->cbOp; i++)
2494 abInstr[i] = 0x90; /* nop */
2495
2496 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2497 AssertRC(rc);
2498
2499 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2500 pPatch->cbNewOp = pPatch->cbOp;
2501 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2502
2503 Log(("Acceptable read/shr candidate!\n"));
2504 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2505 }
2506 else
2507 {
2508 pPatch->enmType = HMTPRINSTR_READ;
2509 pPatch->uDstOperand = idxMmioReg;
2510
2511 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2512 AssertRC(rc);
2513
2514 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2515 pPatch->cbNewOp = sizeof(s_abVMMCall);
2516 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2517 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2518 }
2519 }
2520
2521 pPatch->Core.Key = pCtx->eip;
2522 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2523 AssertRC(rc);
2524
2525 pVM->hm.s.cPatches++;
2526 return VINF_SUCCESS;
2527 }
2528
2529 /*
2530 * Save invalid patch, so we will not try again.
2531 */
2532 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2533 pPatch->Core.Key = pCtx->eip;
2534 pPatch->enmType = HMTPRINSTR_INVALID;
2535 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2536 AssertRC(rc);
2537 pVM->hm.s.cPatches++;
2538 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2539 return VINF_SUCCESS;
2540}
2541
2542
2543/**
2544 * Callback to patch a TPR instruction (jump to generated code).
2545 *
2546 * @returns VBox strict status code.
2547 * @param pVM The cross context VM structure.
2548 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2549 * @param pvUser User specified CPU context.
2550 *
2551 */
2552static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2553{
2554 /*
2555 * Only execute the handler on the VCPU the original patch request was
2556 * issued. (The other CPU(s) might not yet have switched to protected
2557 * mode, nor have the correct memory context.)
2558 */
2559 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2560 if (pVCpu->idCpu != idCpu)
2561 return VINF_SUCCESS;
2562
2563 /*
2564 * We're racing other VCPUs here, so don't try patch the instruction twice
2565 * and make sure there is still room for our patch record.
2566 */
2567 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2568 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2569 if (pPatch)
2570 {
2571 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2572 return VINF_SUCCESS;
2573 }
2574 uint32_t const idx = pVM->hm.s.cPatches;
2575 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2576 {
2577 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2578 return VINF_SUCCESS;
2579 }
2580 pPatch = &pVM->hm.s.aPatches[idx];
2581
2582 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2583 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2584
2585 /*
2586 * Disassemble the instruction and get cracking.
2587 */
2588 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2589 uint32_t cbOp;
2590 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2591 AssertRC(rc);
2592 if ( rc == VINF_SUCCESS
2593 && pDis->pCurInstr->uOpcode == OP_MOV
2594 && cbOp >= 5)
2595 {
2596 uint8_t aPatch[64];
2597 uint32_t off = 0;
2598
2599 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2600 AssertRC(rc);
2601
2602 pPatch->cbOp = cbOp;
2603 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2604
2605 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2606 {
2607 /*
2608 * TPR write:
2609 *
2610 * push ECX [51]
2611 * push EDX [52]
2612 * push EAX [50]
2613 * xor EDX,EDX [31 D2]
2614 * mov EAX,EAX [89 C0]
2615 * or
2616 * mov EAX,0000000CCh [B8 CC 00 00 00]
2617 * mov ECX,0C0000082h [B9 82 00 00 C0]
2618 * wrmsr [0F 30]
2619 * pop EAX [58]
2620 * pop EDX [5A]
2621 * pop ECX [59]
2622 * jmp return_address [E9 return_address]
2623 */
2624 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2625
2626 aPatch[off++] = 0x51; /* push ecx */
2627 aPatch[off++] = 0x52; /* push edx */
2628 if (!fUsesEax)
2629 aPatch[off++] = 0x50; /* push eax */
2630 aPatch[off++] = 0x31; /* xor edx, edx */
2631 aPatch[off++] = 0xd2;
2632 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2633 {
2634 if (!fUsesEax)
2635 {
2636 aPatch[off++] = 0x89; /* mov eax, src_reg */
2637 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2638 }
2639 }
2640 else
2641 {
2642 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2643 aPatch[off++] = 0xb8; /* mov eax, immediate */
2644 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2645 off += sizeof(uint32_t);
2646 }
2647 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2648 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2649 off += sizeof(uint32_t);
2650
2651 aPatch[off++] = 0x0f; /* wrmsr */
2652 aPatch[off++] = 0x30;
2653 if (!fUsesEax)
2654 aPatch[off++] = 0x58; /* pop eax */
2655 aPatch[off++] = 0x5a; /* pop edx */
2656 aPatch[off++] = 0x59; /* pop ecx */
2657 }
2658 else
2659 {
2660 /*
2661 * TPR read:
2662 *
2663 * push ECX [51]
2664 * push EDX [52]
2665 * push EAX [50]
2666 * mov ECX,0C0000082h [B9 82 00 00 C0]
2667 * rdmsr [0F 32]
2668 * mov EAX,EAX [89 C0]
2669 * pop EAX [58]
2670 * pop EDX [5A]
2671 * pop ECX [59]
2672 * jmp return_address [E9 return_address]
2673 */
2674 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2675
2676 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2677 aPatch[off++] = 0x51; /* push ecx */
2678 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2679 aPatch[off++] = 0x52; /* push edx */
2680 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2681 aPatch[off++] = 0x50; /* push eax */
2682
2683 aPatch[off++] = 0x31; /* xor edx, edx */
2684 aPatch[off++] = 0xd2;
2685
2686 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2687 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2688 off += sizeof(uint32_t);
2689
2690 aPatch[off++] = 0x0f; /* rdmsr */
2691 aPatch[off++] = 0x32;
2692
2693 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2694 {
2695 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2696 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2697 }
2698
2699 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2700 aPatch[off++] = 0x58; /* pop eax */
2701 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2702 aPatch[off++] = 0x5a; /* pop edx */
2703 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2704 aPatch[off++] = 0x59; /* pop ecx */
2705 }
2706 aPatch[off++] = 0xe9; /* jmp return_address */
2707 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2708 off += sizeof(RTRCUINTPTR);
2709
2710 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2711 {
2712 /* Write new code to the patch buffer. */
2713 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2714 AssertRC(rc);
2715
2716#ifdef LOG_ENABLED
2717 uint32_t cbCurInstr;
2718 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2719 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2720 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2721 {
2722 char szOutput[256];
2723 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2724 szOutput, sizeof(szOutput), &cbCurInstr);
2725 if (RT_SUCCESS(rc))
2726 Log(("Patch instr %s\n", szOutput));
2727 else
2728 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2729 }
2730#endif
2731
2732 pPatch->aNewOpcode[0] = 0xE9;
2733 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2734
2735 /* Overwrite the TPR instruction with a jump. */
2736 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2737 AssertRC(rc);
2738
2739 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2740
2741 pVM->hm.s.pFreeGuestPatchMem += off;
2742 pPatch->cbNewOp = 5;
2743
2744 pPatch->Core.Key = pCtx->eip;
2745 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2746 AssertRC(rc);
2747
2748 pVM->hm.s.cPatches++;
2749 pVM->hm.s.fTPRPatchingActive = true;
2750 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2751 return VINF_SUCCESS;
2752 }
2753
2754 Log(("Ran out of space in our patch buffer!\n"));
2755 }
2756 else
2757 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2758
2759
2760 /*
2761 * Save invalid patch, so we will not try again.
2762 */
2763 pPatch = &pVM->hm.s.aPatches[idx];
2764 pPatch->Core.Key = pCtx->eip;
2765 pPatch->enmType = HMTPRINSTR_INVALID;
2766 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2767 AssertRC(rc);
2768 pVM->hm.s.cPatches++;
2769 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2770 return VINF_SUCCESS;
2771}
2772
2773
2774/**
2775 * Attempt to patch TPR mmio instructions.
2776 *
2777 * @returns VBox status code.
2778 * @param pVM The cross context VM structure.
2779 * @param pVCpu The cross context virtual CPU structure.
2780 */
2781VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2782{
2783 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2784 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2785 (void *)(uintptr_t)pVCpu->idCpu);
2786 AssertRC(rc);
2787 return rc;
2788}
2789
2790
2791/**
2792 * Checks if we need to reschedule due to VMM device heap changes.
2793 *
2794 * @returns true if a reschedule is required, otherwise false.
2795 * @param pVM The cross context VM structure.
2796 * @param pCtx VM execution context.
2797 */
2798VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2799{
2800 /*
2801 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2802 * when the unrestricted guest execution feature is missing (VT-x only).
2803 */
2804 if ( pVM->hm.s.vmx.fEnabled
2805 && !pVM->hm.s.vmx.fUnrestrictedGuest
2806 && CPUMIsGuestInRealModeEx(pCtx)
2807 && !PDMVmmDevHeapIsEnabled(pVM))
2808 return true;
2809
2810 return false;
2811}
2812
2813
2814/**
2815 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2816 * event settings changes.
2817 *
2818 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2819 * function is just updating the VM globals.
2820 *
2821 * @param pVM The VM cross context VM structure.
2822 * @thread EMT(0)
2823 */
2824VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2825{
2826 /* Interrupts. */
2827 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2828 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2829
2830 /* CPU Exceptions. */
2831 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2832 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2833 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2834 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2835
2836 /* Common VM exits. */
2837 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2838 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2839 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2840 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2841
2842 /* Vendor specific VM exits. */
2843 if (HMR3IsVmxEnabled(pVM->pUVM))
2844 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2845 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2846 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2847 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2848 else
2849 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2850 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2851 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2852 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2853
2854 /* Done. */
2855 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2856}
2857
2858
2859/**
2860 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2861 *
2862 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2863 * per CPU settings.
2864 *
2865 * @param pVM The VM cross context VM structure.
2866 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2867 */
2868VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2869{
2870 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2871}
2872
2873
2874/**
2875 * Checks if we are currently using hardware acceleration.
2876 *
2877 * @returns true if hardware acceleration is being used, otherwise false.
2878 * @param pVCpu The cross context virtual CPU structure.
2879 */
2880VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2881{
2882 return pVCpu->hm.s.fActive;
2883}
2884
2885
2886/**
2887 * External interface for querying whether hardware acceleration is enabled.
2888 *
2889 * @returns true if VT-x or AMD-V is being used, otherwise false.
2890 * @param pUVM The user mode VM handle.
2891 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2892 */
2893VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2894{
2895 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2896 PVM pVM = pUVM->pVM;
2897 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2898 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2899}
2900
2901
2902/**
2903 * External interface for querying whether VT-x is being used.
2904 *
2905 * @returns true if VT-x is being used, otherwise false.
2906 * @param pUVM The user mode VM handle.
2907 * @sa HMR3IsSvmEnabled, HMIsEnabled
2908 */
2909VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2910{
2911 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2912 PVM pVM = pUVM->pVM;
2913 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2914 return pVM->hm.s.vmx.fEnabled
2915 && pVM->hm.s.vmx.fSupported
2916 && pVM->fHMEnabled;
2917}
2918
2919
2920/**
2921 * External interface for querying whether AMD-V is being used.
2922 *
2923 * @returns true if VT-x is being used, otherwise false.
2924 * @param pUVM The user mode VM handle.
2925 * @sa HMR3IsVmxEnabled, HMIsEnabled
2926 */
2927VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2928{
2929 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2930 PVM pVM = pUVM->pVM;
2931 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2932 return pVM->hm.s.svm.fEnabled
2933 && pVM->hm.s.svm.fSupported
2934 && pVM->fHMEnabled;
2935}
2936
2937
2938/**
2939 * Checks if we are currently using nested paging.
2940 *
2941 * @returns true if nested paging is being used, otherwise false.
2942 * @param pUVM The user mode VM handle.
2943 */
2944VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2945{
2946 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2947 PVM pVM = pUVM->pVM;
2948 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2949 return pVM->hm.s.fNestedPaging;
2950}
2951
2952
2953/**
2954 * Checks if virtualized APIC registers is enabled.
2955 *
2956 * When enabled this feature allows the hardware to access most of the
2957 * APIC registers in the virtual-APIC page without causing VM-exits. See
2958 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2959 *
2960 * @returns true if virtualized APIC registers is enabled, otherwise
2961 * false.
2962 * @param pUVM The user mode VM handle.
2963 */
2964VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2965{
2966 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2967 PVM pVM = pUVM->pVM;
2968 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2969 return pVM->hm.s.fVirtApicRegs;
2970}
2971
2972
2973/**
2974 * Checks if APIC posted-interrupt processing is enabled.
2975 *
2976 * This returns whether we can deliver interrupts to the guest without
2977 * leaving guest-context by updating APIC state from host-context.
2978 *
2979 * @returns true if APIC posted-interrupt processing is enabled,
2980 * otherwise false.
2981 * @param pUVM The user mode VM handle.
2982 */
2983VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2984{
2985 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2986 PVM pVM = pUVM->pVM;
2987 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2988 return pVM->hm.s.fPostedIntrs;
2989}
2990
2991
2992/**
2993 * Checks if we are currently using VPID in VT-x mode.
2994 *
2995 * @returns true if VPID is being used, otherwise false.
2996 * @param pUVM The user mode VM handle.
2997 */
2998VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2999{
3000 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3001 PVM pVM = pUVM->pVM;
3002 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3003 return pVM->hm.s.vmx.fVpid;
3004}
3005
3006
3007/**
3008 * Checks if we are currently using VT-x unrestricted execution,
3009 * aka UX.
3010 *
3011 * @returns true if UX is being used, otherwise false.
3012 * @param pUVM The user mode VM handle.
3013 */
3014VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3015{
3016 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3017 PVM pVM = pUVM->pVM;
3018 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3019 return pVM->hm.s.vmx.fUnrestrictedGuest
3020 || pVM->hm.s.svm.fSupported;
3021}
3022
3023
3024/**
3025 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3026 *
3027 * @returns true if an internal event is pending, otherwise false.
3028 * @param pVCpu The cross context virtual CPU structure.
3029 */
3030VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3031{
3032 return HMIsEnabled(pVCpu->pVMR3)
3033 && pVCpu->hm.s.Event.fPending;
3034}
3035
3036
3037/**
3038 * Checks if the VMX-preemption timer is being used.
3039 *
3040 * @returns true if the VMX-preemption timer is being used, otherwise false.
3041 * @param pVM The cross context VM structure.
3042 */
3043VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3044{
3045 return HMIsEnabled(pVM)
3046 && pVM->hm.s.vmx.fEnabled
3047 && pVM->hm.s.vmx.fUsePreemptTimer;
3048}
3049
3050
3051/**
3052 * Check fatal VT-x/AMD-V error and produce some meaningful
3053 * log release message.
3054 *
3055 * @param pVM The cross context VM structure.
3056 * @param iStatusCode VBox status code.
3057 */
3058VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3059{
3060 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3061 {
3062 PVMCPU pVCpu = &pVM->aCpus[i];
3063 switch (iStatusCode)
3064 {
3065 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3066 * might be getting inaccurate values for non-guru'ing EMTs. */
3067 case VERR_VMX_INVALID_VMCS_FIELD:
3068 break;
3069
3070 case VERR_VMX_INVALID_VMCS_PTR:
3071 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3072 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3073 pVCpu->hm.s.vmx.HCPhysVmcs));
3074 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3075 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3076 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3077 break;
3078
3079 case VERR_VMX_UNABLE_TO_START_VM:
3080 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3081 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3082 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3083
3084 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3085 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3086 {
3087 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3088 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3089 }
3090 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3091 {
3092 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3093 {
3094 uint32_t const u32Val = pVCpu->hm.s.vmx.u32PinCtls;
3095 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
3096 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
3097 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
3098 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
3099 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
3100 }
3101 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3102 {
3103 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls;
3104 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
3105 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
3106 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
3107 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
3108 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
3109 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
3110 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
3111 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
3112 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
3113 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
3114 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
3115 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
3116 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
3117 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
3118 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
3119 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
3120 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
3121 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
3122 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
3123 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
3124 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
3125 }
3126 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3127 {
3128 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls2;
3129 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
3130 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
3131 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
3132 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
3133 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
3134 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
3135 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
3136 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
3137 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
3138 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
3139 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
3140 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
3141 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
3142 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
3143 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
3144 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
3145 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
3146 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
3147 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
3148 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_FROM_PT );
3149 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
3150 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
3151 }
3152 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3153 {
3154 uint32_t const u32Val = pVCpu->hm.s.vmx.u32EntryCtls;
3155 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3156 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3157 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3158 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3159 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3160 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3161 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3162 }
3163 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3164 {
3165 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ExitCtls;
3166 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3167 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3168 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3169 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3170 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3171 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3172 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3173 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3174 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3175 }
3176 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3177 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3178 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3179 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3180 }
3181 /** @todo Log VM-entry event injection control fields
3182 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3183 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3184 break;
3185
3186 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3187 case VERR_VMX_INVALID_VMXON_PTR:
3188 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3189 case VERR_VMX_INVALID_GUEST_STATE:
3190 case VERR_VMX_UNEXPECTED_EXIT:
3191 case VERR_SVM_UNKNOWN_EXIT:
3192 case VERR_SVM_UNEXPECTED_EXIT:
3193 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3194 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3195 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3196 break;
3197 }
3198 }
3199
3200 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3201 {
3202 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3203 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.disallowed0));
3204 }
3205 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3206 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3207}
3208
3209
3210/**
3211 * Execute state save operation.
3212 *
3213 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3214 * is because we always save the VM state from ring-3 and thus most HM state
3215 * will be re-synced dynamically at runtime and don't need to be part of the VM
3216 * saved state.
3217 *
3218 * @returns VBox status code.
3219 * @param pVM The cross context VM structure.
3220 * @param pSSM SSM operation handle.
3221 */
3222static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3223{
3224 int rc;
3225
3226 Log(("hmR3Save:\n"));
3227
3228 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3229 {
3230 Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3231 if (pVM->cpum.ro.GuestFeatures.fSvm)
3232 {
3233 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3234 rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3235 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3236 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3237 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3238 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3239 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3240 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3241 rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3242 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3243 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3244 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3245 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3246 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3247 AssertRCReturn(rc, rc);
3248 }
3249 }
3250
3251 /* Save the guest patch data. */
3252 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3253 rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3254 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3255
3256 /* Store all the guest patch records too. */
3257 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3258 AssertRCReturn(rc, rc);
3259
3260 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3261 {
3262 AssertCompileSize(HMTPRINSTR, 4);
3263 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3264 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3265 rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3266 rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
3267 rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3268 rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3269 rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3270 rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3271 rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3272 rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3273 rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
3274 AssertRCReturn(rc, rc);
3275 }
3276
3277 return VINF_SUCCESS;
3278}
3279
3280
3281/**
3282 * Execute state load operation.
3283 *
3284 * @returns VBox status code.
3285 * @param pVM The cross context VM structure.
3286 * @param pSSM SSM operation handle.
3287 * @param uVersion Data layout version.
3288 * @param uPass The data pass.
3289 */
3290static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3291{
3292 int rc;
3293
3294 LogFlowFunc(("uVersion=%u\n", uVersion));
3295 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3296
3297 /*
3298 * Validate version.
3299 */
3300 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3301 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3302 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3303 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3304 {
3305 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3306 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3307 }
3308
3309 /*
3310 * Load per-VCPU state.
3311 */
3312 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3313 {
3314 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3315 {
3316 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3317 if (pVM->cpum.ro.GuestFeatures.fSvm)
3318 {
3319 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3320 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3321 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3322 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3323 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3324 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3325 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3326 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3327 rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3328 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3329 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3330 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3331 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3332 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3333 AssertRCReturn(rc, rc);
3334 }
3335 }
3336 else
3337 {
3338 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3339 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3340 rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3341 rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3342
3343 /* VMX fWasInRealMode related data. */
3344 uint32_t uDummy;
3345 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3346 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3347 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3348 AssertRCReturn(rc, rc);
3349 }
3350 }
3351
3352 /*
3353 * Load TPR patching data.
3354 */
3355 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3356 {
3357 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3358 rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3359 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3360
3361 /* Fetch all TPR patch records. */
3362 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3363 AssertRCReturn(rc, rc);
3364 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3365 {
3366 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3367 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3368 rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3369 rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
3370 rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3371 rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3372 rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3373
3374 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3375 pVM->hm.s.fTPRPatchingActive = true;
3376 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3377
3378 rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3379 rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3380 rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
3381 rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3382 AssertRCReturn(rc, rc);
3383
3384 LogFlow(("hmR3Load: patch %d\n", i));
3385 LogFlow(("Key = %x\n", pPatch->Core.Key));
3386 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3387 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3388 LogFlow(("type = %d\n", pPatch->enmType));
3389 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3390 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3391 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3392 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3393
3394 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3395 AssertRCReturn(rc, rc);
3396 }
3397 }
3398
3399 return VINF_SUCCESS;
3400}
3401
3402
3403/**
3404 * Gets the name of a VT-x exit code.
3405 *
3406 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3407 * @param uExit The VT-x exit to name.
3408 */
3409VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
3410{
3411 if (uExit < RT_ELEMENTS(g_apszVmxExitReasons))
3412 return g_apszVmxExitReasons[uExit];
3413 return NULL;
3414}
3415
3416
3417/**
3418 * Gets the name of an AMD-V exit code.
3419 *
3420 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3421 * @param uExit The AMD-V exit to name.
3422 */
3423VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
3424{
3425 if (uExit < RT_ELEMENTS(g_apszSvmExitReasons))
3426 return g_apszSvmExitReasons[uExit];
3427 return hmSvmGetSpecialExitReasonDesc(uExit);
3428}
3429
3430
3431/**
3432 * Displays HM info.
3433 *
3434 * @param pVM The cross context VM structure.
3435 * @param pHlp The info helper functions.
3436 * @param pszArgs Arguments, ignored.
3437 */
3438static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3439{
3440 NOREF(pszArgs);
3441 PVMCPU pVCpu = VMMGetCpu(pVM);
3442 if (!pVCpu)
3443 pVCpu = &pVM->aCpus[0];
3444
3445 if (HMIsEnabled(pVM))
3446 {
3447 if (pVM->hm.s.vmx.fSupported)
3448 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3449 else
3450 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3451 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3452 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3453 }
3454 else
3455 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3456}
3457
3458
3459/**
3460 * Displays the HM pending event.
3461 *
3462 * @param pVM The cross context VM structure.
3463 * @param pHlp The info helper functions.
3464 * @param pszArgs Arguments, ignored.
3465 */
3466static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3467{
3468 NOREF(pszArgs);
3469 PVMCPU pVCpu = VMMGetCpu(pVM);
3470 if (!pVCpu)
3471 pVCpu = &pVM->aCpus[0];
3472
3473 if (HMIsEnabled(pVM))
3474 {
3475 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3476 if (pVCpu->hm.s.Event.fPending)
3477 {
3478 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3479 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3480 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3481 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3482 }
3483 }
3484 else
3485 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3486}
3487
3488
3489/**
3490 * Displays the SVM nested-guest VMCB cache.
3491 *
3492 * @param pVM The cross context VM structure.
3493 * @param pHlp The info helper functions.
3494 * @param pszArgs Arguments, ignored.
3495 */
3496static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3497{
3498 NOREF(pszArgs);
3499 PVMCPU pVCpu = VMMGetCpu(pVM);
3500 if (!pVCpu)
3501 pVCpu = &pVM->aCpus[0];
3502
3503 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3504 if ( fSvmEnabled
3505 && pVM->cpum.ro.GuestFeatures.fSvm)
3506 {
3507 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3508 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3509 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3510 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3511 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3512 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3513 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3514 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3515 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3516 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3517 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3518 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3519 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3520 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3521 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3522 }
3523 else
3524 {
3525 if (!fSvmEnabled)
3526 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3527 else
3528 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3529 }
3530}
3531
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