VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 78043

Last change on this file since 78043 was 77591, checked in by vboxsync, 6 years ago

VMM/HM: Dump Real-on-v86 state as part of HM debugger info (and thus as part of guru meditations)
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  • Property svn:keywords set to Id Revision
File size: 148.0 KB
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1/* $Id: HM.cpp 77591 2019-03-07 04:49:52Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/pdmapi.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/ssm.h>
48#include <VBox/vmm/gim.h>
49#include <VBox/vmm/trpm.h>
50#include <VBox/vmm/dbgf.h>
51#include <VBox/vmm/iom.h>
52#include <VBox/vmm/iem.h>
53#include <VBox/vmm/patm.h>
54#include <VBox/vmm/csam.h>
55#include <VBox/vmm/selm.h>
56#include <VBox/vmm/nem.h>
57#ifdef VBOX_WITH_REM
58# include <VBox/vmm/rem.h>
59#endif
60#include <VBox/vmm/hm_vmx.h>
61#include <VBox/vmm/hm_svm.h>
62#include "HMInternal.h"
63#include <VBox/vmm/vm.h>
64#include <VBox/vmm/uvm.h>
65#include <VBox/err.h>
66#include <VBox/param.h>
67
68#include <iprt/assert.h>
69#include <VBox/log.h>
70#include <iprt/asm.h>
71#include <iprt/asm-amd64-x86.h>
72#include <iprt/env.h>
73#include <iprt/thread.h>
74
75
76/*********************************************************************************************************************************
77* Defined Constants And Macros *
78*********************************************************************************************************************************/
79/** @def HMVMX_REPORT_FEAT
80 * Reports VT-x feature to the release log.
81 *
82 * @param a_uAllowed1 Mask of allowed-1 feature bits.
83 * @param a_uAllowed0 Mask of allowed-0 feature bits.
84 * @param a_StrDesc The description string to report.
85 * @param a_Featflag Mask of the feature to report.
86 */
87#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
88 do { \
89 if ((a_uAllowed1) & (a_Featflag)) \
90 { \
91 if ((a_uAllowed0) & (a_Featflag)) \
92 LogRel(("HM: " a_StrDesc " (must be set)\n")); \
93 else \
94 LogRel(("HM: " a_StrDesc "\n")); \
95 } \
96 else \
97 LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
98 } while (0)
99
100/** @def HMVMX_REPORT_ALLOWED_FEAT
101 * Reports an allowed VT-x feature to the release log.
102 *
103 * @param a_uAllowed1 Mask of allowed-1 feature bits.
104 * @param a_StrDesc The description string to report.
105 * @param a_FeatFlag Mask of the feature to report.
106 */
107#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
108 do { \
109 if ((a_uAllowed1) & (a_FeatFlag)) \
110 LogRel(("HM: " a_StrDesc "\n")); \
111 else \
112 LogRel(("HM: " a_StrDesc " not supported\n")); \
113 } while (0)
114
115/** @def HMVMX_REPORT_MSR_CAP
116 * Reports MSR feature capability.
117 *
118 * @param a_MsrCaps Mask of MSR feature bits.
119 * @param a_StrDesc The description string to report.
120 * @param a_fCap Mask of the feature to report.
121 */
122#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
123 do { \
124 if ((a_MsrCaps) & (a_fCap)) \
125 LogRel(("HM: " a_StrDesc "\n")); \
126 } while (0)
127
128/** @def HMVMX_LOGREL_FEAT
129 * Dumps a feature flag from a bitmap of features to the release log.
130 *
131 * @param a_fVal The value of all the features.
132 * @param a_fMask The specific bitmask of the feature.
133 */
134#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
135 do { \
136 if ((a_fVal) & (a_fMask)) \
137 LogRel(("HM: %s\n", #a_fMask)); \
138 } while (0)
139
140
141/*********************************************************************************************************************************
142* Internal Functions *
143*********************************************************************************************************************************/
144static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
145static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
146static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
148static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
149static int hmR3InitFinalizeR3(PVM pVM);
150static int hmR3InitFinalizeR0(PVM pVM);
151static int hmR3InitFinalizeR0Intel(PVM pVM);
152static int hmR3InitFinalizeR0Amd(PVM pVM);
153static int hmR3TermCPU(PVM pVM);
154
155
156
157/**
158 * Initializes the HM.
159 *
160 * This is the very first component to really do init after CFGM so that we can
161 * establish the predominant execution engine for the VM prior to initializing
162 * other modules. It takes care of NEM initialization if needed (HM disabled or
163 * not available in HW).
164 *
165 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
166 * hypervisor API via NEM, and then back on raw-mode if that isn't available
167 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
168 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
169 * X, OS/2 and others).
170 *
171 * Note that a lot of the set up work is done in ring-0 and thus postponed till
172 * the ring-3 and ring-0 callback to HMR3InitCompleted.
173 *
174 * @returns VBox status code.
175 * @param pVM The cross context VM structure.
176 *
177 * @remarks Be careful with what we call here, since most of the VMM components
178 * are uninitialized.
179 */
180VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
181{
182 LogFlow(("HMR3Init\n"));
183
184 /*
185 * Assert alignment and sizes.
186 */
187 AssertCompileMemberAlignment(VM, hm.s, 32);
188 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
189
190 /*
191 * Register the saved state data unit.
192 */
193 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
194 NULL, NULL, NULL,
195 NULL, hmR3Save, NULL,
196 NULL, hmR3Load, NULL);
197 if (RT_FAILURE(rc))
198 return rc;
199
200 /*
201 * Register info handlers.
202 */
203 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
204 AssertRCReturn(rc, rc);
205
206 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
207 DBGFINFO_FLAGS_ALL_EMTS);
208 AssertRCReturn(rc, rc);
209
210 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
211 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
212 AssertRCReturn(rc, rc);
213
214 /*
215 * Read configuration.
216 */
217 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
218
219 /*
220 * Validate the HM settings.
221 */
222 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
223 "HMForced"
224 "|UseNEMInstead"
225 "|FallbackToNEM"
226 "|EnableNestedPaging"
227 "|EnableUX"
228 "|EnableLargePages"
229 "|EnableVPID"
230 "|IBPBOnVMExit"
231 "|IBPBOnVMEntry"
232 "|SpecCtrlByHost"
233 "|L1DFlushOnSched"
234 "|L1DFlushOnVMEntry"
235 "|TPRPatchingEnabled"
236 "|64bitEnabled"
237 "|Exclusive"
238 "|MaxResumeLoops"
239 "|VmxPleGap"
240 "|VmxPleWindow"
241 "|UseVmxPreemptTimer"
242 "|SvmPauseFilter"
243 "|SvmPauseFilterThreshold"
244 "|SvmVirtVmsaveVmload"
245 "|SvmVGif"
246 "|LovelyMesaDrvWorkaround",
247 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
248 if (RT_FAILURE(rc))
249 return rc;
250
251 /** @cfgm{/HM/HMForced, bool, false}
252 * Forces hardware virtualization, no falling back on raw-mode. HM must be
253 * enabled, i.e. /HMEnabled must be true. */
254 bool fHMForced;
255#ifdef VBOX_WITH_RAW_MODE
256 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
257 AssertRCReturn(rc, rc);
258 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
259 VERR_INVALID_PARAMETER);
260# if defined(RT_OS_DARWIN)
261 if (pVM->fHMEnabled)
262 fHMForced = true;
263# endif
264 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
265 VERR_INVALID_PARAMETER);
266 if (pVM->cCpus > 1)
267 fHMForced = true;
268#else /* !VBOX_WITH_RAW_MODE */
269 AssertRelease(pVM->fHMEnabled);
270 fHMForced = true;
271#endif /* !VBOX_WITH_RAW_MODE */
272
273 /** @cfgm{/HM/UseNEMInstead, bool, true}
274 * Don't use HM, use NEM instead. */
275 bool fUseNEMInstead = false;
276 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
277 AssertRCReturn(rc, rc);
278 if (fUseNEMInstead && pVM->fHMEnabled)
279 {
280 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
281 pVM->fHMEnabled = false;
282 }
283
284 /** @cfgm{/HM/FallbackToNEM, bool, true}
285 * Enables fallback on NEM. */
286 bool fFallbackToNEM = true;
287 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
288 AssertRCReturn(rc, rc);
289
290 /** @cfgm{/HM/EnableNestedPaging, bool, false}
291 * Enables nested paging (aka extended page tables). */
292 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
293 AssertRCReturn(rc, rc);
294
295 /** @cfgm{/HM/EnableUX, bool, true}
296 * Enables the VT-x unrestricted execution feature. */
297 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
298 AssertRCReturn(rc, rc);
299
300 /** @cfgm{/HM/EnableLargePages, bool, false}
301 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
302 * page table walking and maybe better TLB hit rate in some cases. */
303 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
304 AssertRCReturn(rc, rc);
305
306 /** @cfgm{/HM/EnableVPID, bool, false}
307 * Enables the VT-x VPID feature. */
308 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
309 AssertRCReturn(rc, rc);
310
311 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
312 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
313 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
314 AssertRCReturn(rc, rc);
315
316 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
317 * Enables AMD64 cpu features.
318 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
319 * already have the support. */
320#ifdef VBOX_ENABLE_64_BITS_GUESTS
321 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
322 AssertLogRelRCReturn(rc, rc);
323#else
324 pVM->hm.s.fAllow64BitGuests = false;
325#endif
326
327 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
328 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
329 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
330 * latest PAUSE instruction to be start of a new PAUSE loop.
331 */
332 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
333 AssertRCReturn(rc, rc);
334
335 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
336 * The pause-filter exiting window in TSC ticks. When the number of ticks
337 * between the current PAUSE instruction and first PAUSE of a loop exceeds
338 * VmxPleWindow, a VM-exit is triggered.
339 *
340 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
341 */
342 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
343 AssertRCReturn(rc, rc);
344
345 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
346 * A counter that is decrement each time a PAUSE instruction is executed by the
347 * guest. When the counter is 0, a \#VMEXIT is triggered.
348 *
349 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
350 */
351 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
352 AssertRCReturn(rc, rc);
353
354 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
355 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
356 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
357 * PauseFilter count is reset to its initial value. However, if PAUSE is
358 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
359 * be triggered.
360 *
361 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
362 * activated.
363 */
364 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
365 AssertRCReturn(rc, rc);
366
367 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
368 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
369 * available. */
370 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
371 AssertRCReturn(rc, rc);
372
373 /** @cfgm{/HM/SvmVGif, bool, true}
374 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
375 * if it's available. */
376 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
377 AssertRCReturn(rc, rc);
378
379 /** @cfgm{/HM/Exclusive, bool}
380 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
381 * global init for each host CPU. If false, we do local init each time we wish
382 * to execute guest code.
383 *
384 * On Windows, default is false due to the higher risk of conflicts with other
385 * hypervisors.
386 *
387 * On Mac OS X, this setting is ignored since the code does not handle local
388 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
389 */
390#if defined(RT_OS_DARWIN)
391 pVM->hm.s.fGlobalInit = true;
392#else
393 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
394# if defined(RT_OS_WINDOWS)
395 false
396# else
397 true
398# endif
399 );
400 AssertLogRelRCReturn(rc, rc);
401#endif
402
403 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
404 * The number of times to resume guest execution before we forcibly return to
405 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
406 * determines the default value. */
407 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
408 AssertLogRelRCReturn(rc, rc);
409
410 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
411 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
412 * available. */
413 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
414 AssertLogRelRCReturn(rc, rc);
415
416 /** @cfgm{/HM/IBPBOnVMExit, bool}
417 * Costly paranoia setting. */
418 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
419 AssertLogRelRCReturn(rc, rc);
420
421 /** @cfgm{/HM/IBPBOnVMEntry, bool}
422 * Costly paranoia setting. */
423 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
424 AssertLogRelRCReturn(rc, rc);
425
426 /** @cfgm{/HM/L1DFlushOnSched, bool, true}
427 * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
428 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
429 AssertLogRelRCReturn(rc, rc);
430
431 /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
432 * CVS-2018-3646 workaround, ignored on CPUs that aren't affected. */
433 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
434 AssertLogRelRCReturn(rc, rc);
435
436 /* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
437 if (pVM->hm.s.fL1dFlushOnVmEntry)
438 pVM->hm.s.fL1dFlushOnSched = false;
439
440 /** @cfgm{/HM/SpecCtrlByHost, bool}
441 * Another expensive paranoia setting. */
442 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
443 AssertLogRelRCReturn(rc, rc);
444
445 /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
446 * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
447 * the hypervisor it is running under. */
448 bool f;
449 rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
450 AssertLogRelRCReturn(rc, rc);
451 for (VMCPUID i = 0; i < pVM->cCpus; i++)
452 pVM->aCpus[i].hm.s.fTrapXcptGpForLovelyMesaDrv = f;
453
454 /*
455 * Check if VT-x or AMD-v support according to the users wishes.
456 */
457 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
458 * VERR_SVM_IN_USE. */
459 if (pVM->fHMEnabled)
460 {
461 uint32_t fCaps;
462 rc = SUPR3QueryVTCaps(&fCaps);
463 if (RT_SUCCESS(rc))
464 {
465 if (fCaps & SUPVTCAPS_AMD_V)
466 {
467 pVM->hm.s.svm.fSupported = true;
468 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
469 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
470 }
471 else if (fCaps & SUPVTCAPS_VT_X)
472 {
473 const char *pszWhy;
474 rc = SUPR3QueryVTxSupported(&pszWhy);
475 if (RT_SUCCESS(rc))
476 {
477 pVM->hm.s.vmx.fSupported = true;
478 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
479 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
480 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
481 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
482 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
483 }
484 else
485 {
486 /*
487 * Before failing, try fallback to NEM if we're allowed to do that.
488 */
489 pVM->fHMEnabled = false;
490 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
491 if (fFallbackToNEM)
492 {
493 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
494 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
495
496 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
497 if ( RT_SUCCESS(rc2)
498 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
499 rc = VINF_SUCCESS;
500 }
501 if (RT_FAILURE(rc))
502 {
503 if (fHMForced)
504 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
505
506 /* Fall back to raw-mode. */
507 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
508 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
509 }
510 }
511 }
512 else
513 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
514 VERR_INTERNAL_ERROR_5);
515
516 /*
517 * Do we require a little bit or raw-mode for 64-bit guest execution?
518 */
519 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
520 && pVM->fHMEnabled
521 && pVM->hm.s.fAllow64BitGuests;
522
523 /*
524 * Disable nested paging and unrestricted guest execution now if they're
525 * configured so that CPUM can make decisions based on our configuration.
526 */
527 Assert(!pVM->hm.s.fNestedPaging);
528 if (pVM->hm.s.fAllowNestedPaging)
529 {
530 if (fCaps & SUPVTCAPS_NESTED_PAGING)
531 pVM->hm.s.fNestedPaging = true;
532 else
533 pVM->hm.s.fAllowNestedPaging = false;
534 }
535
536 if (fCaps & SUPVTCAPS_VT_X)
537 {
538 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
539 if (pVM->hm.s.vmx.fAllowUnrestricted)
540 {
541 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
542 && pVM->hm.s.fNestedPaging)
543 pVM->hm.s.vmx.fUnrestrictedGuest = true;
544 else
545 pVM->hm.s.vmx.fAllowUnrestricted = false;
546 }
547 }
548 }
549 else
550 {
551 const char *pszMsg;
552 switch (rc)
553 {
554 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
555 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
556 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
557 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
558 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
559 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
560 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
561 default:
562 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
563 }
564
565 /*
566 * Before failing, try fallback to NEM if we're allowed to do that.
567 */
568 pVM->fHMEnabled = false;
569 if (fFallbackToNEM)
570 {
571 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
572 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
573 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
574 if ( RT_SUCCESS(rc2)
575 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
576 rc = VINF_SUCCESS;
577 }
578 if (RT_FAILURE(rc))
579 {
580 if (fHMForced)
581 return VM_SET_ERROR(pVM, rc, pszMsg);
582
583 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
584 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
585 }
586 }
587 }
588 else
589 {
590 /*
591 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
592 */
593 if (!fUseNEMInstead)
594 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
595 else
596 {
597 rc = NEMR3Init(pVM, false /*fFallback*/, true);
598 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
599 if (RT_FAILURE(rc))
600 return rc;
601 }
602 }
603
604 return VINF_SUCCESS;
605}
606
607
608/**
609 * Initializes HM components after ring-3 phase has been fully initialized.
610 *
611 * @returns VBox status code.
612 * @param pVM The cross context VM structure.
613 */
614static int hmR3InitFinalizeR3(PVM pVM)
615{
616 LogFlow(("HMR3InitCPU\n"));
617
618 if (!HMIsEnabled(pVM))
619 return VINF_SUCCESS;
620
621 for (VMCPUID i = 0; i < pVM->cCpus; i++)
622 {
623 PVMCPU pVCpu = &pVM->aCpus[i];
624 pVCpu->hm.s.fActive = false;
625 pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
626 }
627
628#ifdef VBOX_WITH_STATISTICS
629 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
630 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
631 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
632 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
633 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
634#endif
635
636 /*
637 * Statistics.
638 */
639 for (VMCPUID i = 0; i < pVM->cCpus; i++)
640 {
641 PVMCPU pVCpu = &pVM->aCpus[i];
642 int rc;
643
644#ifdef VBOX_WITH_STATISTICS
645 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
646 "Profiling of RTMpPokeCpu.",
647 "/PROF/CPU%d/HM/Poke", i);
648 AssertRC(rc);
649 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
650 "Profiling of poke wait.",
651 "/PROF/CPU%d/HM/PokeWait", i);
652 AssertRC(rc);
653 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
654 "Profiling of poke wait when RTMpPokeCpu fails.",
655 "/PROF/CPU%d/HM/PokeWaitFailed", i);
656 AssertRC(rc);
657 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
658 "Profiling of entry until entering GC.",
659 "/PROF/CPU%d/HM/Entry", i);
660 AssertRC(rc);
661 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
662 "Profiling of pre-exit processing after returning from GC.",
663 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
664 AssertRC(rc);
665 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
666 "Profiling of exit handling (longjmps not included!)",
667 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
668 AssertRC(rc);
669
670 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
671 "I/O.",
672 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
673 AssertRC(rc);
674 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
675 "MOV CRx.",
676 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
677 AssertRC(rc);
678 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
679 "Exceptions, NMIs.",
680 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
681 AssertRC(rc);
682
683 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
684 "Profiling of importing guest state from hardware after VM-exit.",
685 "/PROF/CPU%d/HM/ImportGuestState", i);
686 AssertRC(rc);
687 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
688 "Profiling of exporting guest state to hardware before VM-entry.",
689 "/PROF/CPU%d/HM/ExportGuestState", i);
690 AssertRC(rc);
691 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
692 "Profiling of CPUMR0LoadGuestFPU.",
693 "/PROF/CPU%d/HM/LoadGuestFpuState", i);
694 AssertRC(rc);
695 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
696 "Profiling of execution of guest-code in hardware.",
697 "/PROF/CPU%d/HM/InGC", i);
698 AssertRC(rc);
699
700# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
701 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
702 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
703 "/PROF/CPU%d/HM/Switcher3264", i);
704 AssertRC(rc);
705# endif
706
707# ifdef HM_PROFILE_EXIT_DISPATCH
708 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
709 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
710 "/PROF/CPU%d/HM/ExitDispatch", i);
711 AssertRC(rc);
712# endif
713
714#endif
715# define HM_REG_COUNTER(a, b, desc) \
716 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
717 AssertRC(rc);
718
719#ifdef VBOX_WITH_STATISTICS
720 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
721 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
722 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
725 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
726 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
729 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
730 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
732 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
733 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
734 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
735 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
736 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
737 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
738 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
740 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
741 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
742 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
743 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
744 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
745 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
746 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
747 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
748 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
749 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
750 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
751 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
752 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
753 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
754 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
755 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
756 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
757 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
758 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
759 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
760 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
761 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
762 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
763 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
764 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
765 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
766 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
767 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
768#endif
769 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
770#ifdef VBOX_WITH_STATISTICS
771 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
772 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
773 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
774 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
775 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
776
777 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
778 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
779 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
780 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
781 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
782 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
783 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
784 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
785 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
786#endif
787 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
788#ifdef VBOX_WITH_STATISTICS
789 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptExportHostState, "/HM/CPU%d/Switch/ExportHostState", "Preemption caused us to re-export the host state.");
790
791 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
792 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
793 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
794 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
795
796 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
797 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
798 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
799 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
800 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
801 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
802 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
803 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
804 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
805 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
806 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
807 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
808 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
809 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
810
811 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
812 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
813 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
814
815 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
816 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
817 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
818
819 HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
820 HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
821 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
822
823 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
824 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
825 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr, "/HM/CPU%d/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
826
827 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelBase, "/HM/CPU%d/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
828 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit, "/HM/CPU%d/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
829 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr, "/HM/CPU%d/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
830
831 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
832 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
833 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
834 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
835
836#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
837 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
838 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
839#endif
840
841#undef HM_REG_COUNTER
842
843 bool const fCpuSupportsVmx = ASMIsIntelCpu() || ASMIsViaCentaurCpu() || ASMIsShanghaiCpu();
844
845 /*
846 * Guest Exit reason stats.
847 */
848 pVCpu->hm.s.paStatExitReason = NULL;
849 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
850 (void **)&pVCpu->hm.s.paStatExitReason);
851 AssertRCReturn(rc, rc);
852
853 if (fCpuSupportsVmx)
854 {
855 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
856 {
857 const char *pszExitName = HMGetVmxExitName(j);
858 if (pszExitName)
859 {
860 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
861 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
862 AssertRCReturn(rc, rc);
863 }
864 }
865 }
866 else
867 {
868 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
869 {
870 const char *pszExitName = HMGetSvmExitName(j);
871 if (pszExitName)
872 {
873 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
874 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
875 AssertRCReturn(rc, rc);
876 }
877 }
878 }
879 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
880 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
881 AssertRCReturn(rc, rc);
882 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
883# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
884 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
885# else
886 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
887# endif
888
889#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
890 /*
891 * Nested-guest VM-exit reason stats.
892 */
893 pVCpu->hm.s.paStatNestedExitReason = NULL;
894 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
895 (void **)&pVCpu->hm.s.paStatNestedExitReason);
896 AssertRCReturn(rc, rc);
897 if (fCpuSupportsVmx)
898 {
899 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
900 {
901 const char *pszExitName = HMGetVmxExitName(j);
902 if (pszExitName)
903 {
904 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
905 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
906 AssertRC(rc);
907 }
908 }
909 }
910 else
911 {
912 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
913 {
914 const char *pszExitName = HMGetSvmExitName(j);
915 if (pszExitName)
916 {
917 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
918 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
919 AssertRC(rc);
920 }
921 }
922 }
923 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
924 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
925 AssertRCReturn(rc, rc);
926 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
927# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
928 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
929# else
930 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
931# endif
932#endif
933
934 /*
935 * Injected events stats.
936 */
937 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
938 AssertRCReturn(rc, rc);
939 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
940# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
941 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
942# else
943 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
944# endif
945 for (unsigned j = 0; j < 255; j++)
946 {
947 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
948 "Injected event.",
949 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
950 }
951
952#endif /* VBOX_WITH_STATISTICS */
953 }
954
955#ifdef VBOX_WITH_CRASHDUMP_MAGIC
956 /*
957 * Magic marker for searching in crash dumps.
958 */
959 for (VMCPUID i = 0; i < pVM->cCpus; i++)
960 {
961 PVMCPU pVCpu = &pVM->aCpus[i];
962
963 PVMXVMCSBATCHCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsBatchCache;
964 strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
965 pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
966 }
967#endif
968
969 return VINF_SUCCESS;
970}
971
972
973/**
974 * Called when a init phase has completed.
975 *
976 * @returns VBox status code.
977 * @param pVM The cross context VM structure.
978 * @param enmWhat The phase that completed.
979 */
980VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
981{
982 switch (enmWhat)
983 {
984 case VMINITCOMPLETED_RING3:
985 return hmR3InitFinalizeR3(pVM);
986 case VMINITCOMPLETED_RING0:
987 return hmR3InitFinalizeR0(pVM);
988 default:
989 return VINF_SUCCESS;
990 }
991}
992
993
994/**
995 * Turns off normal raw mode features.
996 *
997 * @param pVM The cross context VM structure.
998 */
999static void hmR3DisableRawMode(PVM pVM)
1000{
1001/** @todo r=bird: HM shouldn't be doing this crap. */
1002 /* Reinit the paging mode to force the new shadow mode. */
1003 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1004 {
1005 PVMCPU pVCpu = &pVM->aCpus[i];
1006 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1007 }
1008}
1009
1010
1011/**
1012 * Initialize VT-x or AMD-V.
1013 *
1014 * @returns VBox status code.
1015 * @param pVM The cross context VM structure.
1016 */
1017static int hmR3InitFinalizeR0(PVM pVM)
1018{
1019 int rc;
1020
1021 if (!HMIsEnabled(pVM))
1022 return VINF_SUCCESS;
1023
1024 /*
1025 * Hack to allow users to work around broken BIOSes that incorrectly set
1026 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1027 */
1028 if ( !pVM->hm.s.vmx.fSupported
1029 && !pVM->hm.s.svm.fSupported
1030 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1031 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1032 {
1033 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1034 pVM->hm.s.svm.fSupported = true;
1035 pVM->hm.s.svm.fIgnoreInUseError = true;
1036 pVM->hm.s.rcInit = VINF_SUCCESS;
1037 }
1038
1039 /*
1040 * Report ring-0 init errors.
1041 */
1042 if ( !pVM->hm.s.vmx.fSupported
1043 && !pVM->hm.s.svm.fSupported)
1044 {
1045 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1046 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1047 switch (pVM->hm.s.rcInit)
1048 {
1049 case VERR_VMX_IN_VMX_ROOT_MODE:
1050 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1051 case VERR_VMX_NO_VMX:
1052 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1053 case VERR_VMX_MSR_VMX_DISABLED:
1054 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1055 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1056 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1057 case VERR_VMX_MSR_LOCKING_FAILED:
1058 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1059 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1060 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1061 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1062 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1063
1064 case VERR_SVM_IN_USE:
1065 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1066 case VERR_SVM_NO_SVM:
1067 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1068 case VERR_SVM_DISABLED:
1069 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1070 }
1071 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1072 }
1073
1074 /*
1075 * Enable VT-x or AMD-V on all host CPUs.
1076 */
1077 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1078 if (RT_FAILURE(rc))
1079 {
1080 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1081 HMR3CheckError(pVM, rc);
1082 return rc;
1083 }
1084
1085 /*
1086 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1087 * (Main should have taken care of this already)
1088 */
1089 if (!PDMHasIoApic(pVM))
1090 {
1091 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1092 pVM->hm.s.fTprPatchingAllowed = false;
1093 }
1094
1095 /*
1096 * Check if L1D flush is needed/possible.
1097 */
1098 if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1099 || pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1100 || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1101 || pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1102 || pVM->cpum.ro.HostFeatures.fArchRdclNo)
1103 pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1104
1105 /*
1106 * Sync options.
1107 */
1108 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1109 * That will require a little bit of work, of course. */
1110 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1111 {
1112 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1113 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1114 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1115 if (pVM->cpum.ro.HostFeatures.fIbpb)
1116 {
1117 if (pVM->hm.s.fIbpbOnVmExit)
1118 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1119 if (pVM->hm.s.fIbpbOnVmEntry)
1120 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1121 }
1122 if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1123 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_L1D_ENTRY;
1124 if (iCpu == 0)
1125 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool\n",
1126 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1127 pVM->hm.s.fL1dFlushOnSched));
1128 }
1129
1130 /*
1131 * Do the vendor specific initialization
1132 *
1133 * Note! We disable release log buffering here since we're doing relatively
1134 * lot of logging and doesn't want to hit the disk with each LogRel
1135 * statement.
1136 */
1137 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1138 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1139 if (pVM->hm.s.vmx.fSupported)
1140 rc = hmR3InitFinalizeR0Intel(pVM);
1141 else
1142 rc = hmR3InitFinalizeR0Amd(pVM);
1143 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1144 RTLogRelSetBuffering(fOldBuffered);
1145 pVM->hm.s.fInitialized = true;
1146
1147 return rc;
1148}
1149
1150
1151/**
1152 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1153 */
1154static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1155{
1156 NOREF(pVM);
1157 NOREF(pvAllocation);
1158 NOREF(GCPhysAllocation);
1159}
1160
1161
1162/**
1163 * Returns a description of the VMCS (and associated regions') memory type given the
1164 * IA32_VMX_BASIC MSR.
1165 *
1166 * @returns The descriptive memory type.
1167 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1168 */
1169static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1170{
1171 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1172 switch (uMemType)
1173 {
1174 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1175 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1176 }
1177 return "Unknown";
1178}
1179
1180
1181/**
1182 * Returns a single-line description of all the activity-states supported by the CPU
1183 * given the IA32_VMX_MISC MSR.
1184 *
1185 * @returns All supported activity states.
1186 * @param uMsrMisc IA32_VMX_MISC MSR value.
1187 */
1188static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1189{
1190 static const char * const s_apszActStates[] =
1191 {
1192 "",
1193 " ( HLT )",
1194 " ( SHUTDOWN )",
1195 " ( HLT SHUTDOWN )",
1196 " ( SIPI_WAIT )",
1197 " ( HLT SIPI_WAIT )",
1198 " ( SHUTDOWN SIPI_WAIT )",
1199 " ( HLT SHUTDOWN SIPI_WAIT )"
1200 };
1201 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1202 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1203 return s_apszActStates[idxActStates];
1204}
1205
1206
1207/**
1208 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1209 *
1210 * @param fFeatMsr The feature control MSR value.
1211 */
1212static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1213{
1214 uint64_t const val = fFeatMsr;
1215 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1216 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1217 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1218 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1219 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1220 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1221 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1222 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1223 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1224 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1225 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1226 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1227 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1228 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1229 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1230 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1231 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1232}
1233
1234
1235/**
1236 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1237 *
1238 * @param uBasicMsr The VMX basic MSR value.
1239 */
1240static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1241{
1242 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1243 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1244 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1245 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1246 "< 4 GB" : "None"));
1247 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1248 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1249 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1250 LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1251}
1252
1253
1254/**
1255 * Reports MSR_IA32_PINBASED_CTLS to the log.
1256 *
1257 * @param pVmxMsr Pointer to the VMX MSR.
1258 */
1259static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1260{
1261 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1262 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1263 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1264 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1265 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1266 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1267 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1268 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1269}
1270
1271
1272/**
1273 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1274 *
1275 * @param pVmxMsr Pointer to the VMX MSR.
1276 */
1277static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1278{
1279 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1280 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1281 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1282 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1283 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1284 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1285 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1286 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1287 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1288 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1289 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1290 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1291 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1292 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1293 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1294 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1295 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1296 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1297 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1298 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1299 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1300 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1301 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1302 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1303}
1304
1305
1306/**
1307 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1308 *
1309 * @param pVmxMsr Pointer to the VMX MSR.
1310 */
1311static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1312{
1313 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1314 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1315 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1316 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1317 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1318 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1319 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1320 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1321 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1322 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1323 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1324 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1325 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1326 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1327 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1328 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1329 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1330 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1331 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1332 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1333 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1334 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1335 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_FROM_PT", VMX_PROC_CTLS2_CONCEAL_FROM_PT);
1336 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1337 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1338}
1339
1340
1341/**
1342 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1343 *
1344 * @param pVmxMsr Pointer to the VMX MSR.
1345 */
1346static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1347{
1348 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1349 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1350 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1351 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1352 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1353 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1354 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1355 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1356 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1357 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1358}
1359
1360
1361/**
1362 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1363 *
1364 * @param pVmxMsr Pointer to the VMX MSR.
1365 */
1366static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1367{
1368 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1369 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1370 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1371 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1372 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1373 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1374 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1375 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1376 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1377 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1378 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1379 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1380}
1381
1382
1383/**
1384 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1385 *
1386 * @param fCaps The VMX EPT/VPID capability MSR value.
1387 */
1388static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1389{
1390 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1391 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1392 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1393 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1394 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1395 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1396 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1397 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1398 HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1399 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1400 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1401 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1402 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1403 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1404 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1405 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1406}
1407
1408
1409/**
1410 * Reports MSR_IA32_VMX_MISC MSR to the log.
1411 *
1412 * @param pVM Pointer to the VM.
1413 * @param fMisc The VMX misc. MSR value.
1414 */
1415static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1416{
1417 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1418 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1419 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1420 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1421 else
1422 {
1423 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1424 pVM->hm.s.vmx.cPreemptTimerShift));
1425 }
1426 LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1427 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1428 hmR3VmxGetActivityStateAllDesc(fMisc)));
1429 LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1430 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1431 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1432 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1433 VMX_MISC_MAX_MSRS(fMisc)));
1434 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1435 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1436 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1437 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1438}
1439
1440
1441/**
1442 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1443 *
1444 * @param uVmcsEnum The VMX VMCS enum MSR value.
1445 */
1446static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1447{
1448 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1449 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1450}
1451
1452
1453/**
1454 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1455 *
1456 * @param uVmFunc The VMX VMFUNC MSR value.
1457 */
1458static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1459{
1460 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1461 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1462}
1463
1464
1465/**
1466 * Reports VMX CR0, CR4 fixed MSRs.
1467 *
1468 * @param pMsrs Pointer to the VMX MSRs.
1469 */
1470static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1471{
1472 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1473 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1474 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1475 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1476}
1477
1478
1479/**
1480 * Finish VT-x initialization (after ring-0 init).
1481 *
1482 * @returns VBox status code.
1483 * @param pVM The cross context VM structure.
1484 */
1485static int hmR3InitFinalizeR0Intel(PVM pVM)
1486{
1487 int rc;
1488
1489 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1490 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1491
1492 LogRel(("HM: Using VT-x implementation 2.0\n"));
1493 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1494 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1495 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1496 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1497
1498 hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1499 hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1500
1501 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1502 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1503 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1504 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1505
1506 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1507 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1508
1509 if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1510 {
1511 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1512 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1513 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1514 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1515 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1516 }
1517
1518 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1519 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1520 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1521 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1522 if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1523 hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1524 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1525
1526 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1527 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1528 {
1529 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1530 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1531 }
1532
1533 /*
1534 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1535 */
1536 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1537 || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1538 VERR_HM_IPE_1);
1539 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1540 || ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1541 && pVM->hm.s.fNestedPaging),
1542 VERR_HM_IPE_1);
1543
1544 /*
1545 * Enable VPID if configured and supported.
1546 */
1547 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1548 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1549
1550#if 0
1551 /*
1552 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1553 */
1554 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1555 && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1556 pVM->hm.s.fVirtApicRegs = true;
1557
1558 /*
1559 * Enable posted-interrupt processing if supported.
1560 */
1561 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1562 * here. */
1563 if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1564 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1565 pVM->hm.s.fPostedIntrs = true;
1566#endif
1567
1568 /*
1569 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1570 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1571 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1572 */
1573 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1574 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1575 {
1576 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1577 LogRel(("HM: Disabled RDTSCP\n"));
1578 }
1579
1580 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1581 {
1582 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1583 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1584 if (RT_SUCCESS(rc))
1585 {
1586 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1587 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1588 esp. Figure 20-5.*/
1589 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1590 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1591
1592 /* Bit set to 0 means software interrupts are redirected to the
1593 8086 program interrupt handler rather than switching to
1594 protected-mode handler. */
1595 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1596
1597 /* Allow all port IO, so that port IO instructions do not cause
1598 exceptions and would instead cause a VM-exit (based on VT-x's
1599 IO bitmap which we currently configure to always cause an exit). */
1600 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1601 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1602
1603 /*
1604 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1605 * page table used in real and protected mode without paging with EPT.
1606 */
1607 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1608 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1609 {
1610 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1611 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1612 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1613 | X86_PDE4M_G;
1614 }
1615
1616 /* We convert it here every time as PCI regions could be reconfigured. */
1617 if (PDMVmmDevHeapIsEnabled(pVM))
1618 {
1619 RTGCPHYS GCPhys;
1620 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1621 AssertRCReturn(rc, rc);
1622 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1623
1624 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1625 AssertRCReturn(rc, rc);
1626 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1627 }
1628 }
1629 else
1630 {
1631 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1632 pVM->hm.s.vmx.pRealModeTSS = NULL;
1633 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1634 return VMSetError(pVM, rc, RT_SRC_POS,
1635 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1636 }
1637 }
1638
1639 LogRel((pVM->hm.s.fAllow64BitGuests
1640 ? "HM: Guest support: 32-bit and 64-bit\n"
1641 : "HM: Guest support: 32-bit only\n"));
1642
1643 /*
1644 * Call ring-0 to set up the VM.
1645 */
1646 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1647 if (rc != VINF_SUCCESS)
1648 {
1649 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1650 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1651 {
1652 PVMCPU pVCpu = &pVM->aCpus[i];
1653 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1654 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1655 }
1656 HMR3CheckError(pVM, rc);
1657 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1658 }
1659
1660 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1661 LogRel(("HM: Enabled VMX\n"));
1662 pVM->hm.s.vmx.fEnabled = true;
1663
1664 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1665
1666 /*
1667 * Change the CPU features.
1668 */
1669 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1670 if (pVM->hm.s.fAllow64BitGuests)
1671 {
1672 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1673 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1674 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1675 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1676 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1677 }
1678 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1679 (we reuse the host EFER in the switcher). */
1680 /** @todo this needs to be fixed properly!! */
1681 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1682 {
1683 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1684 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1685 else
1686 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1687 }
1688
1689 /*
1690 * Log configuration details.
1691 */
1692 if (pVM->hm.s.fNestedPaging)
1693 {
1694 LogRel(("HM: Enabled nested paging\n"));
1695 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1696 LogRel(("HM: EPT flush type = Single context\n"));
1697 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1698 LogRel(("HM: EPT flush type = All contexts\n"));
1699 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1700 LogRel(("HM: EPT flush type = Not supported\n"));
1701 else
1702 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1703
1704 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1705 LogRel(("HM: Enabled unrestricted guest execution\n"));
1706
1707#if HC_ARCH_BITS == 64
1708 if (pVM->hm.s.fLargePages)
1709 {
1710 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1711 PGMSetLargePageUsage(pVM, true);
1712 LogRel(("HM: Enabled large page support\n"));
1713 }
1714#endif
1715 }
1716 else
1717 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1718
1719 if (pVM->hm.s.fVirtApicRegs)
1720 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1721
1722 if (pVM->hm.s.fPostedIntrs)
1723 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1724
1725 if (pVM->hm.s.vmx.fVpid)
1726 {
1727 LogRel(("HM: Enabled VPID\n"));
1728 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1729 LogRel(("HM: VPID flush type = Individual addresses\n"));
1730 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1731 LogRel(("HM: VPID flush type = Single context\n"));
1732 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1733 LogRel(("HM: VPID flush type = All contexts\n"));
1734 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1735 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1736 else
1737 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1738 }
1739 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1740 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1741
1742 if (pVM->hm.s.vmx.fUsePreemptTimer)
1743 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1744 else
1745 LogRel(("HM: Disabled VMX-preemption timer\n"));
1746
1747 return VINF_SUCCESS;
1748}
1749
1750
1751/**
1752 * Finish AMD-V initialization (after ring-0 init).
1753 *
1754 * @returns VBox status code.
1755 * @param pVM The cross context VM structure.
1756 */
1757static int hmR3InitFinalizeR0Amd(PVM pVM)
1758{
1759 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1760
1761 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1762
1763 uint32_t u32Family;
1764 uint32_t u32Model;
1765 uint32_t u32Stepping;
1766 if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1767 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1768 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1769 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1770 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1771 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1772 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1773
1774 /*
1775 * Enumerate AMD-V features.
1776 */
1777 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1778 {
1779#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1780 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1781 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1782 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1783 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1784 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1785 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1786 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1787 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1788 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1789 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1790 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1791 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1792 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1793#undef HMSVM_REPORT_FEATURE
1794 };
1795
1796 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1797 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1798 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1799 {
1800 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1801 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1802 }
1803 if (fSvmFeatures)
1804 for (unsigned iBit = 0; iBit < 32; iBit++)
1805 if (RT_BIT_32(iBit) & fSvmFeatures)
1806 LogRel(("HM: Reserved bit %u\n", iBit));
1807
1808 /*
1809 * Nested paging is determined in HMR3Init, verify the sanity of that.
1810 */
1811 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1812 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1813 VERR_HM_IPE_1);
1814
1815#if 0
1816 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1817 * here. */
1818 if (RTR0IsPostIpiSupport())
1819 pVM->hm.s.fPostedIntrs = true;
1820#endif
1821
1822 /*
1823 * Call ring-0 to set up the VM.
1824 */
1825 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1826 if (rc != VINF_SUCCESS)
1827 {
1828 AssertMsgFailed(("%Rrc\n", rc));
1829 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1830 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1831 }
1832
1833 LogRel(("HM: Enabled SVM\n"));
1834 pVM->hm.s.svm.fEnabled = true;
1835
1836 if (pVM->hm.s.fNestedPaging)
1837 {
1838 LogRel(("HM: Enabled nested paging\n"));
1839
1840 /*
1841 * Enable large pages (2 MB) if applicable.
1842 */
1843#if HC_ARCH_BITS == 64
1844 if (pVM->hm.s.fLargePages)
1845 {
1846 PGMSetLargePageUsage(pVM, true);
1847 LogRel(("HM: Enabled large page support\n"));
1848 }
1849#endif
1850 }
1851
1852 if (pVM->hm.s.fVirtApicRegs)
1853 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1854
1855 if (pVM->hm.s.fPostedIntrs)
1856 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1857
1858 hmR3DisableRawMode(pVM);
1859
1860 /*
1861 * Change the CPU features.
1862 */
1863 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1864 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1865 if (pVM->hm.s.fAllow64BitGuests)
1866 {
1867 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1868 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1869 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1870 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1871 }
1872 /* Turn on NXE if PAE has been enabled. */
1873 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1874 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1875
1876 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1877
1878 LogRel((pVM->hm.s.fAllow64BitGuests
1879 ? "HM: Guest support: 32-bit and 64-bit\n"
1880 : "HM: Guest support: 32-bit only\n"));
1881
1882 return VINF_SUCCESS;
1883}
1884
1885
1886/**
1887 * Applies relocations to data and code managed by this
1888 * component. This function will be called at init and
1889 * whenever the VMM need to relocate it self inside the GC.
1890 *
1891 * @param pVM The cross context VM structure.
1892 */
1893VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1894{
1895 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1896
1897 /* Fetch the current paging mode during the relocate callback during state loading. */
1898 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1899 {
1900 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1901 {
1902 PVMCPU pVCpu = &pVM->aCpus[i];
1903 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1904 }
1905 }
1906#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1907 if (HMIsEnabled(pVM))
1908 {
1909 switch (PGMGetHostMode(pVM))
1910 {
1911 case PGMMODE_32_BIT:
1912 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1913 break;
1914
1915 case PGMMODE_PAE:
1916 case PGMMODE_PAE_NX:
1917 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1918 break;
1919
1920 default:
1921 AssertFailed();
1922 break;
1923 }
1924 }
1925#endif
1926 return;
1927}
1928
1929
1930/**
1931 * Terminates the HM.
1932 *
1933 * Termination means cleaning up and freeing all resources,
1934 * the VM itself is, at this point, powered off or suspended.
1935 *
1936 * @returns VBox status code.
1937 * @param pVM The cross context VM structure.
1938 */
1939VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1940{
1941 if (pVM->hm.s.vmx.pRealModeTSS)
1942 {
1943 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1944 pVM->hm.s.vmx.pRealModeTSS = 0;
1945 }
1946 hmR3TermCPU(pVM);
1947 return 0;
1948}
1949
1950
1951/**
1952 * Terminates the per-VCPU HM.
1953 *
1954 * @returns VBox status code.
1955 * @param pVM The cross context VM structure.
1956 */
1957static int hmR3TermCPU(PVM pVM)
1958{
1959 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1960 {
1961 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1962
1963#ifdef VBOX_WITH_STATISTICS
1964 if (pVCpu->hm.s.paStatExitReason)
1965 {
1966 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1967 pVCpu->hm.s.paStatExitReason = NULL;
1968 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1969 }
1970 if (pVCpu->hm.s.paStatInjectedIrqs)
1971 {
1972 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1973 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1974 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1975 }
1976#endif
1977
1978#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1979 memset(pVCpu->hm.s.vmx.VmcsBatchCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VmcsBatchCache.aMagic));
1980 pVCpu->hm.s.vmx.VmcsBatchCache.uMagic = 0;
1981 pVCpu->hm.s.vmx.VmcsBatchCache.uPos = 0xffffffff;
1982#endif
1983 }
1984 return 0;
1985}
1986
1987
1988/**
1989 * Resets a virtual CPU.
1990 *
1991 * Used by HMR3Reset and CPU hot plugging.
1992 *
1993 * @param pVCpu The cross context virtual CPU structure to reset.
1994 */
1995VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1996{
1997 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1998 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1999 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2000
2001 pVCpu->hm.s.fActive = false;
2002 pVCpu->hm.s.Event.fPending = false;
2003 pVCpu->hm.s.vmx.fWasInRealMode = true;
2004 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2005 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2006
2007 /* Reset the contents of the read cache. */
2008 PVMXVMCSBATCHCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsBatchCache;
2009 for (unsigned j = 0; j < pVmcsCache->Read.cValidEntries; j++)
2010 pVmcsCache->Read.aFieldVal[j] = 0;
2011
2012#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2013 /* Magic marker for searching in crash dumps. */
2014 strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
2015 pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2016#endif
2017}
2018
2019
2020/**
2021 * The VM is being reset.
2022 *
2023 * For the HM component this means that any GDT/LDT/TSS monitors
2024 * needs to be removed.
2025 *
2026 * @param pVM The cross context VM structure.
2027 */
2028VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2029{
2030 LogFlow(("HMR3Reset:\n"));
2031
2032 if (HMIsEnabled(pVM))
2033 hmR3DisableRawMode(pVM);
2034
2035 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2036 {
2037 PVMCPU pVCpu = &pVM->aCpus[i];
2038
2039 HMR3ResetCpu(pVCpu);
2040 }
2041
2042 /* Clear all patch information. */
2043 pVM->hm.s.pGuestPatchMem = 0;
2044 pVM->hm.s.pFreeGuestPatchMem = 0;
2045 pVM->hm.s.cbGuestPatchMem = 0;
2046 pVM->hm.s.cPatches = 0;
2047 pVM->hm.s.PatchTree = 0;
2048 pVM->hm.s.fTPRPatchingActive = false;
2049 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2050}
2051
2052
2053/**
2054 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2055 *
2056 * @returns VBox strict status code.
2057 * @param pVM The cross context VM structure.
2058 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2059 * @param pvUser Unused.
2060 */
2061static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2062{
2063 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2064
2065 /* Only execute the handler on the VCPU the original patch request was issued. */
2066 if (pVCpu->idCpu != idCpu)
2067 return VINF_SUCCESS;
2068
2069 Log(("hmR3RemovePatches\n"));
2070 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2071 {
2072 uint8_t abInstr[15];
2073 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2074 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2075 int rc;
2076
2077#ifdef LOG_ENABLED
2078 char szOutput[256];
2079 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2080 szOutput, sizeof(szOutput), NULL);
2081 if (RT_SUCCESS(rc))
2082 Log(("Patched instr: %s\n", szOutput));
2083#endif
2084
2085 /* Check if the instruction is still the same. */
2086 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2087 if (rc != VINF_SUCCESS)
2088 {
2089 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2090 continue; /* swapped out or otherwise removed; skip it. */
2091 }
2092
2093 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2094 {
2095 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2096 continue; /* skip it. */
2097 }
2098
2099 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2100 AssertRC(rc);
2101
2102#ifdef LOG_ENABLED
2103 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2104 szOutput, sizeof(szOutput), NULL);
2105 if (RT_SUCCESS(rc))
2106 Log(("Original instr: %s\n", szOutput));
2107#endif
2108 }
2109 pVM->hm.s.cPatches = 0;
2110 pVM->hm.s.PatchTree = 0;
2111 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2112 pVM->hm.s.fTPRPatchingActive = false;
2113 return VINF_SUCCESS;
2114}
2115
2116
2117/**
2118 * Worker for enabling patching in a VT-x/AMD-V guest.
2119 *
2120 * @returns VBox status code.
2121 * @param pVM The cross context VM structure.
2122 * @param idCpu VCPU to execute hmR3RemovePatches on.
2123 * @param pPatchMem Patch memory range.
2124 * @param cbPatchMem Size of the memory range.
2125 */
2126static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2127{
2128 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2129 AssertRC(rc);
2130
2131 pVM->hm.s.pGuestPatchMem = pPatchMem;
2132 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2133 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2134 return VINF_SUCCESS;
2135}
2136
2137
2138/**
2139 * Enable patching in a VT-x/AMD-V guest
2140 *
2141 * @returns VBox status code.
2142 * @param pVM The cross context VM structure.
2143 * @param pPatchMem Patch memory range.
2144 * @param cbPatchMem Size of the memory range.
2145 */
2146VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2147{
2148 VM_ASSERT_EMT(pVM);
2149 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2150 if (pVM->cCpus > 1)
2151 {
2152 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2153 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2154 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2155 AssertRC(rc);
2156 return rc;
2157 }
2158 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2159}
2160
2161
2162/**
2163 * Disable patching in a VT-x/AMD-V guest.
2164 *
2165 * @returns VBox status code.
2166 * @param pVM The cross context VM structure.
2167 * @param pPatchMem Patch memory range.
2168 * @param cbPatchMem Size of the memory range.
2169 */
2170VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2171{
2172 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2173 RT_NOREF2(pPatchMem, cbPatchMem);
2174
2175 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2176 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2177
2178 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2179 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2180 (void *)(uintptr_t)VMMGetCpuId(pVM));
2181 AssertRC(rc);
2182
2183 pVM->hm.s.pGuestPatchMem = 0;
2184 pVM->hm.s.pFreeGuestPatchMem = 0;
2185 pVM->hm.s.cbGuestPatchMem = 0;
2186 pVM->hm.s.fTPRPatchingActive = false;
2187 return VINF_SUCCESS;
2188}
2189
2190
2191/**
2192 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2193 *
2194 * @returns VBox strict status code.
2195 * @param pVM The cross context VM structure.
2196 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2197 * @param pvUser User specified CPU context.
2198 *
2199 */
2200static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2201{
2202 /*
2203 * Only execute the handler on the VCPU the original patch request was
2204 * issued. (The other CPU(s) might not yet have switched to protected
2205 * mode, nor have the correct memory context.)
2206 */
2207 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2208 if (pVCpu->idCpu != idCpu)
2209 return VINF_SUCCESS;
2210
2211 /*
2212 * We're racing other VCPUs here, so don't try patch the instruction twice
2213 * and make sure there is still room for our patch record.
2214 */
2215 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2216 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2217 if (pPatch)
2218 {
2219 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2220 return VINF_SUCCESS;
2221 }
2222 uint32_t const idx = pVM->hm.s.cPatches;
2223 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2224 {
2225 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2226 return VINF_SUCCESS;
2227 }
2228 pPatch = &pVM->hm.s.aPatches[idx];
2229
2230 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2231
2232 /*
2233 * Disassembler the instruction and get cracking.
2234 */
2235 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2236 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2237 uint32_t cbOp;
2238 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2239 AssertRC(rc);
2240 if ( rc == VINF_SUCCESS
2241 && pDis->pCurInstr->uOpcode == OP_MOV
2242 && cbOp >= 3)
2243 {
2244 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2245
2246 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2247 AssertRC(rc);
2248
2249 pPatch->cbOp = cbOp;
2250
2251 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2252 {
2253 /* write. */
2254 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2255 {
2256 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2257 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2258 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2259 }
2260 else
2261 {
2262 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2263 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2264 pPatch->uSrcOperand = pDis->Param2.uValue;
2265 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2266 }
2267 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2268 AssertRC(rc);
2269
2270 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2271 pPatch->cbNewOp = sizeof(s_abVMMCall);
2272 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2273 }
2274 else
2275 {
2276 /*
2277 * TPR Read.
2278 *
2279 * Found:
2280 * mov eax, dword [fffe0080] (5 bytes)
2281 * Check if next instruction is:
2282 * shr eax, 4
2283 */
2284 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2285
2286 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2287 uint8_t const cbOpMmio = cbOp;
2288 uint64_t const uSavedRip = pCtx->rip;
2289
2290 pCtx->rip += cbOp;
2291 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2292 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2293 pCtx->rip = uSavedRip;
2294
2295 if ( rc == VINF_SUCCESS
2296 && pDis->pCurInstr->uOpcode == OP_SHR
2297 && pDis->Param1.fUse == DISUSE_REG_GEN32
2298 && pDis->Param1.Base.idxGenReg == idxMmioReg
2299 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2300 && pDis->Param2.uValue == 4
2301 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2302 {
2303 uint8_t abInstr[15];
2304
2305 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2306 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2307 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2308 AssertRC(rc);
2309
2310 pPatch->cbOp = cbOpMmio + cbOp;
2311
2312 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2313 abInstr[0] = 0xf0;
2314 abInstr[1] = 0x0f;
2315 abInstr[2] = 0x20;
2316 abInstr[3] = 0xc0 | pDis->Param1.Base.idxGenReg;
2317 for (unsigned i = 4; i < pPatch->cbOp; i++)
2318 abInstr[i] = 0x90; /* nop */
2319
2320 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2321 AssertRC(rc);
2322
2323 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2324 pPatch->cbNewOp = pPatch->cbOp;
2325 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2326
2327 Log(("Acceptable read/shr candidate!\n"));
2328 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2329 }
2330 else
2331 {
2332 pPatch->enmType = HMTPRINSTR_READ;
2333 pPatch->uDstOperand = idxMmioReg;
2334
2335 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2336 AssertRC(rc);
2337
2338 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2339 pPatch->cbNewOp = sizeof(s_abVMMCall);
2340 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2341 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2342 }
2343 }
2344
2345 pPatch->Core.Key = pCtx->eip;
2346 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2347 AssertRC(rc);
2348
2349 pVM->hm.s.cPatches++;
2350 return VINF_SUCCESS;
2351 }
2352
2353 /*
2354 * Save invalid patch, so we will not try again.
2355 */
2356 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2357 pPatch->Core.Key = pCtx->eip;
2358 pPatch->enmType = HMTPRINSTR_INVALID;
2359 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2360 AssertRC(rc);
2361 pVM->hm.s.cPatches++;
2362 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2363 return VINF_SUCCESS;
2364}
2365
2366
2367/**
2368 * Callback to patch a TPR instruction (jump to generated code).
2369 *
2370 * @returns VBox strict status code.
2371 * @param pVM The cross context VM structure.
2372 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2373 * @param pvUser User specified CPU context.
2374 *
2375 */
2376static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2377{
2378 /*
2379 * Only execute the handler on the VCPU the original patch request was
2380 * issued. (The other CPU(s) might not yet have switched to protected
2381 * mode, nor have the correct memory context.)
2382 */
2383 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2384 if (pVCpu->idCpu != idCpu)
2385 return VINF_SUCCESS;
2386
2387 /*
2388 * We're racing other VCPUs here, so don't try patch the instruction twice
2389 * and make sure there is still room for our patch record.
2390 */
2391 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2392 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2393 if (pPatch)
2394 {
2395 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2396 return VINF_SUCCESS;
2397 }
2398 uint32_t const idx = pVM->hm.s.cPatches;
2399 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2400 {
2401 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2402 return VINF_SUCCESS;
2403 }
2404 pPatch = &pVM->hm.s.aPatches[idx];
2405
2406 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2407 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2408
2409 /*
2410 * Disassemble the instruction and get cracking.
2411 */
2412 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2413 uint32_t cbOp;
2414 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2415 AssertRC(rc);
2416 if ( rc == VINF_SUCCESS
2417 && pDis->pCurInstr->uOpcode == OP_MOV
2418 && cbOp >= 5)
2419 {
2420 uint8_t aPatch[64];
2421 uint32_t off = 0;
2422
2423 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2424 AssertRC(rc);
2425
2426 pPatch->cbOp = cbOp;
2427 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2428
2429 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2430 {
2431 /*
2432 * TPR write:
2433 *
2434 * push ECX [51]
2435 * push EDX [52]
2436 * push EAX [50]
2437 * xor EDX,EDX [31 D2]
2438 * mov EAX,EAX [89 C0]
2439 * or
2440 * mov EAX,0000000CCh [B8 CC 00 00 00]
2441 * mov ECX,0C0000082h [B9 82 00 00 C0]
2442 * wrmsr [0F 30]
2443 * pop EAX [58]
2444 * pop EDX [5A]
2445 * pop ECX [59]
2446 * jmp return_address [E9 return_address]
2447 */
2448 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2449
2450 aPatch[off++] = 0x51; /* push ecx */
2451 aPatch[off++] = 0x52; /* push edx */
2452 if (!fUsesEax)
2453 aPatch[off++] = 0x50; /* push eax */
2454 aPatch[off++] = 0x31; /* xor edx, edx */
2455 aPatch[off++] = 0xd2;
2456 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2457 {
2458 if (!fUsesEax)
2459 {
2460 aPatch[off++] = 0x89; /* mov eax, src_reg */
2461 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2462 }
2463 }
2464 else
2465 {
2466 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2467 aPatch[off++] = 0xb8; /* mov eax, immediate */
2468 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2469 off += sizeof(uint32_t);
2470 }
2471 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2472 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2473 off += sizeof(uint32_t);
2474
2475 aPatch[off++] = 0x0f; /* wrmsr */
2476 aPatch[off++] = 0x30;
2477 if (!fUsesEax)
2478 aPatch[off++] = 0x58; /* pop eax */
2479 aPatch[off++] = 0x5a; /* pop edx */
2480 aPatch[off++] = 0x59; /* pop ecx */
2481 }
2482 else
2483 {
2484 /*
2485 * TPR read:
2486 *
2487 * push ECX [51]
2488 * push EDX [52]
2489 * push EAX [50]
2490 * mov ECX,0C0000082h [B9 82 00 00 C0]
2491 * rdmsr [0F 32]
2492 * mov EAX,EAX [89 C0]
2493 * pop EAX [58]
2494 * pop EDX [5A]
2495 * pop ECX [59]
2496 * jmp return_address [E9 return_address]
2497 */
2498 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2499
2500 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2501 aPatch[off++] = 0x51; /* push ecx */
2502 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2503 aPatch[off++] = 0x52; /* push edx */
2504 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2505 aPatch[off++] = 0x50; /* push eax */
2506
2507 aPatch[off++] = 0x31; /* xor edx, edx */
2508 aPatch[off++] = 0xd2;
2509
2510 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2511 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2512 off += sizeof(uint32_t);
2513
2514 aPatch[off++] = 0x0f; /* rdmsr */
2515 aPatch[off++] = 0x32;
2516
2517 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2518 {
2519 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2520 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2521 }
2522
2523 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2524 aPatch[off++] = 0x58; /* pop eax */
2525 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2526 aPatch[off++] = 0x5a; /* pop edx */
2527 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2528 aPatch[off++] = 0x59; /* pop ecx */
2529 }
2530 aPatch[off++] = 0xe9; /* jmp return_address */
2531 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2532 off += sizeof(RTRCUINTPTR);
2533
2534 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2535 {
2536 /* Write new code to the patch buffer. */
2537 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2538 AssertRC(rc);
2539
2540#ifdef LOG_ENABLED
2541 uint32_t cbCurInstr;
2542 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2543 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2544 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2545 {
2546 char szOutput[256];
2547 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2548 szOutput, sizeof(szOutput), &cbCurInstr);
2549 if (RT_SUCCESS(rc))
2550 Log(("Patch instr %s\n", szOutput));
2551 else
2552 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2553 }
2554#endif
2555
2556 pPatch->aNewOpcode[0] = 0xE9;
2557 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2558
2559 /* Overwrite the TPR instruction with a jump. */
2560 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2561 AssertRC(rc);
2562
2563 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2564
2565 pVM->hm.s.pFreeGuestPatchMem += off;
2566 pPatch->cbNewOp = 5;
2567
2568 pPatch->Core.Key = pCtx->eip;
2569 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2570 AssertRC(rc);
2571
2572 pVM->hm.s.cPatches++;
2573 pVM->hm.s.fTPRPatchingActive = true;
2574 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2575 return VINF_SUCCESS;
2576 }
2577
2578 Log(("Ran out of space in our patch buffer!\n"));
2579 }
2580 else
2581 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2582
2583
2584 /*
2585 * Save invalid patch, so we will not try again.
2586 */
2587 pPatch = &pVM->hm.s.aPatches[idx];
2588 pPatch->Core.Key = pCtx->eip;
2589 pPatch->enmType = HMTPRINSTR_INVALID;
2590 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2591 AssertRC(rc);
2592 pVM->hm.s.cPatches++;
2593 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2594 return VINF_SUCCESS;
2595}
2596
2597
2598/**
2599 * Attempt to patch TPR mmio instructions.
2600 *
2601 * @returns VBox status code.
2602 * @param pVM The cross context VM structure.
2603 * @param pVCpu The cross context virtual CPU structure.
2604 */
2605VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2606{
2607 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2608 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2609 (void *)(uintptr_t)pVCpu->idCpu);
2610 AssertRC(rc);
2611 return rc;
2612}
2613
2614
2615/**
2616 * Checks if we need to reschedule due to VMM device heap changes.
2617 *
2618 * @returns true if a reschedule is required, otherwise false.
2619 * @param pVM The cross context VM structure.
2620 * @param pCtx VM execution context.
2621 */
2622VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2623{
2624 /*
2625 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2626 * when the unrestricted guest execution feature is missing (VT-x only).
2627 */
2628 if ( pVM->hm.s.vmx.fEnabled
2629 && !pVM->hm.s.vmx.fUnrestrictedGuest
2630 && CPUMIsGuestInRealModeEx(pCtx)
2631 && !PDMVmmDevHeapIsEnabled(pVM))
2632 return true;
2633
2634 return false;
2635}
2636
2637
2638/**
2639 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2640 * event settings changes.
2641 *
2642 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2643 * function is just updating the VM globals.
2644 *
2645 * @param pVM The VM cross context VM structure.
2646 * @thread EMT(0)
2647 */
2648VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2649{
2650 /* Interrupts. */
2651 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2652 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2653
2654 /* CPU Exceptions. */
2655 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2656 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2657 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2658 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2659
2660 /* Common VM exits. */
2661 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2662 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2663 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2664 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2665
2666 /* Vendor specific VM exits. */
2667 if (HMR3IsVmxEnabled(pVM->pUVM))
2668 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2669 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2670 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2671 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2672 else
2673 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2674 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2675 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2676 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2677
2678 /* Done. */
2679 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2680}
2681
2682
2683/**
2684 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2685 *
2686 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2687 * per CPU settings.
2688 *
2689 * @param pVM The VM cross context VM structure.
2690 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2691 */
2692VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2693{
2694 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2695}
2696
2697
2698/**
2699 * Checks if we are currently using hardware acceleration.
2700 *
2701 * @returns true if hardware acceleration is being used, otherwise false.
2702 * @param pVCpu The cross context virtual CPU structure.
2703 */
2704VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2705{
2706 return pVCpu->hm.s.fActive;
2707}
2708
2709
2710/**
2711 * External interface for querying whether hardware acceleration is enabled.
2712 *
2713 * @returns true if VT-x or AMD-V is being used, otherwise false.
2714 * @param pUVM The user mode VM handle.
2715 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2716 */
2717VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2718{
2719 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2720 PVM pVM = pUVM->pVM;
2721 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2722 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2723}
2724
2725
2726/**
2727 * External interface for querying whether VT-x is being used.
2728 *
2729 * @returns true if VT-x is being used, otherwise false.
2730 * @param pUVM The user mode VM handle.
2731 * @sa HMR3IsSvmEnabled, HMIsEnabled
2732 */
2733VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2734{
2735 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2736 PVM pVM = pUVM->pVM;
2737 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2738 return pVM->hm.s.vmx.fEnabled
2739 && pVM->hm.s.vmx.fSupported
2740 && pVM->fHMEnabled;
2741}
2742
2743
2744/**
2745 * External interface for querying whether AMD-V is being used.
2746 *
2747 * @returns true if VT-x is being used, otherwise false.
2748 * @param pUVM The user mode VM handle.
2749 * @sa HMR3IsVmxEnabled, HMIsEnabled
2750 */
2751VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2752{
2753 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2754 PVM pVM = pUVM->pVM;
2755 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2756 return pVM->hm.s.svm.fEnabled
2757 && pVM->hm.s.svm.fSupported
2758 && pVM->fHMEnabled;
2759}
2760
2761
2762/**
2763 * Checks if we are currently using nested paging.
2764 *
2765 * @returns true if nested paging is being used, otherwise false.
2766 * @param pUVM The user mode VM handle.
2767 */
2768VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2769{
2770 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2771 PVM pVM = pUVM->pVM;
2772 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2773 return pVM->hm.s.fNestedPaging;
2774}
2775
2776
2777/**
2778 * Checks if virtualized APIC registers is enabled.
2779 *
2780 * When enabled this feature allows the hardware to access most of the
2781 * APIC registers in the virtual-APIC page without causing VM-exits. See
2782 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2783 *
2784 * @returns true if virtualized APIC registers is enabled, otherwise
2785 * false.
2786 * @param pUVM The user mode VM handle.
2787 */
2788VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2789{
2790 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2791 PVM pVM = pUVM->pVM;
2792 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2793 return pVM->hm.s.fVirtApicRegs;
2794}
2795
2796
2797/**
2798 * Checks if APIC posted-interrupt processing is enabled.
2799 *
2800 * This returns whether we can deliver interrupts to the guest without
2801 * leaving guest-context by updating APIC state from host-context.
2802 *
2803 * @returns true if APIC posted-interrupt processing is enabled,
2804 * otherwise false.
2805 * @param pUVM The user mode VM handle.
2806 */
2807VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2808{
2809 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2810 PVM pVM = pUVM->pVM;
2811 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2812 return pVM->hm.s.fPostedIntrs;
2813}
2814
2815
2816/**
2817 * Checks if we are currently using VPID in VT-x mode.
2818 *
2819 * @returns true if VPID is being used, otherwise false.
2820 * @param pUVM The user mode VM handle.
2821 */
2822VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2823{
2824 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2825 PVM pVM = pUVM->pVM;
2826 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2827 return pVM->hm.s.vmx.fVpid;
2828}
2829
2830
2831/**
2832 * Checks if we are currently using VT-x unrestricted execution,
2833 * aka UX.
2834 *
2835 * @returns true if UX is being used, otherwise false.
2836 * @param pUVM The user mode VM handle.
2837 */
2838VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2839{
2840 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2841 PVM pVM = pUVM->pVM;
2842 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2843 return pVM->hm.s.vmx.fUnrestrictedGuest
2844 || pVM->hm.s.svm.fSupported;
2845}
2846
2847
2848/**
2849 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2850 *
2851 * @returns true if an internal event is pending, otherwise false.
2852 * @param pVCpu The cross context virtual CPU structure.
2853 */
2854VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2855{
2856 return HMIsEnabled(pVCpu->pVMR3)
2857 && pVCpu->hm.s.Event.fPending;
2858}
2859
2860
2861/**
2862 * Checks if the VMX-preemption timer is being used.
2863 *
2864 * @returns true if the VMX-preemption timer is being used, otherwise false.
2865 * @param pVM The cross context VM structure.
2866 */
2867VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2868{
2869 return HMIsEnabled(pVM)
2870 && pVM->hm.s.vmx.fEnabled
2871 && pVM->hm.s.vmx.fUsePreemptTimer;
2872}
2873
2874
2875/**
2876 * Check fatal VT-x/AMD-V error and produce some meaningful
2877 * log release message.
2878 *
2879 * @param pVM The cross context VM structure.
2880 * @param iStatusCode VBox status code.
2881 */
2882VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2883{
2884 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2885 {
2886 PVMCPU pVCpu = &pVM->aCpus[i];
2887 switch (iStatusCode)
2888 {
2889 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2890 * might be getting inaccurate values for non-guru'ing EMTs. */
2891 case VERR_VMX_INVALID_VMCS_FIELD:
2892 break;
2893
2894 case VERR_VMX_INVALID_VMCS_PTR:
2895 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2896 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VmcsPhys,
2897 pVCpu->hm.s.vmx.HCPhysVmcs));
2898 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2899 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2900 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2901 break;
2902
2903 case VERR_VMX_UNABLE_TO_START_VM:
2904 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2905 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
2906 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2907
2908 if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
2909 || pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
2910 {
2911 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2912 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2913 }
2914 else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
2915 {
2916 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.Ctls.u32PinCtls));
2917 {
2918 uint32_t const u32Val = pVCpu->hm.s.vmx.Ctls.u32PinCtls;
2919 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2920 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2921 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2922 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2923 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2924 }
2925 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.Ctls.u32ProcCtls));
2926 {
2927 uint32_t const u32Val = pVCpu->hm.s.vmx.Ctls.u32ProcCtls;
2928 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2929 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2930 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2931 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2932 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2933 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2934 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2935 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2936 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2937 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2938 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2939 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2940 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2941 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2942 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2943 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2944 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2945 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2946 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2947 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2948 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2949 }
2950 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.Ctls.u32ProcCtls2));
2951 {
2952 uint32_t const u32Val = pVCpu->hm.s.vmx.Ctls.u32ProcCtls2;
2953 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2954 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2955 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2956 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2957 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2958 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2959 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2960 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
2961 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2962 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2963 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2964 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2965 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2966 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2967 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2968 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2969 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2970 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2971 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2972 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_FROM_PT );
2973 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2974 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2975 }
2976 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.Ctls.u32EntryCtls));
2977 {
2978 uint32_t const u32Val = pVCpu->hm.s.vmx.Ctls.u32EntryCtls;
2979 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2980 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2981 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2982 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2983 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2984 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2985 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2986 }
2987 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.Ctls.u32ExitCtls));
2988 {
2989 uint32_t const u32Val = pVCpu->hm.s.vmx.Ctls.u32ExitCtls;
2990 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2991 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2992 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2993 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2994 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2995 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2996 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2997 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2998 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2999 }
3000 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3001 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3002 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3003 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3004 }
3005 /** @todo Log VM-entry event injection control fields
3006 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3007 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3008 break;
3009
3010 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3011 case VERR_VMX_INVALID_VMXON_PTR:
3012 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3013 case VERR_VMX_INVALID_GUEST_STATE:
3014 case VERR_VMX_UNEXPECTED_EXIT:
3015 case VERR_SVM_UNKNOWN_EXIT:
3016 case VERR_SVM_UNEXPECTED_EXIT:
3017 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3018 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3019 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3020 break;
3021 }
3022 }
3023
3024 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3025 {
3026 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3027 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3028 }
3029 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3030 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3031}
3032
3033
3034/**
3035 * Execute state save operation.
3036 *
3037 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3038 * is because we always save the VM state from ring-3 and thus most HM state
3039 * will be re-synced dynamically at runtime and don't need to be part of the VM
3040 * saved state.
3041 *
3042 * @returns VBox status code.
3043 * @param pVM The cross context VM structure.
3044 * @param pSSM SSM operation handle.
3045 */
3046static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3047{
3048 int rc;
3049
3050 Log(("hmR3Save:\n"));
3051
3052 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3053 {
3054 Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3055 if (pVM->cpum.ro.GuestFeatures.fSvm)
3056 {
3057 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3058 rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3059 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3060 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3061 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3062 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3063 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3064 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3065 rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3066 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3067 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3068 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3069 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3070 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3071 AssertRCReturn(rc, rc);
3072 }
3073 }
3074
3075 /* Save the guest patch data. */
3076 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3077 rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3078 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3079
3080 /* Store all the guest patch records too. */
3081 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3082 AssertRCReturn(rc, rc);
3083
3084 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3085 {
3086 AssertCompileSize(HMTPRINSTR, 4);
3087 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3088 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3089 rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3090 rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
3091 rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3092 rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3093 rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3094 rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3095 rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3096 rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3097 rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
3098 AssertRCReturn(rc, rc);
3099 }
3100
3101 return VINF_SUCCESS;
3102}
3103
3104
3105/**
3106 * Execute state load operation.
3107 *
3108 * @returns VBox status code.
3109 * @param pVM The cross context VM structure.
3110 * @param pSSM SSM operation handle.
3111 * @param uVersion Data layout version.
3112 * @param uPass The data pass.
3113 */
3114static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3115{
3116 int rc;
3117
3118 LogFlowFunc(("uVersion=%u\n", uVersion));
3119 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3120
3121 /*
3122 * Validate version.
3123 */
3124 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3125 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3126 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3127 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3128 {
3129 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3130 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3131 }
3132
3133 /*
3134 * Load per-VCPU state.
3135 */
3136 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3137 {
3138 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3139 {
3140 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3141 if (pVM->cpum.ro.GuestFeatures.fSvm)
3142 {
3143 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3144 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3145 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3146 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3147 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3148 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3149 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3150 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3151 rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3152 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3153 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3154 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3155 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3156 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3157 AssertRCReturn(rc, rc);
3158 }
3159 }
3160 else
3161 {
3162 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3163 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3164 rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3165 rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3166
3167 /* VMX fWasInRealMode related data. */
3168 uint32_t uDummy;
3169 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3170 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3171 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3172 AssertRCReturn(rc, rc);
3173 }
3174 }
3175
3176 /*
3177 * Load TPR patching data.
3178 */
3179 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3180 {
3181 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3182 rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3183 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3184
3185 /* Fetch all TPR patch records. */
3186 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3187 AssertRCReturn(rc, rc);
3188 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3189 {
3190 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3191 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3192 rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3193 rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
3194 rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3195 rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3196 rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3197
3198 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3199 pVM->hm.s.fTPRPatchingActive = true;
3200 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3201
3202 rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3203 rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3204 rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
3205 rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3206 AssertRCReturn(rc, rc);
3207
3208 LogFlow(("hmR3Load: patch %d\n", i));
3209 LogFlow(("Key = %x\n", pPatch->Core.Key));
3210 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3211 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3212 LogFlow(("type = %d\n", pPatch->enmType));
3213 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3214 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3215 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3216 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3217
3218 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3219 AssertRCReturn(rc, rc);
3220 }
3221 }
3222
3223 return VINF_SUCCESS;
3224}
3225
3226
3227/**
3228 * Displays HM info.
3229 *
3230 * @param pVM The cross context VM structure.
3231 * @param pHlp The info helper functions.
3232 * @param pszArgs Arguments, ignored.
3233 */
3234static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3235{
3236 NOREF(pszArgs);
3237 PVMCPU pVCpu = VMMGetCpu(pVM);
3238 if (!pVCpu)
3239 pVCpu = &pVM->aCpus[0];
3240
3241 if (HMIsEnabled(pVM))
3242 {
3243 if (pVM->hm.s.vmx.fSupported)
3244 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3245 else
3246 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3247 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3248 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3249 if (pVM->hm.s.vmx.fSupported)
3250 {
3251 bool const fRealOnV86Active = pVCpu->hm.s.vmx.RealMode.fRealOnV86Active;
3252 pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3253 if (fRealOnV86Active)
3254 {
3255 pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVCpu->hm.s.vmx.RealMode.Eflags.u32);
3256 pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVCpu->hm.s.vmx.RealMode.AttrCS.u);
3257 pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVCpu->hm.s.vmx.RealMode.AttrSS.u);
3258 pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVCpu->hm.s.vmx.RealMode.AttrDS.u);
3259 pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVCpu->hm.s.vmx.RealMode.AttrES.u);
3260 pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVCpu->hm.s.vmx.RealMode.AttrFS.u);
3261 pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVCpu->hm.s.vmx.RealMode.AttrGS.u);
3262 }
3263 }
3264 }
3265 else
3266 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3267}
3268
3269
3270/**
3271 * Displays the HM pending event.
3272 *
3273 * @param pVM The cross context VM structure.
3274 * @param pHlp The info helper functions.
3275 * @param pszArgs Arguments, ignored.
3276 */
3277static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3278{
3279 NOREF(pszArgs);
3280 PVMCPU pVCpu = VMMGetCpu(pVM);
3281 if (!pVCpu)
3282 pVCpu = &pVM->aCpus[0];
3283
3284 if (HMIsEnabled(pVM))
3285 {
3286 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3287 if (pVCpu->hm.s.Event.fPending)
3288 {
3289 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3290 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3291 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3292 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3293 }
3294 }
3295 else
3296 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3297}
3298
3299
3300/**
3301 * Displays the SVM nested-guest VMCB cache.
3302 *
3303 * @param pVM The cross context VM structure.
3304 * @param pHlp The info helper functions.
3305 * @param pszArgs Arguments, ignored.
3306 */
3307static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3308{
3309 NOREF(pszArgs);
3310 PVMCPU pVCpu = VMMGetCpu(pVM);
3311 if (!pVCpu)
3312 pVCpu = &pVM->aCpus[0];
3313
3314 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3315 if ( fSvmEnabled
3316 && pVM->cpum.ro.GuestFeatures.fSvm)
3317 {
3318 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3319 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3320 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3321 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3322 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3323 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3324 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3325 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3326 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3327 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3328 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3329 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3330 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3331 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3332 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3333 }
3334 else
3335 {
3336 if (!fSvmEnabled)
3337 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3338 else
3339 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3340 }
3341}
3342
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