HM.cpp@ 79537

Last change on this file since 79537 was 79537, checked in by vboxsync, 5 years ago
VMM/HMVMXR0: Nested VMX: bugref:9180 Add missing #AC exception stat counter.
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1	/* $Id: HM.cpp 79537 2019-07-05 06:46:27Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/patm.h>
54	#include <VBox/vmm/csam.h>
55	#include <VBox/vmm/selm.h>
56	#include <VBox/vmm/nem.h>
57	#ifdef VBOX_WITH_REM
58	# include <VBox/vmm/rem.h>
59	#endif
60	#include <VBox/vmm/hm_vmx.h>
61	#include <VBox/vmm/hm_svm.h>
62	#include "HMInternal.h"
63	#include <VBox/vmm/vm.h>
64	#include <VBox/vmm/uvm.h>
65	#include <VBox/err.h>
66	#include <VBox/param.h>
67
68	#include <iprt/assert.h>
69	#include <VBox/log.h>
70	#include <iprt/asm.h>
71	#include <iprt/asm-amd64-x86.h>
72	#include <iprt/env.h>
73	#include <iprt/thread.h>
74
75
76	/*********************************************************************************************************************************
77	* Defined Constants And Macros *
78	*********************************************************************************************************************************/
79	/** @def HMVMX_REPORT_FEAT
80	* Reports VT-x feature to the release log.
81	*
82	* @param a_uAllowed1 Mask of allowed-1 feature bits.
83	* @param a_uAllowed0 Mask of allowed-0 feature bits.
84	* @param a_StrDesc The description string to report.
85	* @param a_Featflag Mask of the feature to report.
86	*/
87	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
88	do { \
89	if ((a_uAllowed1) & (a_Featflag)) \
90	{ \
91	if ((a_uAllowed0) & (a_Featflag)) \
92	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
93	else \
94	LogRel(("HM: " a_StrDesc "\n")); \
95	} \
96	else \
97	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
98	} while (0)
99
100	/** @def HMVMX_REPORT_ALLOWED_FEAT
101	* Reports an allowed VT-x feature to the release log.
102	*
103	* @param a_uAllowed1 Mask of allowed-1 feature bits.
104	* @param a_StrDesc The description string to report.
105	* @param a_FeatFlag Mask of the feature to report.
106	*/
107	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
108	do { \
109	if ((a_uAllowed1) & (a_FeatFlag)) \
110	LogRel(("HM: " a_StrDesc "\n")); \
111	else \
112	LogRel(("HM: " a_StrDesc " not supported\n")); \
113	} while (0)
114
115	/** @def HMVMX_REPORT_MSR_CAP
116	* Reports MSR feature capability.
117	*
118	* @param a_MsrCaps Mask of MSR feature bits.
119	* @param a_StrDesc The description string to report.
120	* @param a_fCap Mask of the feature to report.
121	*/
122	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
123	do { \
124	if ((a_MsrCaps) & (a_fCap)) \
125	LogRel(("HM: " a_StrDesc "\n")); \
126	} while (0)
127
128	/** @def HMVMX_LOGREL_FEAT
129	* Dumps a feature flag from a bitmap of features to the release log.
130	*
131	* @param a_fVal The value of all the features.
132	* @param a_fMask The specific bitmask of the feature.
133	*/
134	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
135	do { \
136	if ((a_fVal) & (a_fMask)) \
137	LogRel(("HM: %s\n", #a_fMask)); \
138	} while (0)
139
140
141	/*********************************************************************************************************************************
142	* Internal Functions *
143	*********************************************************************************************************************************/
144	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
145	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
146	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
148	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
149	static int hmR3InitFinalizeR3(PVM pVM);
150	static int hmR3InitFinalizeR0(PVM pVM);
151	static int hmR3InitFinalizeR0Intel(PVM pVM);
152	static int hmR3InitFinalizeR0Amd(PVM pVM);
153	static int hmR3TermCPU(PVM pVM);
154
155
156
157	/**
158	* Initializes the HM.
159	*
160	* This is the very first component to really do init after CFGM so that we can
161	* establish the predominant execution engine for the VM prior to initializing
162	* other modules. It takes care of NEM initialization if needed (HM disabled or
163	* not available in HW).
164	*
165	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
166	* hypervisor API via NEM, and then back on raw-mode if that isn't available
167	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
168	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
169	* X, OS/2 and others).
170	*
171	* Note that a lot of the set up work is done in ring-0 and thus postponed till
172	* the ring-3 and ring-0 callback to HMR3InitCompleted.
173	*
174	* @returns VBox status code.
175	* @param pVM The cross context VM structure.
176	*
177	* @remarks Be careful with what we call here, since most of the VMM components
178	* are uninitialized.
179	*/
180	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
181	{
182	LogFlowFunc(("\n"));
183
184	/*
185	* Assert alignment and sizes.
186	*/
187	AssertCompileMemberAlignment(VM, hm.s, 32);
188	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
189
190	/*
191	* Register the saved state data unit.
192	*/
193	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
194	NULL, NULL, NULL,
195	NULL, hmR3Save, NULL,
196	NULL, hmR3Load, NULL);
197	if (RT_FAILURE(rc))
198	return rc;
199
200	/*
201	* Register info handlers.
202	*/
203	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
204	AssertRCReturn(rc, rc);
205
206	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
207	DBGFINFO_FLAGS_ALL_EMTS);
208	AssertRCReturn(rc, rc);
209
210	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
211	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
212	AssertRCReturn(rc, rc);
213
214	/*
215	* Read configuration.
216	*/
217	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
218
219	/*
220	* Validate the HM settings.
221	*/
222	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
223	"HMForced"
224	"\|UseNEMInstead"
225	"\|FallbackToNEM"
226	"\|EnableNestedPaging"
227	"\|EnableUX"
228	"\|EnableLargePages"
229	"\|EnableVPID"
230	"\|IBPBOnVMExit"
231	"\|IBPBOnVMEntry"
232	"\|SpecCtrlByHost"
233	"\|L1DFlushOnSched"
234	"\|L1DFlushOnVMEntry"
235	"\|MDSClearOnSched"
236	"\|MDSClearOnVMEntry"
237	"\|TPRPatchingEnabled"
238	"\|64bitEnabled"
239	"\|Exclusive"
240	"\|MaxResumeLoops"
241	"\|VmxPleGap"
242	"\|VmxPleWindow"
243	"\|UseVmxPreemptTimer"
244	"\|SvmPauseFilter"
245	"\|SvmPauseFilterThreshold"
246	"\|SvmVirtVmsaveVmload"
247	"\|SvmVGif"
248	"\|LovelyMesaDrvWorkaround",
249	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
250	if (RT_FAILURE(rc))
251	return rc;
252
253	/** @cfgm{/HM/HMForced, bool, false}
254	* Forces hardware virtualization, no falling back on raw-mode. HM must be
255	* enabled, i.e. /HMEnabled must be true. */
256	bool fHMForced;
257	#ifdef VBOX_WITH_RAW_MODE
258	rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
259	AssertRCReturn(rc, rc);
260	AssertLogRelMsgReturn(!fHMForced \|\| pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
261	VERR_INVALID_PARAMETER);
262	# if defined(RT_OS_DARWIN)
263	if (pVM->fHMEnabled)
264	fHMForced = true;
265	# endif
266	AssertLogRelMsgReturn(pVM->cCpus == 1 \|\| pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
267	VERR_INVALID_PARAMETER);
268	if (pVM->cCpus > 1)
269	fHMForced = true;
270	#else /* !VBOX_WITH_RAW_MODE */
271	AssertRelease(pVM->fHMEnabled);
272	fHMForced = true;
273	#endif /* !VBOX_WITH_RAW_MODE */
274
275	/** @cfgm{/HM/UseNEMInstead, bool, true}
276	* Don't use HM, use NEM instead. */
277	bool fUseNEMInstead = false;
278	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
279	AssertRCReturn(rc, rc);
280	if (fUseNEMInstead && pVM->fHMEnabled)
281	{
282	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
283	pVM->fHMEnabled = false;
284	}
285
286	/** @cfgm{/HM/FallbackToNEM, bool, true}
287	* Enables fallback on NEM. */
288	bool fFallbackToNEM = true;
289	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
290	AssertRCReturn(rc, rc);
291
292	/** @cfgm{/HM/EnableNestedPaging, bool, false}
293	* Enables nested paging (aka extended page tables). */
294	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
295	AssertRCReturn(rc, rc);
296
297	/** @cfgm{/HM/EnableUX, bool, true}
298	* Enables the VT-x unrestricted execution feature. */
299	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
300	AssertRCReturn(rc, rc);
301
302	/** @cfgm{/HM/EnableLargePages, bool, false}
303	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
304	* page table walking and maybe better TLB hit rate in some cases. */
305	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
306	AssertRCReturn(rc, rc);
307
308	/** @cfgm{/HM/EnableVPID, bool, false}
309	* Enables the VT-x VPID feature. */
310	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
311	AssertRCReturn(rc, rc);
312
313	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
314	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
315	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
316	AssertRCReturn(rc, rc);
317
318	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
319	* Enables AMD64 cpu features.
320	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
321	* already have the support. */
322	#ifdef VBOX_ENABLE_64_BITS_GUESTS
323	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
324	AssertLogRelRCReturn(rc, rc);
325	#else
326	pVM->hm.s.fAllow64BitGuests = false;
327	#endif
328
329	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
330	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
331	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
332	* latest PAUSE instruction to be start of a new PAUSE loop.
333	*/
334	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
335	AssertRCReturn(rc, rc);
336
337	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
338	* The pause-filter exiting window in TSC ticks. When the number of ticks
339	* between the current PAUSE instruction and first PAUSE of a loop exceeds
340	* VmxPleWindow, a VM-exit is triggered.
341	*
342	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
343	*/
344	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
345	AssertRCReturn(rc, rc);
346
347	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
348	* A counter that is decrement each time a PAUSE instruction is executed by the
349	* guest. When the counter is 0, a \#VMEXIT is triggered.
350	*
351	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
352	*/
353	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
354	AssertRCReturn(rc, rc);
355
356	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
357	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
358	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
359	* PauseFilter count is reset to its initial value. However, if PAUSE is
360	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
361	* be triggered.
362	*
363	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
364	* activated.
365	*/
366	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
367	AssertRCReturn(rc, rc);
368
369	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
370	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
371	* available. */
372	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
373	AssertRCReturn(rc, rc);
374
375	/** @cfgm{/HM/SvmVGif, bool, true}
376	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
377	* if it's available. */
378	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
379	AssertRCReturn(rc, rc);
380
381	/** @cfgm{/HM/Exclusive, bool}
382	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
383	* global init for each host CPU. If false, we do local init each time we wish
384	* to execute guest code.
385	*
386	* On Windows, default is false due to the higher risk of conflicts with other
387	* hypervisors.
388	*
389	* On Mac OS X, this setting is ignored since the code does not handle local
390	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
391	*/
392	#if defined(RT_OS_DARWIN)
393	pVM->hm.s.fGlobalInit = true;
394	#else
395	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
396	# if defined(RT_OS_WINDOWS)
397	false
398	# else
399	true
400	# endif
401	);
402	AssertLogRelRCReturn(rc, rc);
403	#endif
404
405	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
406	* The number of times to resume guest execution before we forcibly return to
407	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
408	* determines the default value. */
409	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
410	AssertLogRelRCReturn(rc, rc);
411
412	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
413	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
414	* available. */
415	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
416	AssertLogRelRCReturn(rc, rc);
417
418	/** @cfgm{/HM/IBPBOnVMExit, bool}
419	* Costly paranoia setting. */
420	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
421	AssertLogRelRCReturn(rc, rc);
422
423	/** @cfgm{/HM/IBPBOnVMEntry, bool}
424	* Costly paranoia setting. */
425	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
426	AssertLogRelRCReturn(rc, rc);
427
428	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
429	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
430	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
431	AssertLogRelRCReturn(rc, rc);
432
433	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
434	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
435	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
436	AssertLogRelRCReturn(rc, rc);
437
438	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
439	if (pVM->hm.s.fL1dFlushOnVmEntry)
440	pVM->hm.s.fL1dFlushOnSched = false;
441
442	/** @cfgm{/HM/SpecCtrlByHost, bool}
443	* Another expensive paranoia setting. */
444	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
445	AssertLogRelRCReturn(rc, rc);
446
447	/** @cfgm{/HM/MDSClearOnSched, bool, true}
448	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
449	* ignored on CPUs that aren't affected. */
450	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
451	AssertLogRelRCReturn(rc, rc);
452
453	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
454	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
455	* ignored on CPUs that aren't affected. */
456	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
457	AssertLogRelRCReturn(rc, rc);
458
459	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
460	if (pVM->hm.s.fMdsClearOnVmEntry)
461	pVM->hm.s.fMdsClearOnSched = false;
462
463	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
464	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
465	* the hypervisor it is running under. */
466	bool f;
467	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
468	AssertLogRelRCReturn(rc, rc);
469	for (VMCPUID i = 0; i < pVM->cCpus; i++)
470	pVM->aCpus[i].hm.s.fTrapXcptGpForLovelyMesaDrv = f;
471
472	/*
473	* Check if VT-x or AMD-v support according to the users wishes.
474	*/
475	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
476	* VERR_SVM_IN_USE. */
477	if (pVM->fHMEnabled)
478	{
479	uint32_t fCaps;
480	rc = SUPR3QueryVTCaps(&fCaps);
481	if (RT_SUCCESS(rc))
482	{
483	if (fCaps & SUPVTCAPS_AMD_V)
484	{
485	pVM->hm.s.svm.fSupported = true;
486	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
487	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
488	}
489	else if (fCaps & SUPVTCAPS_VT_X)
490	{
491	const char *pszWhy;
492	rc = SUPR3QueryVTxSupported(&pszWhy);
493	if (RT_SUCCESS(rc))
494	{
495	pVM->hm.s.vmx.fSupported = true;
496	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
497	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
498	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
499	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
500	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
501	}
502	else
503	{
504	/*
505	* Before failing, try fallback to NEM if we're allowed to do that.
506	*/
507	pVM->fHMEnabled = false;
508	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
509	if (fFallbackToNEM)
510	{
511	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
512	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
513
514	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
515	if ( RT_SUCCESS(rc2)
516	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
517	rc = VINF_SUCCESS;
518	}
519	if (RT_FAILURE(rc))
520	{
521	if (fHMForced)
522	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
523
524	/* Fall back to raw-mode. */
525	LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
526	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
527	}
528	}
529	}
530	else
531	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
532	VERR_INTERNAL_ERROR_5);
533
534	/*
535	* Do we require a little bit or raw-mode for 64-bit guest execution?
536	*/
537	pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
538	&& pVM->fHMEnabled
539	&& pVM->hm.s.fAllow64BitGuests;
540
541	/*
542	* Disable nested paging and unrestricted guest execution now if they're
543	* configured so that CPUM can make decisions based on our configuration.
544	*/
545	Assert(!pVM->hm.s.fNestedPaging);
546	if (pVM->hm.s.fAllowNestedPaging)
547	{
548	if (fCaps & SUPVTCAPS_NESTED_PAGING)
549	pVM->hm.s.fNestedPaging = true;
550	else
551	pVM->hm.s.fAllowNestedPaging = false;
552	}
553
554	if (fCaps & SUPVTCAPS_VT_X)
555	{
556	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
557	if (pVM->hm.s.vmx.fAllowUnrestricted)
558	{
559	if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
560	&& pVM->hm.s.fNestedPaging)
561	pVM->hm.s.vmx.fUnrestrictedGuest = true;
562	else
563	pVM->hm.s.vmx.fAllowUnrestricted = false;
564	}
565	}
566	}
567	else
568	{
569	const char *pszMsg;
570	switch (rc)
571	{
572	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
573	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
574	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
575	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
576	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
577	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
578	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
579	default:
580	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
581	}
582
583	/*
584	* Before failing, try fallback to NEM if we're allowed to do that.
585	*/
586	pVM->fHMEnabled = false;
587	if (fFallbackToNEM)
588	{
589	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
590	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
591	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
592	if ( RT_SUCCESS(rc2)
593	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
594	rc = VINF_SUCCESS;
595	}
596	if (RT_FAILURE(rc))
597	{
598	if (fHMForced)
599	return VM_SET_ERROR(pVM, rc, pszMsg);
600
601	LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
602	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
603	}
604	}
605	}
606	else
607	{
608	/*
609	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
610	*/
611	if (!fUseNEMInstead)
612	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
613	else
614	{
615	rc = NEMR3Init(pVM, false /fFallback/, true);
616	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
617	if (RT_FAILURE(rc))
618	return rc;
619	}
620	}
621
622	return VINF_SUCCESS;
623	}
624
625
626	/**
627	* Initializes HM components after ring-3 phase has been fully initialized.
628	*
629	* @returns VBox status code.
630	* @param pVM The cross context VM structure.
631	*/
632	static int hmR3InitFinalizeR3(PVM pVM)
633	{
634	LogFlowFunc(("\n"));
635
636	if (!HMIsEnabled(pVM))
637	return VINF_SUCCESS;
638
639	for (VMCPUID i = 0; i < pVM->cCpus; i++)
640	{
641	PVMCPU pVCpu = &pVM->aCpus[i];
642	pVCpu->hm.s.fActive = false;
643	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
644	}
645
646	#ifdef VBOX_WITH_STATISTICS
647	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
648	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
649	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
650	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
651	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
652	#endif
653
654	/*
655	* Statistics.
656	*/
657	for (VMCPUID i = 0; i < pVM->cCpus; i++)
658	{
659	PVMCPU pVCpu = &pVM->aCpus[i];
660	int rc;
661
662	#ifdef VBOX_WITH_STATISTICS
663	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
664	"Profiling of RTMpPokeCpu.",
665	"/PROF/CPU%d/HM/Poke", i);
666	AssertRC(rc);
667	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
668	"Profiling of poke wait.",
669	"/PROF/CPU%d/HM/PokeWait", i);
670	AssertRC(rc);
671	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
672	"Profiling of poke wait when RTMpPokeCpu fails.",
673	"/PROF/CPU%d/HM/PokeWaitFailed", i);
674	AssertRC(rc);
675	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
676	"Profiling of entry until entering GC.",
677	"/PROF/CPU%d/HM/Entry", i);
678	AssertRC(rc);
679	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
680	"Profiling of pre-exit processing after returning from GC.",
681	"/PROF/CPU%d/HM/SwitchFromGC_1", i);
682	AssertRC(rc);
683	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
684	"Profiling of exit handling (longjmps not included!)",
685	"/PROF/CPU%d/HM/SwitchFromGC_2", i);
686	AssertRC(rc);
687
688	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
689	"I/O.",
690	"/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
691	AssertRC(rc);
692	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
693	"MOV CRx.",
694	"/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
695	AssertRC(rc);
696	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
697	"Exceptions, NMIs.",
698	"/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
699	AssertRC(rc);
700	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitVmentry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
701	"VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.",
702	"/PROF/CPU%d/HM/SwitchFromGC_2/Vmentry", i);
703	AssertRC(rc);
704	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
705	"Profiling of importing guest state from hardware after VM-exit.",
706	"/PROF/CPU%d/HM/ImportGuestState", i);
707	AssertRC(rc);
708	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
709	"Profiling of exporting guest state to hardware before VM-entry.",
710	"/PROF/CPU%d/HM/ExportGuestState", i);
711	AssertRC(rc);
712	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
713	"Profiling of CPUMR0LoadGuestFPU.",
714	"/PROF/CPU%d/HM/LoadGuestFpuState", i);
715	AssertRC(rc);
716	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
717	"Profiling of execution of guest-code in hardware.",
718	"/PROF/CPU%d/HM/InGC", i);
719	AssertRC(rc);
720
721	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
722	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
723	STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
724	"/PROF/CPU%d/HM/Switcher3264", i);
725	AssertRC(rc);
726	# endif
727
728	# ifdef HM_PROFILE_EXIT_DISPATCH
729	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
730	STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
731	"/PROF/CPU%d/HM/ExitDispatch", i);
732	AssertRC(rc);
733	# endif
734
735	#endif
736	# define HM_REG_COUNTER(a, b, desc) \
737	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
738	AssertRC(rc);
739
740	#ifdef VBOX_WITH_STATISTICS
741	HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Total exits (including nested-guest exits).");
742	HM_REG_COUNTER(&pVCpu->hm.s.StatNestedExitAll, "/HM/CPU%d/Exit/NestedGuest/All", "Total nested-guest exits.");
743	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
744	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
745	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
746	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
747	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
748	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
749	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
750	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
751	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
752	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
753	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
754	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestAC, "/HM/CPU%d/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
755	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
756	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
757	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
758	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
759	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "MSR read.");
760	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "MSR write.");
761	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
762	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
763	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
764	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
765	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
766	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
767	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
768	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
769	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
770	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
771	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
772	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
773	HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
774	HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
775	HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
776	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/Instr/IO/Write", "I/O write.");
777	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/Instr/IO/Read", "I/O read.");
778	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/Instr/IO/WriteString", "String I/O write.");
779	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/Instr/IO/ReadString", "String I/O read.");
780	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
781	HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
782	#endif
783	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
784	#ifdef VBOX_WITH_STATISTICS
785	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
786	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
787	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
788	HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
789
790	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
791	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
792	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
793	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
794	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchVmReq, "/HM/CPU%d/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
795	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPgmPoolFlush, "/HM/CPU%d/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
796	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchDma, "/HM/CPU%d/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
797	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
798	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
799	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
800	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
801	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
802	#endif
803	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
804	#ifdef VBOX_WITH_STATISTICS
805	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchNstGstVmexit, "/HM/CPU%d/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
806
807	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
808	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
809	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
810	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
811
812	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
813	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
814	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
815	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
816	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
817	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
818	HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
819	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
820	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
821	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
822	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
823	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
824	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
825	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
826
827	HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
828	HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
829	HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
830
831	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
832	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
833	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
834
835	HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
836	HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
837	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
838	HM_REG_COUNTER(&pVCpu->hm.s.StatExportHostState, "/HM/CPU%d/Export/HostState", "VM-entry exporting host-state.");
839
840	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
841	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
842	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr, "/HM/CPU%d/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
843
844	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelBase, "/HM/CPU%d/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
845	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit, "/HM/CPU%d/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
846	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr, "/HM/CPU%d/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
847
848	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
849	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
850	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
851	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
852
853	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
854	HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
855	HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
856	#endif
857
858	#undef HM_REG_COUNTER
859
860	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
861
862	/*
863	* Guest Exit reason stats.
864	*/
865	pVCpu->hm.s.paStatExitReason = NULL;
866	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
867	(void **)&pVCpu->hm.s.paStatExitReason);
868	AssertRCReturn(rc, rc);
869
870	if (fCpuSupportsVmx)
871	{
872	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
873	{
874	const char *pszExitName = HMGetVmxExitName(j);
875	if (pszExitName)
876	{
877	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
878	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
879	AssertRCReturn(rc, rc);
880	}
881	}
882	}
883	else
884	{
885	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
886	{
887	const char *pszExitName = HMGetSvmExitName(j);
888	if (pszExitName)
889	{
890	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
891	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
892	AssertRCReturn(rc, rc);
893	}
894	}
895	}
896	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
897	"Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
898	AssertRCReturn(rc, rc);
899	pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
900	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
901	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
902	# else
903	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
904	# endif
905
906	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
907	/*
908	* Nested-guest VM-exit reason stats.
909	*/
910	pVCpu->hm.s.paStatNestedExitReason = NULL;
911	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
912	(void **)&pVCpu->hm.s.paStatNestedExitReason);
913	AssertRCReturn(rc, rc);
914	if (fCpuSupportsVmx)
915	{
916	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
917	{
918	const char *pszExitName = HMGetVmxExitName(j);
919	if (pszExitName)
920	{
921	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
922	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/NestedGuest/Reason/%02x", i, j);
923	AssertRC(rc);
924	}
925	}
926	}
927	else
928	{
929	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
930	{
931	const char *pszExitName = HMGetSvmExitName(j);
932	if (pszExitName)
933	{
934	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
935	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/NestedGuest/Reason/%02x", i, j);
936	AssertRC(rc);
937	}
938	}
939	}
940	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
941	STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/Exit/NestedGuest/Reason/#NPF", i);
942	AssertRCReturn(rc, rc);
943	pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
944	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
945	Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
946	# else
947	Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
948	# endif
949	#endif
950
951	/*
952	* Injected events stats.
953	*/
954	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
955	AssertRCReturn(rc, rc);
956	pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
957	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
958	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
959	# else
960	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
961	# endif
962	for (unsigned j = 0; j < 255; j++)
963	{
964	STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
965	"Injected event.",
966	(j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
967	}
968
969	#endif /* VBOX_WITH_STATISTICS */
970	}
971
972	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
973	/*
974	* Magic marker for searching in crash dumps.
975	*/
976	for (VMCPUID i = 0; i < pVM->cCpus; i++)
977	{
978	PVMCPU pVCpu = &pVM->aCpus[i];
979
980	PVMXVMCSCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsCache;
981	strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
982	pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
983	}
984	#endif
985
986	return VINF_SUCCESS;
987	}
988
989
990	/**
991	* Called when a init phase has completed.
992	*
993	* @returns VBox status code.
994	* @param pVM The cross context VM structure.
995	* @param enmWhat The phase that completed.
996	*/
997	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
998	{
999	switch (enmWhat)
1000	{
1001	case VMINITCOMPLETED_RING3:
1002	return hmR3InitFinalizeR3(pVM);
1003	case VMINITCOMPLETED_RING0:
1004	return hmR3InitFinalizeR0(pVM);
1005	default:
1006	return VINF_SUCCESS;
1007	}
1008	}
1009
1010
1011	/**
1012	* Turns off normal raw mode features.
1013	*
1014	* @param pVM The cross context VM structure.
1015	*/
1016	static void hmR3DisableRawMode(PVM pVM)
1017	{
1018	/** @todo r=bird: HM shouldn't be doing this crap. */
1019	/* Reinit the paging mode to force the new shadow mode. */
1020	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1021	{
1022	PVMCPU pVCpu = &pVM->aCpus[i];
1023	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1024	}
1025	}
1026
1027
1028	/**
1029	* Initialize VT-x or AMD-V.
1030	*
1031	* @returns VBox status code.
1032	* @param pVM The cross context VM structure.
1033	*/
1034	static int hmR3InitFinalizeR0(PVM pVM)
1035	{
1036	int rc;
1037
1038	if (!HMIsEnabled(pVM))
1039	return VINF_SUCCESS;
1040
1041	/*
1042	* Hack to allow users to work around broken BIOSes that incorrectly set
1043	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1044	*/
1045	if ( !pVM->hm.s.vmx.fSupported
1046	&& !pVM->hm.s.svm.fSupported
1047	&& pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1048	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1049	{
1050	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1051	pVM->hm.s.svm.fSupported = true;
1052	pVM->hm.s.svm.fIgnoreInUseError = true;
1053	pVM->hm.s.rcInit = VINF_SUCCESS;
1054	}
1055
1056	/*
1057	* Report ring-0 init errors.
1058	*/
1059	if ( !pVM->hm.s.vmx.fSupported
1060	&& !pVM->hm.s.svm.fSupported)
1061	{
1062	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1063	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1064	switch (pVM->hm.s.rcInit)
1065	{
1066	case VERR_VMX_IN_VMX_ROOT_MODE:
1067	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1068	case VERR_VMX_NO_VMX:
1069	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1070	case VERR_VMX_MSR_VMX_DISABLED:
1071	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1072	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1073	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1074	case VERR_VMX_MSR_LOCKING_FAILED:
1075	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1076	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1077	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1078	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1079	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1080
1081	case VERR_SVM_IN_USE:
1082	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1083	case VERR_SVM_NO_SVM:
1084	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1085	case VERR_SVM_DISABLED:
1086	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1087	}
1088	return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1089	}
1090
1091	/*
1092	* Enable VT-x or AMD-V on all host CPUs.
1093	*/
1094	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1095	if (RT_FAILURE(rc))
1096	{
1097	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1098	HMR3CheckError(pVM, rc);
1099	return rc;
1100	}
1101
1102	/*
1103	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1104	* (Main should have taken care of this already)
1105	*/
1106	if (!PDMHasIoApic(pVM))
1107	{
1108	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1109	pVM->hm.s.fTprPatchingAllowed = false;
1110	}
1111
1112	/*
1113	* Check if L1D flush is needed/possible.
1114	*/
1115	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1116	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1117	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1118	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1119	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
1120	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1121
1122	/*
1123	* Check if MDS flush is needed/possible.
1124	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
1125	*/
1126	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1127	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
1128	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1129	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1130	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1131	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1132	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1133	{
1134	if (!pVM->hm.s.fMdsClearOnSched)
1135	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1136	pVM->hm.s.fMdsClearOnVmEntry = false;
1137	}
1138	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1139	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1140	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1141
1142	/*
1143	* Sync options.
1144	*/
1145	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1146	* That will require a little bit of work, of course. */
1147	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1148	{
1149	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1150	PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1151	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1152	if (pVM->cpum.ro.HostFeatures.fIbpb)
1153	{
1154	if (pVM->hm.s.fIbpbOnVmExit)
1155	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1156	if (pVM->hm.s.fIbpbOnVmEntry)
1157	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1158	}
1159	if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1160	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_L1D_ENTRY;
1161	if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1162	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_MDS_ENTRY;
1163	if (iCpu == 0)
1164	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1165	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1166	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1167	}
1168
1169	/*
1170	* Do the vendor specific initialization
1171	*
1172	* Note! We disable release log buffering here since we're doing relatively
1173	* lot of logging and doesn't want to hit the disk with each LogRel
1174	* statement.
1175	*/
1176	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1177	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1178	if (pVM->hm.s.vmx.fSupported)
1179	rc = hmR3InitFinalizeR0Intel(pVM);
1180	else
1181	rc = hmR3InitFinalizeR0Amd(pVM);
1182	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1183	: "HM: VT-x/AMD-V init method: Local\n"));
1184	RTLogRelSetBuffering(fOldBuffered);
1185	pVM->hm.s.fInitialized = true;
1186
1187	return rc;
1188	}
1189
1190
1191	/**
1192	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1193	*/
1194	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1195	{
1196	NOREF(pVM);
1197	NOREF(pvAllocation);
1198	NOREF(GCPhysAllocation);
1199	}
1200
1201
1202	/**
1203	* Returns a description of the VMCS (and associated regions') memory type given the
1204	* IA32_VMX_BASIC MSR.
1205	*
1206	* @returns The descriptive memory type.
1207	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1208	*/
1209	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1210	{
1211	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1212	switch (uMemType)
1213	{
1214	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1215	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1216	}
1217	return "Unknown";
1218	}
1219
1220
1221	/**
1222	* Returns a single-line description of all the activity-states supported by the CPU
1223	* given the IA32_VMX_MISC MSR.
1224	*
1225	* @returns All supported activity states.
1226	* @param uMsrMisc IA32_VMX_MISC MSR value.
1227	*/
1228	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1229	{
1230	static const char * const s_apszActStates[] =
1231	{
1232	"",
1233	" ( HLT )",
1234	" ( SHUTDOWN )",
1235	" ( HLT SHUTDOWN )",
1236	" ( SIPI_WAIT )",
1237	" ( HLT SIPI_WAIT )",
1238	" ( SHUTDOWN SIPI_WAIT )",
1239	" ( HLT SHUTDOWN SIPI_WAIT )"
1240	};
1241	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1242	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1243	return s_apszActStates[idxActStates];
1244	}
1245
1246
1247	/**
1248	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1249	*
1250	* @param fFeatMsr The feature control MSR value.
1251	*/
1252	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1253	{
1254	uint64_t const val = fFeatMsr;
1255	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1256	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1257	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1258	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1259	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1260	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1261	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1262	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1263	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1264	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1265	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1266	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1267	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1268	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1269	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1270	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1271	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1272	}
1273
1274
1275	/**
1276	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1277	*
1278	* @param uBasicMsr The VMX basic MSR value.
1279	*/
1280	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1281	{
1282	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1283	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1284	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1285	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1286	"< 4 GB" : "None"));
1287	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1288	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1289	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1290	LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1291	}
1292
1293
1294	/**
1295	* Reports MSR_IA32_PINBASED_CTLS to the log.
1296	*
1297	* @param pVmxMsr Pointer to the VMX MSR.
1298	*/
1299	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1300	{
1301	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1302	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1303	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1309	}
1310
1311
1312	/**
1313	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1314	*
1315	* @param pVmxMsr Pointer to the VMX MSR.
1316	*/
1317	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1318	{
1319	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1320	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1321	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1322	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1323	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1324	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1343	}
1344
1345
1346	/**
1347	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1348	*
1349	* @param pVmxMsr Pointer to the VMX MSR.
1350	*/
1351	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1352	{
1353	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1354	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1355	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1357	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1358	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1359	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1360	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1361	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1366	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1367	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1368	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1383	}
1384
1385
1386	/**
1387	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1388	*
1389	* @param pVmxMsr Pointer to the VMX MSR.
1390	*/
1391	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1392	{
1393	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1394	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1395	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1406	}
1407
1408
1409	/**
1410	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1411	*
1412	* @param pVmxMsr Pointer to the VMX MSR.
1413	*/
1414	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1415	{
1416	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1417	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1418	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1419	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1420	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1421	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1422	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1423	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1424	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1425	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1428	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1429	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1431	}
1432
1433
1434	/**
1435	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1436	*
1437	* @param fCaps The VMX EPT/VPID capability MSR value.
1438	*/
1439	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1440	{
1441	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1442	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1443	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1444	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1445	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1446	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1447	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1448	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1449	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1450	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1451	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1452	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1453	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1454	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1455	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1456	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1457	}
1458
1459
1460	/**
1461	* Reports MSR_IA32_VMX_MISC MSR to the log.
1462	*
1463	* @param pVM Pointer to the VM.
1464	* @param fMisc The VMX misc. MSR value.
1465	*/
1466	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1467	{
1468	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1469	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1470	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1471	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1472	else
1473	{
1474	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1475	pVM->hm.s.vmx.cPreemptTimerShift));
1476	}
1477	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1478	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1479	hmR3VmxGetActivityStateAllDesc(fMisc)));
1480	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1481	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1482	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1483	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1484	VMX_MISC_MAX_MSRS(fMisc)));
1485	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1486	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1487	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1488	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1489	}
1490
1491
1492	/**
1493	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1494	*
1495	* @param uVmcsEnum The VMX VMCS enum MSR value.
1496	*/
1497	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1498	{
1499	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1500	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1501	}
1502
1503
1504	/**
1505	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1506	*
1507	* @param uVmFunc The VMX VMFUNC MSR value.
1508	*/
1509	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1510	{
1511	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1512	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1513	}
1514
1515
1516	/**
1517	* Reports VMX CR0, CR4 fixed MSRs.
1518	*
1519	* @param pMsrs Pointer to the VMX MSRs.
1520	*/
1521	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1522	{
1523	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1524	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1525	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1526	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1527	}
1528
1529
1530	/**
1531	* Finish VT-x initialization (after ring-0 init).
1532	*
1533	* @returns VBox status code.
1534	* @param pVM The cross context VM structure.
1535	*/
1536	static int hmR3InitFinalizeR0Intel(PVM pVM)
1537	{
1538	int rc;
1539
1540	Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1541	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1542
1543	LogRel(("HM: Using VT-x implementation 3.0\n"));
1544	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1545	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1546	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1547	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1548
1549	hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1550	hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1551
1552	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1553	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1554	if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1555	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1556
1557	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1558	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1559
1560	if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1561	{
1562	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1563	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1564	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1565	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1566	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1567	}
1568
1569	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1570	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1571	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1572	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1573	if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1574	hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1575	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1576
1577	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1578	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1579	{
1580	PCVMXVMCSINFO pVmcsInfo = &pVM->aCpus[i].hm.s.vmx.VmcsInfo;
1581	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVmcsInfo->HCPhysMsrBitmap));
1582	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVmcsInfo->HCPhysVmcs));
1583	}
1584	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1585	if (pVM->cpum.ro.GuestFeatures.fVmx)
1586	{
1587	LogRel(("HM: Nested-guest:\n"));
1588	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1589	{
1590	PCVMXVMCSINFO pVmcsInfoNstGst = &pVM->aCpus[i].hm.s.vmx.VmcsInfoNstGst;
1591	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVmcsInfoNstGst->HCPhysMsrBitmap));
1592	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVmcsInfoNstGst->HCPhysVmcs));
1593	}
1594	}
1595	#endif
1596
1597	/*
1598	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1599	*/
1600	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1601	\|\| (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1602	VERR_HM_IPE_1);
1603	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1604	\|\| ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1605	&& pVM->hm.s.fNestedPaging),
1606	VERR_HM_IPE_1);
1607
1608	/*
1609	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1610	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1611	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1612	*/
1613	if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1614	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1615	{
1616	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1617	LogRel(("HM: Disabled RDTSCP\n"));
1618	}
1619
1620	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1621	{
1622	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1623	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1624	if (RT_SUCCESS(rc))
1625	{
1626	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1627	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1628	esp. Figure 20-5.*/
1629	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1630	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1631
1632	/* Bit set to 0 means software interrupts are redirected to the
1633	8086 program interrupt handler rather than switching to
1634	protected-mode handler. */
1635	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1636
1637	/* Allow all port IO, so that port IO instructions do not cause
1638	exceptions and would instead cause a VM-exit (based on VT-x's
1639	IO bitmap which we currently configure to always cause an exit). */
1640	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1641	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1642
1643	/*
1644	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1645	* page table used in real and protected mode without paging with EPT.
1646	*/
1647	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1648	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1649	{
1650	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1651	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1652	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1653	\| X86_PDE4M_G;
1654	}
1655
1656	/* We convert it here every time as PCI regions could be reconfigured. */
1657	if (PDMVmmDevHeapIsEnabled(pVM))
1658	{
1659	RTGCPHYS GCPhys;
1660	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1661	AssertRCReturn(rc, rc);
1662	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1663
1664	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1665	AssertRCReturn(rc, rc);
1666	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1667	}
1668	}
1669	else
1670	{
1671	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1672	pVM->hm.s.vmx.pRealModeTSS = NULL;
1673	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1674	return VMSetError(pVM, rc, RT_SRC_POS,
1675	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1676	}
1677	}
1678
1679	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1680	: "HM: Guest support: 32-bit only\n"));
1681
1682	/*
1683	* Call ring-0 to set up the VM.
1684	*/
1685	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1686	if (rc != VINF_SUCCESS)
1687	{
1688	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1689	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1690	{
1691	PVMCPU pVCpu = &pVM->aCpus[i];
1692	LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1693	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1694	}
1695	HMR3CheckError(pVM, rc);
1696	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1697	}
1698
1699	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1700	LogRel(("HM: Enabled VMX\n"));
1701	pVM->hm.s.vmx.fEnabled = true;
1702
1703	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1704
1705	/*
1706	* Change the CPU features.
1707	*/
1708	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1709	if (pVM->hm.s.fAllow64BitGuests)
1710	{
1711	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1712	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1713	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1714	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1715	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1716	}
1717	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1718	(we reuse the host EFER in the switcher). */
1719	/** @todo this needs to be fixed properly!! */
1720	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1721	{
1722	if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1723	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1724	else
1725	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1726	}
1727
1728	/*
1729	* Log configuration details.
1730	*/
1731	if (pVM->hm.s.fNestedPaging)
1732	{
1733	LogRel(("HM: Enabled nested paging\n"));
1734	if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1735	LogRel(("HM: EPT flush type = Single context\n"));
1736	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1737	LogRel(("HM: EPT flush type = All contexts\n"));
1738	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1739	LogRel(("HM: EPT flush type = Not supported\n"));
1740	else
1741	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1742
1743	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1744	LogRel(("HM: Enabled unrestricted guest execution\n"));
1745
1746	#if HC_ARCH_BITS == 64
1747	if (pVM->hm.s.fLargePages)
1748	{
1749	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1750	PGMSetLargePageUsage(pVM, true);
1751	LogRel(("HM: Enabled large page support\n"));
1752	}
1753	#endif
1754	}
1755	else
1756	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1757
1758	if (pVM->hm.s.vmx.fVpid)
1759	{
1760	LogRel(("HM: Enabled VPID\n"));
1761	if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1762	LogRel(("HM: VPID flush type = Individual addresses\n"));
1763	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1764	LogRel(("HM: VPID flush type = Single context\n"));
1765	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1766	LogRel(("HM: VPID flush type = All contexts\n"));
1767	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1768	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1769	else
1770	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1771	}
1772	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1773	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1774
1775	if (pVM->hm.s.vmx.fUsePreemptTimer)
1776	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1777	else
1778	LogRel(("HM: Disabled VMX-preemption timer\n"));
1779
1780	if (pVM->hm.s.fVirtApicRegs)
1781	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1782
1783	if (pVM->hm.s.fPostedIntrs)
1784	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1785
1786	if (pVM->hm.s.vmx.fUseVmcsShadowing)
1787	{
1788	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1789	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1790	}
1791
1792	return VINF_SUCCESS;
1793	}
1794
1795
1796	/**
1797	* Finish AMD-V initialization (after ring-0 init).
1798	*
1799	* @returns VBox status code.
1800	* @param pVM The cross context VM structure.
1801	*/
1802	static int hmR3InitFinalizeR0Amd(PVM pVM)
1803	{
1804	Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1805
1806	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1807
1808	uint32_t u32Family;
1809	uint32_t u32Model;
1810	uint32_t u32Stepping;
1811	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1812	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1813	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1814	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1815	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1816	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1817	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1818
1819	/*
1820	* Enumerate AMD-V features.
1821	*/
1822	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1823	{
1824	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1825	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1826	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1827	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1828	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1829	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1830	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1831	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1832	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1833	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1834	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1835	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1836	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1837	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1838	#undef HMSVM_REPORT_FEATURE
1839	};
1840
1841	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1842	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1843	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1844	{
1845	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1846	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1847	}
1848	if (fSvmFeatures)
1849	for (unsigned iBit = 0; iBit < 32; iBit++)
1850	if (RT_BIT_32(iBit) & fSvmFeatures)
1851	LogRel(("HM: Reserved bit %u\n", iBit));
1852
1853	/*
1854	* Nested paging is determined in HMR3Init, verify the sanity of that.
1855	*/
1856	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1857	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1858	VERR_HM_IPE_1);
1859
1860	#if 0
1861	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1862	* here. */
1863	if (RTR0IsPostIpiSupport())
1864	pVM->hm.s.fPostedIntrs = true;
1865	#endif
1866
1867	/*
1868	* Call ring-0 to set up the VM.
1869	*/
1870	int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1871	if (rc != VINF_SUCCESS)
1872	{
1873	AssertMsgFailed(("%Rrc\n", rc));
1874	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1875	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1876	}
1877
1878	LogRel(("HM: Enabled SVM\n"));
1879	pVM->hm.s.svm.fEnabled = true;
1880
1881	if (pVM->hm.s.fNestedPaging)
1882	{
1883	LogRel(("HM: Enabled nested paging\n"));
1884
1885	/*
1886	* Enable large pages (2 MB) if applicable.
1887	*/
1888	#if HC_ARCH_BITS == 64
1889	if (pVM->hm.s.fLargePages)
1890	{
1891	PGMSetLargePageUsage(pVM, true);
1892	LogRel(("HM: Enabled large page support\n"));
1893	}
1894	#endif
1895	}
1896
1897	if (pVM->hm.s.fVirtApicRegs)
1898	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1899
1900	if (pVM->hm.s.fPostedIntrs)
1901	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1902
1903	hmR3DisableRawMode(pVM);
1904
1905	/*
1906	* Change the CPU features.
1907	*/
1908	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1909	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1910	if (pVM->hm.s.fAllow64BitGuests)
1911	{
1912	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1913	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1914	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1915	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1916	}
1917	/* Turn on NXE if PAE has been enabled. */
1918	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1919	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1920
1921	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1922	: "HM: Disabled TPR patching\n"));
1923
1924	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1925	: "HM: Guest support: 32-bit only\n"));
1926	return VINF_SUCCESS;
1927	}
1928
1929
1930	/**
1931	* Applies relocations to data and code managed by this
1932	* component. This function will be called at init and
1933	* whenever the VMM need to relocate it self inside the GC.
1934	*
1935	* @param pVM The cross context VM structure.
1936	*/
1937	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1938	{
1939	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1940
1941	/* Fetch the current paging mode during the relocate callback during state loading. */
1942	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1943	{
1944	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1945	{
1946	PVMCPU pVCpu = &pVM->aCpus[i];
1947	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1948	}
1949	}
1950	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1951	if (HMIsEnabled(pVM))
1952	{
1953	switch (PGMGetHostMode(pVM))
1954	{
1955	case PGMMODE_32_BIT:
1956	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1957	break;
1958
1959	case PGMMODE_PAE:
1960	case PGMMODE_PAE_NX:
1961	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1962	break;
1963
1964	default:
1965	AssertFailed();
1966	break;
1967	}
1968	}
1969	#endif
1970	return;
1971	}
1972
1973
1974	/**
1975	* Terminates the HM.
1976	*
1977	* Termination means cleaning up and freeing all resources,
1978	* the VM itself is, at this point, powered off or suspended.
1979	*
1980	* @returns VBox status code.
1981	* @param pVM The cross context VM structure.
1982	*/
1983	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1984	{
1985	if (pVM->hm.s.vmx.pRealModeTSS)
1986	{
1987	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1988	pVM->hm.s.vmx.pRealModeTSS = 0;
1989	}
1990	hmR3TermCPU(pVM);
1991	return 0;
1992	}
1993
1994
1995	/**
1996	* Terminates the per-VCPU HM.
1997	*
1998	* @returns VBox status code.
1999	* @param pVM The cross context VM structure.
2000	*/
2001	static int hmR3TermCPU(PVM pVM)
2002	{
2003	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2004	{
2005	PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2006
2007	#ifdef VBOX_WITH_STATISTICS
2008	if (pVCpu->hm.s.paStatExitReason)
2009	{
2010	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2011	pVCpu->hm.s.paStatExitReason = NULL;
2012	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2013	}
2014	if (pVCpu->hm.s.paStatInjectedIrqs)
2015	{
2016	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2017	pVCpu->hm.s.paStatInjectedIrqs = NULL;
2018	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2019	}
2020	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
2021	if (pVCpu->hm.s.paStatNestedExitReason)
2022	{
2023	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
2024	pVCpu->hm.s.paStatNestedExitReason = NULL;
2025	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
2026	}
2027	# endif
2028	#endif
2029
2030	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2031	memset(pVCpu->hm.s.vmx.VmcsCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VmcsCache.aMagic));
2032	pVCpu->hm.s.vmx.VmcsCache.uMagic = 0;
2033	pVCpu->hm.s.vmx.VmcsCache.uPos = 0xffffffff;
2034	#endif
2035	}
2036	return 0;
2037	}
2038
2039
2040	/**
2041	* Resets a virtual CPU.
2042	*
2043	* Used by HMR3Reset and CPU hot plugging.
2044	*
2045	* @param pVCpu The cross context virtual CPU structure to reset.
2046	*/
2047	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2048	{
2049	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2050	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2051	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2052
2053	pVCpu->hm.s.fActive = false;
2054	pVCpu->hm.s.Event.fPending = false;
2055	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2056	pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32 = false;
2057	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2058	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2059	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2060	{
2061	pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32 = false;
2062	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2063	}
2064	#endif
2065
2066	/* Reset the contents of the read cache. */
2067	PVMXVMCSCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsCache;
2068	for (unsigned j = 0; j < pVmcsCache->Read.cValidEntries; j++)
2069	pVmcsCache->Read.aFieldVal[j] = 0;
2070
2071	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2072	/* Magic marker for searching in crash dumps. */
2073	strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
2074	pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2075	#endif
2076	}
2077
2078
2079	/**
2080	* The VM is being reset.
2081	*
2082	* For the HM component this means that any GDT/LDT/TSS monitors
2083	* needs to be removed.
2084	*
2085	* @param pVM The cross context VM structure.
2086	*/
2087	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2088	{
2089	LogFlow(("HMR3Reset:\n"));
2090
2091	if (HMIsEnabled(pVM))
2092	hmR3DisableRawMode(pVM);
2093
2094	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2095	{
2096	PVMCPU pVCpu = &pVM->aCpus[i];
2097
2098	HMR3ResetCpu(pVCpu);
2099	}
2100
2101	/* Clear all patch information. */
2102	pVM->hm.s.pGuestPatchMem = 0;
2103	pVM->hm.s.pFreeGuestPatchMem = 0;
2104	pVM->hm.s.cbGuestPatchMem = 0;
2105	pVM->hm.s.cPatches = 0;
2106	pVM->hm.s.PatchTree = 0;
2107	pVM->hm.s.fTPRPatchingActive = false;
2108	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2109	}
2110
2111
2112	/**
2113	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2114	*
2115	* @returns VBox strict status code.
2116	* @param pVM The cross context VM structure.
2117	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2118	* @param pvUser Unused.
2119	*/
2120	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2121	{
2122	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2123
2124	/* Only execute the handler on the VCPU the original patch request was issued. */
2125	if (pVCpu->idCpu != idCpu)
2126	return VINF_SUCCESS;
2127
2128	Log(("hmR3RemovePatches\n"));
2129	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2130	{
2131	uint8_t abInstr[15];
2132	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2133	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2134	int rc;
2135
2136	#ifdef LOG_ENABLED
2137	char szOutput[256];
2138	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2139	szOutput, sizeof(szOutput), NULL);
2140	if (RT_SUCCESS(rc))
2141	Log(("Patched instr: %s\n", szOutput));
2142	#endif
2143
2144	/* Check if the instruction is still the same. */
2145	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2146	if (rc != VINF_SUCCESS)
2147	{
2148	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2149	continue; /* swapped out or otherwise removed; skip it. */
2150	}
2151
2152	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2153	{
2154	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2155	continue; /* skip it. */
2156	}
2157
2158	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2159	AssertRC(rc);
2160
2161	#ifdef LOG_ENABLED
2162	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2163	szOutput, sizeof(szOutput), NULL);
2164	if (RT_SUCCESS(rc))
2165	Log(("Original instr: %s\n", szOutput));
2166	#endif
2167	}
2168	pVM->hm.s.cPatches = 0;
2169	pVM->hm.s.PatchTree = 0;
2170	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2171	pVM->hm.s.fTPRPatchingActive = false;
2172	return VINF_SUCCESS;
2173	}
2174
2175
2176	/**
2177	* Worker for enabling patching in a VT-x/AMD-V guest.
2178	*
2179	* @returns VBox status code.
2180	* @param pVM The cross context VM structure.
2181	* @param idCpu VCPU to execute hmR3RemovePatches on.
2182	* @param pPatchMem Patch memory range.
2183	* @param cbPatchMem Size of the memory range.
2184	*/
2185	static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2186	{
2187	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2188	AssertRC(rc);
2189
2190	pVM->hm.s.pGuestPatchMem = pPatchMem;
2191	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2192	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2193	return VINF_SUCCESS;
2194	}
2195
2196
2197	/**
2198	* Enable patching in a VT-x/AMD-V guest
2199	*
2200	* @returns VBox status code.
2201	* @param pVM The cross context VM structure.
2202	* @param pPatchMem Patch memory range.
2203	* @param cbPatchMem Size of the memory range.
2204	*/
2205	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2206	{
2207	VM_ASSERT_EMT(pVM);
2208	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2209	if (pVM->cCpus > 1)
2210	{
2211	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2212	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2213	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2214	AssertRC(rc);
2215	return rc;
2216	}
2217	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2218	}
2219
2220
2221	/**
2222	* Disable patching in a VT-x/AMD-V guest.
2223	*
2224	* @returns VBox status code.
2225	* @param pVM The cross context VM structure.
2226	* @param pPatchMem Patch memory range.
2227	* @param cbPatchMem Size of the memory range.
2228	*/
2229	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2230	{
2231	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2232	RT_NOREF2(pPatchMem, cbPatchMem);
2233
2234	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2235	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2236
2237	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2238	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2239	(void *)(uintptr_t)VMMGetCpuId(pVM));
2240	AssertRC(rc);
2241
2242	pVM->hm.s.pGuestPatchMem = 0;
2243	pVM->hm.s.pFreeGuestPatchMem = 0;
2244	pVM->hm.s.cbGuestPatchMem = 0;
2245	pVM->hm.s.fTPRPatchingActive = false;
2246	return VINF_SUCCESS;
2247	}
2248
2249
2250	/**
2251	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2252	*
2253	* @returns VBox strict status code.
2254	* @param pVM The cross context VM structure.
2255	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2256	* @param pvUser User specified CPU context.
2257	*
2258	*/
2259	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2260	{
2261	/*
2262	* Only execute the handler on the VCPU the original patch request was
2263	* issued. (The other CPU(s) might not yet have switched to protected
2264	* mode, nor have the correct memory context.)
2265	*/
2266	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2267	if (pVCpu->idCpu != idCpu)
2268	return VINF_SUCCESS;
2269
2270	/*
2271	* We're racing other VCPUs here, so don't try patch the instruction twice
2272	* and make sure there is still room for our patch record.
2273	*/
2274	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2275	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2276	if (pPatch)
2277	{
2278	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2279	return VINF_SUCCESS;
2280	}
2281	uint32_t const idx = pVM->hm.s.cPatches;
2282	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2283	{
2284	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2285	return VINF_SUCCESS;
2286	}
2287	pPatch = &pVM->hm.s.aPatches[idx];
2288
2289	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2290
2291	/*
2292	* Disassembler the instruction and get cracking.
2293	*/
2294	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2295	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2296	uint32_t cbOp;
2297	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2298	AssertRC(rc);
2299	if ( rc == VINF_SUCCESS
2300	&& pDis->pCurInstr->uOpcode == OP_MOV
2301	&& cbOp >= 3)
2302	{
2303	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2304
2305	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2306	AssertRC(rc);
2307
2308	pPatch->cbOp = cbOp;
2309
2310	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2311	{
2312	/* write. */
2313	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2314	{
2315	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2316	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2317	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2318	}
2319	else
2320	{
2321	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2322	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2323	pPatch->uSrcOperand = pDis->Param2.uValue;
2324	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2325	}
2326	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2327	AssertRC(rc);
2328
2329	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2330	pPatch->cbNewOp = sizeof(s_abVMMCall);
2331	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2332	}
2333	else
2334	{
2335	/*
2336	* TPR Read.
2337	*
2338	* Found:
2339	* mov eax, dword [fffe0080] (5 bytes)
2340	* Check if next instruction is:
2341	* shr eax, 4
2342	*/
2343	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2344
2345	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2346	uint8_t const cbOpMmio = cbOp;
2347	uint64_t const uSavedRip = pCtx->rip;
2348
2349	pCtx->rip += cbOp;
2350	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2351	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2352	pCtx->rip = uSavedRip;
2353
2354	if ( rc == VINF_SUCCESS
2355	&& pDis->pCurInstr->uOpcode == OP_SHR
2356	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2357	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2358	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2359	&& pDis->Param2.uValue == 4
2360	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2361	{
2362	uint8_t abInstr[15];
2363
2364	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2365	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2366	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2367	AssertRC(rc);
2368
2369	pPatch->cbOp = cbOpMmio + cbOp;
2370
2371	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2372	abInstr[0] = 0xf0;
2373	abInstr[1] = 0x0f;
2374	abInstr[2] = 0x20;
2375	abInstr[3] = 0xc0 \| pDis->Param1.Base.idxGenReg;
2376	for (unsigned i = 4; i < pPatch->cbOp; i++)
2377	abInstr[i] = 0x90; /* nop */
2378
2379	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2380	AssertRC(rc);
2381
2382	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2383	pPatch->cbNewOp = pPatch->cbOp;
2384	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2385
2386	Log(("Acceptable read/shr candidate!\n"));
2387	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2388	}
2389	else
2390	{
2391	pPatch->enmType = HMTPRINSTR_READ;
2392	pPatch->uDstOperand = idxMmioReg;
2393
2394	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2395	AssertRC(rc);
2396
2397	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2398	pPatch->cbNewOp = sizeof(s_abVMMCall);
2399	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2400	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2401	}
2402	}
2403
2404	pPatch->Core.Key = pCtx->eip;
2405	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2406	AssertRC(rc);
2407
2408	pVM->hm.s.cPatches++;
2409	return VINF_SUCCESS;
2410	}
2411
2412	/*
2413	* Save invalid patch, so we will not try again.
2414	*/
2415	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2416	pPatch->Core.Key = pCtx->eip;
2417	pPatch->enmType = HMTPRINSTR_INVALID;
2418	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2419	AssertRC(rc);
2420	pVM->hm.s.cPatches++;
2421	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2422	return VINF_SUCCESS;
2423	}
2424
2425
2426	/**
2427	* Callback to patch a TPR instruction (jump to generated code).
2428	*
2429	* @returns VBox strict status code.
2430	* @param pVM The cross context VM structure.
2431	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2432	* @param pvUser User specified CPU context.
2433	*
2434	*/
2435	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2436	{
2437	/*
2438	* Only execute the handler on the VCPU the original patch request was
2439	* issued. (The other CPU(s) might not yet have switched to protected
2440	* mode, nor have the correct memory context.)
2441	*/
2442	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2443	if (pVCpu->idCpu != idCpu)
2444	return VINF_SUCCESS;
2445
2446	/*
2447	* We're racing other VCPUs here, so don't try patch the instruction twice
2448	* and make sure there is still room for our patch record.
2449	*/
2450	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2451	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2452	if (pPatch)
2453	{
2454	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2455	return VINF_SUCCESS;
2456	}
2457	uint32_t const idx = pVM->hm.s.cPatches;
2458	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2459	{
2460	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2461	return VINF_SUCCESS;
2462	}
2463	pPatch = &pVM->hm.s.aPatches[idx];
2464
2465	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2466	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2467
2468	/*
2469	* Disassemble the instruction and get cracking.
2470	*/
2471	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2472	uint32_t cbOp;
2473	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2474	AssertRC(rc);
2475	if ( rc == VINF_SUCCESS
2476	&& pDis->pCurInstr->uOpcode == OP_MOV
2477	&& cbOp >= 5)
2478	{
2479	uint8_t aPatch[64];
2480	uint32_t off = 0;
2481
2482	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2483	AssertRC(rc);
2484
2485	pPatch->cbOp = cbOp;
2486	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2487
2488	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2489	{
2490	/*
2491	* TPR write:
2492	*
2493	* push ECX [51]
2494	* push EDX [52]
2495	* push EAX [50]
2496	* xor EDX,EDX [31 D2]
2497	* mov EAX,EAX [89 C0]
2498	* or
2499	* mov EAX,0000000CCh [B8 CC 00 00 00]
2500	* mov ECX,0C0000082h [B9 82 00 00 C0]
2501	* wrmsr [0F 30]
2502	* pop EAX [58]
2503	* pop EDX [5A]
2504	* pop ECX [59]
2505	* jmp return_address [E9 return_address]
2506	*/
2507	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2508
2509	aPatch[off++] = 0x51; /* push ecx */
2510	aPatch[off++] = 0x52; /* push edx */
2511	if (!fUsesEax)
2512	aPatch[off++] = 0x50; /* push eax */
2513	aPatch[off++] = 0x31; /* xor edx, edx */
2514	aPatch[off++] = 0xd2;
2515	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2516	{
2517	if (!fUsesEax)
2518	{
2519	aPatch[off++] = 0x89; /* mov eax, src_reg */
2520	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2521	}
2522	}
2523	else
2524	{
2525	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2526	aPatch[off++] = 0xb8; /* mov eax, immediate */
2527	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2528	off += sizeof(uint32_t);
2529	}
2530	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2531	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2532	off += sizeof(uint32_t);
2533
2534	aPatch[off++] = 0x0f; /* wrmsr */
2535	aPatch[off++] = 0x30;
2536	if (!fUsesEax)
2537	aPatch[off++] = 0x58; /* pop eax */
2538	aPatch[off++] = 0x5a; /* pop edx */
2539	aPatch[off++] = 0x59; /* pop ecx */
2540	}
2541	else
2542	{
2543	/*
2544	* TPR read:
2545	*
2546	* push ECX [51]
2547	* push EDX [52]
2548	* push EAX [50]
2549	* mov ECX,0C0000082h [B9 82 00 00 C0]
2550	* rdmsr [0F 32]
2551	* mov EAX,EAX [89 C0]
2552	* pop EAX [58]
2553	* pop EDX [5A]
2554	* pop ECX [59]
2555	* jmp return_address [E9 return_address]
2556	*/
2557	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2558
2559	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2560	aPatch[off++] = 0x51; /* push ecx */
2561	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2562	aPatch[off++] = 0x52; /* push edx */
2563	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2564	aPatch[off++] = 0x50; /* push eax */
2565
2566	aPatch[off++] = 0x31; /* xor edx, edx */
2567	aPatch[off++] = 0xd2;
2568
2569	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2570	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2571	off += sizeof(uint32_t);
2572
2573	aPatch[off++] = 0x0f; /* rdmsr */
2574	aPatch[off++] = 0x32;
2575
2576	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2577	{
2578	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2579	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2580	}
2581
2582	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2583	aPatch[off++] = 0x58; /* pop eax */
2584	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2585	aPatch[off++] = 0x5a; /* pop edx */
2586	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2587	aPatch[off++] = 0x59; /* pop ecx */
2588	}
2589	aPatch[off++] = 0xe9; /* jmp return_address */
2590	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2591	off += sizeof(RTRCUINTPTR);
2592
2593	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2594	{
2595	/* Write new code to the patch buffer. */
2596	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2597	AssertRC(rc);
2598
2599	#ifdef LOG_ENABLED
2600	uint32_t cbCurInstr;
2601	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2602	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2603	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2604	{
2605	char szOutput[256];
2606	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2607	szOutput, sizeof(szOutput), &cbCurInstr);
2608	if (RT_SUCCESS(rc))
2609	Log(("Patch instr %s\n", szOutput));
2610	else
2611	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2612	}
2613	#endif
2614
2615	pPatch->aNewOpcode[0] = 0xE9;
2616	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2617
2618	/* Overwrite the TPR instruction with a jump. */
2619	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2620	AssertRC(rc);
2621
2622	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2623
2624	pVM->hm.s.pFreeGuestPatchMem += off;
2625	pPatch->cbNewOp = 5;
2626
2627	pPatch->Core.Key = pCtx->eip;
2628	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2629	AssertRC(rc);
2630
2631	pVM->hm.s.cPatches++;
2632	pVM->hm.s.fTPRPatchingActive = true;
2633	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2634	return VINF_SUCCESS;
2635	}
2636
2637	Log(("Ran out of space in our patch buffer!\n"));
2638	}
2639	else
2640	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2641
2642
2643	/*
2644	* Save invalid patch, so we will not try again.
2645	*/
2646	pPatch = &pVM->hm.s.aPatches[idx];
2647	pPatch->Core.Key = pCtx->eip;
2648	pPatch->enmType = HMTPRINSTR_INVALID;
2649	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2650	AssertRC(rc);
2651	pVM->hm.s.cPatches++;
2652	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2653	return VINF_SUCCESS;
2654	}
2655
2656
2657	/**
2658	* Attempt to patch TPR mmio instructions.
2659	*
2660	* @returns VBox status code.
2661	* @param pVM The cross context VM structure.
2662	* @param pVCpu The cross context virtual CPU structure.
2663	*/
2664	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2665	{
2666	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2667	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2668	(void *)(uintptr_t)pVCpu->idCpu);
2669	AssertRC(rc);
2670	return rc;
2671	}
2672
2673
2674	/**
2675	* Checks if we need to reschedule due to VMM device heap changes.
2676	*
2677	* @returns true if a reschedule is required, otherwise false.
2678	* @param pVM The cross context VM structure.
2679	* @param pCtx VM execution context.
2680	*/
2681	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2682	{
2683	/*
2684	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2685	* when the unrestricted guest execution feature is missing (VT-x only).
2686	*/
2687	if ( pVM->hm.s.vmx.fEnabled
2688	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2689	&& CPUMIsGuestInRealModeEx(pCtx)
2690	&& !PDMVmmDevHeapIsEnabled(pVM))
2691	return true;
2692
2693	return false;
2694	}
2695
2696
2697	/**
2698	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2699	* event settings changes.
2700	*
2701	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2702	* function is just updating the VM globals.
2703	*
2704	* @param pVM The VM cross context VM structure.
2705	* @thread EMT(0)
2706	*/
2707	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2708	{
2709	/* Interrupts. */
2710	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2711	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2712
2713	/* CPU Exceptions. */
2714	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2715	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2716	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2717	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2718
2719	/* Common VM exits. */
2720	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2721	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2722	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2723	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2724
2725	/* Vendor specific VM exits. */
2726	if (HMR3IsVmxEnabled(pVM->pUVM))
2727	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2728	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2729	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2730	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2731	else
2732	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2733	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2734	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2735	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2736
2737	/* Done. */
2738	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2739	}
2740
2741
2742	/**
2743	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2744	*
2745	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2746	* per CPU settings.
2747	*
2748	* @param pVM The VM cross context VM structure.
2749	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2750	*/
2751	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2752	{
2753	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2754	}
2755
2756
2757	/**
2758	* Checks if we are currently using hardware acceleration.
2759	*
2760	* @returns true if hardware acceleration is being used, otherwise false.
2761	* @param pVCpu The cross context virtual CPU structure.
2762	*/
2763	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2764	{
2765	return pVCpu->hm.s.fActive;
2766	}
2767
2768
2769	/**
2770	* External interface for querying whether hardware acceleration is enabled.
2771	*
2772	* @returns true if VT-x or AMD-V is being used, otherwise false.
2773	* @param pUVM The user mode VM handle.
2774	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2775	*/
2776	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2777	{
2778	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2779	PVM pVM = pUVM->pVM;
2780	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2781	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2782	}
2783
2784
2785	/**
2786	* External interface for querying whether VT-x is being used.
2787	*
2788	* @returns true if VT-x is being used, otherwise false.
2789	* @param pUVM The user mode VM handle.
2790	* @sa HMR3IsSvmEnabled, HMIsEnabled
2791	*/
2792	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2793	{
2794	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2795	PVM pVM = pUVM->pVM;
2796	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2797	return pVM->hm.s.vmx.fEnabled
2798	&& pVM->hm.s.vmx.fSupported
2799	&& pVM->fHMEnabled;
2800	}
2801
2802
2803	/**
2804	* External interface for querying whether AMD-V is being used.
2805	*
2806	* @returns true if VT-x is being used, otherwise false.
2807	* @param pUVM The user mode VM handle.
2808	* @sa HMR3IsVmxEnabled, HMIsEnabled
2809	*/
2810	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2811	{
2812	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2813	PVM pVM = pUVM->pVM;
2814	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2815	return pVM->hm.s.svm.fEnabled
2816	&& pVM->hm.s.svm.fSupported
2817	&& pVM->fHMEnabled;
2818	}
2819
2820
2821	/**
2822	* Checks if we are currently using nested paging.
2823	*
2824	* @returns true if nested paging is being used, otherwise false.
2825	* @param pUVM The user mode VM handle.
2826	*/
2827	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2828	{
2829	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2830	PVM pVM = pUVM->pVM;
2831	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2832	return pVM->hm.s.fNestedPaging;
2833	}
2834
2835
2836	/**
2837	* Checks if virtualized APIC registers is enabled.
2838	*
2839	* When enabled this feature allows the hardware to access most of the
2840	* APIC registers in the virtual-APIC page without causing VM-exits. See
2841	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2842	*
2843	* @returns true if virtualized APIC registers is enabled, otherwise
2844	* false.
2845	* @param pUVM The user mode VM handle.
2846	*/
2847	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2848	{
2849	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2850	PVM pVM = pUVM->pVM;
2851	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2852	return pVM->hm.s.fVirtApicRegs;
2853	}
2854
2855
2856	/**
2857	* Checks if APIC posted-interrupt processing is enabled.
2858	*
2859	* This returns whether we can deliver interrupts to the guest without
2860	* leaving guest-context by updating APIC state from host-context.
2861	*
2862	* @returns true if APIC posted-interrupt processing is enabled,
2863	* otherwise false.
2864	* @param pUVM The user mode VM handle.
2865	*/
2866	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2867	{
2868	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2869	PVM pVM = pUVM->pVM;
2870	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2871	return pVM->hm.s.fPostedIntrs;
2872	}
2873
2874
2875	/**
2876	* Checks if we are currently using VPID in VT-x mode.
2877	*
2878	* @returns true if VPID is being used, otherwise false.
2879	* @param pUVM The user mode VM handle.
2880	*/
2881	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2882	{
2883	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2884	PVM pVM = pUVM->pVM;
2885	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2886	return pVM->hm.s.vmx.fVpid;
2887	}
2888
2889
2890	/**
2891	* Checks if we are currently using VT-x unrestricted execution,
2892	* aka UX.
2893	*
2894	* @returns true if UX is being used, otherwise false.
2895	* @param pUVM The user mode VM handle.
2896	*/
2897	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2898	{
2899	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2900	PVM pVM = pUVM->pVM;
2901	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2902	return pVM->hm.s.vmx.fUnrestrictedGuest
2903	\|\| pVM->hm.s.svm.fSupported;
2904	}
2905
2906
2907	/**
2908	* Checks if the VMX-preemption timer is being used.
2909	*
2910	* @returns true if the VMX-preemption timer is being used, otherwise false.
2911	* @param pVM The cross context VM structure.
2912	*/
2913	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2914	{
2915	return HMIsEnabled(pVM)
2916	&& pVM->hm.s.vmx.fEnabled
2917	&& pVM->hm.s.vmx.fUsePreemptTimer;
2918	}
2919
2920
2921	/**
2922	* Helper for HMR3CheckError to log VMCS controls to the release log.
2923	*
2924	* @param idCpu The Virtual CPU ID.
2925	* @param pVmcsInfo The VMCS info. object.
2926	*/
2927	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2928	{
2929	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2930	{
2931	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2937	}
2938	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2939	{
2940	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2962	}
2963	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2964	{
2965	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2975	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2976	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2993	}
2994	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2995	{
2996	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2997	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2998	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2999	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3000	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
3007	}
3008	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
3009	{
3010	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
3011	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3012	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3013	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3014	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3015	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3016	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3017	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3018	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3019	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3020	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3021	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3022	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3023	}
3024	}
3025
3026
3027	/**
3028	* Check fatal VT-x/AMD-V error and produce some meaningful
3029	* log release message.
3030	*
3031	* @param pVM The cross context VM structure.
3032	* @param iStatusCode VBox status code.
3033	*/
3034	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3035	{
3036	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3037	{
3038	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3039	* might be getting inaccurate values for non-guru'ing EMTs. */
3040	PVMCPU pVCpu = &pVM->aCpus[i];
3041	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3042	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3043	switch (iStatusCode)
3044	{
3045	case VERR_VMX_INVALID_VMCS_PTR:
3046	{
3047	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3048	LogRel(("HM: CPU[%u] %s VMCS active\n", i, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3049	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", i, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3050	pVmcsInfo->HCPhysVmcs));
3051	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3052	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3053	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3054	break;
3055	}
3056
3057	case VERR_VMX_UNABLE_TO_START_VM:
3058	{
3059	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3060	LogRel(("HM: CPU[%u] %s VMCS active\n", i, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3061	LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3062	LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3063
3064	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3065	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3066	{
3067	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3068	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3069	}
3070	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3071	{
3072	hmR3CheckErrorLogVmcsCtls(i, pVmcsInfo);
3073	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVmcsInfo->HCPhysMsrBitmap));
3074	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", i, pVmcsInfo->HCPhysGuestMsrLoad));
3075	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", i, pVmcsInfo->HCPhysGuestMsrStore));
3076	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", i, pVmcsInfo->HCPhysHostMsrLoad));
3077	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", i, pVmcsInfo->cEntryMsrLoad));
3078	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", i, pVmcsInfo->cExitMsrStore));
3079	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", i, pVmcsInfo->cExitMsrLoad));
3080	}
3081	/** @todo Log VM-entry event injection control fields
3082	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3083	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3084	break;
3085	}
3086
3087	case VERR_VMX_INVALID_GUEST_STATE:
3088	{
3089	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3090	hmR3CheckErrorLogVmcsCtls(i, pVmcsInfo);
3091	break;
3092	}
3093
3094	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3095	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3096	case VERR_VMX_INVALID_VMXON_PTR:
3097	case VERR_VMX_UNEXPECTED_EXIT:
3098	case VERR_VMX_INVALID_VMCS_FIELD:
3099	case VERR_SVM_UNKNOWN_EXIT:
3100	case VERR_SVM_UNEXPECTED_EXIT:
3101	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3102	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3103	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3104	break;
3105	}
3106	}
3107
3108	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3109	{
3110	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3111	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3112	}
3113	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3114	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3115	}
3116
3117
3118	/**
3119	* Execute state save operation.
3120	*
3121	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3122	* is because we always save the VM state from ring-3 and thus most HM state
3123	* will be re-synced dynamically at runtime and don't need to be part of the VM
3124	* saved state.
3125	*
3126	* @returns VBox status code.
3127	* @param pVM The cross context VM structure.
3128	* @param pSSM SSM operation handle.
3129	*/
3130	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3131	{
3132	int rc;
3133
3134	Log(("hmR3Save:\n"));
3135
3136	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3137	{
3138	Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3139	if (pVM->cpum.ro.GuestFeatures.fSvm)
3140	{
3141	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3142	rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3143	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3144	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3145	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3146	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3147	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3148	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3149	rc \|= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3150	rc \|= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3151	rc \|= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3152	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3153	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3154	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3155	AssertRCReturn(rc, rc);
3156	}
3157	}
3158
3159	/* Save the guest patch data. */
3160	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3161	rc \|= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3162	rc \|= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3163
3164	/* Store all the guest patch records too. */
3165	rc \|= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3166	AssertRCReturn(rc, rc);
3167
3168	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3169	{
3170	AssertCompileSize(HMTPRINSTR, 4);
3171	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3172	rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3173	rc \|= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3174	rc \|= SSMR3PutU32(pSSM, pPatch->cbOp);
3175	rc \|= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3176	rc \|= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3177	rc \|= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3178	rc \|= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3179	rc \|= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3180	rc \|= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3181	rc \|= SSMR3PutU32(pSSM, pPatch->cFaults);
3182	AssertRCReturn(rc, rc);
3183	}
3184
3185	return VINF_SUCCESS;
3186	}
3187
3188
3189	/**
3190	* Execute state load operation.
3191	*
3192	* @returns VBox status code.
3193	* @param pVM The cross context VM structure.
3194	* @param pSSM SSM operation handle.
3195	* @param uVersion Data layout version.
3196	* @param uPass The data pass.
3197	*/
3198	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3199	{
3200	int rc;
3201
3202	LogFlowFunc(("uVersion=%u\n", uVersion));
3203	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3204
3205	/*
3206	* Validate version.
3207	*/
3208	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3209	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3210	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3211	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3212	{
3213	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3214	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3215	}
3216
3217	/*
3218	* Load per-VCPU state.
3219	*/
3220	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3221	{
3222	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3223	{
3224	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3225	if (pVM->cpum.ro.GuestFeatures.fSvm)
3226	{
3227	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3228	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3229	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3230	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3231	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3232	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3233	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3234	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3235	rc \|= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3236	rc \|= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3237	rc \|= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3238	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3239	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3240	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3241	AssertRCReturn(rc, rc);
3242	}
3243	}
3244	else
3245	{
3246	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3247	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3248	rc \|= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3249	rc \|= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3250
3251	/* VMX fWasInRealMode related data. */
3252	uint32_t uDummy;
3253	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3254	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3255	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3256	AssertRCReturn(rc, rc);
3257	}
3258	}
3259
3260	/*
3261	* Load TPR patching data.
3262	*/
3263	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3264	{
3265	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3266	rc \|= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3267	rc \|= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3268
3269	/* Fetch all TPR patch records. */
3270	rc \|= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3271	AssertRCReturn(rc, rc);
3272	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3273	{
3274	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3275	rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3276	rc \|= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3277	rc \|= SSMR3GetU32(pSSM, &pPatch->cbOp);
3278	rc \|= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3279	rc \|= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3280	rc \|= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3281
3282	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3283	pVM->hm.s.fTPRPatchingActive = true;
3284	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3285
3286	rc \|= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3287	rc \|= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3288	rc \|= SSMR3GetU32(pSSM, &pPatch->cFaults);
3289	rc \|= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3290	AssertRCReturn(rc, rc);
3291
3292	LogFlow(("hmR3Load: patch %d\n", i));
3293	LogFlow(("Key = %x\n", pPatch->Core.Key));
3294	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3295	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3296	LogFlow(("type = %d\n", pPatch->enmType));
3297	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3298	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3299	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3300	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3301
3302	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3303	AssertRCReturn(rc, rc);
3304	}
3305	}
3306
3307	return VINF_SUCCESS;
3308	}
3309
3310
3311	/**
3312	* Displays HM info.
3313	*
3314	* @param pVM The cross context VM structure.
3315	* @param pHlp The info helper functions.
3316	* @param pszArgs Arguments, ignored.
3317	*/
3318	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3319	{
3320	NOREF(pszArgs);
3321	PVMCPU pVCpu = VMMGetCpu(pVM);
3322	if (!pVCpu)
3323	pVCpu = &pVM->aCpus[0];
3324
3325	if (HMIsEnabled(pVM))
3326	{
3327	if (pVM->hm.s.vmx.fSupported)
3328	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3329	else
3330	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3331	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3332	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3333	if (pVM->hm.s.vmx.fSupported)
3334	{
3335	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3336	bool const fRealOnV86Active = pVmcsInfo->RealMode.fRealOnV86Active;
3337	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3338
3339	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3340	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3341	if (fRealOnV86Active)
3342	{
3343	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfo->RealMode.Eflags.u32);
3344	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfo->RealMode.AttrCS.u);
3345	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfo->RealMode.AttrSS.u);
3346	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfo->RealMode.AttrDS.u);
3347	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfo->RealMode.AttrES.u);
3348	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfo->RealMode.AttrFS.u);
3349	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfo->RealMode.AttrGS.u);
3350	}
3351	}
3352	}
3353	else
3354	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3355	}
3356
3357
3358	/**
3359	* Displays the HM pending event.
3360	*
3361	* @param pVM The cross context VM structure.
3362	* @param pHlp The info helper functions.
3363	* @param pszArgs Arguments, ignored.
3364	*/
3365	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3366	{
3367	NOREF(pszArgs);
3368	PVMCPU pVCpu = VMMGetCpu(pVM);
3369	if (!pVCpu)
3370	pVCpu = &pVM->aCpus[0];
3371
3372	if (HMIsEnabled(pVM))
3373	{
3374	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3375	if (pVCpu->hm.s.Event.fPending)
3376	{
3377	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3378	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3379	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3380	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3381	}
3382	}
3383	else
3384	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3385	}
3386
3387
3388	/**
3389	* Displays the SVM nested-guest VMCB cache.
3390	*
3391	* @param pVM The cross context VM structure.
3392	* @param pHlp The info helper functions.
3393	* @param pszArgs Arguments, ignored.
3394	*/
3395	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3396	{
3397	NOREF(pszArgs);
3398	PVMCPU pVCpu = VMMGetCpu(pVM);
3399	if (!pVCpu)
3400	pVCpu = &pVM->aCpus[0];
3401
3402	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3403	if ( fSvmEnabled
3404	&& pVM->cpum.ro.GuestFeatures.fSvm)
3405	{
3406	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3407	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3408	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3409	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3410	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3411	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3412	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3413	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3414	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3415	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3416	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3417	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3418	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3419	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3420	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3421	}
3422	else
3423	{
3424	if (!fSvmEnabled)
3425	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3426	else
3427	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3428	}
3429	}
3430

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 79537

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