HM.cpp@ 79581

Last change on this file since 79581 was 79581, checked in by vboxsync, 5 years ago
VMM/HM: Nested VMX: bugref:9180 Clarify that the task switch counter here is for task switch through a task gate in IDT (and not other sources like CALL/IRET/JMP instruction).
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 152.7 KB

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1	/* $Id: HM.cpp 79581 2019-07-08 04:46:28Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/patm.h>
54	#include <VBox/vmm/csam.h>
55	#include <VBox/vmm/selm.h>
56	#include <VBox/vmm/nem.h>
57	#ifdef VBOX_WITH_REM
58	# include <VBox/vmm/rem.h>
59	#endif
60	#include <VBox/vmm/hm_vmx.h>
61	#include <VBox/vmm/hm_svm.h>
62	#include "HMInternal.h"
63	#include <VBox/vmm/vm.h>
64	#include <VBox/vmm/uvm.h>
65	#include <VBox/err.h>
66	#include <VBox/param.h>
67
68	#include <iprt/assert.h>
69	#include <VBox/log.h>
70	#include <iprt/asm.h>
71	#include <iprt/asm-amd64-x86.h>
72	#include <iprt/env.h>
73	#include <iprt/thread.h>
74
75
76	/*********************************************************************************************************************************
77	* Defined Constants And Macros *
78	*********************************************************************************************************************************/
79	/** @def HMVMX_REPORT_FEAT
80	* Reports VT-x feature to the release log.
81	*
82	* @param a_uAllowed1 Mask of allowed-1 feature bits.
83	* @param a_uAllowed0 Mask of allowed-0 feature bits.
84	* @param a_StrDesc The description string to report.
85	* @param a_Featflag Mask of the feature to report.
86	*/
87	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
88	do { \
89	if ((a_uAllowed1) & (a_Featflag)) \
90	{ \
91	if ((a_uAllowed0) & (a_Featflag)) \
92	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
93	else \
94	LogRel(("HM: " a_StrDesc "\n")); \
95	} \
96	else \
97	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
98	} while (0)
99
100	/** @def HMVMX_REPORT_ALLOWED_FEAT
101	* Reports an allowed VT-x feature to the release log.
102	*
103	* @param a_uAllowed1 Mask of allowed-1 feature bits.
104	* @param a_StrDesc The description string to report.
105	* @param a_FeatFlag Mask of the feature to report.
106	*/
107	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
108	do { \
109	if ((a_uAllowed1) & (a_FeatFlag)) \
110	LogRel(("HM: " a_StrDesc "\n")); \
111	else \
112	LogRel(("HM: " a_StrDesc " not supported\n")); \
113	} while (0)
114
115	/** @def HMVMX_REPORT_MSR_CAP
116	* Reports MSR feature capability.
117	*
118	* @param a_MsrCaps Mask of MSR feature bits.
119	* @param a_StrDesc The description string to report.
120	* @param a_fCap Mask of the feature to report.
121	*/
122	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
123	do { \
124	if ((a_MsrCaps) & (a_fCap)) \
125	LogRel(("HM: " a_StrDesc "\n")); \
126	} while (0)
127
128	/** @def HMVMX_LOGREL_FEAT
129	* Dumps a feature flag from a bitmap of features to the release log.
130	*
131	* @param a_fVal The value of all the features.
132	* @param a_fMask The specific bitmask of the feature.
133	*/
134	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
135	do { \
136	if ((a_fVal) & (a_fMask)) \
137	LogRel(("HM: %s\n", #a_fMask)); \
138	} while (0)
139
140
141	/*********************************************************************************************************************************
142	* Internal Functions *
143	*********************************************************************************************************************************/
144	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
145	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
146	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
147	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
148	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
149	static int hmR3InitFinalizeR3(PVM pVM);
150	static int hmR3InitFinalizeR0(PVM pVM);
151	static int hmR3InitFinalizeR0Intel(PVM pVM);
152	static int hmR3InitFinalizeR0Amd(PVM pVM);
153	static int hmR3TermCPU(PVM pVM);
154
155
156
157	/**
158	* Initializes the HM.
159	*
160	* This is the very first component to really do init after CFGM so that we can
161	* establish the predominant execution engine for the VM prior to initializing
162	* other modules. It takes care of NEM initialization if needed (HM disabled or
163	* not available in HW).
164	*
165	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
166	* hypervisor API via NEM, and then back on raw-mode if that isn't available
167	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
168	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
169	* X, OS/2 and others).
170	*
171	* Note that a lot of the set up work is done in ring-0 and thus postponed till
172	* the ring-3 and ring-0 callback to HMR3InitCompleted.
173	*
174	* @returns VBox status code.
175	* @param pVM The cross context VM structure.
176	*
177	* @remarks Be careful with what we call here, since most of the VMM components
178	* are uninitialized.
179	*/
180	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
181	{
182	LogFlowFunc(("\n"));
183
184	/*
185	* Assert alignment and sizes.
186	*/
187	AssertCompileMemberAlignment(VM, hm.s, 32);
188	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
189
190	/*
191	* Register the saved state data unit.
192	*/
193	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
194	NULL, NULL, NULL,
195	NULL, hmR3Save, NULL,
196	NULL, hmR3Load, NULL);
197	if (RT_FAILURE(rc))
198	return rc;
199
200	/*
201	* Register info handlers.
202	*/
203	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
204	AssertRCReturn(rc, rc);
205
206	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
207	DBGFINFO_FLAGS_ALL_EMTS);
208	AssertRCReturn(rc, rc);
209
210	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
211	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
212	AssertRCReturn(rc, rc);
213
214	/*
215	* Read configuration.
216	*/
217	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
218
219	/*
220	* Validate the HM settings.
221	*/
222	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
223	"HMForced"
224	"\|UseNEMInstead"
225	"\|FallbackToNEM"
226	"\|EnableNestedPaging"
227	"\|EnableUX"
228	"\|EnableLargePages"
229	"\|EnableVPID"
230	"\|IBPBOnVMExit"
231	"\|IBPBOnVMEntry"
232	"\|SpecCtrlByHost"
233	"\|L1DFlushOnSched"
234	"\|L1DFlushOnVMEntry"
235	"\|MDSClearOnSched"
236	"\|MDSClearOnVMEntry"
237	"\|TPRPatchingEnabled"
238	"\|64bitEnabled"
239	"\|Exclusive"
240	"\|MaxResumeLoops"
241	"\|VmxPleGap"
242	"\|VmxPleWindow"
243	"\|UseVmxPreemptTimer"
244	"\|SvmPauseFilter"
245	"\|SvmPauseFilterThreshold"
246	"\|SvmVirtVmsaveVmload"
247	"\|SvmVGif"
248	"\|LovelyMesaDrvWorkaround",
249	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
250	if (RT_FAILURE(rc))
251	return rc;
252
253	/** @cfgm{/HM/HMForced, bool, false}
254	* Forces hardware virtualization, no falling back on raw-mode. HM must be
255	* enabled, i.e. /HMEnabled must be true. */
256	bool fHMForced;
257	#ifdef VBOX_WITH_RAW_MODE
258	rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
259	AssertRCReturn(rc, rc);
260	AssertLogRelMsgReturn(!fHMForced \|\| pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
261	VERR_INVALID_PARAMETER);
262	# if defined(RT_OS_DARWIN)
263	if (pVM->fHMEnabled)
264	fHMForced = true;
265	# endif
266	AssertLogRelMsgReturn(pVM->cCpus == 1 \|\| pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
267	VERR_INVALID_PARAMETER);
268	if (pVM->cCpus > 1)
269	fHMForced = true;
270	#else /* !VBOX_WITH_RAW_MODE */
271	AssertRelease(pVM->fHMEnabled);
272	fHMForced = true;
273	#endif /* !VBOX_WITH_RAW_MODE */
274
275	/** @cfgm{/HM/UseNEMInstead, bool, true}
276	* Don't use HM, use NEM instead. */
277	bool fUseNEMInstead = false;
278	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
279	AssertRCReturn(rc, rc);
280	if (fUseNEMInstead && pVM->fHMEnabled)
281	{
282	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
283	pVM->fHMEnabled = false;
284	}
285
286	/** @cfgm{/HM/FallbackToNEM, bool, true}
287	* Enables fallback on NEM. */
288	bool fFallbackToNEM = true;
289	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
290	AssertRCReturn(rc, rc);
291
292	/** @cfgm{/HM/EnableNestedPaging, bool, false}
293	* Enables nested paging (aka extended page tables). */
294	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
295	AssertRCReturn(rc, rc);
296
297	/** @cfgm{/HM/EnableUX, bool, true}
298	* Enables the VT-x unrestricted execution feature. */
299	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
300	AssertRCReturn(rc, rc);
301
302	/** @cfgm{/HM/EnableLargePages, bool, false}
303	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
304	* page table walking and maybe better TLB hit rate in some cases. */
305	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
306	AssertRCReturn(rc, rc);
307
308	/** @cfgm{/HM/EnableVPID, bool, false}
309	* Enables the VT-x VPID feature. */
310	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
311	AssertRCReturn(rc, rc);
312
313	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
314	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
315	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
316	AssertRCReturn(rc, rc);
317
318	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
319	* Enables AMD64 cpu features.
320	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
321	* already have the support. */
322	#ifdef VBOX_ENABLE_64_BITS_GUESTS
323	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
324	AssertLogRelRCReturn(rc, rc);
325	#else
326	pVM->hm.s.fAllow64BitGuests = false;
327	#endif
328
329	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
330	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
331	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
332	* latest PAUSE instruction to be start of a new PAUSE loop.
333	*/
334	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
335	AssertRCReturn(rc, rc);
336
337	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
338	* The pause-filter exiting window in TSC ticks. When the number of ticks
339	* between the current PAUSE instruction and first PAUSE of a loop exceeds
340	* VmxPleWindow, a VM-exit is triggered.
341	*
342	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
343	*/
344	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
345	AssertRCReturn(rc, rc);
346
347	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
348	* A counter that is decrement each time a PAUSE instruction is executed by the
349	* guest. When the counter is 0, a \#VMEXIT is triggered.
350	*
351	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
352	*/
353	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
354	AssertRCReturn(rc, rc);
355
356	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
357	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
358	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
359	* PauseFilter count is reset to its initial value. However, if PAUSE is
360	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
361	* be triggered.
362	*
363	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
364	* activated.
365	*/
366	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
367	AssertRCReturn(rc, rc);
368
369	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
370	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
371	* available. */
372	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
373	AssertRCReturn(rc, rc);
374
375	/** @cfgm{/HM/SvmVGif, bool, true}
376	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
377	* if it's available. */
378	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
379	AssertRCReturn(rc, rc);
380
381	/** @cfgm{/HM/Exclusive, bool}
382	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
383	* global init for each host CPU. If false, we do local init each time we wish
384	* to execute guest code.
385	*
386	* On Windows, default is false due to the higher risk of conflicts with other
387	* hypervisors.
388	*
389	* On Mac OS X, this setting is ignored since the code does not handle local
390	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
391	*/
392	#if defined(RT_OS_DARWIN)
393	pVM->hm.s.fGlobalInit = true;
394	#else
395	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
396	# if defined(RT_OS_WINDOWS)
397	false
398	# else
399	true
400	# endif
401	);
402	AssertLogRelRCReturn(rc, rc);
403	#endif
404
405	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
406	* The number of times to resume guest execution before we forcibly return to
407	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
408	* determines the default value. */
409	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
410	AssertLogRelRCReturn(rc, rc);
411
412	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
413	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
414	* available. */
415	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
416	AssertLogRelRCReturn(rc, rc);
417
418	/** @cfgm{/HM/IBPBOnVMExit, bool}
419	* Costly paranoia setting. */
420	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
421	AssertLogRelRCReturn(rc, rc);
422
423	/** @cfgm{/HM/IBPBOnVMEntry, bool}
424	* Costly paranoia setting. */
425	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
426	AssertLogRelRCReturn(rc, rc);
427
428	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
429	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
430	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
431	AssertLogRelRCReturn(rc, rc);
432
433	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
434	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
435	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
436	AssertLogRelRCReturn(rc, rc);
437
438	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
439	if (pVM->hm.s.fL1dFlushOnVmEntry)
440	pVM->hm.s.fL1dFlushOnSched = false;
441
442	/** @cfgm{/HM/SpecCtrlByHost, bool}
443	* Another expensive paranoia setting. */
444	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
445	AssertLogRelRCReturn(rc, rc);
446
447	/** @cfgm{/HM/MDSClearOnSched, bool, true}
448	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
449	* ignored on CPUs that aren't affected. */
450	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
451	AssertLogRelRCReturn(rc, rc);
452
453	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
454	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
455	* ignored on CPUs that aren't affected. */
456	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
457	AssertLogRelRCReturn(rc, rc);
458
459	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
460	if (pVM->hm.s.fMdsClearOnVmEntry)
461	pVM->hm.s.fMdsClearOnSched = false;
462
463	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
464	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
465	* the hypervisor it is running under. */
466	bool f;
467	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
468	AssertLogRelRCReturn(rc, rc);
469	for (VMCPUID i = 0; i < pVM->cCpus; i++)
470	pVM->aCpus[i].hm.s.fTrapXcptGpForLovelyMesaDrv = f;
471
472	/*
473	* Check if VT-x or AMD-v support according to the users wishes.
474	*/
475	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
476	* VERR_SVM_IN_USE. */
477	if (pVM->fHMEnabled)
478	{
479	uint32_t fCaps;
480	rc = SUPR3QueryVTCaps(&fCaps);
481	if (RT_SUCCESS(rc))
482	{
483	if (fCaps & SUPVTCAPS_AMD_V)
484	{
485	pVM->hm.s.svm.fSupported = true;
486	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
487	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
488	}
489	else if (fCaps & SUPVTCAPS_VT_X)
490	{
491	const char *pszWhy;
492	rc = SUPR3QueryVTxSupported(&pszWhy);
493	if (RT_SUCCESS(rc))
494	{
495	pVM->hm.s.vmx.fSupported = true;
496	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
497	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
498	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
499	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
500	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
501	}
502	else
503	{
504	/*
505	* Before failing, try fallback to NEM if we're allowed to do that.
506	*/
507	pVM->fHMEnabled = false;
508	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
509	if (fFallbackToNEM)
510	{
511	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
512	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
513
514	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
515	if ( RT_SUCCESS(rc2)
516	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
517	rc = VINF_SUCCESS;
518	}
519	if (RT_FAILURE(rc))
520	{
521	if (fHMForced)
522	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
523
524	/* Fall back to raw-mode. */
525	LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
526	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
527	}
528	}
529	}
530	else
531	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
532	VERR_INTERNAL_ERROR_5);
533
534	/*
535	* Do we require a little bit or raw-mode for 64-bit guest execution?
536	*/
537	pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
538	&& pVM->fHMEnabled
539	&& pVM->hm.s.fAllow64BitGuests;
540
541	/*
542	* Disable nested paging and unrestricted guest execution now if they're
543	* configured so that CPUM can make decisions based on our configuration.
544	*/
545	Assert(!pVM->hm.s.fNestedPaging);
546	if (pVM->hm.s.fAllowNestedPaging)
547	{
548	if (fCaps & SUPVTCAPS_NESTED_PAGING)
549	pVM->hm.s.fNestedPaging = true;
550	else
551	pVM->hm.s.fAllowNestedPaging = false;
552	}
553
554	if (fCaps & SUPVTCAPS_VT_X)
555	{
556	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
557	if (pVM->hm.s.vmx.fAllowUnrestricted)
558	{
559	if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
560	&& pVM->hm.s.fNestedPaging)
561	pVM->hm.s.vmx.fUnrestrictedGuest = true;
562	else
563	pVM->hm.s.vmx.fAllowUnrestricted = false;
564	}
565	}
566	}
567	else
568	{
569	const char *pszMsg;
570	switch (rc)
571	{
572	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
573	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
574	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
575	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
576	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
577	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
578	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
579	default:
580	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
581	}
582
583	/*
584	* Before failing, try fallback to NEM if we're allowed to do that.
585	*/
586	pVM->fHMEnabled = false;
587	if (fFallbackToNEM)
588	{
589	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
590	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
591	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
592	if ( RT_SUCCESS(rc2)
593	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
594	rc = VINF_SUCCESS;
595	}
596	if (RT_FAILURE(rc))
597	{
598	if (fHMForced)
599	return VM_SET_ERROR(pVM, rc, pszMsg);
600
601	LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
602	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
603	}
604	}
605	}
606	else
607	{
608	/*
609	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
610	*/
611	if (!fUseNEMInstead)
612	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
613	else
614	{
615	rc = NEMR3Init(pVM, false /fFallback/, true);
616	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
617	if (RT_FAILURE(rc))
618	return rc;
619	}
620	}
621
622	return VINF_SUCCESS;
623	}
624
625
626	/**
627	* Initializes HM components after ring-3 phase has been fully initialized.
628	*
629	* @returns VBox status code.
630	* @param pVM The cross context VM structure.
631	*/
632	static int hmR3InitFinalizeR3(PVM pVM)
633	{
634	LogFlowFunc(("\n"));
635
636	if (!HMIsEnabled(pVM))
637	return VINF_SUCCESS;
638
639	for (VMCPUID i = 0; i < pVM->cCpus; i++)
640	{
641	PVMCPU pVCpu = &pVM->aCpus[i];
642	pVCpu->hm.s.fActive = false;
643	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
644	}
645
646	#ifdef VBOX_WITH_STATISTICS
647	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
648	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
649	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
650	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
651	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
652	#endif
653
654	/*
655	* Statistics.
656	*/
657	for (VMCPUID i = 0; i < pVM->cCpus; i++)
658	{
659	PVMCPU pVCpu = &pVM->aCpus[i];
660	int rc;
661
662	#ifdef VBOX_WITH_STATISTICS
663	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
664	"Profiling of RTMpPokeCpu.",
665	"/PROF/CPU%d/HM/Poke", i);
666	AssertRC(rc);
667	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
668	"Profiling of poke wait.",
669	"/PROF/CPU%d/HM/PokeWait", i);
670	AssertRC(rc);
671	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
672	"Profiling of poke wait when RTMpPokeCpu fails.",
673	"/PROF/CPU%d/HM/PokeWaitFailed", i);
674	AssertRC(rc);
675	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
676	"Profiling of entry until entering GC.",
677	"/PROF/CPU%d/HM/Entry", i);
678	AssertRC(rc);
679	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
680	"Profiling of pre-exit processing after returning from GC.",
681	"/PROF/CPU%d/HM/SwitchFromGC_1", i);
682	AssertRC(rc);
683	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
684	"Profiling of exit handling (longjmps not included!)",
685	"/PROF/CPU%d/HM/SwitchFromGC_2", i);
686	AssertRC(rc);
687
688	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
689	"I/O.",
690	"/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
691	AssertRC(rc);
692	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
693	"MOV CRx.",
694	"/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
695	AssertRC(rc);
696	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
697	"Exceptions, NMIs.",
698	"/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
699	AssertRC(rc);
700	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitVmentry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
701	"VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.",
702	"/PROF/CPU%d/HM/SwitchFromGC_2/Vmentry", i);
703	AssertRC(rc);
704	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
705	"Profiling of importing guest state from hardware after VM-exit.",
706	"/PROF/CPU%d/HM/ImportGuestState", i);
707	AssertRC(rc);
708	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
709	"Profiling of exporting guest state to hardware before VM-entry.",
710	"/PROF/CPU%d/HM/ExportGuestState", i);
711	AssertRC(rc);
712	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
713	"Profiling of CPUMR0LoadGuestFPU.",
714	"/PROF/CPU%d/HM/LoadGuestFpuState", i);
715	AssertRC(rc);
716	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
717	"Profiling of execution of guest-code in hardware.",
718	"/PROF/CPU%d/HM/InGC", i);
719	AssertRC(rc);
720
721	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
722	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
723	STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
724	"/PROF/CPU%d/HM/Switcher3264", i);
725	AssertRC(rc);
726	# endif
727
728	# ifdef HM_PROFILE_EXIT_DISPATCH
729	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
730	STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
731	"/PROF/CPU%d/HM/ExitDispatch", i);
732	AssertRC(rc);
733	# endif
734
735	#endif
736	# define HM_REG_COUNTER(a, b, desc) \
737	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
738	AssertRC(rc);
739
740	#ifdef VBOX_WITH_STATISTICS
741	HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Total exits (including nested-guest exits).");
742	HM_REG_COUNTER(&pVCpu->hm.s.StatNestedExitAll, "/HM/CPU%d/Exit/NestedGuest/All", "Total nested-guest exits.");
743	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
744	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
745	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
746	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
747	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
748	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
749	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
750	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
751	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestTS, "/HM/CPU%d/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
752	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestOF, "/HM/CPU%d/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
753	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
754	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
755	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDF, "/HM/CPU%d/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
756	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBR, "/HM/CPU%d/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
757	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestAC, "/HM/CPU%d/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
758	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
759	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
760	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
761	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
762	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
763	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "MSR read.");
764	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "MSR write.");
765	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
766	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
767	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
768	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
769	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
770	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
771	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
772	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
773	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
774	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
775	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
776	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
777	HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
778	HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
779	HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
780	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/Instr/IO/Write", "I/O write.");
781	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/Instr/IO/Read", "I/O read.");
782	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/Instr/IO/WriteString", "String I/O write.");
783	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/Instr/IO/ReadString", "String I/O read.");
784	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
785	HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
786	#endif
787	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
788	#ifdef VBOX_WITH_STATISTICS
789	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
790	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
791	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
792	HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
793
794	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
795	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
796	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
797	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
798	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchVmReq, "/HM/CPU%d/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
799	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPgmPoolFlush, "/HM/CPU%d/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
800	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchDma, "/HM/CPU%d/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
801	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
802	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
803	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
804	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
805	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
806	#endif
807	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
808	#ifdef VBOX_WITH_STATISTICS
809	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchNstGstVmexit, "/HM/CPU%d/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
810
811	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
812	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
813	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
814	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
815
816	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
817	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
818	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
819	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
820	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
821	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
822	HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
823	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
824	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
825	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
826	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
827	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
828	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
829	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
830
831	HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
832	HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
833	HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
834
835	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
836	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
837	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
838
839	HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
840	HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
841	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
842	HM_REG_COUNTER(&pVCpu->hm.s.StatExportHostState, "/HM/CPU%d/Export/HostState", "VM-entry exporting host-state.");
843
844	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
845	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
846	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr, "/HM/CPU%d/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
847
848	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelBase, "/HM/CPU%d/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
849	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelLimit, "/HM/CPU%d/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
850	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadV86SelAttr, "/HM/CPU%d/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
851
852	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
853	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
854	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
855	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
856
857	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
858	HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
859	HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
860	#endif
861
862	#undef HM_REG_COUNTER
863
864	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
865
866	/*
867	* Guest Exit reason stats.
868	*/
869	pVCpu->hm.s.paStatExitReason = NULL;
870	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
871	(void **)&pVCpu->hm.s.paStatExitReason);
872	AssertRCReturn(rc, rc);
873
874	if (fCpuSupportsVmx)
875	{
876	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
877	{
878	const char *pszExitName = HMGetVmxExitName(j);
879	if (pszExitName)
880	{
881	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
882	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
883	AssertRCReturn(rc, rc);
884	}
885	}
886	}
887	else
888	{
889	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
890	{
891	const char *pszExitName = HMGetSvmExitName(j);
892	if (pszExitName)
893	{
894	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
895	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/Reason/%02x", i, j);
896	AssertRCReturn(rc, rc);
897	}
898	}
899	}
900	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
901	"Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
902	AssertRCReturn(rc, rc);
903	pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
904	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
905	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
906	# else
907	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
908	# endif
909
910	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
911	/*
912	* Nested-guest VM-exit reason stats.
913	*/
914	pVCpu->hm.s.paStatNestedExitReason = NULL;
915	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
916	(void **)&pVCpu->hm.s.paStatNestedExitReason);
917	AssertRCReturn(rc, rc);
918	if (fCpuSupportsVmx)
919	{
920	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
921	{
922	const char *pszExitName = HMGetVmxExitName(j);
923	if (pszExitName)
924	{
925	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
926	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/NestedGuest/Reason/%02x", i, j);
927	AssertRC(rc);
928	}
929	}
930	}
931	else
932	{
933	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
934	{
935	const char *pszExitName = HMGetSvmExitName(j);
936	if (pszExitName)
937	{
938	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
939	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%d/Exit/NestedGuest/Reason/%02x", i, j);
940	AssertRC(rc);
941	}
942	}
943	}
944	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
945	STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/Exit/NestedGuest/Reason/#NPF", i);
946	AssertRCReturn(rc, rc);
947	pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
948	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
949	Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
950	# else
951	Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
952	# endif
953	#endif
954
955	/*
956	* Injected events stats.
957	*/
958	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
959	AssertRCReturn(rc, rc);
960	pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
961	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
962	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
963	# else
964	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
965	# endif
966	for (unsigned j = 0; j < 255; j++)
967	{
968	STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
969	"Injected event.",
970	(j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
971	}
972
973	#endif /* VBOX_WITH_STATISTICS */
974	}
975
976	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
977	/*
978	* Magic marker for searching in crash dumps.
979	*/
980	for (VMCPUID i = 0; i < pVM->cCpus; i++)
981	{
982	PVMCPU pVCpu = &pVM->aCpus[i];
983
984	PVMXVMCSCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsCache;
985	strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
986	pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
987	}
988	#endif
989
990	return VINF_SUCCESS;
991	}
992
993
994	/**
995	* Called when a init phase has completed.
996	*
997	* @returns VBox status code.
998	* @param pVM The cross context VM structure.
999	* @param enmWhat The phase that completed.
1000	*/
1001	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1002	{
1003	switch (enmWhat)
1004	{
1005	case VMINITCOMPLETED_RING3:
1006	return hmR3InitFinalizeR3(pVM);
1007	case VMINITCOMPLETED_RING0:
1008	return hmR3InitFinalizeR0(pVM);
1009	default:
1010	return VINF_SUCCESS;
1011	}
1012	}
1013
1014
1015	/**
1016	* Turns off normal raw mode features.
1017	*
1018	* @param pVM The cross context VM structure.
1019	*/
1020	static void hmR3DisableRawMode(PVM pVM)
1021	{
1022	/** @todo r=bird: HM shouldn't be doing this crap. */
1023	/* Reinit the paging mode to force the new shadow mode. */
1024	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1025	{
1026	PVMCPU pVCpu = &pVM->aCpus[i];
1027	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1028	}
1029	}
1030
1031
1032	/**
1033	* Initialize VT-x or AMD-V.
1034	*
1035	* @returns VBox status code.
1036	* @param pVM The cross context VM structure.
1037	*/
1038	static int hmR3InitFinalizeR0(PVM pVM)
1039	{
1040	int rc;
1041
1042	if (!HMIsEnabled(pVM))
1043	return VINF_SUCCESS;
1044
1045	/*
1046	* Hack to allow users to work around broken BIOSes that incorrectly set
1047	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1048	*/
1049	if ( !pVM->hm.s.vmx.fSupported
1050	&& !pVM->hm.s.svm.fSupported
1051	&& pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1052	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1053	{
1054	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1055	pVM->hm.s.svm.fSupported = true;
1056	pVM->hm.s.svm.fIgnoreInUseError = true;
1057	pVM->hm.s.rcInit = VINF_SUCCESS;
1058	}
1059
1060	/*
1061	* Report ring-0 init errors.
1062	*/
1063	if ( !pVM->hm.s.vmx.fSupported
1064	&& !pVM->hm.s.svm.fSupported)
1065	{
1066	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1067	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1068	switch (pVM->hm.s.rcInit)
1069	{
1070	case VERR_VMX_IN_VMX_ROOT_MODE:
1071	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1072	case VERR_VMX_NO_VMX:
1073	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1074	case VERR_VMX_MSR_VMX_DISABLED:
1075	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1076	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1077	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1078	case VERR_VMX_MSR_LOCKING_FAILED:
1079	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1080	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1081	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1082	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1083	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1084
1085	case VERR_SVM_IN_USE:
1086	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1087	case VERR_SVM_NO_SVM:
1088	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1089	case VERR_SVM_DISABLED:
1090	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1091	}
1092	return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1093	}
1094
1095	/*
1096	* Enable VT-x or AMD-V on all host CPUs.
1097	*/
1098	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1099	if (RT_FAILURE(rc))
1100	{
1101	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1102	HMR3CheckError(pVM, rc);
1103	return rc;
1104	}
1105
1106	/*
1107	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1108	* (Main should have taken care of this already)
1109	*/
1110	if (!PDMHasIoApic(pVM))
1111	{
1112	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1113	pVM->hm.s.fTprPatchingAllowed = false;
1114	}
1115
1116	/*
1117	* Check if L1D flush is needed/possible.
1118	*/
1119	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1120	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1121	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1122	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1123	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
1124	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1125
1126	/*
1127	* Check if MDS flush is needed/possible.
1128	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
1129	*/
1130	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1131	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
1132	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1133	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1134	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1135	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1136	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1137	{
1138	if (!pVM->hm.s.fMdsClearOnSched)
1139	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1140	pVM->hm.s.fMdsClearOnVmEntry = false;
1141	}
1142	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1143	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1144	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1145
1146	/*
1147	* Sync options.
1148	*/
1149	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1150	* That will require a little bit of work, of course. */
1151	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1152	{
1153	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1154	PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1155	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1156	if (pVM->cpum.ro.HostFeatures.fIbpb)
1157	{
1158	if (pVM->hm.s.fIbpbOnVmExit)
1159	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1160	if (pVM->hm.s.fIbpbOnVmEntry)
1161	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1162	}
1163	if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1164	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_L1D_ENTRY;
1165	if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1166	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_MDS_ENTRY;
1167	if (iCpu == 0)
1168	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1169	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1170	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1171	}
1172
1173	/*
1174	* Do the vendor specific initialization
1175	*
1176	* Note! We disable release log buffering here since we're doing relatively
1177	* lot of logging and doesn't want to hit the disk with each LogRel
1178	* statement.
1179	*/
1180	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1181	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1182	if (pVM->hm.s.vmx.fSupported)
1183	rc = hmR3InitFinalizeR0Intel(pVM);
1184	else
1185	rc = hmR3InitFinalizeR0Amd(pVM);
1186	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1187	: "HM: VT-x/AMD-V init method: Local\n"));
1188	RTLogRelSetBuffering(fOldBuffered);
1189	pVM->hm.s.fInitialized = true;
1190
1191	return rc;
1192	}
1193
1194
1195	/**
1196	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1197	*/
1198	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1199	{
1200	NOREF(pVM);
1201	NOREF(pvAllocation);
1202	NOREF(GCPhysAllocation);
1203	}
1204
1205
1206	/**
1207	* Returns a description of the VMCS (and associated regions') memory type given the
1208	* IA32_VMX_BASIC MSR.
1209	*
1210	* @returns The descriptive memory type.
1211	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1212	*/
1213	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1214	{
1215	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1216	switch (uMemType)
1217	{
1218	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1219	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1220	}
1221	return "Unknown";
1222	}
1223
1224
1225	/**
1226	* Returns a single-line description of all the activity-states supported by the CPU
1227	* given the IA32_VMX_MISC MSR.
1228	*
1229	* @returns All supported activity states.
1230	* @param uMsrMisc IA32_VMX_MISC MSR value.
1231	*/
1232	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1233	{
1234	static const char * const s_apszActStates[] =
1235	{
1236	"",
1237	" ( HLT )",
1238	" ( SHUTDOWN )",
1239	" ( HLT SHUTDOWN )",
1240	" ( SIPI_WAIT )",
1241	" ( HLT SIPI_WAIT )",
1242	" ( SHUTDOWN SIPI_WAIT )",
1243	" ( HLT SHUTDOWN SIPI_WAIT )"
1244	};
1245	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1246	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1247	return s_apszActStates[idxActStates];
1248	}
1249
1250
1251	/**
1252	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1253	*
1254	* @param fFeatMsr The feature control MSR value.
1255	*/
1256	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1257	{
1258	uint64_t const val = fFeatMsr;
1259	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1260	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1261	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1262	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1263	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1264	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1265	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1266	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1267	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1268	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1269	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1270	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1271	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1272	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1273	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1274	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1275	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1276	}
1277
1278
1279	/**
1280	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1281	*
1282	* @param uBasicMsr The VMX basic MSR value.
1283	*/
1284	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1285	{
1286	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1287	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1288	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1289	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1290	"< 4 GB" : "None"));
1291	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1292	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1293	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1294	LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1295	}
1296
1297
1298	/**
1299	* Reports MSR_IA32_PINBASED_CTLS to the log.
1300	*
1301	* @param pVmxMsr Pointer to the VMX MSR.
1302	*/
1303	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1304	{
1305	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1306	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1307	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1313	}
1314
1315
1316	/**
1317	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1318	*
1319	* @param pVmxMsr Pointer to the VMX MSR.
1320	*/
1321	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1322	{
1323	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1324	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1325	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1347	}
1348
1349
1350	/**
1351	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1352	*
1353	* @param pVmxMsr Pointer to the VMX MSR.
1354	*/
1355	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1356	{
1357	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1358	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1359	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1360	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1361	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1366	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1367	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1368	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1387	}
1388
1389
1390	/**
1391	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1392	*
1393	* @param pVmxMsr Pointer to the VMX MSR.
1394	*/
1395	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1396	{
1397	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1398	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1399	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1409	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1410	}
1411
1412
1413	/**
1414	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1415	*
1416	* @param pVmxMsr Pointer to the VMX MSR.
1417	*/
1418	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1419	{
1420	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1421	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1422	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1423	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1424	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1425	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1428	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1429	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1430	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1431	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1432	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1433	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1434	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1435	}
1436
1437
1438	/**
1439	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1440	*
1441	* @param fCaps The VMX EPT/VPID capability MSR value.
1442	*/
1443	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1444	{
1445	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1446	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1447	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1448	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1449	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1450	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1451	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1452	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1453	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1454	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1455	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1456	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1457	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1458	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1459	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1460	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1461	}
1462
1463
1464	/**
1465	* Reports MSR_IA32_VMX_MISC MSR to the log.
1466	*
1467	* @param pVM Pointer to the VM.
1468	* @param fMisc The VMX misc. MSR value.
1469	*/
1470	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1471	{
1472	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1473	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1474	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1475	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1476	else
1477	{
1478	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1479	pVM->hm.s.vmx.cPreemptTimerShift));
1480	}
1481	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1482	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1483	hmR3VmxGetActivityStateAllDesc(fMisc)));
1484	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1485	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1486	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1487	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1488	VMX_MISC_MAX_MSRS(fMisc)));
1489	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1490	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1491	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1492	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1493	}
1494
1495
1496	/**
1497	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1498	*
1499	* @param uVmcsEnum The VMX VMCS enum MSR value.
1500	*/
1501	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1502	{
1503	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1504	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1505	}
1506
1507
1508	/**
1509	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1510	*
1511	* @param uVmFunc The VMX VMFUNC MSR value.
1512	*/
1513	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1514	{
1515	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1516	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1517	}
1518
1519
1520	/**
1521	* Reports VMX CR0, CR4 fixed MSRs.
1522	*
1523	* @param pMsrs Pointer to the VMX MSRs.
1524	*/
1525	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1526	{
1527	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1528	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1529	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1530	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1531	}
1532
1533
1534	/**
1535	* Finish VT-x initialization (after ring-0 init).
1536	*
1537	* @returns VBox status code.
1538	* @param pVM The cross context VM structure.
1539	*/
1540	static int hmR3InitFinalizeR0Intel(PVM pVM)
1541	{
1542	int rc;
1543
1544	Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1545	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1546
1547	LogRel(("HM: Using VT-x implementation 3.0\n"));
1548	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1549	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1550	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1551	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1552
1553	hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1554	hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1555
1556	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1557	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1558	if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1559	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1560
1561	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1562	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1563
1564	if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1565	{
1566	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1567	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1568	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1569	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1570	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1571	}
1572
1573	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1574	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1575	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1576	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1577	if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1578	hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1579	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1580
1581	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1582	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1583	{
1584	PCVMXVMCSINFO pVmcsInfo = &pVM->aCpus[i].hm.s.vmx.VmcsInfo;
1585	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVmcsInfo->HCPhysMsrBitmap));
1586	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVmcsInfo->HCPhysVmcs));
1587	}
1588	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1589	if (pVM->cpum.ro.GuestFeatures.fVmx)
1590	{
1591	LogRel(("HM: Nested-guest:\n"));
1592	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1593	{
1594	PCVMXVMCSINFO pVmcsInfoNstGst = &pVM->aCpus[i].hm.s.vmx.VmcsInfoNstGst;
1595	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVmcsInfoNstGst->HCPhysMsrBitmap));
1596	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVmcsInfoNstGst->HCPhysVmcs));
1597	}
1598	}
1599	#endif
1600
1601	/*
1602	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1603	*/
1604	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1605	\|\| (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1606	VERR_HM_IPE_1);
1607	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1608	\|\| ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1609	&& pVM->hm.s.fNestedPaging),
1610	VERR_HM_IPE_1);
1611
1612	/*
1613	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1614	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1615	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1616	*/
1617	if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1618	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1619	{
1620	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1621	LogRel(("HM: Disabled RDTSCP\n"));
1622	}
1623
1624	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1625	{
1626	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1627	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1628	if (RT_SUCCESS(rc))
1629	{
1630	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1631	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1632	esp. Figure 20-5.*/
1633	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1634	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1635
1636	/* Bit set to 0 means software interrupts are redirected to the
1637	8086 program interrupt handler rather than switching to
1638	protected-mode handler. */
1639	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1640
1641	/* Allow all port IO, so that port IO instructions do not cause
1642	exceptions and would instead cause a VM-exit (based on VT-x's
1643	IO bitmap which we currently configure to always cause an exit). */
1644	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1645	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1646
1647	/*
1648	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1649	* page table used in real and protected mode without paging with EPT.
1650	*/
1651	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1652	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1653	{
1654	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1655	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1656	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1657	\| X86_PDE4M_G;
1658	}
1659
1660	/* We convert it here every time as PCI regions could be reconfigured. */
1661	if (PDMVmmDevHeapIsEnabled(pVM))
1662	{
1663	RTGCPHYS GCPhys;
1664	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1665	AssertRCReturn(rc, rc);
1666	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1667
1668	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1669	AssertRCReturn(rc, rc);
1670	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1671	}
1672	}
1673	else
1674	{
1675	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1676	pVM->hm.s.vmx.pRealModeTSS = NULL;
1677	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1678	return VMSetError(pVM, rc, RT_SRC_POS,
1679	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1680	}
1681	}
1682
1683	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1684	: "HM: Guest support: 32-bit only\n"));
1685
1686	/*
1687	* Call ring-0 to set up the VM.
1688	*/
1689	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1690	if (rc != VINF_SUCCESS)
1691	{
1692	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1693	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1694	{
1695	PVMCPU pVCpu = &pVM->aCpus[i];
1696	LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1697	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1698	}
1699	HMR3CheckError(pVM, rc);
1700	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1701	}
1702
1703	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1704	LogRel(("HM: Enabled VMX\n"));
1705	pVM->hm.s.vmx.fEnabled = true;
1706
1707	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1708
1709	/*
1710	* Change the CPU features.
1711	*/
1712	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1713	if (pVM->hm.s.fAllow64BitGuests)
1714	{
1715	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1716	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1717	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1718	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1719	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1720	}
1721	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1722	(we reuse the host EFER in the switcher). */
1723	/** @todo this needs to be fixed properly!! */
1724	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1725	{
1726	if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1727	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1728	else
1729	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1730	}
1731
1732	/*
1733	* Log configuration details.
1734	*/
1735	if (pVM->hm.s.fNestedPaging)
1736	{
1737	LogRel(("HM: Enabled nested paging\n"));
1738	if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1739	LogRel(("HM: EPT flush type = Single context\n"));
1740	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1741	LogRel(("HM: EPT flush type = All contexts\n"));
1742	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1743	LogRel(("HM: EPT flush type = Not supported\n"));
1744	else
1745	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1746
1747	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1748	LogRel(("HM: Enabled unrestricted guest execution\n"));
1749
1750	#if HC_ARCH_BITS == 64
1751	if (pVM->hm.s.fLargePages)
1752	{
1753	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1754	PGMSetLargePageUsage(pVM, true);
1755	LogRel(("HM: Enabled large page support\n"));
1756	}
1757	#endif
1758	}
1759	else
1760	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1761
1762	if (pVM->hm.s.vmx.fVpid)
1763	{
1764	LogRel(("HM: Enabled VPID\n"));
1765	if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1766	LogRel(("HM: VPID flush type = Individual addresses\n"));
1767	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1768	LogRel(("HM: VPID flush type = Single context\n"));
1769	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1770	LogRel(("HM: VPID flush type = All contexts\n"));
1771	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1772	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1773	else
1774	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1775	}
1776	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1777	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1778
1779	if (pVM->hm.s.vmx.fUsePreemptTimer)
1780	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1781	else
1782	LogRel(("HM: Disabled VMX-preemption timer\n"));
1783
1784	if (pVM->hm.s.fVirtApicRegs)
1785	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1786
1787	if (pVM->hm.s.fPostedIntrs)
1788	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1789
1790	if (pVM->hm.s.vmx.fUseVmcsShadowing)
1791	{
1792	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1793	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1794	}
1795
1796	return VINF_SUCCESS;
1797	}
1798
1799
1800	/**
1801	* Finish AMD-V initialization (after ring-0 init).
1802	*
1803	* @returns VBox status code.
1804	* @param pVM The cross context VM structure.
1805	*/
1806	static int hmR3InitFinalizeR0Amd(PVM pVM)
1807	{
1808	Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1809
1810	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1811
1812	uint32_t u32Family;
1813	uint32_t u32Model;
1814	uint32_t u32Stepping;
1815	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1816	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1817	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1818	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1819	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1820	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1821	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1822
1823	/*
1824	* Enumerate AMD-V features.
1825	*/
1826	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1827	{
1828	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1829	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1830	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1831	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1832	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1833	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1834	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1835	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1836	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1837	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1838	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1839	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1840	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1841	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1842	#undef HMSVM_REPORT_FEATURE
1843	};
1844
1845	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1846	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1847	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1848	{
1849	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1850	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1851	}
1852	if (fSvmFeatures)
1853	for (unsigned iBit = 0; iBit < 32; iBit++)
1854	if (RT_BIT_32(iBit) & fSvmFeatures)
1855	LogRel(("HM: Reserved bit %u\n", iBit));
1856
1857	/*
1858	* Nested paging is determined in HMR3Init, verify the sanity of that.
1859	*/
1860	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1861	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1862	VERR_HM_IPE_1);
1863
1864	#if 0
1865	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1866	* here. */
1867	if (RTR0IsPostIpiSupport())
1868	pVM->hm.s.fPostedIntrs = true;
1869	#endif
1870
1871	/*
1872	* Call ring-0 to set up the VM.
1873	*/
1874	int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1875	if (rc != VINF_SUCCESS)
1876	{
1877	AssertMsgFailed(("%Rrc\n", rc));
1878	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1879	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1880	}
1881
1882	LogRel(("HM: Enabled SVM\n"));
1883	pVM->hm.s.svm.fEnabled = true;
1884
1885	if (pVM->hm.s.fNestedPaging)
1886	{
1887	LogRel(("HM: Enabled nested paging\n"));
1888
1889	/*
1890	* Enable large pages (2 MB) if applicable.
1891	*/
1892	#if HC_ARCH_BITS == 64
1893	if (pVM->hm.s.fLargePages)
1894	{
1895	PGMSetLargePageUsage(pVM, true);
1896	LogRel(("HM: Enabled large page support\n"));
1897	}
1898	#endif
1899	}
1900
1901	if (pVM->hm.s.fVirtApicRegs)
1902	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1903
1904	if (pVM->hm.s.fPostedIntrs)
1905	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1906
1907	hmR3DisableRawMode(pVM);
1908
1909	/*
1910	* Change the CPU features.
1911	*/
1912	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1913	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1914	if (pVM->hm.s.fAllow64BitGuests)
1915	{
1916	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1917	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1918	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1919	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1920	}
1921	/* Turn on NXE if PAE has been enabled. */
1922	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1923	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1924
1925	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1926	: "HM: Disabled TPR patching\n"));
1927
1928	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1929	: "HM: Guest support: 32-bit only\n"));
1930	return VINF_SUCCESS;
1931	}
1932
1933
1934	/**
1935	* Applies relocations to data and code managed by this
1936	* component. This function will be called at init and
1937	* whenever the VMM need to relocate it self inside the GC.
1938	*
1939	* @param pVM The cross context VM structure.
1940	*/
1941	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1942	{
1943	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1944
1945	/* Fetch the current paging mode during the relocate callback during state loading. */
1946	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1947	{
1948	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1949	{
1950	PVMCPU pVCpu = &pVM->aCpus[i];
1951	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1952	}
1953	}
1954	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1955	if (HMIsEnabled(pVM))
1956	{
1957	switch (PGMGetHostMode(pVM))
1958	{
1959	case PGMMODE_32_BIT:
1960	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1961	break;
1962
1963	case PGMMODE_PAE:
1964	case PGMMODE_PAE_NX:
1965	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1966	break;
1967
1968	default:
1969	AssertFailed();
1970	break;
1971	}
1972	}
1973	#endif
1974	return;
1975	}
1976
1977
1978	/**
1979	* Terminates the HM.
1980	*
1981	* Termination means cleaning up and freeing all resources,
1982	* the VM itself is, at this point, powered off or suspended.
1983	*
1984	* @returns VBox status code.
1985	* @param pVM The cross context VM structure.
1986	*/
1987	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1988	{
1989	if (pVM->hm.s.vmx.pRealModeTSS)
1990	{
1991	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1992	pVM->hm.s.vmx.pRealModeTSS = 0;
1993	}
1994	hmR3TermCPU(pVM);
1995	return 0;
1996	}
1997
1998
1999	/**
2000	* Terminates the per-VCPU HM.
2001	*
2002	* @returns VBox status code.
2003	* @param pVM The cross context VM structure.
2004	*/
2005	static int hmR3TermCPU(PVM pVM)
2006	{
2007	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2008	{
2009	PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2010
2011	#ifdef VBOX_WITH_STATISTICS
2012	if (pVCpu->hm.s.paStatExitReason)
2013	{
2014	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2015	pVCpu->hm.s.paStatExitReason = NULL;
2016	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2017	}
2018	if (pVCpu->hm.s.paStatInjectedIrqs)
2019	{
2020	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2021	pVCpu->hm.s.paStatInjectedIrqs = NULL;
2022	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2023	}
2024	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
2025	if (pVCpu->hm.s.paStatNestedExitReason)
2026	{
2027	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
2028	pVCpu->hm.s.paStatNestedExitReason = NULL;
2029	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
2030	}
2031	# endif
2032	#endif
2033
2034	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2035	memset(pVCpu->hm.s.vmx.VmcsCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VmcsCache.aMagic));
2036	pVCpu->hm.s.vmx.VmcsCache.uMagic = 0;
2037	pVCpu->hm.s.vmx.VmcsCache.uPos = 0xffffffff;
2038	#endif
2039	}
2040	return 0;
2041	}
2042
2043
2044	/**
2045	* Resets a virtual CPU.
2046	*
2047	* Used by HMR3Reset and CPU hot plugging.
2048	*
2049	* @param pVCpu The cross context virtual CPU structure to reset.
2050	*/
2051	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2052	{
2053	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2054	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2055	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2056
2057	pVCpu->hm.s.fActive = false;
2058	pVCpu->hm.s.Event.fPending = false;
2059	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2060	pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32 = false;
2061	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2062	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2063	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2064	{
2065	pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32 = false;
2066	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2067	}
2068	#endif
2069
2070	/* Reset the contents of the read cache. */
2071	PVMXVMCSCACHE pVmcsCache = &pVCpu->hm.s.vmx.VmcsCache;
2072	for (unsigned j = 0; j < pVmcsCache->Read.cValidEntries; j++)
2073	pVmcsCache->Read.aFieldVal[j] = 0;
2074
2075	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2076	/* Magic marker for searching in crash dumps. */
2077	strcpy((char *)pVmcsCache->aMagic, "VMCSCACHE Magic");
2078	pVmcsCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2079	#endif
2080	}
2081
2082
2083	/**
2084	* The VM is being reset.
2085	*
2086	* For the HM component this means that any GDT/LDT/TSS monitors
2087	* needs to be removed.
2088	*
2089	* @param pVM The cross context VM structure.
2090	*/
2091	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2092	{
2093	LogFlow(("HMR3Reset:\n"));
2094
2095	if (HMIsEnabled(pVM))
2096	hmR3DisableRawMode(pVM);
2097
2098	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2099	{
2100	PVMCPU pVCpu = &pVM->aCpus[i];
2101
2102	HMR3ResetCpu(pVCpu);
2103	}
2104
2105	/* Clear all patch information. */
2106	pVM->hm.s.pGuestPatchMem = 0;
2107	pVM->hm.s.pFreeGuestPatchMem = 0;
2108	pVM->hm.s.cbGuestPatchMem = 0;
2109	pVM->hm.s.cPatches = 0;
2110	pVM->hm.s.PatchTree = 0;
2111	pVM->hm.s.fTPRPatchingActive = false;
2112	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2113	}
2114
2115
2116	/**
2117	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2118	*
2119	* @returns VBox strict status code.
2120	* @param pVM The cross context VM structure.
2121	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2122	* @param pvUser Unused.
2123	*/
2124	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2125	{
2126	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2127
2128	/* Only execute the handler on the VCPU the original patch request was issued. */
2129	if (pVCpu->idCpu != idCpu)
2130	return VINF_SUCCESS;
2131
2132	Log(("hmR3RemovePatches\n"));
2133	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2134	{
2135	uint8_t abInstr[15];
2136	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2137	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2138	int rc;
2139
2140	#ifdef LOG_ENABLED
2141	char szOutput[256];
2142	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2143	szOutput, sizeof(szOutput), NULL);
2144	if (RT_SUCCESS(rc))
2145	Log(("Patched instr: %s\n", szOutput));
2146	#endif
2147
2148	/* Check if the instruction is still the same. */
2149	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2150	if (rc != VINF_SUCCESS)
2151	{
2152	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2153	continue; /* swapped out or otherwise removed; skip it. */
2154	}
2155
2156	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2157	{
2158	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2159	continue; /* skip it. */
2160	}
2161
2162	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2163	AssertRC(rc);
2164
2165	#ifdef LOG_ENABLED
2166	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2167	szOutput, sizeof(szOutput), NULL);
2168	if (RT_SUCCESS(rc))
2169	Log(("Original instr: %s\n", szOutput));
2170	#endif
2171	}
2172	pVM->hm.s.cPatches = 0;
2173	pVM->hm.s.PatchTree = 0;
2174	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2175	pVM->hm.s.fTPRPatchingActive = false;
2176	return VINF_SUCCESS;
2177	}
2178
2179
2180	/**
2181	* Worker for enabling patching in a VT-x/AMD-V guest.
2182	*
2183	* @returns VBox status code.
2184	* @param pVM The cross context VM structure.
2185	* @param idCpu VCPU to execute hmR3RemovePatches on.
2186	* @param pPatchMem Patch memory range.
2187	* @param cbPatchMem Size of the memory range.
2188	*/
2189	static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2190	{
2191	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2192	AssertRC(rc);
2193
2194	pVM->hm.s.pGuestPatchMem = pPatchMem;
2195	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2196	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2197	return VINF_SUCCESS;
2198	}
2199
2200
2201	/**
2202	* Enable patching in a VT-x/AMD-V guest
2203	*
2204	* @returns VBox status code.
2205	* @param pVM The cross context VM structure.
2206	* @param pPatchMem Patch memory range.
2207	* @param cbPatchMem Size of the memory range.
2208	*/
2209	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2210	{
2211	VM_ASSERT_EMT(pVM);
2212	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2213	if (pVM->cCpus > 1)
2214	{
2215	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2216	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2217	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2218	AssertRC(rc);
2219	return rc;
2220	}
2221	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2222	}
2223
2224
2225	/**
2226	* Disable patching in a VT-x/AMD-V guest.
2227	*
2228	* @returns VBox status code.
2229	* @param pVM The cross context VM structure.
2230	* @param pPatchMem Patch memory range.
2231	* @param cbPatchMem Size of the memory range.
2232	*/
2233	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2234	{
2235	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2236	RT_NOREF2(pPatchMem, cbPatchMem);
2237
2238	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2239	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2240
2241	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2242	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2243	(void *)(uintptr_t)VMMGetCpuId(pVM));
2244	AssertRC(rc);
2245
2246	pVM->hm.s.pGuestPatchMem = 0;
2247	pVM->hm.s.pFreeGuestPatchMem = 0;
2248	pVM->hm.s.cbGuestPatchMem = 0;
2249	pVM->hm.s.fTPRPatchingActive = false;
2250	return VINF_SUCCESS;
2251	}
2252
2253
2254	/**
2255	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2256	*
2257	* @returns VBox strict status code.
2258	* @param pVM The cross context VM structure.
2259	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2260	* @param pvUser User specified CPU context.
2261	*
2262	*/
2263	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2264	{
2265	/*
2266	* Only execute the handler on the VCPU the original patch request was
2267	* issued. (The other CPU(s) might not yet have switched to protected
2268	* mode, nor have the correct memory context.)
2269	*/
2270	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2271	if (pVCpu->idCpu != idCpu)
2272	return VINF_SUCCESS;
2273
2274	/*
2275	* We're racing other VCPUs here, so don't try patch the instruction twice
2276	* and make sure there is still room for our patch record.
2277	*/
2278	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2279	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2280	if (pPatch)
2281	{
2282	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2283	return VINF_SUCCESS;
2284	}
2285	uint32_t const idx = pVM->hm.s.cPatches;
2286	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2287	{
2288	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2289	return VINF_SUCCESS;
2290	}
2291	pPatch = &pVM->hm.s.aPatches[idx];
2292
2293	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2294
2295	/*
2296	* Disassembler the instruction and get cracking.
2297	*/
2298	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2299	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2300	uint32_t cbOp;
2301	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2302	AssertRC(rc);
2303	if ( rc == VINF_SUCCESS
2304	&& pDis->pCurInstr->uOpcode == OP_MOV
2305	&& cbOp >= 3)
2306	{
2307	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2308
2309	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2310	AssertRC(rc);
2311
2312	pPatch->cbOp = cbOp;
2313
2314	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2315	{
2316	/* write. */
2317	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2318	{
2319	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2320	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2321	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2322	}
2323	else
2324	{
2325	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2326	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2327	pPatch->uSrcOperand = pDis->Param2.uValue;
2328	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2329	}
2330	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2331	AssertRC(rc);
2332
2333	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2334	pPatch->cbNewOp = sizeof(s_abVMMCall);
2335	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2336	}
2337	else
2338	{
2339	/*
2340	* TPR Read.
2341	*
2342	* Found:
2343	* mov eax, dword [fffe0080] (5 bytes)
2344	* Check if next instruction is:
2345	* shr eax, 4
2346	*/
2347	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2348
2349	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2350	uint8_t const cbOpMmio = cbOp;
2351	uint64_t const uSavedRip = pCtx->rip;
2352
2353	pCtx->rip += cbOp;
2354	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2355	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2356	pCtx->rip = uSavedRip;
2357
2358	if ( rc == VINF_SUCCESS
2359	&& pDis->pCurInstr->uOpcode == OP_SHR
2360	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2361	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2362	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2363	&& pDis->Param2.uValue == 4
2364	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2365	{
2366	uint8_t abInstr[15];
2367
2368	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2369	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2370	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2371	AssertRC(rc);
2372
2373	pPatch->cbOp = cbOpMmio + cbOp;
2374
2375	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2376	abInstr[0] = 0xf0;
2377	abInstr[1] = 0x0f;
2378	abInstr[2] = 0x20;
2379	abInstr[3] = 0xc0 \| pDis->Param1.Base.idxGenReg;
2380	for (unsigned i = 4; i < pPatch->cbOp; i++)
2381	abInstr[i] = 0x90; /* nop */
2382
2383	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2384	AssertRC(rc);
2385
2386	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2387	pPatch->cbNewOp = pPatch->cbOp;
2388	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2389
2390	Log(("Acceptable read/shr candidate!\n"));
2391	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2392	}
2393	else
2394	{
2395	pPatch->enmType = HMTPRINSTR_READ;
2396	pPatch->uDstOperand = idxMmioReg;
2397
2398	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2399	AssertRC(rc);
2400
2401	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2402	pPatch->cbNewOp = sizeof(s_abVMMCall);
2403	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2404	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2405	}
2406	}
2407
2408	pPatch->Core.Key = pCtx->eip;
2409	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2410	AssertRC(rc);
2411
2412	pVM->hm.s.cPatches++;
2413	return VINF_SUCCESS;
2414	}
2415
2416	/*
2417	* Save invalid patch, so we will not try again.
2418	*/
2419	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2420	pPatch->Core.Key = pCtx->eip;
2421	pPatch->enmType = HMTPRINSTR_INVALID;
2422	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2423	AssertRC(rc);
2424	pVM->hm.s.cPatches++;
2425	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2426	return VINF_SUCCESS;
2427	}
2428
2429
2430	/**
2431	* Callback to patch a TPR instruction (jump to generated code).
2432	*
2433	* @returns VBox strict status code.
2434	* @param pVM The cross context VM structure.
2435	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2436	* @param pvUser User specified CPU context.
2437	*
2438	*/
2439	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2440	{
2441	/*
2442	* Only execute the handler on the VCPU the original patch request was
2443	* issued. (The other CPU(s) might not yet have switched to protected
2444	* mode, nor have the correct memory context.)
2445	*/
2446	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2447	if (pVCpu->idCpu != idCpu)
2448	return VINF_SUCCESS;
2449
2450	/*
2451	* We're racing other VCPUs here, so don't try patch the instruction twice
2452	* and make sure there is still room for our patch record.
2453	*/
2454	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2455	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2456	if (pPatch)
2457	{
2458	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2459	return VINF_SUCCESS;
2460	}
2461	uint32_t const idx = pVM->hm.s.cPatches;
2462	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2463	{
2464	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2465	return VINF_SUCCESS;
2466	}
2467	pPatch = &pVM->hm.s.aPatches[idx];
2468
2469	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2470	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2471
2472	/*
2473	* Disassemble the instruction and get cracking.
2474	*/
2475	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2476	uint32_t cbOp;
2477	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2478	AssertRC(rc);
2479	if ( rc == VINF_SUCCESS
2480	&& pDis->pCurInstr->uOpcode == OP_MOV
2481	&& cbOp >= 5)
2482	{
2483	uint8_t aPatch[64];
2484	uint32_t off = 0;
2485
2486	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2487	AssertRC(rc);
2488
2489	pPatch->cbOp = cbOp;
2490	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2491
2492	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2493	{
2494	/*
2495	* TPR write:
2496	*
2497	* push ECX [51]
2498	* push EDX [52]
2499	* push EAX [50]
2500	* xor EDX,EDX [31 D2]
2501	* mov EAX,EAX [89 C0]
2502	* or
2503	* mov EAX,0000000CCh [B8 CC 00 00 00]
2504	* mov ECX,0C0000082h [B9 82 00 00 C0]
2505	* wrmsr [0F 30]
2506	* pop EAX [58]
2507	* pop EDX [5A]
2508	* pop ECX [59]
2509	* jmp return_address [E9 return_address]
2510	*/
2511	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2512
2513	aPatch[off++] = 0x51; /* push ecx */
2514	aPatch[off++] = 0x52; /* push edx */
2515	if (!fUsesEax)
2516	aPatch[off++] = 0x50; /* push eax */
2517	aPatch[off++] = 0x31; /* xor edx, edx */
2518	aPatch[off++] = 0xd2;
2519	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2520	{
2521	if (!fUsesEax)
2522	{
2523	aPatch[off++] = 0x89; /* mov eax, src_reg */
2524	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2525	}
2526	}
2527	else
2528	{
2529	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2530	aPatch[off++] = 0xb8; /* mov eax, immediate */
2531	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2532	off += sizeof(uint32_t);
2533	}
2534	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2535	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2536	off += sizeof(uint32_t);
2537
2538	aPatch[off++] = 0x0f; /* wrmsr */
2539	aPatch[off++] = 0x30;
2540	if (!fUsesEax)
2541	aPatch[off++] = 0x58; /* pop eax */
2542	aPatch[off++] = 0x5a; /* pop edx */
2543	aPatch[off++] = 0x59; /* pop ecx */
2544	}
2545	else
2546	{
2547	/*
2548	* TPR read:
2549	*
2550	* push ECX [51]
2551	* push EDX [52]
2552	* push EAX [50]
2553	* mov ECX,0C0000082h [B9 82 00 00 C0]
2554	* rdmsr [0F 32]
2555	* mov EAX,EAX [89 C0]
2556	* pop EAX [58]
2557	* pop EDX [5A]
2558	* pop ECX [59]
2559	* jmp return_address [E9 return_address]
2560	*/
2561	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2562
2563	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2564	aPatch[off++] = 0x51; /* push ecx */
2565	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2566	aPatch[off++] = 0x52; /* push edx */
2567	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2568	aPatch[off++] = 0x50; /* push eax */
2569
2570	aPatch[off++] = 0x31; /* xor edx, edx */
2571	aPatch[off++] = 0xd2;
2572
2573	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2574	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2575	off += sizeof(uint32_t);
2576
2577	aPatch[off++] = 0x0f; /* rdmsr */
2578	aPatch[off++] = 0x32;
2579
2580	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2581	{
2582	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2583	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2584	}
2585
2586	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2587	aPatch[off++] = 0x58; /* pop eax */
2588	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2589	aPatch[off++] = 0x5a; /* pop edx */
2590	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2591	aPatch[off++] = 0x59; /* pop ecx */
2592	}
2593	aPatch[off++] = 0xe9; /* jmp return_address */
2594	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2595	off += sizeof(RTRCUINTPTR);
2596
2597	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2598	{
2599	/* Write new code to the patch buffer. */
2600	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2601	AssertRC(rc);
2602
2603	#ifdef LOG_ENABLED
2604	uint32_t cbCurInstr;
2605	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2606	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2607	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2608	{
2609	char szOutput[256];
2610	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2611	szOutput, sizeof(szOutput), &cbCurInstr);
2612	if (RT_SUCCESS(rc))
2613	Log(("Patch instr %s\n", szOutput));
2614	else
2615	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2616	}
2617	#endif
2618
2619	pPatch->aNewOpcode[0] = 0xE9;
2620	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2621
2622	/* Overwrite the TPR instruction with a jump. */
2623	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2624	AssertRC(rc);
2625
2626	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2627
2628	pVM->hm.s.pFreeGuestPatchMem += off;
2629	pPatch->cbNewOp = 5;
2630
2631	pPatch->Core.Key = pCtx->eip;
2632	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2633	AssertRC(rc);
2634
2635	pVM->hm.s.cPatches++;
2636	pVM->hm.s.fTPRPatchingActive = true;
2637	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2638	return VINF_SUCCESS;
2639	}
2640
2641	Log(("Ran out of space in our patch buffer!\n"));
2642	}
2643	else
2644	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2645
2646
2647	/*
2648	* Save invalid patch, so we will not try again.
2649	*/
2650	pPatch = &pVM->hm.s.aPatches[idx];
2651	pPatch->Core.Key = pCtx->eip;
2652	pPatch->enmType = HMTPRINSTR_INVALID;
2653	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2654	AssertRC(rc);
2655	pVM->hm.s.cPatches++;
2656	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2657	return VINF_SUCCESS;
2658	}
2659
2660
2661	/**
2662	* Attempt to patch TPR mmio instructions.
2663	*
2664	* @returns VBox status code.
2665	* @param pVM The cross context VM structure.
2666	* @param pVCpu The cross context virtual CPU structure.
2667	*/
2668	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2669	{
2670	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2671	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2672	(void *)(uintptr_t)pVCpu->idCpu);
2673	AssertRC(rc);
2674	return rc;
2675	}
2676
2677
2678	/**
2679	* Checks if we need to reschedule due to VMM device heap changes.
2680	*
2681	* @returns true if a reschedule is required, otherwise false.
2682	* @param pVM The cross context VM structure.
2683	* @param pCtx VM execution context.
2684	*/
2685	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2686	{
2687	/*
2688	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2689	* when the unrestricted guest execution feature is missing (VT-x only).
2690	*/
2691	if ( pVM->hm.s.vmx.fEnabled
2692	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2693	&& CPUMIsGuestInRealModeEx(pCtx)
2694	&& !PDMVmmDevHeapIsEnabled(pVM))
2695	return true;
2696
2697	return false;
2698	}
2699
2700
2701	/**
2702	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2703	* event settings changes.
2704	*
2705	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2706	* function is just updating the VM globals.
2707	*
2708	* @param pVM The VM cross context VM structure.
2709	* @thread EMT(0)
2710	*/
2711	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2712	{
2713	/* Interrupts. */
2714	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2715	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2716
2717	/* CPU Exceptions. */
2718	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2719	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2720	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2721	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2722
2723	/* Common VM exits. */
2724	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2725	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2726	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2727	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2728
2729	/* Vendor specific VM exits. */
2730	if (HMR3IsVmxEnabled(pVM->pUVM))
2731	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2732	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2733	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2734	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2735	else
2736	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2737	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2738	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2739	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2740
2741	/* Done. */
2742	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2743	}
2744
2745
2746	/**
2747	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2748	*
2749	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2750	* per CPU settings.
2751	*
2752	* @param pVM The VM cross context VM structure.
2753	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2754	*/
2755	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2756	{
2757	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2758	}
2759
2760
2761	/**
2762	* Checks if we are currently using hardware acceleration.
2763	*
2764	* @returns true if hardware acceleration is being used, otherwise false.
2765	* @param pVCpu The cross context virtual CPU structure.
2766	*/
2767	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2768	{
2769	return pVCpu->hm.s.fActive;
2770	}
2771
2772
2773	/**
2774	* External interface for querying whether hardware acceleration is enabled.
2775	*
2776	* @returns true if VT-x or AMD-V is being used, otherwise false.
2777	* @param pUVM The user mode VM handle.
2778	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2779	*/
2780	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2781	{
2782	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2783	PVM pVM = pUVM->pVM;
2784	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2785	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2786	}
2787
2788
2789	/**
2790	* External interface for querying whether VT-x is being used.
2791	*
2792	* @returns true if VT-x is being used, otherwise false.
2793	* @param pUVM The user mode VM handle.
2794	* @sa HMR3IsSvmEnabled, HMIsEnabled
2795	*/
2796	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2797	{
2798	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2799	PVM pVM = pUVM->pVM;
2800	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2801	return pVM->hm.s.vmx.fEnabled
2802	&& pVM->hm.s.vmx.fSupported
2803	&& pVM->fHMEnabled;
2804	}
2805
2806
2807	/**
2808	* External interface for querying whether AMD-V is being used.
2809	*
2810	* @returns true if VT-x is being used, otherwise false.
2811	* @param pUVM The user mode VM handle.
2812	* @sa HMR3IsVmxEnabled, HMIsEnabled
2813	*/
2814	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2815	{
2816	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2817	PVM pVM = pUVM->pVM;
2818	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2819	return pVM->hm.s.svm.fEnabled
2820	&& pVM->hm.s.svm.fSupported
2821	&& pVM->fHMEnabled;
2822	}
2823
2824
2825	/**
2826	* Checks if we are currently using nested paging.
2827	*
2828	* @returns true if nested paging is being used, otherwise false.
2829	* @param pUVM The user mode VM handle.
2830	*/
2831	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2832	{
2833	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2834	PVM pVM = pUVM->pVM;
2835	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2836	return pVM->hm.s.fNestedPaging;
2837	}
2838
2839
2840	/**
2841	* Checks if virtualized APIC registers is enabled.
2842	*
2843	* When enabled this feature allows the hardware to access most of the
2844	* APIC registers in the virtual-APIC page without causing VM-exits. See
2845	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2846	*
2847	* @returns true if virtualized APIC registers is enabled, otherwise
2848	* false.
2849	* @param pUVM The user mode VM handle.
2850	*/
2851	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2852	{
2853	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2854	PVM pVM = pUVM->pVM;
2855	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2856	return pVM->hm.s.fVirtApicRegs;
2857	}
2858
2859
2860	/**
2861	* Checks if APIC posted-interrupt processing is enabled.
2862	*
2863	* This returns whether we can deliver interrupts to the guest without
2864	* leaving guest-context by updating APIC state from host-context.
2865	*
2866	* @returns true if APIC posted-interrupt processing is enabled,
2867	* otherwise false.
2868	* @param pUVM The user mode VM handle.
2869	*/
2870	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2871	{
2872	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2873	PVM pVM = pUVM->pVM;
2874	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2875	return pVM->hm.s.fPostedIntrs;
2876	}
2877
2878
2879	/**
2880	* Checks if we are currently using VPID in VT-x mode.
2881	*
2882	* @returns true if VPID is being used, otherwise false.
2883	* @param pUVM The user mode VM handle.
2884	*/
2885	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2886	{
2887	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2888	PVM pVM = pUVM->pVM;
2889	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2890	return pVM->hm.s.vmx.fVpid;
2891	}
2892
2893
2894	/**
2895	* Checks if we are currently using VT-x unrestricted execution,
2896	* aka UX.
2897	*
2898	* @returns true if UX is being used, otherwise false.
2899	* @param pUVM The user mode VM handle.
2900	*/
2901	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2902	{
2903	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2904	PVM pVM = pUVM->pVM;
2905	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2906	return pVM->hm.s.vmx.fUnrestrictedGuest
2907	\|\| pVM->hm.s.svm.fSupported;
2908	}
2909
2910
2911	/**
2912	* Checks if the VMX-preemption timer is being used.
2913	*
2914	* @returns true if the VMX-preemption timer is being used, otherwise false.
2915	* @param pVM The cross context VM structure.
2916	*/
2917	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2918	{
2919	return HMIsEnabled(pVM)
2920	&& pVM->hm.s.vmx.fEnabled
2921	&& pVM->hm.s.vmx.fUsePreemptTimer;
2922	}
2923
2924
2925	/**
2926	* Helper for HMR3CheckError to log VMCS controls to the release log.
2927	*
2928	* @param idCpu The Virtual CPU ID.
2929	* @param pVmcsInfo The VMCS info. object.
2930	*/
2931	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2932	{
2933	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2934	{
2935	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2941	}
2942	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2943	{
2944	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2966	}
2967	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2968	{
2969	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2973	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2974	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2975	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2976	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2989	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2990	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2993	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2994	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2995	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2996	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2997	}
2998	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2999	{
3000	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3007	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3008	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
3009	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
3010	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
3011	}
3012	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
3013	{
3014	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
3015	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3016	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3017	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3018	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3019	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3020	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3021	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3022	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3023	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3024	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3025	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3026	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3027	}
3028	}
3029
3030
3031	/**
3032	* Check fatal VT-x/AMD-V error and produce some meaningful
3033	* log release message.
3034	*
3035	* @param pVM The cross context VM structure.
3036	* @param iStatusCode VBox status code.
3037	*/
3038	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3039	{
3040	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3041	{
3042	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3043	* might be getting inaccurate values for non-guru'ing EMTs. */
3044	PVMCPU pVCpu = &pVM->aCpus[i];
3045	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3046	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3047	switch (iStatusCode)
3048	{
3049	case VERR_VMX_INVALID_VMCS_PTR:
3050	{
3051	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3052	LogRel(("HM: CPU[%u] %s VMCS active\n", i, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3053	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", i, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3054	pVmcsInfo->HCPhysVmcs));
3055	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3056	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3057	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3058	break;
3059	}
3060
3061	case VERR_VMX_UNABLE_TO_START_VM:
3062	{
3063	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3064	LogRel(("HM: CPU[%u] %s VMCS active\n", i, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3065	LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3066	LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3067
3068	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3069	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3070	{
3071	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3072	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3073	}
3074	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3075	{
3076	hmR3CheckErrorLogVmcsCtls(i, pVmcsInfo);
3077	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVmcsInfo->HCPhysMsrBitmap));
3078	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", i, pVmcsInfo->HCPhysGuestMsrLoad));
3079	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", i, pVmcsInfo->HCPhysGuestMsrStore));
3080	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", i, pVmcsInfo->HCPhysHostMsrLoad));
3081	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", i, pVmcsInfo->cEntryMsrLoad));
3082	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", i, pVmcsInfo->cExitMsrStore));
3083	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", i, pVmcsInfo->cExitMsrLoad));
3084	}
3085	/** @todo Log VM-entry event injection control fields
3086	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3087	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3088	break;
3089	}
3090
3091	case VERR_VMX_INVALID_GUEST_STATE:
3092	{
3093	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3094	hmR3CheckErrorLogVmcsCtls(i, pVmcsInfo);
3095	break;
3096	}
3097
3098	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3099	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3100	case VERR_VMX_INVALID_VMXON_PTR:
3101	case VERR_VMX_UNEXPECTED_EXIT:
3102	case VERR_VMX_INVALID_VMCS_FIELD:
3103	case VERR_SVM_UNKNOWN_EXIT:
3104	case VERR_SVM_UNEXPECTED_EXIT:
3105	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3106	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3107	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3108	break;
3109	}
3110	}
3111
3112	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3113	{
3114	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3115	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3116	}
3117	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3118	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3119	}
3120
3121
3122	/**
3123	* Execute state save operation.
3124	*
3125	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3126	* is because we always save the VM state from ring-3 and thus most HM state
3127	* will be re-synced dynamically at runtime and don't need to be part of the VM
3128	* saved state.
3129	*
3130	* @returns VBox status code.
3131	* @param pVM The cross context VM structure.
3132	* @param pSSM SSM operation handle.
3133	*/
3134	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3135	{
3136	int rc;
3137
3138	Log(("hmR3Save:\n"));
3139
3140	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3141	{
3142	Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3143	if (pVM->cpum.ro.GuestFeatures.fSvm)
3144	{
3145	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3146	rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3147	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3148	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3149	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3150	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3151	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3152	rc \|= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3153	rc \|= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3154	rc \|= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3155	rc \|= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3156	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3157	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3158	rc \|= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3159	AssertRCReturn(rc, rc);
3160	}
3161	}
3162
3163	/* Save the guest patch data. */
3164	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3165	rc \|= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3166	rc \|= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3167
3168	/* Store all the guest patch records too. */
3169	rc \|= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3170	AssertRCReturn(rc, rc);
3171
3172	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3173	{
3174	AssertCompileSize(HMTPRINSTR, 4);
3175	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3176	rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3177	rc \|= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3178	rc \|= SSMR3PutU32(pSSM, pPatch->cbOp);
3179	rc \|= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3180	rc \|= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3181	rc \|= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3182	rc \|= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3183	rc \|= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3184	rc \|= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3185	rc \|= SSMR3PutU32(pSSM, pPatch->cFaults);
3186	AssertRCReturn(rc, rc);
3187	}
3188
3189	return VINF_SUCCESS;
3190	}
3191
3192
3193	/**
3194	* Execute state load operation.
3195	*
3196	* @returns VBox status code.
3197	* @param pVM The cross context VM structure.
3198	* @param pSSM SSM operation handle.
3199	* @param uVersion Data layout version.
3200	* @param uPass The data pass.
3201	*/
3202	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3203	{
3204	int rc;
3205
3206	LogFlowFunc(("uVersion=%u\n", uVersion));
3207	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3208
3209	/*
3210	* Validate version.
3211	*/
3212	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3213	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3214	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3215	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3216	{
3217	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3218	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3219	}
3220
3221	/*
3222	* Load per-VCPU state.
3223	*/
3224	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3225	{
3226	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3227	{
3228	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3229	if (pVM->cpum.ro.GuestFeatures.fSvm)
3230	{
3231	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3232	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3233	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3234	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3235	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3236	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3237	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3238	rc \|= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3239	rc \|= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3240	rc \|= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3241	rc \|= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3242	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3243	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3244	rc \|= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3245	AssertRCReturn(rc, rc);
3246	}
3247	}
3248	else
3249	{
3250	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3251	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3252	rc \|= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3253	rc \|= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3254
3255	/* VMX fWasInRealMode related data. */
3256	uint32_t uDummy;
3257	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3258	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3259	rc \|= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3260	AssertRCReturn(rc, rc);
3261	}
3262	}
3263
3264	/*
3265	* Load TPR patching data.
3266	*/
3267	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3268	{
3269	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3270	rc \|= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3271	rc \|= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3272
3273	/* Fetch all TPR patch records. */
3274	rc \|= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3275	AssertRCReturn(rc, rc);
3276	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3277	{
3278	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3279	rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3280	rc \|= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3281	rc \|= SSMR3GetU32(pSSM, &pPatch->cbOp);
3282	rc \|= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3283	rc \|= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3284	rc \|= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3285
3286	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3287	pVM->hm.s.fTPRPatchingActive = true;
3288	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3289
3290	rc \|= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3291	rc \|= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3292	rc \|= SSMR3GetU32(pSSM, &pPatch->cFaults);
3293	rc \|= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3294	AssertRCReturn(rc, rc);
3295
3296	LogFlow(("hmR3Load: patch %d\n", i));
3297	LogFlow(("Key = %x\n", pPatch->Core.Key));
3298	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3299	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3300	LogFlow(("type = %d\n", pPatch->enmType));
3301	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3302	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3303	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3304	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3305
3306	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3307	AssertRCReturn(rc, rc);
3308	}
3309	}
3310
3311	return VINF_SUCCESS;
3312	}
3313
3314
3315	/**
3316	* Displays HM info.
3317	*
3318	* @param pVM The cross context VM structure.
3319	* @param pHlp The info helper functions.
3320	* @param pszArgs Arguments, ignored.
3321	*/
3322	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3323	{
3324	NOREF(pszArgs);
3325	PVMCPU pVCpu = VMMGetCpu(pVM);
3326	if (!pVCpu)
3327	pVCpu = &pVM->aCpus[0];
3328
3329	if (HMIsEnabled(pVM))
3330	{
3331	if (pVM->hm.s.vmx.fSupported)
3332	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3333	else
3334	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3335	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3336	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3337	if (pVM->hm.s.vmx.fSupported)
3338	{
3339	PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3340	bool const fRealOnV86Active = pVmcsInfo->RealMode.fRealOnV86Active;
3341	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3342
3343	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3344	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3345	if (fRealOnV86Active)
3346	{
3347	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfo->RealMode.Eflags.u32);
3348	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfo->RealMode.AttrCS.u);
3349	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfo->RealMode.AttrSS.u);
3350	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfo->RealMode.AttrDS.u);
3351	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfo->RealMode.AttrES.u);
3352	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfo->RealMode.AttrFS.u);
3353	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfo->RealMode.AttrGS.u);
3354	}
3355	}
3356	}
3357	else
3358	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3359	}
3360
3361
3362	/**
3363	* Displays the HM pending event.
3364	*
3365	* @param pVM The cross context VM structure.
3366	* @param pHlp The info helper functions.
3367	* @param pszArgs Arguments, ignored.
3368	*/
3369	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3370	{
3371	NOREF(pszArgs);
3372	PVMCPU pVCpu = VMMGetCpu(pVM);
3373	if (!pVCpu)
3374	pVCpu = &pVM->aCpus[0];
3375
3376	if (HMIsEnabled(pVM))
3377	{
3378	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3379	if (pVCpu->hm.s.Event.fPending)
3380	{
3381	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3382	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3383	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3384	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3385	}
3386	}
3387	else
3388	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3389	}
3390
3391
3392	/**
3393	* Displays the SVM nested-guest VMCB cache.
3394	*
3395	* @param pVM The cross context VM structure.
3396	* @param pHlp The info helper functions.
3397	* @param pszArgs Arguments, ignored.
3398	*/
3399	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3400	{
3401	NOREF(pszArgs);
3402	PVMCPU pVCpu = VMMGetCpu(pVM);
3403	if (!pVCpu)
3404	pVCpu = &pVM->aCpus[0];
3405
3406	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3407	if ( fSvmEnabled
3408	&& pVM->cpum.ro.GuestFeatures.fSvm)
3409	{
3410	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3411	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3412	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3413	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3414	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3415	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3416	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3417	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3418	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3419	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3420	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3421	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3422	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3423	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3424	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3425	}
3426	else
3427	{
3428	if (!fSvmEnabled)
3429	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3430	else
3431	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3432	}
3433	}
3434

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 79581

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