VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 82671

Last change on this file since 82671 was 82614, checked in by vboxsync, 5 years ago

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1/* $Id: HM.cpp 82614 2019-12-18 11:08:49Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/pdmapi.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/ssm.h>
48#include <VBox/vmm/gim.h>
49#include <VBox/vmm/trpm.h>
50#include <VBox/vmm/dbgf.h>
51#include <VBox/vmm/iom.h>
52#include <VBox/vmm/iem.h>
53#include <VBox/vmm/selm.h>
54#include <VBox/vmm/nem.h>
55#include <VBox/vmm/hm_vmx.h>
56#include <VBox/vmm/hm_svm.h>
57#include "HMInternal.h"
58#include <VBox/vmm/vmcc.h>
59#include <VBox/err.h>
60#include <VBox/param.h>
61
62#include <iprt/assert.h>
63#include <VBox/log.h>
64#include <iprt/asm.h>
65#include <iprt/asm-amd64-x86.h>
66#include <iprt/env.h>
67#include <iprt/thread.h>
68
69
70/*********************************************************************************************************************************
71* Defined Constants And Macros *
72*********************************************************************************************************************************/
73/** @def HMVMX_REPORT_FEAT
74 * Reports VT-x feature to the release log.
75 *
76 * @param a_uAllowed1 Mask of allowed-1 feature bits.
77 * @param a_uAllowed0 Mask of allowed-0 feature bits.
78 * @param a_StrDesc The description string to report.
79 * @param a_Featflag Mask of the feature to report.
80 */
81#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
82 do { \
83 if ((a_uAllowed1) & (a_Featflag)) \
84 { \
85 if ((a_uAllowed0) & (a_Featflag)) \
86 LogRel(("HM: " a_StrDesc " (must be set)\n")); \
87 else \
88 LogRel(("HM: " a_StrDesc "\n")); \
89 } \
90 else \
91 LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
92 } while (0)
93
94/** @def HMVMX_REPORT_ALLOWED_FEAT
95 * Reports an allowed VT-x feature to the release log.
96 *
97 * @param a_uAllowed1 Mask of allowed-1 feature bits.
98 * @param a_StrDesc The description string to report.
99 * @param a_FeatFlag Mask of the feature to report.
100 */
101#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
102 do { \
103 if ((a_uAllowed1) & (a_FeatFlag)) \
104 LogRel(("HM: " a_StrDesc "\n")); \
105 else \
106 LogRel(("HM: " a_StrDesc " not supported\n")); \
107 } while (0)
108
109/** @def HMVMX_REPORT_MSR_CAP
110 * Reports MSR feature capability.
111 *
112 * @param a_MsrCaps Mask of MSR feature bits.
113 * @param a_StrDesc The description string to report.
114 * @param a_fCap Mask of the feature to report.
115 */
116#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
117 do { \
118 if ((a_MsrCaps) & (a_fCap)) \
119 LogRel(("HM: " a_StrDesc "\n")); \
120 } while (0)
121
122/** @def HMVMX_LOGREL_FEAT
123 * Dumps a feature flag from a bitmap of features to the release log.
124 *
125 * @param a_fVal The value of all the features.
126 * @param a_fMask The specific bitmask of the feature.
127 */
128#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
129 do { \
130 if ((a_fVal) & (a_fMask)) \
131 LogRel(("HM: %s\n", #a_fMask)); \
132 } while (0)
133
134
135/*********************************************************************************************************************************
136* Internal Functions *
137*********************************************************************************************************************************/
138static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
139static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
140static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143static int hmR3InitFinalizeR3(PVM pVM);
144static int hmR3InitFinalizeR0(PVM pVM);
145static int hmR3InitFinalizeR0Intel(PVM pVM);
146static int hmR3InitFinalizeR0Amd(PVM pVM);
147static int hmR3TermCPU(PVM pVM);
148
149
150
151/**
152 * Initializes the HM.
153 *
154 * This is the very first component to really do init after CFGM so that we can
155 * establish the predominant execution engine for the VM prior to initializing
156 * other modules. It takes care of NEM initialization if needed (HM disabled or
157 * not available in HW).
158 *
159 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
160 * hypervisor API via NEM, and then back on raw-mode if that isn't available
161 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
162 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
163 * X, OS/2 and others).
164 *
165 * Note that a lot of the set up work is done in ring-0 and thus postponed till
166 * the ring-3 and ring-0 callback to HMR3InitCompleted.
167 *
168 * @returns VBox status code.
169 * @param pVM The cross context VM structure.
170 *
171 * @remarks Be careful with what we call here, since most of the VMM components
172 * are uninitialized.
173 */
174VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
175{
176 LogFlowFunc(("\n"));
177
178 /*
179 * Assert alignment and sizes.
180 */
181 AssertCompileMemberAlignment(VM, hm.s, 32);
182 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
183
184 /*
185 * Register the saved state data unit.
186 */
187 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
188 NULL, NULL, NULL,
189 NULL, hmR3Save, NULL,
190 NULL, hmR3Load, NULL);
191 if (RT_FAILURE(rc))
192 return rc;
193
194 /*
195 * Register info handlers.
196 */
197 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
198 AssertRCReturn(rc, rc);
199
200 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
201 DBGFINFO_FLAGS_ALL_EMTS);
202 AssertRCReturn(rc, rc);
203
204 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
205 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
206 AssertRCReturn(rc, rc);
207
208 /*
209 * Read configuration.
210 */
211 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
212
213 /*
214 * Validate the HM settings.
215 */
216 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
217 "HMForced" /* implied 'true' these days */
218 "|UseNEMInstead"
219 "|FallbackToNEM"
220 "|EnableNestedPaging"
221 "|EnableUX"
222 "|EnableLargePages"
223 "|EnableVPID"
224 "|IBPBOnVMExit"
225 "|IBPBOnVMEntry"
226 "|SpecCtrlByHost"
227 "|L1DFlushOnSched"
228 "|L1DFlushOnVMEntry"
229 "|MDSClearOnSched"
230 "|MDSClearOnVMEntry"
231 "|TPRPatchingEnabled"
232 "|64bitEnabled"
233 "|Exclusive"
234 "|MaxResumeLoops"
235 "|VmxPleGap"
236 "|VmxPleWindow"
237 "|UseVmxPreemptTimer"
238 "|SvmPauseFilter"
239 "|SvmPauseFilterThreshold"
240 "|SvmVirtVmsaveVmload"
241 "|SvmVGif"
242 "|LovelyMesaDrvWorkaround",
243 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
244 if (RT_FAILURE(rc))
245 return rc;
246
247 /** @cfgm{/HM/HMForced, bool, false}
248 * Forces hardware virtualization, no falling back on raw-mode. HM must be
249 * enabled, i.e. /HMEnabled must be true. */
250 bool fHMForced;
251 AssertRelease(pVM->fHMEnabled);
252 fHMForced = true;
253
254 /** @cfgm{/HM/UseNEMInstead, bool, true}
255 * Don't use HM, use NEM instead. */
256 bool fUseNEMInstead = false;
257 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
258 AssertRCReturn(rc, rc);
259 if (fUseNEMInstead && pVM->fHMEnabled)
260 {
261 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
262 pVM->fHMEnabled = false;
263 }
264
265 /** @cfgm{/HM/FallbackToNEM, bool, true}
266 * Enables fallback on NEM. */
267 bool fFallbackToNEM = true;
268 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
269 AssertRCReturn(rc, rc);
270
271 /** @cfgm{/HM/EnableNestedPaging, bool, false}
272 * Enables nested paging (aka extended page tables). */
273 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
274 AssertRCReturn(rc, rc);
275
276 /** @cfgm{/HM/EnableUX, bool, true}
277 * Enables the VT-x unrestricted execution feature. */
278 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
279 AssertRCReturn(rc, rc);
280
281 /** @cfgm{/HM/EnableLargePages, bool, false}
282 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
283 * page table walking and maybe better TLB hit rate in some cases. */
284 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
285 AssertRCReturn(rc, rc);
286
287 /** @cfgm{/HM/EnableVPID, bool, false}
288 * Enables the VT-x VPID feature. */
289 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
290 AssertRCReturn(rc, rc);
291
292 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
293 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
294 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
295 AssertRCReturn(rc, rc);
296
297 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
298 * Enables AMD64 cpu features.
299 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
300 * already have the support. */
301#ifdef VBOX_WITH_64_BITS_GUESTS
302 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
303 AssertLogRelRCReturn(rc, rc);
304#else
305 pVM->hm.s.fAllow64BitGuests = false;
306#endif
307
308 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
309 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
310 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
311 * latest PAUSE instruction to be start of a new PAUSE loop.
312 */
313 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
314 AssertRCReturn(rc, rc);
315
316 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
317 * The pause-filter exiting window in TSC ticks. When the number of ticks
318 * between the current PAUSE instruction and first PAUSE of a loop exceeds
319 * VmxPleWindow, a VM-exit is triggered.
320 *
321 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
322 */
323 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
324 AssertRCReturn(rc, rc);
325
326 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
327 * A counter that is decrement each time a PAUSE instruction is executed by the
328 * guest. When the counter is 0, a \#VMEXIT is triggered.
329 *
330 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
331 */
332 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
333 AssertRCReturn(rc, rc);
334
335 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
336 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
337 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
338 * PauseFilter count is reset to its initial value. However, if PAUSE is
339 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
340 * be triggered.
341 *
342 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
343 * activated.
344 */
345 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
346 AssertRCReturn(rc, rc);
347
348 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
349 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
350 * available. */
351 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
352 AssertRCReturn(rc, rc);
353
354 /** @cfgm{/HM/SvmVGif, bool, true}
355 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
356 * if it's available. */
357 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
358 AssertRCReturn(rc, rc);
359
360 /** @cfgm{/HM/SvmLbrVirt, bool, false}
361 * Whether to make use of the LBR virtualization feature of the CPU if it's
362 * available. This is disabled by default as it's only useful while debugging
363 * and enabling it causes a small hit to performance. */
364 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
365 AssertRCReturn(rc, rc);
366
367 /** @cfgm{/HM/Exclusive, bool}
368 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
369 * global init for each host CPU. If false, we do local init each time we wish
370 * to execute guest code.
371 *
372 * On Windows, default is false due to the higher risk of conflicts with other
373 * hypervisors.
374 *
375 * On Mac OS X, this setting is ignored since the code does not handle local
376 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
377 */
378#if defined(RT_OS_DARWIN)
379 pVM->hm.s.fGlobalInit = true;
380#else
381 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
382# if defined(RT_OS_WINDOWS)
383 false
384# else
385 true
386# endif
387 );
388 AssertLogRelRCReturn(rc, rc);
389#endif
390
391 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
392 * The number of times to resume guest execution before we forcibly return to
393 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
394 * determines the default value. */
395 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
396 AssertLogRelRCReturn(rc, rc);
397
398 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
399 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
400 * available. */
401 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
402 AssertLogRelRCReturn(rc, rc);
403
404 /** @cfgm{/HM/IBPBOnVMExit, bool}
405 * Costly paranoia setting. */
406 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
407 AssertLogRelRCReturn(rc, rc);
408
409 /** @cfgm{/HM/IBPBOnVMEntry, bool}
410 * Costly paranoia setting. */
411 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
412 AssertLogRelRCReturn(rc, rc);
413
414 /** @cfgm{/HM/L1DFlushOnSched, bool, true}
415 * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
416 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
417 AssertLogRelRCReturn(rc, rc);
418
419 /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
420 * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
421 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
422 AssertLogRelRCReturn(rc, rc);
423
424 /* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
425 if (pVM->hm.s.fL1dFlushOnVmEntry)
426 pVM->hm.s.fL1dFlushOnSched = false;
427
428 /** @cfgm{/HM/SpecCtrlByHost, bool}
429 * Another expensive paranoia setting. */
430 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
431 AssertLogRelRCReturn(rc, rc);
432
433 /** @cfgm{/HM/MDSClearOnSched, bool, true}
434 * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
435 * ignored on CPUs that aren't affected. */
436 rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
437 AssertLogRelRCReturn(rc, rc);
438
439 /** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
440 * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
441 * ignored on CPUs that aren't affected. */
442 rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
443 AssertLogRelRCReturn(rc, rc);
444
445 /* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
446 if (pVM->hm.s.fMdsClearOnVmEntry)
447 pVM->hm.s.fMdsClearOnSched = false;
448
449 /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
450 * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
451 * the hypervisor it is running under. */
452 bool f;
453 rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
454 AssertLogRelRCReturn(rc, rc);
455 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
456 {
457 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
458 pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = f;
459 }
460
461 /*
462 * Check if VT-x or AMD-v support according to the users wishes.
463 */
464 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
465 * VERR_SVM_IN_USE. */
466 if (pVM->fHMEnabled)
467 {
468 uint32_t fCaps;
469 rc = SUPR3QueryVTCaps(&fCaps);
470 if (RT_SUCCESS(rc))
471 {
472 if (fCaps & SUPVTCAPS_AMD_V)
473 {
474 pVM->hm.s.svm.fSupported = true;
475 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
476 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
477 }
478 else if (fCaps & SUPVTCAPS_VT_X)
479 {
480 const char *pszWhy;
481 rc = SUPR3QueryVTxSupported(&pszWhy);
482 if (RT_SUCCESS(rc))
483 {
484 pVM->hm.s.vmx.fSupported = true;
485 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
486 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
487 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
488 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
489 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
490 }
491 else
492 {
493 /*
494 * Before failing, try fallback to NEM if we're allowed to do that.
495 */
496 pVM->fHMEnabled = false;
497 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
498 if (fFallbackToNEM)
499 {
500 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
501 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
502
503 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
504 if ( RT_SUCCESS(rc2)
505 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
506 rc = VINF_SUCCESS;
507 }
508 if (RT_FAILURE(rc))
509 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
510 }
511 }
512 else
513 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
514 VERR_INTERNAL_ERROR_5);
515
516 /*
517 * Disable nested paging and unrestricted guest execution now if they're
518 * configured so that CPUM can make decisions based on our configuration.
519 */
520 Assert(!pVM->hm.s.fNestedPaging);
521 if (pVM->hm.s.fAllowNestedPaging)
522 {
523 if (fCaps & SUPVTCAPS_NESTED_PAGING)
524 pVM->hm.s.fNestedPaging = true;
525 else
526 pVM->hm.s.fAllowNestedPaging = false;
527 }
528
529 if (fCaps & SUPVTCAPS_VT_X)
530 {
531 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
532 if (pVM->hm.s.vmx.fAllowUnrestricted)
533 {
534 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
535 && pVM->hm.s.fNestedPaging)
536 pVM->hm.s.vmx.fUnrestrictedGuest = true;
537 else
538 pVM->hm.s.vmx.fAllowUnrestricted = false;
539 }
540 }
541 }
542 else
543 {
544 const char *pszMsg;
545 switch (rc)
546 {
547 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
548 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
549 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
550 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
551 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
552 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
553 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
554 default:
555 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
556 }
557
558 /*
559 * Before failing, try fallback to NEM if we're allowed to do that.
560 */
561 pVM->fHMEnabled = false;
562 if (fFallbackToNEM)
563 {
564 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
565 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
566 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
567 if ( RT_SUCCESS(rc2)
568 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
569 rc = VINF_SUCCESS;
570 }
571 if (RT_FAILURE(rc))
572 return VM_SET_ERROR(pVM, rc, pszMsg);
573 }
574 }
575 else
576 {
577 /*
578 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
579 */
580 if (fUseNEMInstead)
581 {
582 rc = NEMR3Init(pVM, false /*fFallback*/, true);
583 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
584 if (RT_FAILURE(rc))
585 return rc;
586 }
587 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
588 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
589 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
590 return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
591 }
592
593 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
594 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
595 return VINF_SUCCESS;
596}
597
598
599/**
600 * Initializes HM components after ring-3 phase has been fully initialized.
601 *
602 * @returns VBox status code.
603 * @param pVM The cross context VM structure.
604 */
605static int hmR3InitFinalizeR3(PVM pVM)
606{
607 LogFlowFunc(("\n"));
608
609 if (!HMIsEnabled(pVM))
610 return VINF_SUCCESS;
611
612 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
613 {
614 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
615 pVCpu->hm.s.fActive = false;
616 pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
617 }
618
619#ifdef VBOX_WITH_STATISTICS
620 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
621 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
622 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
623 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
624 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
625#endif
626
627 /*
628 * Statistics.
629 */
630 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
631 {
632 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
633 PHMCPU pHmCpu = &pVCpu->hm.s;
634 int rc;
635
636# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
637 rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
638 AssertRC(rc); \
639 } while (0)
640# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
641 HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
642
643#ifdef VBOX_WITH_STATISTICS
644
645 HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
646 HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
647 HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
648 HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
649 HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
650 HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
651 HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
652 HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
653 HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
654 HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
655 HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
656 HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
657 HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
658 HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
659# ifdef HM_PROFILE_EXIT_DISPATCH
660 HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
661 "/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
662# endif
663#endif
664# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
665
666#ifdef VBOX_WITH_STATISTICS
667 HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
668 HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
669 HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
670 HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
671 HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
672 HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
673 HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
674 HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
675 HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
676 HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
677 HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
678 HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
679 HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
680 HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
681 HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
682 HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
683 HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
684 HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
685 HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
686 HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
687 HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
688 HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
689 HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
690 HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
691 HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
692 HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
693 HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
694 HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
695 HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
696 HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
697 HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
698 HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
699 HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
700 HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
701 HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
702 HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
703 HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
704 HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
705 HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
706 HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
707 HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
708 HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
709 HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
710 HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
711 HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
712#endif
713 HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
714 HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
715#ifdef VBOX_WITH_STATISTICS
716 HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
717 HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
718 HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
719 HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
720
721 HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
722 HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
723 HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
724 HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
725 HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
726 HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
727 HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
728 HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
729 HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
730 HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
731 HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
732 HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
733#endif
734 HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
735#ifdef VBOX_WITH_STATISTICS
736 HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
737
738 HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
739 HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
740 HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
741 HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
742 HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
743 HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
744
745 HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
746 HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
747 HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
748 HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
749 HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
750 HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
751 HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
752 HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
753 HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
754 HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
755 HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
756 HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
757 HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
758 HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
759 HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
760
761 HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
762 HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
763 HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
764
765 HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
766 HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
767 HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
768
769 HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
770 HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
771 HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
772 HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
773
774 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
775 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
776 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
777
778 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
779 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
780 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
781
782 HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
783 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
784 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
785 HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
786
787 bool const fCpuSupportsVmx = ASMIsIntelCpu() || ASMIsViaCentaurCpu() || ASMIsShanghaiCpu();
788
789 /*
790 * Guest Exit reason stats.
791 */
792 pHmCpu->paStatExitReason = NULL;
793 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pHmCpu->paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
794 (void **)&pHmCpu->paStatExitReason);
795 AssertRCReturn(rc, rc);
796
797 if (fCpuSupportsVmx)
798 {
799 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
800 {
801 const char *pszExitName = HMGetVmxExitName(j);
802 if (pszExitName)
803 {
804 rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
805 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
806 AssertRCReturn(rc, rc);
807 }
808 }
809 }
810 else
811 {
812 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
813 {
814 const char *pszExitName = HMGetSvmExitName(j);
815 if (pszExitName)
816 {
817 rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
818 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
819 AssertRC(rc);
820 }
821 }
822 }
823 HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
824
825 pHmCpu->paStatExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatExitReason);
826 Assert(pHmCpu->paStatExitReasonR0 != NIL_RTR0PTR);
827
828#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
829 /*
830 * Nested-guest VM-exit reason stats.
831 */
832 pHmCpu->paStatNestedExitReason = NULL;
833 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pHmCpu->paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
834 (void **)&pHmCpu->paStatNestedExitReason);
835 AssertRCReturn(rc, rc);
836 if (fCpuSupportsVmx)
837 {
838 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
839 {
840 const char *pszExitName = HMGetVmxExitName(j);
841 if (pszExitName)
842 {
843 rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
844 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
845 AssertRC(rc);
846 }
847 }
848 }
849 else
850 {
851 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
852 {
853 const char *pszExitName = HMGetSvmExitName(j);
854 if (pszExitName)
855 {
856 rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
857 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
858 AssertRC(rc);
859 }
860 }
861 }
862 HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
863 pHmCpu->paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatNestedExitReason);
864 Assert(pHmCpu->paStatNestedExitReasonR0 != NIL_RTR0PTR);
865#endif
866
867 /*
868 * Injected events stats.
869 */
870 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedIrqs);
871 AssertRCReturn(rc, rc);
872 pHmCpu->paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedIrqs);
873 Assert(pHmCpu->paStatInjectedIrqsR0 != NIL_RTR0PTR);
874 for (unsigned j = 0; j < 255; j++)
875 {
876 rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
877 STAMUNIT_OCCURENCES, "Injected events.",
878 j < 0x20 ? "/HM/CPU%u/EventInject/InjectTrap/%02X" : "/HM/CPU%u/EventInject/InjectIRQ/%02X",
879 idCpu, j);
880 AssertRC(rc);
881 }
882
883#endif /* VBOX_WITH_STATISTICS */
884#undef HM_REG_COUNTER
885#undef HM_REG_PROFILE
886#undef HM_REG_STAT
887 }
888
889 return VINF_SUCCESS;
890}
891
892
893/**
894 * Called when a init phase has completed.
895 *
896 * @returns VBox status code.
897 * @param pVM The cross context VM structure.
898 * @param enmWhat The phase that completed.
899 */
900VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
901{
902 switch (enmWhat)
903 {
904 case VMINITCOMPLETED_RING3:
905 return hmR3InitFinalizeR3(pVM);
906 case VMINITCOMPLETED_RING0:
907 return hmR3InitFinalizeR0(pVM);
908 default:
909 return VINF_SUCCESS;
910 }
911}
912
913
914/**
915 * Turns off normal raw mode features.
916 *
917 * @param pVM The cross context VM structure.
918 */
919static void hmR3DisableRawMode(PVM pVM)
920{
921/** @todo r=bird: HM shouldn't be doing this crap. */
922 /* Reinit the paging mode to force the new shadow mode. */
923 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
924 {
925 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
926 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
927 }
928}
929
930
931/**
932 * Initialize VT-x or AMD-V.
933 *
934 * @returns VBox status code.
935 * @param pVM The cross context VM structure.
936 */
937static int hmR3InitFinalizeR0(PVM pVM)
938{
939 int rc;
940
941 if (!HMIsEnabled(pVM))
942 return VINF_SUCCESS;
943
944 /*
945 * Hack to allow users to work around broken BIOSes that incorrectly set
946 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
947 */
948 if ( !pVM->hm.s.vmx.fSupported
949 && !pVM->hm.s.svm.fSupported
950 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
951 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
952 {
953 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
954 pVM->hm.s.svm.fSupported = true;
955 pVM->hm.s.svm.fIgnoreInUseError = true;
956 pVM->hm.s.rcInit = VINF_SUCCESS;
957 }
958
959 /*
960 * Report ring-0 init errors.
961 */
962 if ( !pVM->hm.s.vmx.fSupported
963 && !pVM->hm.s.svm.fSupported)
964 {
965 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
966 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
967 switch (pVM->hm.s.rcInit)
968 {
969 case VERR_VMX_IN_VMX_ROOT_MODE:
970 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
971 case VERR_VMX_NO_VMX:
972 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
973 case VERR_VMX_MSR_VMX_DISABLED:
974 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
975 case VERR_VMX_MSR_ALL_VMX_DISABLED:
976 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
977 case VERR_VMX_MSR_LOCKING_FAILED:
978 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
979 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
980 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
981 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
982 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
983
984 case VERR_SVM_IN_USE:
985 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
986 case VERR_SVM_NO_SVM:
987 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
988 case VERR_SVM_DISABLED:
989 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
990 }
991 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
992 }
993
994 /*
995 * Enable VT-x or AMD-V on all host CPUs.
996 */
997 rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
998 if (RT_FAILURE(rc))
999 {
1000 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1001 HMR3CheckError(pVM, rc);
1002 return rc;
1003 }
1004
1005 /*
1006 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1007 * (Main should have taken care of this already)
1008 */
1009 if (!PDMHasIoApic(pVM))
1010 {
1011 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1012 pVM->hm.s.fTprPatchingAllowed = false;
1013 }
1014
1015 /*
1016 * Check if L1D flush is needed/possible.
1017 */
1018 if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1019 || pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1020 || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1021 || pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1022 || pVM->cpum.ro.HostFeatures.fArchRdclNo)
1023 pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1024
1025 /*
1026 * Check if MDS flush is needed/possible.
1027 * On atoms and knight family CPUs, we will only allow clearing on scheduling.
1028 */
1029 if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1030 || pVM->cpum.ro.HostFeatures.fArchMdsNo)
1031 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1032 else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1033 && pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1034 || ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1035 && pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1036 {
1037 if (!pVM->hm.s.fMdsClearOnSched)
1038 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1039 pVM->hm.s.fMdsClearOnVmEntry = false;
1040 }
1041 else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1042 || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1043 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1044
1045 /*
1046 * Sync options.
1047 */
1048 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1049 * That will require a little bit of work, of course. */
1050 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1051 {
1052 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1053 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1054 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1055 if (pVM->cpum.ro.HostFeatures.fIbpb)
1056 {
1057 if (pVM->hm.s.fIbpbOnVmExit)
1058 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1059 if (pVM->hm.s.fIbpbOnVmEntry)
1060 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1061 }
1062 if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1063 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_L1D_ENTRY;
1064 if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1065 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_MDS_ENTRY;
1066 if (idCpu == 0)
1067 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1068 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1069 pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1070 }
1071
1072 /*
1073 * Do the vendor specific initialization
1074 *
1075 * Note! We disable release log buffering here since we're doing relatively
1076 * lot of logging and doesn't want to hit the disk with each LogRel
1077 * statement.
1078 */
1079 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1080 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1081 if (pVM->hm.s.vmx.fSupported)
1082 rc = hmR3InitFinalizeR0Intel(pVM);
1083 else
1084 rc = hmR3InitFinalizeR0Amd(pVM);
1085 LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1086 : "HM: VT-x/AMD-V init method: Local\n"));
1087 RTLogRelSetBuffering(fOldBuffered);
1088 pVM->hm.s.fInitialized = true;
1089
1090 return rc;
1091}
1092
1093
1094/**
1095 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1096 */
1097static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1098{
1099 NOREF(pVM);
1100 NOREF(pvAllocation);
1101 NOREF(GCPhysAllocation);
1102}
1103
1104
1105/**
1106 * Returns a description of the VMCS (and associated regions') memory type given the
1107 * IA32_VMX_BASIC MSR.
1108 *
1109 * @returns The descriptive memory type.
1110 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1111 */
1112static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1113{
1114 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1115 switch (uMemType)
1116 {
1117 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1118 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1119 }
1120 return "Unknown";
1121}
1122
1123
1124/**
1125 * Returns a single-line description of all the activity-states supported by the CPU
1126 * given the IA32_VMX_MISC MSR.
1127 *
1128 * @returns All supported activity states.
1129 * @param uMsrMisc IA32_VMX_MISC MSR value.
1130 */
1131static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1132{
1133 static const char * const s_apszActStates[] =
1134 {
1135 "",
1136 " ( HLT )",
1137 " ( SHUTDOWN )",
1138 " ( HLT SHUTDOWN )",
1139 " ( SIPI_WAIT )",
1140 " ( HLT SIPI_WAIT )",
1141 " ( SHUTDOWN SIPI_WAIT )",
1142 " ( HLT SHUTDOWN SIPI_WAIT )"
1143 };
1144 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1145 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1146 return s_apszActStates[idxActStates];
1147}
1148
1149
1150/**
1151 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1152 *
1153 * @param fFeatMsr The feature control MSR value.
1154 */
1155static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1156{
1157 uint64_t const val = fFeatMsr;
1158 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1159 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1160 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1161 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1162 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1163 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1164 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1165 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1166 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1167 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1168 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1169 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1170 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1171 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1172 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1173 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1174 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1175}
1176
1177
1178/**
1179 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1180 *
1181 * @param uBasicMsr The VMX basic MSR value.
1182 */
1183static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1184{
1185 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1186 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1187 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1188 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1189 "< 4 GB" : "None"));
1190 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1191 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1192 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1193 LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1194 LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1195}
1196
1197
1198/**
1199 * Reports MSR_IA32_PINBASED_CTLS to the log.
1200 *
1201 * @param pVmxMsr Pointer to the VMX MSR.
1202 */
1203static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1204{
1205 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1206 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1207 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1208 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1209 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1210 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1211 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1212 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1213}
1214
1215
1216/**
1217 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1218 *
1219 * @param pVmxMsr Pointer to the VMX MSR.
1220 */
1221static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1222{
1223 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1224 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1225 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1226 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1227 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1228 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1229 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1230 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1231 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1232 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1233 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1234 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1235 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1236 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1237 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1238 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1239 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1240 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1241 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1242 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1243 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1244 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1245 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1246 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1247}
1248
1249
1250/**
1251 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1252 *
1253 * @param pVmxMsr Pointer to the VMX MSR.
1254 */
1255static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1256{
1257 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1258 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1259 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1260 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1261 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1262 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1263 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1264 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1265 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1266 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1267 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1268 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1269 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1270 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1271 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1272 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1273 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1274 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1275 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1276 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1277 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1278 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1279 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1280 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1281 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1282 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1283 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1284 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1285 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1286 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1287}
1288
1289
1290/**
1291 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1292 *
1293 * @param pVmxMsr Pointer to the VMX MSR.
1294 */
1295static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1296{
1297 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1298 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1299 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1300 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1301 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1302 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1303 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1304 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1305 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1306 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1307 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1308 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1309 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1310}
1311
1312
1313/**
1314 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1315 *
1316 * @param pVmxMsr Pointer to the VMX MSR.
1317 */
1318static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1319{
1320 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1321 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1322 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1323 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1324 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1325 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1326 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1327 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1328 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1329 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1330 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1331 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1332 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1333 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1334 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1335}
1336
1337
1338/**
1339 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1340 *
1341 * @param fCaps The VMX EPT/VPID capability MSR value.
1342 */
1343static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1344{
1345 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1346 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1347 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1348 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1349 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1350 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1351 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1352 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1353 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1354 HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1355 HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);
1356 HMVMX_REPORT_MSR_CAP(fCaps, "SSS", MSR_IA32_VMX_EPT_VPID_CAP_SSS);
1357 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1358 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1359 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1360 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1361 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1362 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1363 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1364}
1365
1366
1367/**
1368 * Reports MSR_IA32_VMX_MISC MSR to the log.
1369 *
1370 * @param pVM Pointer to the VM.
1371 * @param fMisc The VMX misc. MSR value.
1372 */
1373static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1374{
1375 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1376 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1377 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1378 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1379 else
1380 {
1381 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1382 pVM->hm.s.vmx.cPreemptTimerShift));
1383 }
1384 LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1385 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1386 hmR3VmxGetActivityStateAllDesc(fMisc)));
1387 LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1388 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1389 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1390 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1391 VMX_MISC_MAX_MSRS(fMisc)));
1392 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1393 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1394 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1395 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1396}
1397
1398
1399/**
1400 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1401 *
1402 * @param uVmcsEnum The VMX VMCS enum MSR value.
1403 */
1404static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1405{
1406 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1407 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1408}
1409
1410
1411/**
1412 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1413 *
1414 * @param uVmFunc The VMX VMFUNC MSR value.
1415 */
1416static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1417{
1418 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1419 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1420}
1421
1422
1423/**
1424 * Reports VMX CR0, CR4 fixed MSRs.
1425 *
1426 * @param pMsrs Pointer to the VMX MSRs.
1427 */
1428static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1429{
1430 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1431 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1432 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1433 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1434}
1435
1436
1437/**
1438 * Finish VT-x initialization (after ring-0 init).
1439 *
1440 * @returns VBox status code.
1441 * @param pVM The cross context VM structure.
1442 */
1443static int hmR3InitFinalizeR0Intel(PVM pVM)
1444{
1445 int rc;
1446
1447 LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1448 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1449
1450 LogRel(("HM: Using VT-x implementation 3.0\n"));
1451 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1452 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1453 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1454 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1455
1456 hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1457 hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1458
1459 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1460 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1461 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1462 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1463
1464 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1465 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1466
1467 if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1468 {
1469 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1470 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1471 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1472 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1473 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1474 }
1475
1476 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1477 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1478 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1479 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1480 if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1481 hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1482 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1483
1484 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1485 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1486 {
1487 PCVMXVMCSINFO pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1488 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1489 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1490 }
1491#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1492 if (pVM->cpum.ro.GuestFeatures.fVmx)
1493 {
1494 LogRel(("HM: Nested-guest:\n"));
1495 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1496 {
1497 PCVMXVMCSINFO pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1498 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1499 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1500 }
1501 }
1502#endif
1503
1504 /*
1505 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1506 */
1507 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1508 || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1509 VERR_HM_IPE_1);
1510 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1511 || ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1512 && pVM->hm.s.fNestedPaging),
1513 VERR_HM_IPE_1);
1514
1515 /*
1516 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1517 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1518 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1519 */
1520 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1521 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1522 {
1523 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1524 LogRel(("HM: Disabled RDTSCP\n"));
1525 }
1526
1527 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1528 {
1529 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1530 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1531 if (RT_SUCCESS(rc))
1532 {
1533 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1534 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1535 esp. Figure 20-5.*/
1536 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1537 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1538
1539 /* Bit set to 0 means software interrupts are redirected to the
1540 8086 program interrupt handler rather than switching to
1541 protected-mode handler. */
1542 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1543
1544 /* Allow all port IO, so that port IO instructions do not cause
1545 exceptions and would instead cause a VM-exit (based on VT-x's
1546 IO bitmap which we currently configure to always cause an exit). */
1547 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1548 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1549
1550 /*
1551 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1552 * page table used in real and protected mode without paging with EPT.
1553 */
1554 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1555 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1556 {
1557 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1558 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1559 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1560 | X86_PDE4M_G;
1561 }
1562
1563 /* We convert it here every time as PCI regions could be reconfigured. */
1564 if (PDMVmmDevHeapIsEnabled(pVM))
1565 {
1566 RTGCPHYS GCPhys;
1567 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1568 AssertRCReturn(rc, rc);
1569 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1570
1571 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1572 AssertRCReturn(rc, rc);
1573 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1574 }
1575 }
1576 else
1577 {
1578 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1579 pVM->hm.s.vmx.pRealModeTSS = NULL;
1580 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1581 return VMSetError(pVM, rc, RT_SRC_POS,
1582 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1583 }
1584 }
1585
1586 LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1587 : "HM: Guest support: 32-bit only\n"));
1588
1589 /*
1590 * Call ring-0 to set up the VM.
1591 */
1592 rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1593 if (rc != VINF_SUCCESS)
1594 {
1595 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1596 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1597 {
1598 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1599 LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1600 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1601 }
1602 HMR3CheckError(pVM, rc);
1603 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1604 }
1605
1606 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1607 LogRel(("HM: Enabled VMX\n"));
1608 pVM->hm.s.vmx.fEnabled = true;
1609
1610 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1611
1612 /*
1613 * Change the CPU features.
1614 */
1615 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1616 if (pVM->hm.s.fAllow64BitGuests)
1617 {
1618 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1619 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1620 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1621 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1622 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1623 }
1624 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1625 (we reuse the host EFER in the switcher). */
1626 /** @todo this needs to be fixed properly!! */
1627 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1628 {
1629 if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1630 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1631 else
1632 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1633 }
1634
1635 /*
1636 * Log configuration details.
1637 */
1638 if (pVM->hm.s.fNestedPaging)
1639 {
1640 LogRel(("HM: Enabled nested paging\n"));
1641 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1642 LogRel(("HM: EPT flush type = Single context\n"));
1643 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1644 LogRel(("HM: EPT flush type = All contexts\n"));
1645 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1646 LogRel(("HM: EPT flush type = Not supported\n"));
1647 else
1648 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1649
1650 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1651 LogRel(("HM: Enabled unrestricted guest execution\n"));
1652
1653 if (pVM->hm.s.fLargePages)
1654 {
1655 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1656 PGMSetLargePageUsage(pVM, true);
1657 LogRel(("HM: Enabled large page support\n"));
1658 }
1659 }
1660 else
1661 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1662
1663 if (pVM->hm.s.vmx.fVpid)
1664 {
1665 LogRel(("HM: Enabled VPID\n"));
1666 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1667 LogRel(("HM: VPID flush type = Individual addresses\n"));
1668 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1669 LogRel(("HM: VPID flush type = Single context\n"));
1670 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1671 LogRel(("HM: VPID flush type = All contexts\n"));
1672 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1673 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1674 else
1675 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1676 }
1677 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1678 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1679
1680 if (pVM->hm.s.vmx.fUsePreemptTimer)
1681 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1682 else
1683 LogRel(("HM: Disabled VMX-preemption timer\n"));
1684
1685 if (pVM->hm.s.fVirtApicRegs)
1686 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1687
1688 if (pVM->hm.s.fPostedIntrs)
1689 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1690
1691 if (pVM->hm.s.vmx.fUseVmcsShadowing)
1692 {
1693 bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1694 LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1695 }
1696
1697 return VINF_SUCCESS;
1698}
1699
1700
1701/**
1702 * Finish AMD-V initialization (after ring-0 init).
1703 *
1704 * @returns VBox status code.
1705 * @param pVM The cross context VM structure.
1706 */
1707static int hmR3InitFinalizeR0Amd(PVM pVM)
1708{
1709 LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1710
1711 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1712
1713 uint32_t u32Family;
1714 uint32_t u32Model;
1715 uint32_t u32Stepping;
1716 if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1717 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1718 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1719 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1720 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1721 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1722 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1723
1724 /*
1725 * Enumerate AMD-V features.
1726 */
1727 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1728 {
1729#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1730 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1731 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1732 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1733 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1734 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1735 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1736 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1737 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1738 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1739 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1740 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1741 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1742 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1743 HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1744#undef HMSVM_REPORT_FEATURE
1745 };
1746
1747 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1748 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1749 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1750 {
1751 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1752 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1753 }
1754 if (fSvmFeatures)
1755 for (unsigned iBit = 0; iBit < 32; iBit++)
1756 if (RT_BIT_32(iBit) & fSvmFeatures)
1757 LogRel(("HM: Reserved bit %u\n", iBit));
1758
1759 /*
1760 * Nested paging is determined in HMR3Init, verify the sanity of that.
1761 */
1762 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1763 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1764 VERR_HM_IPE_1);
1765
1766#if 0
1767 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1768 * here. */
1769 if (RTR0IsPostIpiSupport())
1770 pVM->hm.s.fPostedIntrs = true;
1771#endif
1772
1773 /*
1774 * Call ring-0 to set up the VM.
1775 */
1776 int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1777 if (rc != VINF_SUCCESS)
1778 {
1779 AssertMsgFailed(("%Rrc\n", rc));
1780 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1781 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1782 }
1783
1784 LogRel(("HM: Enabled SVM\n"));
1785 pVM->hm.s.svm.fEnabled = true;
1786
1787 if (pVM->hm.s.fNestedPaging)
1788 {
1789 LogRel(("HM: Enabled nested paging\n"));
1790
1791 /*
1792 * Enable large pages (2 MB) if applicable.
1793 */
1794 if (pVM->hm.s.fLargePages)
1795 {
1796 PGMSetLargePageUsage(pVM, true);
1797 LogRel(("HM: Enabled large page support\n"));
1798 }
1799 }
1800
1801 if (pVM->hm.s.fVirtApicRegs)
1802 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1803
1804 if (pVM->hm.s.fPostedIntrs)
1805 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1806
1807 hmR3DisableRawMode(pVM);
1808
1809 /*
1810 * Change the CPU features.
1811 */
1812 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1813 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1814 if (pVM->hm.s.fAllow64BitGuests)
1815 {
1816 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1817 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1818 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1819 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1820 }
1821 /* Turn on NXE if PAE has been enabled. */
1822 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1823 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1824
1825 LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1826 : "HM: Disabled TPR patching\n"));
1827
1828 LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1829 : "HM: Guest support: 32-bit only\n"));
1830 return VINF_SUCCESS;
1831}
1832
1833
1834/**
1835 * Applies relocations to data and code managed by this
1836 * component. This function will be called at init and
1837 * whenever the VMM need to relocate it self inside the GC.
1838 *
1839 * @param pVM The cross context VM structure.
1840 */
1841VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1842{
1843 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1844
1845 /* Fetch the current paging mode during the relocate callback during state loading. */
1846 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1847 {
1848 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1849 {
1850 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1851 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1852 }
1853 }
1854}
1855
1856
1857/**
1858 * Terminates the HM.
1859 *
1860 * Termination means cleaning up and freeing all resources,
1861 * the VM itself is, at this point, powered off or suspended.
1862 *
1863 * @returns VBox status code.
1864 * @param pVM The cross context VM structure.
1865 */
1866VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1867{
1868 if (pVM->hm.s.vmx.pRealModeTSS)
1869 {
1870 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1871 pVM->hm.s.vmx.pRealModeTSS = 0;
1872 }
1873 hmR3TermCPU(pVM);
1874 return 0;
1875}
1876
1877
1878/**
1879 * Terminates the per-VCPU HM.
1880 *
1881 * @returns VBox status code.
1882 * @param pVM The cross context VM structure.
1883 */
1884static int hmR3TermCPU(PVM pVM)
1885{
1886#ifdef VBOX_WITH_STATISTICS
1887 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1888 {
1889 PVMCPU pVCpu = pVM->apCpusR3[idCpu]; NOREF(pVCpu);
1890 if (pVCpu->hm.s.paStatExitReason)
1891 {
1892 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1893 pVCpu->hm.s.paStatExitReason = NULL;
1894 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1895 }
1896 if (pVCpu->hm.s.paStatInjectedIrqs)
1897 {
1898 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1899 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1900 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1901 }
1902# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1903 if (pVCpu->hm.s.paStatNestedExitReason)
1904 {
1905 MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
1906 pVCpu->hm.s.paStatNestedExitReason = NULL;
1907 pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
1908 }
1909# endif
1910 }
1911#else
1912 RT_NOREF(pVM);
1913#endif
1914 return VINF_SUCCESS;
1915}
1916
1917
1918/**
1919 * Resets a virtual CPU.
1920 *
1921 * Used by HMR3Reset and CPU hot plugging.
1922 *
1923 * @param pVCpu The cross context virtual CPU structure to reset.
1924 */
1925VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1926{
1927 /* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
1928 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1929 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
1930
1931 pVCpu->hm.s.fActive = false;
1932 pVCpu->hm.s.Event.fPending = false;
1933 pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
1934 pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32Obsolete = false;
1935 pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
1936#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1937 if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
1938 {
1939 pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32Obsolete = false;
1940 pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
1941 }
1942#endif
1943}
1944
1945
1946/**
1947 * The VM is being reset.
1948 *
1949 * For the HM component this means that any GDT/LDT/TSS monitors
1950 * needs to be removed.
1951 *
1952 * @param pVM The cross context VM structure.
1953 */
1954VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1955{
1956 LogFlow(("HMR3Reset:\n"));
1957
1958 if (HMIsEnabled(pVM))
1959 hmR3DisableRawMode(pVM);
1960
1961 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1962 HMR3ResetCpu(pVM->apCpusR3[idCpu]);
1963
1964 /* Clear all patch information. */
1965 pVM->hm.s.pGuestPatchMem = 0;
1966 pVM->hm.s.pFreeGuestPatchMem = 0;
1967 pVM->hm.s.cbGuestPatchMem = 0;
1968 pVM->hm.s.cPatches = 0;
1969 pVM->hm.s.PatchTree = 0;
1970 pVM->hm.s.fTPRPatchingActive = false;
1971 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1972}
1973
1974
1975/**
1976 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1977 *
1978 * @returns VBox strict status code.
1979 * @param pVM The cross context VM structure.
1980 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1981 * @param pvUser Unused.
1982 */
1983static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1984{
1985 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1986
1987 /* Only execute the handler on the VCPU the original patch request was issued. */
1988 if (pVCpu->idCpu != idCpu)
1989 return VINF_SUCCESS;
1990
1991 Log(("hmR3RemovePatches\n"));
1992 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1993 {
1994 uint8_t abInstr[15];
1995 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1996 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1997 int rc;
1998
1999#ifdef LOG_ENABLED
2000 char szOutput[256];
2001 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2002 szOutput, sizeof(szOutput), NULL);
2003 if (RT_SUCCESS(rc))
2004 Log(("Patched instr: %s\n", szOutput));
2005#endif
2006
2007 /* Check if the instruction is still the same. */
2008 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2009 if (rc != VINF_SUCCESS)
2010 {
2011 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2012 continue; /* swapped out or otherwise removed; skip it. */
2013 }
2014
2015 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2016 {
2017 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2018 continue; /* skip it. */
2019 }
2020
2021 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2022 AssertRC(rc);
2023
2024#ifdef LOG_ENABLED
2025 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2026 szOutput, sizeof(szOutput), NULL);
2027 if (RT_SUCCESS(rc))
2028 Log(("Original instr: %s\n", szOutput));
2029#endif
2030 }
2031 pVM->hm.s.cPatches = 0;
2032 pVM->hm.s.PatchTree = 0;
2033 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2034 pVM->hm.s.fTPRPatchingActive = false;
2035 return VINF_SUCCESS;
2036}
2037
2038
2039/**
2040 * Worker for enabling patching in a VT-x/AMD-V guest.
2041 *
2042 * @returns VBox status code.
2043 * @param pVM The cross context VM structure.
2044 * @param idCpu VCPU to execute hmR3RemovePatches on.
2045 * @param pPatchMem Patch memory range.
2046 * @param cbPatchMem Size of the memory range.
2047 */
2048static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2049{
2050 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2051 AssertRC(rc);
2052
2053 pVM->hm.s.pGuestPatchMem = pPatchMem;
2054 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2055 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2056 return VINF_SUCCESS;
2057}
2058
2059
2060/**
2061 * Enable patching in a VT-x/AMD-V guest
2062 *
2063 * @returns VBox status code.
2064 * @param pVM The cross context VM structure.
2065 * @param pPatchMem Patch memory range.
2066 * @param cbPatchMem Size of the memory range.
2067 */
2068VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2069{
2070 VM_ASSERT_EMT(pVM);
2071 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2072 if (pVM->cCpus > 1)
2073 {
2074 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2075 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2076 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2077 AssertRC(rc);
2078 return rc;
2079 }
2080 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2081}
2082
2083
2084/**
2085 * Disable patching in a VT-x/AMD-V guest.
2086 *
2087 * @returns VBox status code.
2088 * @param pVM The cross context VM structure.
2089 * @param pPatchMem Patch memory range.
2090 * @param cbPatchMem Size of the memory range.
2091 */
2092VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2093{
2094 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2095 RT_NOREF2(pPatchMem, cbPatchMem);
2096
2097 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2098 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2099
2100 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2101 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2102 (void *)(uintptr_t)VMMGetCpuId(pVM));
2103 AssertRC(rc);
2104
2105 pVM->hm.s.pGuestPatchMem = 0;
2106 pVM->hm.s.pFreeGuestPatchMem = 0;
2107 pVM->hm.s.cbGuestPatchMem = 0;
2108 pVM->hm.s.fTPRPatchingActive = false;
2109 return VINF_SUCCESS;
2110}
2111
2112
2113/**
2114 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2115 *
2116 * @returns VBox strict status code.
2117 * @param pVM The cross context VM structure.
2118 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2119 * @param pvUser User specified CPU context.
2120 *
2121 */
2122static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2123{
2124 /*
2125 * Only execute the handler on the VCPU the original patch request was
2126 * issued. (The other CPU(s) might not yet have switched to protected
2127 * mode, nor have the correct memory context.)
2128 */
2129 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2130 if (pVCpu->idCpu != idCpu)
2131 return VINF_SUCCESS;
2132
2133 /*
2134 * We're racing other VCPUs here, so don't try patch the instruction twice
2135 * and make sure there is still room for our patch record.
2136 */
2137 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2138 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2139 if (pPatch)
2140 {
2141 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2142 return VINF_SUCCESS;
2143 }
2144 uint32_t const idx = pVM->hm.s.cPatches;
2145 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2146 {
2147 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2148 return VINF_SUCCESS;
2149 }
2150 pPatch = &pVM->hm.s.aPatches[idx];
2151
2152 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2153
2154 /*
2155 * Disassembler the instruction and get cracking.
2156 */
2157 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2158 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2159 uint32_t cbOp;
2160 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2161 AssertRC(rc);
2162 if ( rc == VINF_SUCCESS
2163 && pDis->pCurInstr->uOpcode == OP_MOV
2164 && cbOp >= 3)
2165 {
2166 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2167
2168 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2169 AssertRC(rc);
2170
2171 pPatch->cbOp = cbOp;
2172
2173 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2174 {
2175 /* write. */
2176 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2177 {
2178 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2179 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2180 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2181 }
2182 else
2183 {
2184 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2185 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2186 pPatch->uSrcOperand = pDis->Param2.uValue;
2187 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2188 }
2189 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2190 AssertRC(rc);
2191
2192 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2193 pPatch->cbNewOp = sizeof(s_abVMMCall);
2194 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2195 }
2196 else
2197 {
2198 /*
2199 * TPR Read.
2200 *
2201 * Found:
2202 * mov eax, dword [fffe0080] (5 bytes)
2203 * Check if next instruction is:
2204 * shr eax, 4
2205 */
2206 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2207
2208 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2209 uint8_t const cbOpMmio = cbOp;
2210 uint64_t const uSavedRip = pCtx->rip;
2211
2212 pCtx->rip += cbOp;
2213 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2214 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2215 pCtx->rip = uSavedRip;
2216
2217 if ( rc == VINF_SUCCESS
2218 && pDis->pCurInstr->uOpcode == OP_SHR
2219 && pDis->Param1.fUse == DISUSE_REG_GEN32
2220 && pDis->Param1.Base.idxGenReg == idxMmioReg
2221 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2222 && pDis->Param2.uValue == 4
2223 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2224 {
2225 uint8_t abInstr[15];
2226
2227 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2228 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2229 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2230 AssertRC(rc);
2231
2232 pPatch->cbOp = cbOpMmio + cbOp;
2233
2234 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2235 abInstr[0] = 0xf0;
2236 abInstr[1] = 0x0f;
2237 abInstr[2] = 0x20;
2238 abInstr[3] = 0xc0 | pDis->Param1.Base.idxGenReg;
2239 for (unsigned i = 4; i < pPatch->cbOp; i++)
2240 abInstr[i] = 0x90; /* nop */
2241
2242 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2243 AssertRC(rc);
2244
2245 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2246 pPatch->cbNewOp = pPatch->cbOp;
2247 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2248
2249 Log(("Acceptable read/shr candidate!\n"));
2250 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2251 }
2252 else
2253 {
2254 pPatch->enmType = HMTPRINSTR_READ;
2255 pPatch->uDstOperand = idxMmioReg;
2256
2257 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2258 AssertRC(rc);
2259
2260 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2261 pPatch->cbNewOp = sizeof(s_abVMMCall);
2262 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2263 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2264 }
2265 }
2266
2267 pPatch->Core.Key = pCtx->eip;
2268 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2269 AssertRC(rc);
2270
2271 pVM->hm.s.cPatches++;
2272 return VINF_SUCCESS;
2273 }
2274
2275 /*
2276 * Save invalid patch, so we will not try again.
2277 */
2278 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2279 pPatch->Core.Key = pCtx->eip;
2280 pPatch->enmType = HMTPRINSTR_INVALID;
2281 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2282 AssertRC(rc);
2283 pVM->hm.s.cPatches++;
2284 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2285 return VINF_SUCCESS;
2286}
2287
2288
2289/**
2290 * Callback to patch a TPR instruction (jump to generated code).
2291 *
2292 * @returns VBox strict status code.
2293 * @param pVM The cross context VM structure.
2294 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2295 * @param pvUser User specified CPU context.
2296 *
2297 */
2298static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2299{
2300 /*
2301 * Only execute the handler on the VCPU the original patch request was
2302 * issued. (The other CPU(s) might not yet have switched to protected
2303 * mode, nor have the correct memory context.)
2304 */
2305 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2306 if (pVCpu->idCpu != idCpu)
2307 return VINF_SUCCESS;
2308
2309 /*
2310 * We're racing other VCPUs here, so don't try patch the instruction twice
2311 * and make sure there is still room for our patch record.
2312 */
2313 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2314 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2315 if (pPatch)
2316 {
2317 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2318 return VINF_SUCCESS;
2319 }
2320 uint32_t const idx = pVM->hm.s.cPatches;
2321 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2322 {
2323 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2324 return VINF_SUCCESS;
2325 }
2326 pPatch = &pVM->hm.s.aPatches[idx];
2327
2328 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2329 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2330
2331 /*
2332 * Disassemble the instruction and get cracking.
2333 */
2334 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2335 uint32_t cbOp;
2336 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2337 AssertRC(rc);
2338 if ( rc == VINF_SUCCESS
2339 && pDis->pCurInstr->uOpcode == OP_MOV
2340 && cbOp >= 5)
2341 {
2342 uint8_t aPatch[64];
2343 uint32_t off = 0;
2344
2345 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2346 AssertRC(rc);
2347
2348 pPatch->cbOp = cbOp;
2349 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2350
2351 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2352 {
2353 /*
2354 * TPR write:
2355 *
2356 * push ECX [51]
2357 * push EDX [52]
2358 * push EAX [50]
2359 * xor EDX,EDX [31 D2]
2360 * mov EAX,EAX [89 C0]
2361 * or
2362 * mov EAX,0000000CCh [B8 CC 00 00 00]
2363 * mov ECX,0C0000082h [B9 82 00 00 C0]
2364 * wrmsr [0F 30]
2365 * pop EAX [58]
2366 * pop EDX [5A]
2367 * pop ECX [59]
2368 * jmp return_address [E9 return_address]
2369 */
2370 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2371
2372 aPatch[off++] = 0x51; /* push ecx */
2373 aPatch[off++] = 0x52; /* push edx */
2374 if (!fUsesEax)
2375 aPatch[off++] = 0x50; /* push eax */
2376 aPatch[off++] = 0x31; /* xor edx, edx */
2377 aPatch[off++] = 0xd2;
2378 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2379 {
2380 if (!fUsesEax)
2381 {
2382 aPatch[off++] = 0x89; /* mov eax, src_reg */
2383 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2384 }
2385 }
2386 else
2387 {
2388 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2389 aPatch[off++] = 0xb8; /* mov eax, immediate */
2390 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2391 off += sizeof(uint32_t);
2392 }
2393 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2394 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2395 off += sizeof(uint32_t);
2396
2397 aPatch[off++] = 0x0f; /* wrmsr */
2398 aPatch[off++] = 0x30;
2399 if (!fUsesEax)
2400 aPatch[off++] = 0x58; /* pop eax */
2401 aPatch[off++] = 0x5a; /* pop edx */
2402 aPatch[off++] = 0x59; /* pop ecx */
2403 }
2404 else
2405 {
2406 /*
2407 * TPR read:
2408 *
2409 * push ECX [51]
2410 * push EDX [52]
2411 * push EAX [50]
2412 * mov ECX,0C0000082h [B9 82 00 00 C0]
2413 * rdmsr [0F 32]
2414 * mov EAX,EAX [89 C0]
2415 * pop EAX [58]
2416 * pop EDX [5A]
2417 * pop ECX [59]
2418 * jmp return_address [E9 return_address]
2419 */
2420 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2421
2422 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2423 aPatch[off++] = 0x51; /* push ecx */
2424 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2425 aPatch[off++] = 0x52; /* push edx */
2426 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2427 aPatch[off++] = 0x50; /* push eax */
2428
2429 aPatch[off++] = 0x31; /* xor edx, edx */
2430 aPatch[off++] = 0xd2;
2431
2432 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2433 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2434 off += sizeof(uint32_t);
2435
2436 aPatch[off++] = 0x0f; /* rdmsr */
2437 aPatch[off++] = 0x32;
2438
2439 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2440 {
2441 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2442 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2443 }
2444
2445 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2446 aPatch[off++] = 0x58; /* pop eax */
2447 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2448 aPatch[off++] = 0x5a; /* pop edx */
2449 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2450 aPatch[off++] = 0x59; /* pop ecx */
2451 }
2452 aPatch[off++] = 0xe9; /* jmp return_address */
2453 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2454 off += sizeof(RTRCUINTPTR);
2455
2456 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2457 {
2458 /* Write new code to the patch buffer. */
2459 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2460 AssertRC(rc);
2461
2462#ifdef LOG_ENABLED
2463 uint32_t cbCurInstr;
2464 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2465 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2466 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2467 {
2468 char szOutput[256];
2469 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2470 szOutput, sizeof(szOutput), &cbCurInstr);
2471 if (RT_SUCCESS(rc))
2472 Log(("Patch instr %s\n", szOutput));
2473 else
2474 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2475 }
2476#endif
2477
2478 pPatch->aNewOpcode[0] = 0xE9;
2479 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2480
2481 /* Overwrite the TPR instruction with a jump. */
2482 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2483 AssertRC(rc);
2484
2485 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2486
2487 pVM->hm.s.pFreeGuestPatchMem += off;
2488 pPatch->cbNewOp = 5;
2489
2490 pPatch->Core.Key = pCtx->eip;
2491 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2492 AssertRC(rc);
2493
2494 pVM->hm.s.cPatches++;
2495 pVM->hm.s.fTPRPatchingActive = true;
2496 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2497 return VINF_SUCCESS;
2498 }
2499
2500 Log(("Ran out of space in our patch buffer!\n"));
2501 }
2502 else
2503 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2504
2505
2506 /*
2507 * Save invalid patch, so we will not try again.
2508 */
2509 pPatch = &pVM->hm.s.aPatches[idx];
2510 pPatch->Core.Key = pCtx->eip;
2511 pPatch->enmType = HMTPRINSTR_INVALID;
2512 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2513 AssertRC(rc);
2514 pVM->hm.s.cPatches++;
2515 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2516 return VINF_SUCCESS;
2517}
2518
2519
2520/**
2521 * Attempt to patch TPR mmio instructions.
2522 *
2523 * @returns VBox status code.
2524 * @param pVM The cross context VM structure.
2525 * @param pVCpu The cross context virtual CPU structure.
2526 */
2527VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2528{
2529 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2530 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2531 (void *)(uintptr_t)pVCpu->idCpu);
2532 AssertRC(rc);
2533 return rc;
2534}
2535
2536
2537/**
2538 * Checks if we need to reschedule due to VMM device heap changes.
2539 *
2540 * @returns true if a reschedule is required, otherwise false.
2541 * @param pVM The cross context VM structure.
2542 * @param pCtx VM execution context.
2543 */
2544VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2545{
2546 /*
2547 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2548 * when the unrestricted guest execution feature is missing (VT-x only).
2549 */
2550 if ( pVM->hm.s.vmx.fEnabled
2551 && !pVM->hm.s.vmx.fUnrestrictedGuest
2552 && CPUMIsGuestInRealModeEx(pCtx)
2553 && !PDMVmmDevHeapIsEnabled(pVM))
2554 return true;
2555
2556 return false;
2557}
2558
2559
2560/**
2561 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2562 * event settings changes.
2563 *
2564 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2565 * function is just updating the VM globals.
2566 *
2567 * @param pVM The VM cross context VM structure.
2568 * @thread EMT(0)
2569 */
2570VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2571{
2572 /* Interrupts. */
2573 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2574 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2575
2576 /* CPU Exceptions. */
2577 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2578 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2579 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2580 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2581
2582 /* Common VM exits. */
2583 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2584 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2585 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2586 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2587
2588 /* Vendor specific VM exits. */
2589 if (HMR3IsVmxEnabled(pVM->pUVM))
2590 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2591 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2592 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2593 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2594 else
2595 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2596 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2597 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2598 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2599
2600 /* Done. */
2601 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2602}
2603
2604
2605/**
2606 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2607 *
2608 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2609 * per CPU settings.
2610 *
2611 * @param pVM The VM cross context VM structure.
2612 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2613 */
2614VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2615{
2616 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2617}
2618
2619
2620/**
2621 * Checks if we are currently using hardware acceleration.
2622 *
2623 * @returns true if hardware acceleration is being used, otherwise false.
2624 * @param pVCpu The cross context virtual CPU structure.
2625 */
2626VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2627{
2628 return pVCpu->hm.s.fActive;
2629}
2630
2631
2632/**
2633 * External interface for querying whether hardware acceleration is enabled.
2634 *
2635 * @returns true if VT-x or AMD-V is being used, otherwise false.
2636 * @param pUVM The user mode VM handle.
2637 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2638 */
2639VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2640{
2641 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2642 PVM pVM = pUVM->pVM;
2643 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2644 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2645}
2646
2647
2648/**
2649 * External interface for querying whether VT-x is being used.
2650 *
2651 * @returns true if VT-x is being used, otherwise false.
2652 * @param pUVM The user mode VM handle.
2653 * @sa HMR3IsSvmEnabled, HMIsEnabled
2654 */
2655VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2656{
2657 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2658 PVM pVM = pUVM->pVM;
2659 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2660 return pVM->hm.s.vmx.fEnabled
2661 && pVM->hm.s.vmx.fSupported
2662 && pVM->fHMEnabled;
2663}
2664
2665
2666/**
2667 * External interface for querying whether AMD-V is being used.
2668 *
2669 * @returns true if VT-x is being used, otherwise false.
2670 * @param pUVM The user mode VM handle.
2671 * @sa HMR3IsVmxEnabled, HMIsEnabled
2672 */
2673VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2674{
2675 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2676 PVM pVM = pUVM->pVM;
2677 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2678 return pVM->hm.s.svm.fEnabled
2679 && pVM->hm.s.svm.fSupported
2680 && pVM->fHMEnabled;
2681}
2682
2683
2684/**
2685 * Checks if we are currently using nested paging.
2686 *
2687 * @returns true if nested paging is being used, otherwise false.
2688 * @param pUVM The user mode VM handle.
2689 */
2690VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2691{
2692 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2693 PVM pVM = pUVM->pVM;
2694 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2695 return pVM->hm.s.fNestedPaging;
2696}
2697
2698
2699/**
2700 * Checks if virtualized APIC registers is enabled.
2701 *
2702 * When enabled this feature allows the hardware to access most of the
2703 * APIC registers in the virtual-APIC page without causing VM-exits. See
2704 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2705 *
2706 * @returns true if virtualized APIC registers is enabled, otherwise
2707 * false.
2708 * @param pUVM The user mode VM handle.
2709 */
2710VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2711{
2712 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2713 PVM pVM = pUVM->pVM;
2714 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2715 return pVM->hm.s.fVirtApicRegs;
2716}
2717
2718
2719/**
2720 * Checks if APIC posted-interrupt processing is enabled.
2721 *
2722 * This returns whether we can deliver interrupts to the guest without
2723 * leaving guest-context by updating APIC state from host-context.
2724 *
2725 * @returns true if APIC posted-interrupt processing is enabled,
2726 * otherwise false.
2727 * @param pUVM The user mode VM handle.
2728 */
2729VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2730{
2731 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2732 PVM pVM = pUVM->pVM;
2733 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2734 return pVM->hm.s.fPostedIntrs;
2735}
2736
2737
2738/**
2739 * Checks if we are currently using VPID in VT-x mode.
2740 *
2741 * @returns true if VPID is being used, otherwise false.
2742 * @param pUVM The user mode VM handle.
2743 */
2744VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2745{
2746 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2747 PVM pVM = pUVM->pVM;
2748 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2749 return pVM->hm.s.vmx.fVpid;
2750}
2751
2752
2753/**
2754 * Checks if we are currently using VT-x unrestricted execution,
2755 * aka UX.
2756 *
2757 * @returns true if UX is being used, otherwise false.
2758 * @param pUVM The user mode VM handle.
2759 */
2760VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2761{
2762 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2763 PVM pVM = pUVM->pVM;
2764 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2765 return pVM->hm.s.vmx.fUnrestrictedGuest
2766 || pVM->hm.s.svm.fSupported;
2767}
2768
2769
2770/**
2771 * Checks if the VMX-preemption timer is being used.
2772 *
2773 * @returns true if the VMX-preemption timer is being used, otherwise false.
2774 * @param pVM The cross context VM structure.
2775 */
2776VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2777{
2778 return HMIsEnabled(pVM)
2779 && pVM->hm.s.vmx.fEnabled
2780 && pVM->hm.s.vmx.fUsePreemptTimer;
2781}
2782
2783
2784/**
2785 * Helper for HMR3CheckError to log VMCS controls to the release log.
2786 *
2787 * @param idCpu The Virtual CPU ID.
2788 * @param pVmcsInfo The VMCS info. object.
2789 */
2790static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2791{
2792 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2793 {
2794 uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2795 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2796 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2797 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2798 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2799 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2800 }
2801 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2802 {
2803 uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2804 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2805 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2806 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2807 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2808 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2809 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2810 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2811 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2812 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2813 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2814 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2815 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2816 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2817 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2818 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2819 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2820 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2821 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2822 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2823 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2824 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2825 }
2826 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2827 {
2828 uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2829 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2830 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2831 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2832 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2833 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2834 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2835 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2836 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2837 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2838 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2839 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2840 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2841 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2842 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2843 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2844 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2845 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2846 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2847 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2848 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2849 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2850 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2851 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2852 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2853 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2854 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2855 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2856 }
2857 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2858 {
2859 uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2860 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2861 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2862 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2863 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2864 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2865 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2866 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2867 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2868 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2869 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2870 }
2871 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2872 {
2873 uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2874 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2875 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2876 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2877 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2878 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2879 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2880 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2881 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2882 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2883 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2884 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2885 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2886 }
2887}
2888
2889
2890/**
2891 * Check fatal VT-x/AMD-V error and produce some meaningful
2892 * log release message.
2893 *
2894 * @param pVM The cross context VM structure.
2895 * @param iStatusCode VBox status code.
2896 */
2897VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2898{
2899 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2900 {
2901 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2902 * might be getting inaccurate values for non-guru'ing EMTs. */
2903 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2904 PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
2905 bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
2906 switch (iStatusCode)
2907 {
2908 case VERR_VMX_INVALID_VMCS_PTR:
2909 {
2910 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2911 LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2912 LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2913 pVmcsInfo->HCPhysVmcs));
2914 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2915 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2916 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2917 break;
2918 }
2919
2920 case VERR_VMX_UNABLE_TO_START_VM:
2921 {
2922 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2923 LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2924 LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
2925 LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2926
2927 if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
2928 || pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
2929 {
2930 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2931 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2932 }
2933 else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
2934 {
2935 hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
2936 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
2937 LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
2938 LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
2939 LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
2940 LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
2941 LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
2942 LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
2943 }
2944 /** @todo Log VM-entry event injection control fields
2945 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2946 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2947 break;
2948 }
2949
2950 case VERR_VMX_INVALID_GUEST_STATE:
2951 {
2952 LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
2953 LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
2954 LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
2955 hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
2956 break;
2957 }
2958
2959 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
2960 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
2961 case VERR_VMX_INVALID_VMXON_PTR:
2962 case VERR_VMX_UNEXPECTED_EXIT:
2963 case VERR_VMX_INVALID_VMCS_FIELD:
2964 case VERR_SVM_UNKNOWN_EXIT:
2965 case VERR_SVM_UNEXPECTED_EXIT:
2966 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2967 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2968 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
2969 break;
2970 }
2971 }
2972
2973 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2974 {
2975 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
2976 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
2977 }
2978 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
2979 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
2980}
2981
2982
2983/**
2984 * Execute state save operation.
2985 *
2986 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
2987 * is because we always save the VM state from ring-3 and thus most HM state
2988 * will be re-synced dynamically at runtime and don't need to be part of the VM
2989 * saved state.
2990 *
2991 * @returns VBox status code.
2992 * @param pVM The cross context VM structure.
2993 * @param pSSM SSM operation handle.
2994 */
2995static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2996{
2997 Log(("hmR3Save:\n"));
2998
2999 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3000 {
3001 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3002 Assert(!pVCpu->hm.s.Event.fPending);
3003 if (pVM->cpum.ro.GuestFeatures.fSvm)
3004 {
3005 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3006 SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3007 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3008 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3009 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3010 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3011 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3012 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3013 SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3014 SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3015 SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3016 SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3017 SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3018 SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3019 }
3020 }
3021
3022 /* Save the guest patch data. */
3023 SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3024 SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3025 SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3026
3027 /* Store all the guest patch records too. */
3028 int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3029 if (RT_FAILURE(rc))
3030 return rc;
3031
3032 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3033 {
3034 AssertCompileSize(HMTPRINSTR, 4);
3035 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3036 SSMR3PutU32(pSSM, pPatch->Core.Key);
3037 SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3038 SSMR3PutU32(pSSM, pPatch->cbOp);
3039 SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3040 SSMR3PutU32(pSSM, pPatch->cbNewOp);
3041 SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3042 SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3043 SSMR3PutU32(pSSM, pPatch->uDstOperand);
3044 SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3045 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3046 if (RT_FAILURE(rc))
3047 return rc;
3048 }
3049
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/**
3055 * Execute state load operation.
3056 *
3057 * @returns VBox status code.
3058 * @param pVM The cross context VM structure.
3059 * @param pSSM SSM operation handle.
3060 * @param uVersion Data layout version.
3061 * @param uPass The data pass.
3062 */
3063static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3064{
3065 int rc;
3066
3067 LogFlowFunc(("uVersion=%u\n", uVersion));
3068 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3069
3070 /*
3071 * Validate version.
3072 */
3073 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3074 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3075 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3076 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3077 {
3078 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3079 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3080 }
3081
3082 /*
3083 * Load per-VCPU state.
3084 */
3085 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3086 {
3087 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3088 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3089 {
3090 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3091 if (pVM->cpum.ro.GuestFeatures.fSvm)
3092 {
3093 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3094 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3095 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3096 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3097 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3098 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3099 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3100 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3101 SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3102 SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3103 SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3104 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3105 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3106 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3107 AssertRCReturn(rc, rc);
3108 }
3109 }
3110 else
3111 {
3112 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3113 SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3114 SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3115 SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3116
3117 /* VMX fWasInRealMode related data. */
3118 uint32_t uDummy;
3119 SSMR3GetU32(pSSM, &uDummy);
3120 SSMR3GetU32(pSSM, &uDummy);
3121 rc = SSMR3GetU32(pSSM, &uDummy);
3122 AssertRCReturn(rc, rc);
3123 }
3124 }
3125
3126 /*
3127 * Load TPR patching data.
3128 */
3129 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3130 {
3131 SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3132 SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3133 SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3134
3135 /* Fetch all TPR patch records. */
3136 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3137 AssertRCReturn(rc, rc);
3138 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3139 {
3140 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3141 SSMR3GetU32(pSSM, &pPatch->Core.Key);
3142 SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3143 SSMR3GetU32(pSSM, &pPatch->cbOp);
3144 SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3145 SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3146 SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3147
3148 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3149 pVM->hm.s.fTPRPatchingActive = true;
3150 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3151
3152 SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3153 SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3154 SSMR3GetU32(pSSM, &pPatch->cFaults);
3155 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3156 AssertRCReturn(rc, rc);
3157
3158 LogFlow(("hmR3Load: patch %d\n", i));
3159 LogFlow(("Key = %x\n", pPatch->Core.Key));
3160 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3161 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3162 LogFlow(("type = %d\n", pPatch->enmType));
3163 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3164 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3165 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3166 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3167
3168 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3169 AssertRCReturn(rc, rc);
3170 }
3171 }
3172
3173 return VINF_SUCCESS;
3174}
3175
3176
3177/**
3178 * Displays HM info.
3179 *
3180 * @param pVM The cross context VM structure.
3181 * @param pHlp The info helper functions.
3182 * @param pszArgs Arguments, ignored.
3183 */
3184static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3185{
3186 NOREF(pszArgs);
3187 PVMCPU pVCpu = VMMGetCpu(pVM);
3188 if (!pVCpu)
3189 pVCpu = pVM->apCpusR3[0];
3190
3191 if (HMIsEnabled(pVM))
3192 {
3193 if (pVM->hm.s.vmx.fSupported)
3194 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3195 else
3196 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3197 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3198 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3199 if (pVM->hm.s.vmx.fSupported)
3200 {
3201 PCVMXVMCSINFO pVmcsInfo = hmGetVmxActiveVmcsInfo(pVCpu);
3202 bool const fRealOnV86Active = pVmcsInfo->RealMode.fRealOnV86Active;
3203 bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcs;
3204
3205 pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3206 pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3207 if (fRealOnV86Active)
3208 {
3209 pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfo->RealMode.Eflags.u32);
3210 pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfo->RealMode.AttrCS.u);
3211 pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfo->RealMode.AttrSS.u);
3212 pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfo->RealMode.AttrDS.u);
3213 pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfo->RealMode.AttrES.u);
3214 pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfo->RealMode.AttrFS.u);
3215 pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfo->RealMode.AttrGS.u);
3216 }
3217 }
3218 }
3219 else
3220 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3221}
3222
3223
3224/**
3225 * Displays the HM pending event.
3226 *
3227 * @param pVM The cross context VM structure.
3228 * @param pHlp The info helper functions.
3229 * @param pszArgs Arguments, ignored.
3230 */
3231static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3232{
3233 NOREF(pszArgs);
3234 PVMCPU pVCpu = VMMGetCpu(pVM);
3235 if (!pVCpu)
3236 pVCpu = pVM->apCpusR3[0];
3237
3238 if (HMIsEnabled(pVM))
3239 {
3240 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3241 if (pVCpu->hm.s.Event.fPending)
3242 {
3243 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3244 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3245 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3246 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3247 }
3248 }
3249 else
3250 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3251}
3252
3253
3254/**
3255 * Displays the SVM nested-guest VMCB cache.
3256 *
3257 * @param pVM The cross context VM structure.
3258 * @param pHlp The info helper functions.
3259 * @param pszArgs Arguments, ignored.
3260 */
3261static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3262{
3263 NOREF(pszArgs);
3264 PVMCPU pVCpu = VMMGetCpu(pVM);
3265 if (!pVCpu)
3266 pVCpu = pVM->apCpusR3[0];
3267
3268 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3269 if ( fSvmEnabled
3270 && pVM->cpum.ro.GuestFeatures.fSvm)
3271 {
3272 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3273 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3274 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3275 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3276 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3277 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3278 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3279 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3280 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3281 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3282 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3283 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3284 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3285 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3286 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3287 }
3288 else
3289 {
3290 if (!fSvmEnabled)
3291 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3292 else
3293 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3294 }
3295}
3296
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