HM.cpp@ 87491

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1	/* $Id: HM.cpp 87491 2021-01-30 01:15:50Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/mm.h>
44	#include <VBox/vmm/em.h>
45	#include <VBox/vmm/pdmapi.h>
46	#include <VBox/vmm/pgm.h>
47	#include <VBox/vmm/ssm.h>
48	#include <VBox/vmm/gim.h>
49	#include <VBox/vmm/trpm.h>
50	#include <VBox/vmm/dbgf.h>
51	#include <VBox/vmm/iom.h>
52	#include <VBox/vmm/iem.h>
53	#include <VBox/vmm/selm.h>
54	#include <VBox/vmm/nem.h>
55	#include <VBox/vmm/hm_vmx.h>
56	#include <VBox/vmm/hm_svm.h>
57	#include "HMInternal.h"
58	#include <VBox/vmm/vmcc.h>
59	#include <VBox/err.h>
60	#include <VBox/param.h>
61
62	#include <iprt/assert.h>
63	#include <VBox/log.h>
64	#include <iprt/asm.h>
65	#include <iprt/asm-amd64-x86.h>
66	#include <iprt/env.h>
67	#include <iprt/thread.h>
68
69
70	/*********************************************************************************************************************************
71	* Defined Constants And Macros *
72	*********************************************************************************************************************************/
73	/** @def HMVMX_REPORT_FEAT
74	* Reports VT-x feature to the release log.
75	*
76	* @param a_uAllowed1 Mask of allowed-1 feature bits.
77	* @param a_uAllowed0 Mask of allowed-0 feature bits.
78	* @param a_StrDesc The description string to report.
79	* @param a_Featflag Mask of the feature to report.
80	*/
81	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
82	do { \
83	if ((a_uAllowed1) & (a_Featflag)) \
84	{ \
85	if ((a_uAllowed0) & (a_Featflag)) \
86	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
87	else \
88	LogRel(("HM: " a_StrDesc "\n")); \
89	} \
90	else \
91	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
92	} while (0)
93
94	/** @def HMVMX_REPORT_ALLOWED_FEAT
95	* Reports an allowed VT-x feature to the release log.
96	*
97	* @param a_uAllowed1 Mask of allowed-1 feature bits.
98	* @param a_StrDesc The description string to report.
99	* @param a_FeatFlag Mask of the feature to report.
100	*/
101	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
102	do { \
103	if ((a_uAllowed1) & (a_FeatFlag)) \
104	LogRel(("HM: " a_StrDesc "\n")); \
105	else \
106	LogRel(("HM: " a_StrDesc " not supported\n")); \
107	} while (0)
108
109	/** @def HMVMX_REPORT_MSR_CAP
110	* Reports MSR feature capability.
111	*
112	* @param a_MsrCaps Mask of MSR feature bits.
113	* @param a_StrDesc The description string to report.
114	* @param a_fCap Mask of the feature to report.
115	*/
116	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
117	do { \
118	if ((a_MsrCaps) & (a_fCap)) \
119	LogRel(("HM: " a_StrDesc "\n")); \
120	} while (0)
121
122	/** @def HMVMX_LOGREL_FEAT
123	* Dumps a feature flag from a bitmap of features to the release log.
124	*
125	* @param a_fVal The value of all the features.
126	* @param a_fMask The specific bitmask of the feature.
127	*/
128	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
129	do { \
130	if ((a_fVal) & (a_fMask)) \
131	LogRel(("HM: %s\n", #a_fMask)); \
132	} while (0)
133
134
135	/*********************************************************************************************************************************
136	* Internal Functions *
137	*********************************************************************************************************************************/
138	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
139	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
140	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static int hmR3InitFinalizeR3(PVM pVM);
145	static int hmR3InitFinalizeR0(PVM pVM);
146	static int hmR3InitFinalizeR0Intel(PVM pVM);
147	static int hmR3InitFinalizeR0Amd(PVM pVM);
148	static int hmR3TermCPU(PVM pVM);
149
150
151	#ifdef VBOX_WITH_STATISTICS
152	/**
153	* Returns the name of the hardware exception.
154	*
155	* @returns The name of the hardware exception.
156	* @param uVector The exception vector.
157	*/
158	static const char *hmR3GetXcptName(uint8_t uVector)
159	{
160	switch (uVector)
161	{
162	case X86_XCPT_DE: return "#DE";
163	case X86_XCPT_DB: return "#DB";
164	case X86_XCPT_NMI: return "#NMI";
165	case X86_XCPT_BP: return "#BP";
166	case X86_XCPT_OF: return "#OF";
167	case X86_XCPT_BR: return "#BR";
168	case X86_XCPT_UD: return "#UD";
169	case X86_XCPT_NM: return "#NM";
170	case X86_XCPT_DF: return "#DF";
171	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
172	case X86_XCPT_TS: return "#TS";
173	case X86_XCPT_NP: return "#NP";
174	case X86_XCPT_SS: return "#SS";
175	case X86_XCPT_GP: return "#GP";
176	case X86_XCPT_PF: return "#PF";
177	case X86_XCPT_MF: return "#MF";
178	case X86_XCPT_AC: return "#AC";
179	case X86_XCPT_MC: return "#MC";
180	case X86_XCPT_XF: return "#XF";
181	case X86_XCPT_VE: return "#VE";
182	case X86_XCPT_CP: return "#CP";
183	case X86_XCPT_VC: return "#VC";
184	case X86_XCPT_SX: return "#SX";
185	}
186	return "Reserved";
187	}
188	#endif /* VBOX_WITH_STATISTICS */
189
190
191	/**
192	* Initializes the HM.
193	*
194	* This is the very first component to really do init after CFGM so that we can
195	* establish the predominant execution engine for the VM prior to initializing
196	* other modules. It takes care of NEM initialization if needed (HM disabled or
197	* not available in HW).
198	*
199	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
200	* hypervisor API via NEM, and then back on raw-mode if that isn't available
201	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
202	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
203	* X, OS/2 and others).
204	*
205	* Note that a lot of the set up work is done in ring-0 and thus postponed till
206	* the ring-3 and ring-0 callback to HMR3InitCompleted.
207	*
208	* @returns VBox status code.
209	* @param pVM The cross context VM structure.
210	*
211	* @remarks Be careful with what we call here, since most of the VMM components
212	* are uninitialized.
213	*/
214	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
215	{
216	LogFlowFunc(("\n"));
217
218	/*
219	* Assert alignment and sizes.
220	*/
221	AssertCompileMemberAlignment(VM, hm.s, 32);
222	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
223
224	/*
225	* Register the saved state data unit.
226	*/
227	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
228	NULL, NULL, NULL,
229	NULL, hmR3Save, NULL,
230	NULL, hmR3Load, NULL);
231	if (RT_FAILURE(rc))
232	return rc;
233
234	/*
235	* Register info handlers.
236	*/
237	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
238	AssertRCReturn(rc, rc);
239
240	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
241	DBGFINFO_FLAGS_ALL_EMTS);
242	AssertRCReturn(rc, rc);
243
244	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
245	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
246	AssertRCReturn(rc, rc);
247
248	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
249	AssertRCReturn(rc, rc);
250
251	/*
252	* Read configuration.
253	*/
254	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
255
256	/*
257	* Validate the HM settings.
258	*/
259	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
260	"HMForced" /* implied 'true' these days */
261	"\|UseNEMInstead"
262	"\|FallbackToNEM"
263	"\|EnableNestedPaging"
264	"\|EnableUX"
265	"\|EnableLargePages"
266	"\|EnableVPID"
267	"\|IBPBOnVMExit"
268	"\|IBPBOnVMEntry"
269	"\|SpecCtrlByHost"
270	"\|L1DFlushOnSched"
271	"\|L1DFlushOnVMEntry"
272	"\|MDSClearOnSched"
273	"\|MDSClearOnVMEntry"
274	"\|TPRPatchingEnabled"
275	"\|64bitEnabled"
276	"\|Exclusive"
277	"\|MaxResumeLoops"
278	"\|VmxPleGap"
279	"\|VmxPleWindow"
280	"\|VmxLbr"
281	"\|UseVmxPreemptTimer"
282	"\|SvmPauseFilter"
283	"\|SvmPauseFilterThreshold"
284	"\|SvmVirtVmsaveVmload"
285	"\|SvmVGif"
286	"\|LovelyMesaDrvWorkaround",
287	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
288	if (RT_FAILURE(rc))
289	return rc;
290
291	/** @cfgm{/HM/HMForced, bool, false}
292	* Forces hardware virtualization, no falling back on raw-mode. HM must be
293	* enabled, i.e. /HMEnabled must be true. */
294	bool fHMForced;
295	AssertRelease(pVM->fHMEnabled);
296	fHMForced = true;
297
298	/** @cfgm{/HM/UseNEMInstead, bool, true}
299	* Don't use HM, use NEM instead. */
300	bool fUseNEMInstead = false;
301	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
302	AssertRCReturn(rc, rc);
303	if (fUseNEMInstead && pVM->fHMEnabled)
304	{
305	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
306	pVM->fHMEnabled = false;
307	}
308
309	/** @cfgm{/HM/FallbackToNEM, bool, true}
310	* Enables fallback on NEM. */
311	bool fFallbackToNEM = true;
312	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
313	AssertRCReturn(rc, rc);
314
315	/** @cfgm{/HM/EnableNestedPaging, bool, false}
316	* Enables nested paging (aka extended page tables). */
317	bool fAllowNestedPaging = false;
318	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
319	AssertRCReturn(rc, rc);
320
321	/** @cfgm{/HM/EnableUX, bool, true}
322	* Enables the VT-x unrestricted execution feature. */
323	bool fAllowUnrestricted = true;
324	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
325	AssertRCReturn(rc, rc);
326
327	/** @cfgm{/HM/EnableLargePages, bool, false}
328	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
329	* page table walking and maybe better TLB hit rate in some cases. */
330	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
331	AssertRCReturn(rc, rc);
332
333	/** @cfgm{/HM/EnableVPID, bool, false}
334	* Enables the VT-x VPID feature. */
335	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
336	AssertRCReturn(rc, rc);
337
338	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
339	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
340	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
341	AssertRCReturn(rc, rc);
342
343	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
344	* Enables AMD64 cpu features.
345	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
346	* already have the support. */
347	#ifdef VBOX_WITH_64_BITS_GUESTS
348	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
349	AssertLogRelRCReturn(rc, rc);
350	#else
351	pVM->hm.s.fAllow64BitGuests = false;
352	#endif
353
354	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
355	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
356	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
357	* latest PAUSE instruction to be start of a new PAUSE loop.
358	*/
359	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
360	AssertRCReturn(rc, rc);
361
362	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
363	* The pause-filter exiting window in TSC ticks. When the number of ticks
364	* between the current PAUSE instruction and first PAUSE of a loop exceeds
365	* VmxPleWindow, a VM-exit is triggered.
366	*
367	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/VmxLbr, bool, false}
373	* Whether to enable LBR for the guest. This is disabled by default as it's only
374	* useful while debugging and enabling it causes a noticeable performance hit. */
375	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbr, false);
376	AssertRCReturn(rc, rc);
377
378	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
379	* A counter that is decrement each time a PAUSE instruction is executed by the
380	* guest. When the counter is 0, a \#VMEXIT is triggered.
381	*
382	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
383	*/
384	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
385	AssertRCReturn(rc, rc);
386
387	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
388	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
389	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
390	* PauseFilter count is reset to its initial value. However, if PAUSE is
391	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
392	* be triggered.
393	*
394	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
395	* activated.
396	*/
397	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
398	AssertRCReturn(rc, rc);
399
400	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
401	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
402	* available. */
403	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
404	AssertRCReturn(rc, rc);
405
406	/** @cfgm{/HM/SvmVGif, bool, true}
407	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
408	* if it's available. */
409	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
410	AssertRCReturn(rc, rc);
411
412	/** @cfgm{/HM/SvmLbrVirt, bool, false}
413	* Whether to make use of the LBR virtualization feature of the CPU if it's
414	* available. This is disabled by default as it's only useful while debugging
415	* and enabling it causes a small hit to performance. */
416	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
417	AssertRCReturn(rc, rc);
418
419	/** @cfgm{/HM/Exclusive, bool}
420	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
421	* global init for each host CPU. If false, we do local init each time we wish
422	* to execute guest code.
423	*
424	* On Windows, default is false due to the higher risk of conflicts with other
425	* hypervisors.
426	*
427	* On Mac OS X, this setting is ignored since the code does not handle local
428	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
429	*/
430	#if defined(RT_OS_DARWIN)
431	pVM->hm.s.fGlobalInit = true;
432	#else
433	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
434	# if defined(RT_OS_WINDOWS)
435	false
436	# else
437	true
438	# endif
439	);
440	AssertLogRelRCReturn(rc, rc);
441	#endif
442
443	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
444	* The number of times to resume guest execution before we forcibly return to
445	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
446	* determines the default value. */
447	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
448	AssertLogRelRCReturn(rc, rc);
449
450	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
451	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
452	* available. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/IBPBOnVMExit, bool}
457	* Costly paranoia setting. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/** @cfgm{/HM/IBPBOnVMEntry, bool}
462	* Costly paranoia setting. */
463	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
464	AssertLogRelRCReturn(rc, rc);
465
466	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
467	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
468	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
469	AssertLogRelRCReturn(rc, rc);
470
471	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
472	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
474	AssertLogRelRCReturn(rc, rc);
475
476	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
477	if (pVM->hm.s.fL1dFlushOnVmEntry)
478	pVM->hm.s.fL1dFlushOnSched = false;
479
480	/** @cfgm{/HM/SpecCtrlByHost, bool}
481	* Another expensive paranoia setting. */
482	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
483	AssertLogRelRCReturn(rc, rc);
484
485	/** @cfgm{/HM/MDSClearOnSched, bool, true}
486	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
487	* ignored on CPUs that aren't affected. */
488	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
489	AssertLogRelRCReturn(rc, rc);
490
491	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
492	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
493	* ignored on CPUs that aren't affected. */
494	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
495	AssertLogRelRCReturn(rc, rc);
496
497	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
498	if (pVM->hm.s.fMdsClearOnVmEntry)
499	pVM->hm.s.fMdsClearOnSched = false;
500
501	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
502	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
503	* the hypervisor it is running under. */
504	bool f;
505	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
506	AssertLogRelRCReturn(rc, rc);
507	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
508	{
509	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
510	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = f;
511	}
512
513	/*
514	* Check if VT-x or AMD-v support according to the users wishes.
515	*/
516	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
517	* VERR_SVM_IN_USE. */
518	if (pVM->fHMEnabled)
519	{
520	uint32_t fCaps;
521	rc = SUPR3QueryVTCaps(&fCaps);
522	if (RT_SUCCESS(rc))
523	{
524	if (fCaps & SUPVTCAPS_AMD_V)
525	{
526	pVM->hm.s.svm.fSupported = true;
527	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
528	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
529	}
530	else if (fCaps & SUPVTCAPS_VT_X)
531	{
532	const char *pszWhy;
533	rc = SUPR3QueryVTxSupported(&pszWhy);
534	if (RT_SUCCESS(rc))
535	{
536	pVM->hm.s.vmx.fSupported = true;
537	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
538	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
539	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
540	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
541	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
542	}
543	else
544	{
545	/*
546	* Before failing, try fallback to NEM if we're allowed to do that.
547	*/
548	pVM->fHMEnabled = false;
549	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
550	if (fFallbackToNEM)
551	{
552	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
553	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
554
555	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
556	if ( RT_SUCCESS(rc2)
557	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
558	rc = VINF_SUCCESS;
559	}
560	if (RT_FAILURE(rc))
561	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
562	}
563	}
564	else
565	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
566	VERR_INTERNAL_ERROR_5);
567
568	/*
569	* Disable nested paging and unrestricted guest execution now if they're
570	* configured so that CPUM can make decisions based on our configuration.
571	*/
572	if ( fAllowNestedPaging
573	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
574	{
575	pVM->hm.s.fNestedPaging = true;
576	if (fCaps & SUPVTCAPS_VT_X)
577	{
578	if ( fAllowUnrestricted
579	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
580	pVM->hm.s.vmx.fUnrestrictedGuest = true;
581	else
582	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
583	}
584	}
585	else
586	Assert(!pVM->hm.s.fNestedPaging);
587	}
588	else
589	{
590	const char *pszMsg;
591	switch (rc)
592	{
593	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
594	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
595	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
596	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
597	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
598	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
599	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
600	default:
601	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
602	}
603
604	/*
605	* Before failing, try fallback to NEM if we're allowed to do that.
606	*/
607	pVM->fHMEnabled = false;
608	if (fFallbackToNEM)
609	{
610	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
611	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
612	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
613	if ( RT_SUCCESS(rc2)
614	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
615	rc = VINF_SUCCESS;
616	}
617	if (RT_FAILURE(rc))
618	return VM_SET_ERROR(pVM, rc, pszMsg);
619	}
620	}
621	else
622	{
623	/*
624	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
625	*/
626	if (fUseNEMInstead)
627	{
628	rc = NEMR3Init(pVM, false /fFallback/, true);
629	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
630	if (RT_FAILURE(rc))
631	return rc;
632	}
633	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
634	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
635	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
636	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
637	}
638
639	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
640	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
641	return VINF_SUCCESS;
642	}
643
644
645	/**
646	* Initializes HM components after ring-3 phase has been fully initialized.
647	*
648	* @returns VBox status code.
649	* @param pVM The cross context VM structure.
650	*/
651	static int hmR3InitFinalizeR3(PVM pVM)
652	{
653	LogFlowFunc(("\n"));
654
655	if (!HMIsEnabled(pVM))
656	return VINF_SUCCESS;
657
658	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
659	{
660	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
661	pVCpu->hm.s.fActive = false;
662	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
663	}
664
665	#ifdef VBOX_WITH_STATISTICS
666	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
667	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
668	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
669	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
670	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
671	#endif
672
673	/*
674	* Statistics.
675	*/
676	#ifdef VBOX_WITH_STATISTICS
677	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
678	#endif
679	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
680	{
681	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
682	PHMCPU pHmCpu = &pVCpu->hm.s;
683	int rc;
684
685	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
686	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
687	AssertRC(rc); \
688	} while (0)
689	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
690	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
691
692	#ifdef VBOX_WITH_STATISTICS
693
694	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
695	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
696	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
697	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
698	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
699	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
700	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
701	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
702	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
703	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
704	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
705	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
706	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
707	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
708	# ifdef HM_PROFILE_EXIT_DISPATCH
709	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
710	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
711	# endif
712	#endif
713	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
714
715	#ifdef VBOX_WITH_STATISTICS
716	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
717	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
718	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
719	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
720	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
721	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
722	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
723	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
724	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
725	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
726	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
727	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
728	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
729	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
730	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
731	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
732	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
733	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
734	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
735	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
736	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
737	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
738	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
739	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
740	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
741	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
742	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
743	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
744	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
745	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
746	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
747	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
748	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
749	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
750	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
751	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
752	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
753	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
754	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
755	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
756	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
757	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
758	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
759	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
760	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
761	#endif
762	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
763	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
764	#ifdef VBOX_WITH_STATISTICS
765	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
766	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
767	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
768	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
769
770	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
771	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
772	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
773	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
774	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
775	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
776	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
777	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
778	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
779	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
780	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
781	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
782	#endif
783	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
784	#ifdef VBOX_WITH_STATISTICS
785	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
786
787	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
788	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
789	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
790	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
791	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
792	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
793
794	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
795	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
796	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
797	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
798	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
799	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
800	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
801	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
802	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
803	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
804	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
805	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
806	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
807	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
808	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
809
810	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
811	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
812	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
813
814	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
815	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
816	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
817
818	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
819	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
820	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
821	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
822
823	if (fCpuSupportsVmx)
824	{
825	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
826	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
827	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VMLAUNCH instructions.");
828	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VMRESUME instructions.");
829	}
830
831	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
832	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
833	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
834
835	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
836	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
837	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
838
839	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
840	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
841	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
842	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
843
844	/*
845	* Guest Exit reason stats.
846	*/
847	pHmCpu->paStatExitReason = NULL;
848	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
849	(void **)&pHmCpu->paStatExitReason);
850	AssertRCReturn(rc, rc);
851
852	if (fCpuSupportsVmx)
853	{
854	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
855	{
856	const char *pszExitName = HMGetVmxExitName(j);
857	if (pszExitName)
858	{
859	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
860	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
861	AssertRCReturn(rc, rc);
862	}
863	}
864	}
865	else
866	{
867	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
868	{
869	const char *pszExitName = HMGetSvmExitName(j);
870	if (pszExitName)
871	{
872	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
873	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
874	AssertRC(rc);
875	}
876	}
877	}
878	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
879
880	pHmCpu->paStatExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatExitReason);
881	Assert(pHmCpu->paStatExitReasonR0 != NIL_RTR0PTR);
882
883	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
884	/*
885	* Nested-guest VM-exit reason stats.
886	*/
887	pHmCpu->paStatNestedExitReason = NULL;
888	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pHmCpu->paStatNestedExitReason), 0 / uAlignment */, MM_TAG_HM,
889	(void **)&pHmCpu->paStatNestedExitReason);
890	AssertRCReturn(rc, rc);
891	if (fCpuSupportsVmx)
892	{
893	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
894	{
895	const char *pszExitName = HMGetVmxExitName(j);
896	if (pszExitName)
897	{
898	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
899	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
900	AssertRC(rc);
901	}
902	}
903	}
904	else
905	{
906	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
907	{
908	const char *pszExitName = HMGetSvmExitName(j);
909	if (pszExitName)
910	{
911	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
912	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
913	AssertRC(rc);
914	}
915	}
916	}
917	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
918	pHmCpu->paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatNestedExitReason);
919	Assert(pHmCpu->paStatNestedExitReasonR0 != NIL_RTR0PTR);
920	#endif
921
922	/*
923	* Injected interrupts stats.
924	*/
925	{
926	uint32_t const cInterrupts = 0xff + 1;
927	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cInterrupts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedIrqs);
928	AssertRCReturn(rc, rc);
929	pHmCpu->paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedIrqs);
930	Assert(pHmCpu->paStatInjectedIrqsR0 != NIL_RTR0PTR);
931	for (unsigned j = 0; j < cInterrupts; j++)
932	{
933	char aszIntrName[64];
934	RTStrPrintf(&aszIntrName[0], sizeof(aszIntrName), "Interrupt %u", j);
935	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
936	STAMUNIT_OCCURENCES, aszIntrName,
937	"/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
938	AssertRC(rc);
939	}
940	}
941
942	/*
943	* Injected exception stats.
944	*/
945	{
946	uint32_t const cXcpts = X86_XCPT_LAST + 1;
947	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * cXcpts, 8, MM_TAG_HM, (void **)&pHmCpu->paStatInjectedXcpts);
948	AssertRCReturn(rc, rc);
949	pHmCpu->paStatInjectedXcptsR0 = MMHyperR3ToR0(pVM, pHmCpu->paStatInjectedXcpts);
950	Assert(pHmCpu->paStatInjectedXcptsR0 != NIL_RTR0PTR);
951	for (unsigned j = 0; j < cXcpts; j++)
952	{
953	char aszXcptName[64];
954	RTStrPrintf(&aszXcptName[0], sizeof(aszXcptName), "%s exception", hmR3GetXcptName(j));
955	rc = STAMR3RegisterF(pVM, &pHmCpu->paStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
956	STAMUNIT_OCCURENCES, aszXcptName,
957	"/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
958	AssertRC(rc);
959	}
960	}
961
962	#endif /* VBOX_WITH_STATISTICS */
963	#undef HM_REG_COUNTER
964	#undef HM_REG_PROFILE
965	#undef HM_REG_STAT
966	}
967
968	return VINF_SUCCESS;
969	}
970
971
972	/**
973	* Called when a init phase has completed.
974	*
975	* @returns VBox status code.
976	* @param pVM The cross context VM structure.
977	* @param enmWhat The phase that completed.
978	*/
979	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
980	{
981	switch (enmWhat)
982	{
983	case VMINITCOMPLETED_RING3:
984	return hmR3InitFinalizeR3(pVM);
985	case VMINITCOMPLETED_RING0:
986	return hmR3InitFinalizeR0(pVM);
987	default:
988	return VINF_SUCCESS;
989	}
990	}
991
992
993	/**
994	* Turns off normal raw mode features.
995	*
996	* @param pVM The cross context VM structure.
997	*/
998	static void hmR3DisableRawMode(PVM pVM)
999	{
1000	/** @todo r=bird: HM shouldn't be doing this crap. */
1001	/* Reinit the paging mode to force the new shadow mode. */
1002	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1003	{
1004	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1005	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1006	}
1007	}
1008
1009
1010	/**
1011	* Initialize VT-x or AMD-V.
1012	*
1013	* @returns VBox status code.
1014	* @param pVM The cross context VM structure.
1015	*/
1016	static int hmR3InitFinalizeR0(PVM pVM)
1017	{
1018	int rc;
1019
1020	if (!HMIsEnabled(pVM))
1021	return VINF_SUCCESS;
1022
1023	/*
1024	* Hack to allow users to work around broken BIOSes that incorrectly set
1025	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1026	*/
1027	if ( !pVM->hm.s.vmx.fSupported
1028	&& !pVM->hm.s.svm.fSupported
1029	&& pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1030	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1031	{
1032	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1033	pVM->hm.s.svm.fSupported = true;
1034	pVM->hm.s.svm.fIgnoreInUseError = true;
1035	pVM->hm.s.rcInit = VINF_SUCCESS;
1036	}
1037
1038	/*
1039	* Report ring-0 init errors.
1040	*/
1041	if ( !pVM->hm.s.vmx.fSupported
1042	&& !pVM->hm.s.svm.fSupported)
1043	{
1044	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1045	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1046	switch (pVM->hm.s.rcInit)
1047	{
1048	case VERR_VMX_IN_VMX_ROOT_MODE:
1049	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1050	case VERR_VMX_NO_VMX:
1051	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1052	case VERR_VMX_MSR_VMX_DISABLED:
1053	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1054	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1055	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1056	case VERR_VMX_MSR_LOCKING_FAILED:
1057	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1058	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1059	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1060	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1061	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1062
1063	case VERR_SVM_IN_USE:
1064	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1065	case VERR_SVM_NO_SVM:
1066	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1067	case VERR_SVM_DISABLED:
1068	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1069	}
1070	return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1071	}
1072
1073	/*
1074	* Enable VT-x or AMD-V on all host CPUs.
1075	*/
1076	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1077	if (RT_FAILURE(rc))
1078	{
1079	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1080	HMR3CheckError(pVM, rc);
1081	return rc;
1082	}
1083
1084	/*
1085	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1086	* (Main should have taken care of this already)
1087	*/
1088	if (!PDMHasIoApic(pVM))
1089	{
1090	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1091	pVM->hm.s.fTprPatchingAllowed = false;
1092	}
1093
1094	/*
1095	* Check if L1D flush is needed/possible.
1096	*/
1097	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
1098	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1099	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
1100	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
1101	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
1102	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
1103
1104	/*
1105	* Check if MDS flush is needed/possible.
1106	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
1107	*/
1108	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
1109	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
1110	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1111	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
1112	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
1113	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
1114	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
1115	{
1116	if (!pVM->hm.s.fMdsClearOnSched)
1117	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
1118	pVM->hm.s.fMdsClearOnVmEntry = false;
1119	}
1120	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
1121	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
1122	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
1123
1124	/*
1125	* Sync options.
1126	*/
1127	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1128	* That will require a little bit of work, of course. */
1129	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1130	{
1131	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1132	PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1133	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1134	if (pVM->cpum.ro.HostFeatures.fIbpb)
1135	{
1136	if (pVM->hm.s.fIbpbOnVmExit)
1137	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1138	if (pVM->hm.s.fIbpbOnVmEntry)
1139	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1140	}
1141	if (pVM->cpum.ro.HostFeatures.fFlushCmd && pVM->hm.s.fL1dFlushOnVmEntry)
1142	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_L1D_ENTRY;
1143	if (pVM->cpum.ro.HostFeatures.fMdsClear && pVM->hm.s.fMdsClearOnVmEntry)
1144	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_MDS_ENTRY;
1145	if (idCpu == 0)
1146	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1147	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1148	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1149	}
1150
1151	/*
1152	* Do the vendor specific initialization
1153	*
1154	* Note! We disable release log buffering here since we're doing relatively
1155	* lot of logging and doesn't want to hit the disk with each LogRel
1156	* statement.
1157	*/
1158	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1159	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1160	if (pVM->hm.s.vmx.fSupported)
1161	rc = hmR3InitFinalizeR0Intel(pVM);
1162	else
1163	rc = hmR3InitFinalizeR0Amd(pVM);
1164	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1165	: "HM: VT-x/AMD-V init method: Local\n"));
1166	RTLogRelSetBuffering(fOldBuffered);
1167	pVM->hm.s.fInitialized = true;
1168
1169	return rc;
1170	}
1171
1172
1173	/**
1174	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1175	*/
1176	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1177	{
1178	NOREF(pVM);
1179	NOREF(pvAllocation);
1180	NOREF(GCPhysAllocation);
1181	}
1182
1183
1184	/**
1185	* Returns a description of the VMCS (and associated regions') memory type given the
1186	* IA32_VMX_BASIC MSR.
1187	*
1188	* @returns The descriptive memory type.
1189	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1190	*/
1191	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1192	{
1193	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1194	switch (uMemType)
1195	{
1196	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1197	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1198	}
1199	return "Unknown";
1200	}
1201
1202
1203	/**
1204	* Returns a single-line description of all the activity-states supported by the CPU
1205	* given the IA32_VMX_MISC MSR.
1206	*
1207	* @returns All supported activity states.
1208	* @param uMsrMisc IA32_VMX_MISC MSR value.
1209	*/
1210	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1211	{
1212	static const char * const s_apszActStates[] =
1213	{
1214	"",
1215	" ( HLT )",
1216	" ( SHUTDOWN )",
1217	" ( HLT SHUTDOWN )",
1218	" ( SIPI_WAIT )",
1219	" ( HLT SIPI_WAIT )",
1220	" ( SHUTDOWN SIPI_WAIT )",
1221	" ( HLT SHUTDOWN SIPI_WAIT )"
1222	};
1223	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1224	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1225	return s_apszActStates[idxActStates];
1226	}
1227
1228
1229	/**
1230	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1231	*
1232	* @param fFeatMsr The feature control MSR value.
1233	*/
1234	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1235	{
1236	uint64_t const val = fFeatMsr;
1237	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1238	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1239	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1240	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1241	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1242	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1243	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1244	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1245	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1246	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1247	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1248	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1249	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1250	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1251	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1252	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1253	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1254	}
1255
1256
1257	/**
1258	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1259	*
1260	* @param uBasicMsr The VMX basic MSR value.
1261	*/
1262	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1263	{
1264	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1265	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1266	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1267	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1268	"< 4 GB" : "None"));
1269	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1270	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1271	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1272	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1273	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1274	}
1275
1276
1277	/**
1278	* Reports MSR_IA32_PINBASED_CTLS to the log.
1279	*
1280	* @param pVmxMsr Pointer to the VMX MSR.
1281	*/
1282	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1283	{
1284	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1285	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1286	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1287	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1288	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1289	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1290	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1291	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1292	}
1293
1294
1295	/**
1296	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1297	*
1298	* @param pVmxMsr Pointer to the VMX MSR.
1299	*/
1300	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1301	{
1302	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1303	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1304	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1316	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1317	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1318	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1320	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1321	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1322	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1323	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1324	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1326	}
1327
1328
1329	/**
1330	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1331	*
1332	* @param pVmxMsr Pointer to the VMX MSR.
1333	*/
1334	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1335	{
1336	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1337	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1338	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1351	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1352	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1353	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1354	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1355	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1357	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1358	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1359	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1360	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1361	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPPTP_EPT", VMX_PROC_CTLS2_SPPTP_EPT);
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1366	}
1367
1368
1369	/**
1370	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1371	*
1372	* @param pVmxMsr Pointer to the VMX MSR.
1373	*/
1374	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1375	{
1376	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1377	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1378	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1389	}
1390
1391
1392	/**
1393	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1394	*
1395	* @param pVmxMsr Pointer to the VMX MSR.
1396	*/
1397	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1398	{
1399	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1400	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1401	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1409	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1410	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1411	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1412	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1413	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1414	}
1415
1416
1417	/**
1418	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1419	*
1420	* @param fCaps The VMX EPT/VPID capability MSR value.
1421	*/
1422	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1423	{
1424	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1425	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1431	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1432	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1433	HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1434	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT);
1435	HMVMX_REPORT_MSR_CAP(fCaps, "SSS", MSR_IA32_VMX_EPT_VPID_CAP_SSS);
1436	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1437	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1438	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1439	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1440	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1441	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1442	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1443	}
1444
1445
1446	/**
1447	* Reports MSR_IA32_VMX_MISC MSR to the log.
1448	*
1449	* @param pVM Pointer to the VM.
1450	* @param fMisc The VMX misc. MSR value.
1451	*/
1452	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1453	{
1454	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1455	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1456	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1457	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1458	else
1459	{
1460	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1461	pVM->hm.s.vmx.cPreemptTimerShift));
1462	}
1463	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1464	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1465	hmR3VmxGetActivityStateAllDesc(fMisc)));
1466	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1467	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1468	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1469	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1470	VMX_MISC_MAX_MSRS(fMisc)));
1471	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1472	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1473	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1474	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1475	}
1476
1477
1478	/**
1479	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1480	*
1481	* @param uVmcsEnum The VMX VMCS enum MSR value.
1482	*/
1483	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1484	{
1485	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1486	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1487	}
1488
1489
1490	/**
1491	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1492	*
1493	* @param uVmFunc The VMX VMFUNC MSR value.
1494	*/
1495	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1496	{
1497	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1498	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1499	}
1500
1501
1502	/**
1503	* Reports VMX CR0, CR4 fixed MSRs.
1504	*
1505	* @param pMsrs Pointer to the VMX MSRs.
1506	*/
1507	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1508	{
1509	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1510	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1511	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1512	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1513	}
1514
1515
1516	/**
1517	* Finish VT-x initialization (after ring-0 init).
1518	*
1519	* @returns VBox status code.
1520	* @param pVM The cross context VM structure.
1521	*/
1522	static int hmR3InitFinalizeR0Intel(PVM pVM)
1523	{
1524	int rc;
1525
1526	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1527	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1528
1529	LogRel(("HM: Using VT-x implementation 3.0\n"));
1530	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1531	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1532	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostMsrEfer));
1533	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1534
1535	hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1536	hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1537
1538	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1539	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1540	if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1541	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1542
1543	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1544	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1545
1546	if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1547	{
1548	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1549	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1550	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1551	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1552	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1553	}
1554
1555	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1556	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1557	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1558	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1559	if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1560	hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1561	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1562
1563	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1564	#ifdef TODO_9217_VMCSINFO
1565	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1566	{
1567	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1568	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1569	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1570	}
1571	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1572	if (pVM->cpum.ro.GuestFeatures.fVmx)
1573	{
1574	LogRel(("HM: Nested-guest:\n"));
1575	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1576	{
1577	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1578	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1579	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1580	}
1581	}
1582	#endif
1583	#endif /* TODO_9217_VMCSINFO */
1584
1585	/*
1586	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1587	*/
1588	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1589	\|\| (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1590	VERR_HM_IPE_1);
1591	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1592	\|\| ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1593	&& pVM->hm.s.fNestedPaging),
1594	VERR_HM_IPE_1);
1595
1596	/*
1597	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1598	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1599	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1600	*/
1601	if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1602	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1603	{
1604	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1605	LogRel(("HM: Disabled RDTSCP\n"));
1606	}
1607
1608	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1609	{
1610	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1611	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1612	if (RT_SUCCESS(rc))
1613	{
1614	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1615	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1616	esp. Figure 20-5.*/
1617	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1618	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1619
1620	/* Bit set to 0 means software interrupts are redirected to the
1621	8086 program interrupt handler rather than switching to
1622	protected-mode handler. */
1623	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1624
1625	/* Allow all port IO, so that port IO instructions do not cause
1626	exceptions and would instead cause a VM-exit (based on VT-x's
1627	IO bitmap which we currently configure to always cause an exit). */
1628	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1629	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1630
1631	/*
1632	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1633	* page table used in real and protected mode without paging with EPT.
1634	*/
1635	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1636	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1637	{
1638	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1639	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1640	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1641	\| X86_PDE4M_G;
1642	}
1643
1644	/* We convert it here every time as PCI regions could be reconfigured. */
1645	if (PDMVmmDevHeapIsEnabled(pVM))
1646	{
1647	RTGCPHYS GCPhys;
1648	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1649	AssertRCReturn(rc, rc);
1650	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1651
1652	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1653	AssertRCReturn(rc, rc);
1654	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1655	}
1656	}
1657	else
1658	{
1659	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1660	pVM->hm.s.vmx.pRealModeTSS = NULL;
1661	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1662	return VMSetError(pVM, rc, RT_SRC_POS,
1663	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1664	}
1665	}
1666
1667	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1668	: "HM: Guest support: 32-bit only\n"));
1669
1670	/*
1671	* Call ring-0 to set up the VM.
1672	*/
1673	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1674	if (rc != VINF_SUCCESS)
1675	{
1676	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1677	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1678	{
1679	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1680	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1681	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1682	}
1683	HMR3CheckError(pVM, rc);
1684	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1685	}
1686
1687	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1688	LogRel(("HM: Enabled VMX\n"));
1689	pVM->hm.s.vmx.fEnabled = true;
1690
1691	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1692
1693	/*
1694	* Change the CPU features.
1695	*/
1696	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1697	if (pVM->hm.s.fAllow64BitGuests)
1698	{
1699	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1700	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1701	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1702	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1703	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1704	}
1705	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1706	(we reuse the host EFER in the switcher). */
1707	/** @todo this needs to be fixed properly!! */
1708	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1709	{
1710	if (pVM->hm.s.vmx.u64HostMsrEfer & MSR_K6_EFER_NXE)
1711	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1712	else
1713	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1714	}
1715
1716	/*
1717	* Log configuration details.
1718	*/
1719	if (pVM->hm.s.fNestedPaging)
1720	{
1721	LogRel(("HM: Enabled nested paging\n"));
1722	if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1723	LogRel(("HM: EPT flush type = Single context\n"));
1724	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1725	LogRel(("HM: EPT flush type = All contexts\n"));
1726	else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1727	LogRel(("HM: EPT flush type = Not supported\n"));
1728	else
1729	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1730
1731	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1732	LogRel(("HM: Enabled unrestricted guest execution\n"));
1733
1734	if (pVM->hm.s.fLargePages)
1735	{
1736	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1737	PGMSetLargePageUsage(pVM, true);
1738	LogRel(("HM: Enabled large page support\n"));
1739	}
1740	}
1741	else
1742	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1743
1744	if (pVM->hm.s.vmx.fVpid)
1745	{
1746	LogRel(("HM: Enabled VPID\n"));
1747	if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1748	LogRel(("HM: VPID flush type = Individual addresses\n"));
1749	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1750	LogRel(("HM: VPID flush type = Single context\n"));
1751	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1752	LogRel(("HM: VPID flush type = All contexts\n"));
1753	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1754	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1755	else
1756	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1757	}
1758	else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1759	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1760
1761	if (pVM->hm.s.vmx.fUsePreemptTimer)
1762	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1763	else
1764	LogRel(("HM: Disabled VMX-preemption timer\n"));
1765
1766	if (pVM->hm.s.fVirtApicRegs)
1767	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1768
1769	if (pVM->hm.s.fPostedIntrs)
1770	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1771
1772	if (pVM->hm.s.vmx.fUseVmcsShadowing)
1773	{
1774	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1775	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1776	}
1777
1778	return VINF_SUCCESS;
1779	}
1780
1781
1782	/**
1783	* Finish AMD-V initialization (after ring-0 init).
1784	*
1785	* @returns VBox status code.
1786	* @param pVM The cross context VM structure.
1787	*/
1788	static int hmR3InitFinalizeR0Amd(PVM pVM)
1789	{
1790	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1791
1792	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1793
1794	uint32_t u32Family;
1795	uint32_t u32Model;
1796	uint32_t u32Stepping;
1797	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1798	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1799	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1800	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1801	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1802	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1803	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1804
1805	/*
1806	* Enumerate AMD-V features.
1807	*/
1808	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1809	{
1810	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1811	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1812	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1813	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1814	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1815	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1816	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1817	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1818	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1819	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1820	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1821	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1822	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1823	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1824	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1825	#undef HMSVM_REPORT_FEATURE
1826	};
1827
1828	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1829	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1830	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1831	{
1832	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1833	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1834	}
1835	if (fSvmFeatures)
1836	for (unsigned iBit = 0; iBit < 32; iBit++)
1837	if (RT_BIT_32(iBit) & fSvmFeatures)
1838	LogRel(("HM: Reserved bit %u\n", iBit));
1839
1840	/*
1841	* Nested paging is determined in HMR3Init, verify the sanity of that.
1842	*/
1843	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1844	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1845	VERR_HM_IPE_1);
1846
1847	#if 0
1848	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1849	* here. */
1850	if (RTR0IsPostIpiSupport())
1851	pVM->hm.s.fPostedIntrs = true;
1852	#endif
1853
1854	/*
1855	* Determine whether we need to intercept #UD in SVM mode for emulating
1856	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1857	* when executed in long-mode. This is only really applicable when
1858	* non-default CPU profiles are in effect, i.e. guest vendor differs
1859	* from the host one.
1860	*/
1861	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1862	switch (CPUMGetGuestCpuVendor(pVM))
1863	{
1864	case CPUMCPUVENDOR_INTEL:
1865	case CPUMCPUVENDOR_VIA: /?/
1866	case CPUMCPUVENDOR_SHANGHAI: /?/
1867	switch (CPUMGetHostCpuVendor(pVM))
1868	{
1869	case CPUMCPUVENDOR_AMD:
1870	case CPUMCPUVENDOR_HYGON:
1871	if (pVM->hm.s.fAllow64BitGuests)
1872	{
1873	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1874	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1875	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1876	}
1877	break;
1878	default: break;
1879	}
1880	default: break;
1881	}
1882
1883	/*
1884	* Call ring-0 to set up the VM.
1885	*/
1886	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1887	if (rc != VINF_SUCCESS)
1888	{
1889	AssertMsgFailed(("%Rrc\n", rc));
1890	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1891	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1892	}
1893
1894	LogRel(("HM: Enabled SVM\n"));
1895	pVM->hm.s.svm.fEnabled = true;
1896
1897	if (pVM->hm.s.fNestedPaging)
1898	{
1899	LogRel(("HM: Enabled nested paging\n"));
1900
1901	/*
1902	* Enable large pages (2 MB) if applicable.
1903	*/
1904	if (pVM->hm.s.fLargePages)
1905	{
1906	PGMSetLargePageUsage(pVM, true);
1907	LogRel(("HM: Enabled large page support\n"));
1908	}
1909	}
1910
1911	if (pVM->hm.s.fVirtApicRegs)
1912	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1913
1914	if (pVM->hm.s.fPostedIntrs)
1915	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1916
1917	hmR3DisableRawMode(pVM);
1918
1919	/*
1920	* Change the CPU features.
1921	*/
1922	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1923	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1924	if (pVM->hm.s.fAllow64BitGuests)
1925	{
1926	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1927	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1928	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1929	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1930	}
1931	/* Turn on NXE if PAE has been enabled. */
1932	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1933	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1934
1935	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1936	: "HM: Disabled TPR patching\n"));
1937
1938	LogRel((pVM->hm.s.fAllow64BitGuests ? "HM: Guest support: 32-bit and 64-bit\n"
1939	: "HM: Guest support: 32-bit only\n"));
1940	return VINF_SUCCESS;
1941	}
1942
1943
1944	/**
1945	* Applies relocations to data and code managed by this
1946	* component. This function will be called at init and
1947	* whenever the VMM need to relocate it self inside the GC.
1948	*
1949	* @param pVM The cross context VM structure.
1950	*/
1951	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1952	{
1953	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1954
1955	/* Fetch the current paging mode during the relocate callback during state loading. */
1956	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1957	{
1958	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1959	{
1960	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1961	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1962	}
1963	}
1964	}
1965
1966
1967	/**
1968	* Terminates the HM.
1969	*
1970	* Termination means cleaning up and freeing all resources,
1971	* the VM itself is, at this point, powered off or suspended.
1972	*
1973	* @returns VBox status code.
1974	* @param pVM The cross context VM structure.
1975	*/
1976	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1977	{
1978	if (pVM->hm.s.vmx.pRealModeTSS)
1979	{
1980	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1981	pVM->hm.s.vmx.pRealModeTSS = 0;
1982	}
1983	hmR3TermCPU(pVM);
1984	return 0;
1985	}
1986
1987
1988	/**
1989	* Terminates the per-VCPU HM.
1990	*
1991	* @returns VBox status code.
1992	* @param pVM The cross context VM structure.
1993	*/
1994	static int hmR3TermCPU(PVM pVM)
1995	{
1996	#ifdef VBOX_WITH_STATISTICS
1997	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1998	{
1999	PVMCPU pVCpu = pVM->apCpusR3[idCpu]; NOREF(pVCpu);
2000	if (pVCpu->hm.s.paStatExitReason)
2001	{
2002	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2003	pVCpu->hm.s.paStatExitReason = NULL;
2004	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2005	}
2006	if (pVCpu->hm.s.paStatInjectedIrqs)
2007	{
2008	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2009	pVCpu->hm.s.paStatInjectedIrqs = NULL;
2010	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2011	}
2012	if (pVCpu->hm.s.paStatInjectedXcpts)
2013	{
2014	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedXcpts);
2015	pVCpu->hm.s.paStatInjectedXcpts = NULL;
2016	pVCpu->hm.s.paStatInjectedXcptsR0 = NIL_RTR0PTR;
2017	}
2018	# if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
2019	if (pVCpu->hm.s.paStatNestedExitReason)
2020	{
2021	MMHyperFree(pVM, pVCpu->hm.s.paStatNestedExitReason);
2022	pVCpu->hm.s.paStatNestedExitReason = NULL;
2023	pVCpu->hm.s.paStatNestedExitReasonR0 = NIL_RTR0PTR;
2024	}
2025	# endif
2026	}
2027	#else
2028	RT_NOREF(pVM);
2029	#endif
2030	return VINF_SUCCESS;
2031	}
2032
2033
2034	/**
2035	* Resets a virtual CPU.
2036	*
2037	* Used by HMR3Reset and CPU hot plugging.
2038	*
2039	* @param pVCpu The cross context virtual CPU structure to reset.
2040	*/
2041	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2042	{
2043	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2044	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2045	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2046
2047	pVCpu->hm.s.fActive = false;
2048	pVCpu->hm.s.Event.fPending = false;
2049	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2050	pVCpu->hm.s.vmx.VmcsInfo.fSwitchedTo64on32Obsolete = false;
2051	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2052	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2053	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2054	{
2055	pVCpu->hm.s.vmx.VmcsInfoNstGst.fSwitchedTo64on32Obsolete = false;
2056	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2057	}
2058	#endif
2059	}
2060
2061
2062	/**
2063	* The VM is being reset.
2064	*
2065	* For the HM component this means that any GDT/LDT/TSS monitors
2066	* needs to be removed.
2067	*
2068	* @param pVM The cross context VM structure.
2069	*/
2070	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2071	{
2072	LogFlow(("HMR3Reset:\n"));
2073
2074	if (HMIsEnabled(pVM))
2075	hmR3DisableRawMode(pVM);
2076
2077	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2078	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2079
2080	/* Clear all patch information. */
2081	pVM->hm.s.pGuestPatchMem = 0;
2082	pVM->hm.s.pFreeGuestPatchMem = 0;
2083	pVM->hm.s.cbGuestPatchMem = 0;
2084	pVM->hm.s.cPatches = 0;
2085	pVM->hm.s.PatchTree = 0;
2086	pVM->hm.s.fTPRPatchingActive = false;
2087	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2088	}
2089
2090
2091	/**
2092	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2093	*
2094	* @returns VBox strict status code.
2095	* @param pVM The cross context VM structure.
2096	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2097	* @param pvUser Unused.
2098	*/
2099	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2100	{
2101	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2102
2103	/* Only execute the handler on the VCPU the original patch request was issued. */
2104	if (pVCpu->idCpu != idCpu)
2105	return VINF_SUCCESS;
2106
2107	Log(("hmR3RemovePatches\n"));
2108	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2109	{
2110	uint8_t abInstr[15];
2111	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2112	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2113	int rc;
2114
2115	#ifdef LOG_ENABLED
2116	char szOutput[256];
2117	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2118	szOutput, sizeof(szOutput), NULL);
2119	if (RT_SUCCESS(rc))
2120	Log(("Patched instr: %s\n", szOutput));
2121	#endif
2122
2123	/* Check if the instruction is still the same. */
2124	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2125	if (rc != VINF_SUCCESS)
2126	{
2127	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2128	continue; /* swapped out or otherwise removed; skip it. */
2129	}
2130
2131	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2132	{
2133	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2134	continue; /* skip it. */
2135	}
2136
2137	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2138	AssertRC(rc);
2139
2140	#ifdef LOG_ENABLED
2141	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2142	szOutput, sizeof(szOutput), NULL);
2143	if (RT_SUCCESS(rc))
2144	Log(("Original instr: %s\n", szOutput));
2145	#endif
2146	}
2147	pVM->hm.s.cPatches = 0;
2148	pVM->hm.s.PatchTree = 0;
2149	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2150	pVM->hm.s.fTPRPatchingActive = false;
2151	return VINF_SUCCESS;
2152	}
2153
2154
2155	/**
2156	* Worker for enabling patching in a VT-x/AMD-V guest.
2157	*
2158	* @returns VBox status code.
2159	* @param pVM The cross context VM structure.
2160	* @param idCpu VCPU to execute hmR3RemovePatches on.
2161	* @param pPatchMem Patch memory range.
2162	* @param cbPatchMem Size of the memory range.
2163	*/
2164	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2165	{
2166	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2167	AssertRC(rc);
2168
2169	pVM->hm.s.pGuestPatchMem = pPatchMem;
2170	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2171	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2172	return VINF_SUCCESS;
2173	}
2174
2175
2176	/**
2177	* Enable patching in a VT-x/AMD-V guest
2178	*
2179	* @returns VBox status code.
2180	* @param pVM The cross context VM structure.
2181	* @param pPatchMem Patch memory range.
2182	* @param cbPatchMem Size of the memory range.
2183	*/
2184	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2185	{
2186	VM_ASSERT_EMT(pVM);
2187	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2188	if (pVM->cCpus > 1)
2189	{
2190	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2191	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2192	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2193	AssertRC(rc);
2194	return rc;
2195	}
2196	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2197	}
2198
2199
2200	/**
2201	* Disable patching in a VT-x/AMD-V guest.
2202	*
2203	* @returns VBox status code.
2204	* @param pVM The cross context VM structure.
2205	* @param pPatchMem Patch memory range.
2206	* @param cbPatchMem Size of the memory range.
2207	*/
2208	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2209	{
2210	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2211	RT_NOREF2(pPatchMem, cbPatchMem);
2212
2213	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2214	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2215
2216	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2217	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2218	(void *)(uintptr_t)VMMGetCpuId(pVM));
2219	AssertRC(rc);
2220
2221	pVM->hm.s.pGuestPatchMem = 0;
2222	pVM->hm.s.pFreeGuestPatchMem = 0;
2223	pVM->hm.s.cbGuestPatchMem = 0;
2224	pVM->hm.s.fTPRPatchingActive = false;
2225	return VINF_SUCCESS;
2226	}
2227
2228
2229	/**
2230	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2231	*
2232	* @returns VBox strict status code.
2233	* @param pVM The cross context VM structure.
2234	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2235	* @param pvUser User specified CPU context.
2236	*
2237	*/
2238	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2239	{
2240	/*
2241	* Only execute the handler on the VCPU the original patch request was
2242	* issued. (The other CPU(s) might not yet have switched to protected
2243	* mode, nor have the correct memory context.)
2244	*/
2245	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2246	if (pVCpu->idCpu != idCpu)
2247	return VINF_SUCCESS;
2248
2249	/*
2250	* We're racing other VCPUs here, so don't try patch the instruction twice
2251	* and make sure there is still room for our patch record.
2252	*/
2253	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2254	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2255	if (pPatch)
2256	{
2257	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2258	return VINF_SUCCESS;
2259	}
2260	uint32_t const idx = pVM->hm.s.cPatches;
2261	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2262	{
2263	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2264	return VINF_SUCCESS;
2265	}
2266	pPatch = &pVM->hm.s.aPatches[idx];
2267
2268	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2269
2270	/*
2271	* Disassembler the instruction and get cracking.
2272	*/
2273	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2274	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2275	uint32_t cbOp;
2276	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2277	AssertRC(rc);
2278	if ( rc == VINF_SUCCESS
2279	&& pDis->pCurInstr->uOpcode == OP_MOV
2280	&& cbOp >= 3)
2281	{
2282	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2283
2284	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2285	AssertRC(rc);
2286
2287	pPatch->cbOp = cbOp;
2288
2289	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2290	{
2291	/* write. */
2292	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2293	{
2294	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2295	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2296	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2297	}
2298	else
2299	{
2300	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2301	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2302	pPatch->uSrcOperand = pDis->Param2.uValue;
2303	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2304	}
2305	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2306	AssertRC(rc);
2307
2308	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2309	pPatch->cbNewOp = sizeof(s_abVMMCall);
2310	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2311	}
2312	else
2313	{
2314	/*
2315	* TPR Read.
2316	*
2317	* Found:
2318	* mov eax, dword [fffe0080] (5 bytes)
2319	* Check if next instruction is:
2320	* shr eax, 4
2321	*/
2322	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2323
2324	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2325	uint8_t const cbOpMmio = cbOp;
2326	uint64_t const uSavedRip = pCtx->rip;
2327
2328	pCtx->rip += cbOp;
2329	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2330	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2331	pCtx->rip = uSavedRip;
2332
2333	if ( rc == VINF_SUCCESS
2334	&& pDis->pCurInstr->uOpcode == OP_SHR
2335	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2336	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2337	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2338	&& pDis->Param2.uValue == 4
2339	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2340	{
2341	uint8_t abInstr[15];
2342
2343	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2344	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2345	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2346	AssertRC(rc);
2347
2348	pPatch->cbOp = cbOpMmio + cbOp;
2349
2350	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2351	abInstr[0] = 0xf0;
2352	abInstr[1] = 0x0f;
2353	abInstr[2] = 0x20;
2354	abInstr[3] = 0xc0 \| pDis->Param1.Base.idxGenReg;
2355	for (unsigned i = 4; i < pPatch->cbOp; i++)
2356	abInstr[i] = 0x90; /* nop */
2357
2358	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2359	AssertRC(rc);
2360
2361	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2362	pPatch->cbNewOp = pPatch->cbOp;
2363	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2364
2365	Log(("Acceptable read/shr candidate!\n"));
2366	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2367	}
2368	else
2369	{
2370	pPatch->enmType = HMTPRINSTR_READ;
2371	pPatch->uDstOperand = idxMmioReg;
2372
2373	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2374	AssertRC(rc);
2375
2376	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2377	pPatch->cbNewOp = sizeof(s_abVMMCall);
2378	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2379	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2380	}
2381	}
2382
2383	pPatch->Core.Key = pCtx->eip;
2384	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2385	AssertRC(rc);
2386
2387	pVM->hm.s.cPatches++;
2388	return VINF_SUCCESS;
2389	}
2390
2391	/*
2392	* Save invalid patch, so we will not try again.
2393	*/
2394	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2395	pPatch->Core.Key = pCtx->eip;
2396	pPatch->enmType = HMTPRINSTR_INVALID;
2397	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2398	AssertRC(rc);
2399	pVM->hm.s.cPatches++;
2400	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2401	return VINF_SUCCESS;
2402	}
2403
2404
2405	/**
2406	* Callback to patch a TPR instruction (jump to generated code).
2407	*
2408	* @returns VBox strict status code.
2409	* @param pVM The cross context VM structure.
2410	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2411	* @param pvUser User specified CPU context.
2412	*
2413	*/
2414	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2415	{
2416	/*
2417	* Only execute the handler on the VCPU the original patch request was
2418	* issued. (The other CPU(s) might not yet have switched to protected
2419	* mode, nor have the correct memory context.)
2420	*/
2421	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2422	if (pVCpu->idCpu != idCpu)
2423	return VINF_SUCCESS;
2424
2425	/*
2426	* We're racing other VCPUs here, so don't try patch the instruction twice
2427	* and make sure there is still room for our patch record.
2428	*/
2429	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2430	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2431	if (pPatch)
2432	{
2433	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2434	return VINF_SUCCESS;
2435	}
2436	uint32_t const idx = pVM->hm.s.cPatches;
2437	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2438	{
2439	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2440	return VINF_SUCCESS;
2441	}
2442	pPatch = &pVM->hm.s.aPatches[idx];
2443
2444	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2445	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2446
2447	/*
2448	* Disassemble the instruction and get cracking.
2449	*/
2450	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2451	uint32_t cbOp;
2452	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2453	AssertRC(rc);
2454	if ( rc == VINF_SUCCESS
2455	&& pDis->pCurInstr->uOpcode == OP_MOV
2456	&& cbOp >= 5)
2457	{
2458	uint8_t aPatch[64];
2459	uint32_t off = 0;
2460
2461	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2462	AssertRC(rc);
2463
2464	pPatch->cbOp = cbOp;
2465	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2466
2467	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2468	{
2469	/*
2470	* TPR write:
2471	*
2472	* push ECX [51]
2473	* push EDX [52]
2474	* push EAX [50]
2475	* xor EDX,EDX [31 D2]
2476	* mov EAX,EAX [89 C0]
2477	* or
2478	* mov EAX,0000000CCh [B8 CC 00 00 00]
2479	* mov ECX,0C0000082h [B9 82 00 00 C0]
2480	* wrmsr [0F 30]
2481	* pop EAX [58]
2482	* pop EDX [5A]
2483	* pop ECX [59]
2484	* jmp return_address [E9 return_address]
2485	*/
2486	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2487
2488	aPatch[off++] = 0x51; /* push ecx */
2489	aPatch[off++] = 0x52; /* push edx */
2490	if (!fUsesEax)
2491	aPatch[off++] = 0x50; /* push eax */
2492	aPatch[off++] = 0x31; /* xor edx, edx */
2493	aPatch[off++] = 0xd2;
2494	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2495	{
2496	if (!fUsesEax)
2497	{
2498	aPatch[off++] = 0x89; /* mov eax, src_reg */
2499	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2500	}
2501	}
2502	else
2503	{
2504	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2505	aPatch[off++] = 0xb8; /* mov eax, immediate */
2506	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2507	off += sizeof(uint32_t);
2508	}
2509	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2510	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2511	off += sizeof(uint32_t);
2512
2513	aPatch[off++] = 0x0f; /* wrmsr */
2514	aPatch[off++] = 0x30;
2515	if (!fUsesEax)
2516	aPatch[off++] = 0x58; /* pop eax */
2517	aPatch[off++] = 0x5a; /* pop edx */
2518	aPatch[off++] = 0x59; /* pop ecx */
2519	}
2520	else
2521	{
2522	/*
2523	* TPR read:
2524	*
2525	* push ECX [51]
2526	* push EDX [52]
2527	* push EAX [50]
2528	* mov ECX,0C0000082h [B9 82 00 00 C0]
2529	* rdmsr [0F 32]
2530	* mov EAX,EAX [89 C0]
2531	* pop EAX [58]
2532	* pop EDX [5A]
2533	* pop ECX [59]
2534	* jmp return_address [E9 return_address]
2535	*/
2536	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2537
2538	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2539	aPatch[off++] = 0x51; /* push ecx */
2540	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2541	aPatch[off++] = 0x52; /* push edx */
2542	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2543	aPatch[off++] = 0x50; /* push eax */
2544
2545	aPatch[off++] = 0x31; /* xor edx, edx */
2546	aPatch[off++] = 0xd2;
2547
2548	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2549	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2550	off += sizeof(uint32_t);
2551
2552	aPatch[off++] = 0x0f; /* rdmsr */
2553	aPatch[off++] = 0x32;
2554
2555	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2556	{
2557	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2558	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2559	}
2560
2561	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2562	aPatch[off++] = 0x58; /* pop eax */
2563	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2564	aPatch[off++] = 0x5a; /* pop edx */
2565	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2566	aPatch[off++] = 0x59; /* pop ecx */
2567	}
2568	aPatch[off++] = 0xe9; /* jmp return_address */
2569	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2570	off += sizeof(RTRCUINTPTR);
2571
2572	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2573	{
2574	/* Write new code to the patch buffer. */
2575	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2576	AssertRC(rc);
2577
2578	#ifdef LOG_ENABLED
2579	uint32_t cbCurInstr;
2580	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2581	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2582	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2583	{
2584	char szOutput[256];
2585	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2586	szOutput, sizeof(szOutput), &cbCurInstr);
2587	if (RT_SUCCESS(rc))
2588	Log(("Patch instr %s\n", szOutput));
2589	else
2590	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2591	}
2592	#endif
2593
2594	pPatch->aNewOpcode[0] = 0xE9;
2595	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2596
2597	/* Overwrite the TPR instruction with a jump. */
2598	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2599	AssertRC(rc);
2600
2601	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2602
2603	pVM->hm.s.pFreeGuestPatchMem += off;
2604	pPatch->cbNewOp = 5;
2605
2606	pPatch->Core.Key = pCtx->eip;
2607	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2608	AssertRC(rc);
2609
2610	pVM->hm.s.cPatches++;
2611	pVM->hm.s.fTPRPatchingActive = true;
2612	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2613	return VINF_SUCCESS;
2614	}
2615
2616	Log(("Ran out of space in our patch buffer!\n"));
2617	}
2618	else
2619	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2620
2621
2622	/*
2623	* Save invalid patch, so we will not try again.
2624	*/
2625	pPatch = &pVM->hm.s.aPatches[idx];
2626	pPatch->Core.Key = pCtx->eip;
2627	pPatch->enmType = HMTPRINSTR_INVALID;
2628	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2629	AssertRC(rc);
2630	pVM->hm.s.cPatches++;
2631	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2632	return VINF_SUCCESS;
2633	}
2634
2635
2636	/**
2637	* Attempt to patch TPR mmio instructions.
2638	*
2639	* @returns VBox status code.
2640	* @param pVM The cross context VM structure.
2641	* @param pVCpu The cross context virtual CPU structure.
2642	*/
2643	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2644	{
2645	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2646	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2647	(void *)(uintptr_t)pVCpu->idCpu);
2648	AssertRC(rc);
2649	return rc;
2650	}
2651
2652
2653	/**
2654	* Checks if we need to reschedule due to VMM device heap changes.
2655	*
2656	* @returns true if a reschedule is required, otherwise false.
2657	* @param pVM The cross context VM structure.
2658	* @param pCtx VM execution context.
2659	*/
2660	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2661	{
2662	/*
2663	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2664	* when the unrestricted guest execution feature is missing (VT-x only).
2665	*/
2666	if ( pVM->hm.s.vmx.fEnabled
2667	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2668	&& CPUMIsGuestInRealModeEx(pCtx)
2669	&& !PDMVmmDevHeapIsEnabled(pVM))
2670	return true;
2671
2672	return false;
2673	}
2674
2675
2676	/**
2677	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2678	* event settings changes.
2679	*
2680	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2681	* function is just updating the VM globals.
2682	*
2683	* @param pVM The VM cross context VM structure.
2684	* @thread EMT(0)
2685	*/
2686	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2687	{
2688	/* Interrupts. */
2689	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2690	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2691
2692	/* CPU Exceptions. */
2693	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2694	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2695	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2696	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2697
2698	/* Common VM exits. */
2699	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2700	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2701	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2702	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2703
2704	/* Vendor specific VM exits. */
2705	if (HMR3IsVmxEnabled(pVM->pUVM))
2706	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2707	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2708	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2709	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2710	else
2711	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2712	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2713	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2714	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2715
2716	/* Done. */
2717	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2718	}
2719
2720
2721	/**
2722	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2723	*
2724	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2725	* per CPU settings.
2726	*
2727	* @param pVM The VM cross context VM structure.
2728	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2729	*/
2730	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2731	{
2732	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2733	}
2734
2735
2736	/**
2737	* Checks if we are currently using hardware acceleration.
2738	*
2739	* @returns true if hardware acceleration is being used, otherwise false.
2740	* @param pVCpu The cross context virtual CPU structure.
2741	*/
2742	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2743	{
2744	return pVCpu->hm.s.fActive;
2745	}
2746
2747
2748	/**
2749	* External interface for querying whether hardware acceleration is enabled.
2750	*
2751	* @returns true if VT-x or AMD-V is being used, otherwise false.
2752	* @param pUVM The user mode VM handle.
2753	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2754	*/
2755	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2756	{
2757	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2758	PVM pVM = pUVM->pVM;
2759	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2760	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2761	}
2762
2763
2764	/**
2765	* External interface for querying whether VT-x is being used.
2766	*
2767	* @returns true if VT-x is being used, otherwise false.
2768	* @param pUVM The user mode VM handle.
2769	* @sa HMR3IsSvmEnabled, HMIsEnabled
2770	*/
2771	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2772	{
2773	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2774	PVM pVM = pUVM->pVM;
2775	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2776	return pVM->hm.s.vmx.fEnabled
2777	&& pVM->hm.s.vmx.fSupported
2778	&& pVM->fHMEnabled;
2779	}
2780
2781
2782	/**
2783	* External interface for querying whether AMD-V is being used.
2784	*
2785	* @returns true if VT-x is being used, otherwise false.
2786	* @param pUVM The user mode VM handle.
2787	* @sa HMR3IsVmxEnabled, HMIsEnabled
2788	*/
2789	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2790	{
2791	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2792	PVM pVM = pUVM->pVM;
2793	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2794	return pVM->hm.s.svm.fEnabled
2795	&& pVM->hm.s.svm.fSupported
2796	&& pVM->fHMEnabled;
2797	}
2798
2799
2800	/**
2801	* Checks if we are currently using nested paging.
2802	*
2803	* @returns true if nested paging is being used, otherwise false.
2804	* @param pUVM The user mode VM handle.
2805	*/
2806	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2807	{
2808	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2809	PVM pVM = pUVM->pVM;
2810	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2811	return pVM->hm.s.fNestedPaging;
2812	}
2813
2814
2815	/**
2816	* Checks if virtualized APIC registers is enabled.
2817	*
2818	* When enabled this feature allows the hardware to access most of the
2819	* APIC registers in the virtual-APIC page without causing VM-exits. See
2820	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2821	*
2822	* @returns true if virtualized APIC registers is enabled, otherwise
2823	* false.
2824	* @param pUVM The user mode VM handle.
2825	*/
2826	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2827	{
2828	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2829	PVM pVM = pUVM->pVM;
2830	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2831	return pVM->hm.s.fVirtApicRegs;
2832	}
2833
2834
2835	/**
2836	* Checks if APIC posted-interrupt processing is enabled.
2837	*
2838	* This returns whether we can deliver interrupts to the guest without
2839	* leaving guest-context by updating APIC state from host-context.
2840	*
2841	* @returns true if APIC posted-interrupt processing is enabled,
2842	* otherwise false.
2843	* @param pUVM The user mode VM handle.
2844	*/
2845	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2846	{
2847	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2848	PVM pVM = pUVM->pVM;
2849	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2850	return pVM->hm.s.fPostedIntrs;
2851	}
2852
2853
2854	/**
2855	* Checks if we are currently using VPID in VT-x mode.
2856	*
2857	* @returns true if VPID is being used, otherwise false.
2858	* @param pUVM The user mode VM handle.
2859	*/
2860	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2861	{
2862	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2863	PVM pVM = pUVM->pVM;
2864	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2865	return pVM->hm.s.vmx.fVpid;
2866	}
2867
2868
2869	/**
2870	* Checks if we are currently using VT-x unrestricted execution,
2871	* aka UX.
2872	*
2873	* @returns true if UX is being used, otherwise false.
2874	* @param pUVM The user mode VM handle.
2875	*/
2876	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2877	{
2878	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2879	PVM pVM = pUVM->pVM;
2880	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2881	return pVM->hm.s.vmx.fUnrestrictedGuest
2882	\|\| pVM->hm.s.svm.fSupported;
2883	}
2884
2885
2886	/**
2887	* Checks if the VMX-preemption timer is being used.
2888	*
2889	* @returns true if the VMX-preemption timer is being used, otherwise false.
2890	* @param pVM The cross context VM structure.
2891	*/
2892	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2893	{
2894	return HMIsEnabled(pVM)
2895	&& pVM->hm.s.vmx.fEnabled
2896	&& pVM->hm.s.vmx.fUsePreemptTimer;
2897	}
2898
2899
2900	#ifdef TODO_9217_VMCSINFO
2901	/**
2902	* Helper for HMR3CheckError to log VMCS controls to the release log.
2903	*
2904	* @param idCpu The Virtual CPU ID.
2905	* @param pVmcsInfo The VMCS info. object.
2906	*/
2907	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2908	{
2909	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2910	{
2911	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2917	}
2918	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2919	{
2920	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2942	}
2943	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2944	{
2945	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPPTP_EPT );
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2973	}
2974	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2975	{
2976	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2987	}
2988	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2989	{
2990	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2991	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2992	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2993	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2994	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2995	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2996	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2997	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2998	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2999	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3000	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3003	}
3004	}
3005	#endif
3006
3007
3008	/**
3009	* Check fatal VT-x/AMD-V error and produce some meaningful
3010	* log release message.
3011	*
3012	* @param pVM The cross context VM structure.
3013	* @param iStatusCode VBox status code.
3014	*/
3015	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3016	{
3017	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3018	{
3019	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3020	* might be getting inaccurate values for non-guru'ing EMTs. */
3021	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3022	#ifdef TODO_9217_VMCSINFO
3023	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3024	#endif
3025	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3026	switch (iStatusCode)
3027	{
3028	case VERR_VMX_INVALID_VMCS_PTR:
3029	{
3030	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3031	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3032	#ifdef TODO_9217_VMCSINFO
3033	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3034	pVmcsInfo->HCPhysVmcs));
3035	#endif
3036	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3037	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3038	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3039	break;
3040	}
3041
3042	case VERR_VMX_UNABLE_TO_START_VM:
3043	{
3044	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3045	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3046	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3047	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3048
3049	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3050	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3051	{
3052	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3053	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3054	}
3055	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3056	{
3057	#ifdef TODO_9217_VMCSINFO
3058	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3059	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3060	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3061	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3062	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3063	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3064	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3065	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3066	#endif
3067	}
3068	/** @todo Log VM-entry event injection control fields
3069	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3070	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3071	break;
3072	}
3073
3074	case VERR_VMX_INVALID_GUEST_STATE:
3075	{
3076	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3077	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3078	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3079	#ifdef TODO_9217_VMCSINFO
3080	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3081	#endif
3082	break;
3083	}
3084
3085	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3086	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3087	case VERR_VMX_INVALID_VMXON_PTR:
3088	case VERR_VMX_UNEXPECTED_EXIT:
3089	case VERR_VMX_INVALID_VMCS_FIELD:
3090	case VERR_SVM_UNKNOWN_EXIT:
3091	case VERR_SVM_UNEXPECTED_EXIT:
3092	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3093	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3094	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3095	break;
3096	}
3097	}
3098
3099	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3100	{
3101	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3102	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3103	}
3104	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3105	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3106	}
3107
3108
3109	/**
3110	* Execute state save operation.
3111	*
3112	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3113	* is because we always save the VM state from ring-3 and thus most HM state
3114	* will be re-synced dynamically at runtime and don't need to be part of the VM
3115	* saved state.
3116	*
3117	* @returns VBox status code.
3118	* @param pVM The cross context VM structure.
3119	* @param pSSM SSM operation handle.
3120	*/
3121	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3122	{
3123	Log(("hmR3Save:\n"));
3124
3125	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3126	{
3127	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3128	Assert(!pVCpu->hm.s.Event.fPending);
3129	if (pVM->cpum.ro.GuestFeatures.fSvm)
3130	{
3131	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3132	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3133	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3134	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3135	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3136	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3137	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3138	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3139	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3140	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3141	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3142	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3143	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3144	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3145	}
3146	}
3147
3148	/* Save the guest patch data. */
3149	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3150	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3151	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3152
3153	/* Store all the guest patch records too. */
3154	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3155	if (RT_FAILURE(rc))
3156	return rc;
3157
3158	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3159	{
3160	AssertCompileSize(HMTPRINSTR, 4);
3161	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3162	SSMR3PutU32(pSSM, pPatch->Core.Key);
3163	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3164	SSMR3PutU32(pSSM, pPatch->cbOp);
3165	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3166	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3167	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3168	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3169	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3170	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3171	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3172	if (RT_FAILURE(rc))
3173	return rc;
3174	}
3175
3176	return VINF_SUCCESS;
3177	}
3178
3179
3180	/**
3181	* Execute state load operation.
3182	*
3183	* @returns VBox status code.
3184	* @param pVM The cross context VM structure.
3185	* @param pSSM SSM operation handle.
3186	* @param uVersion Data layout version.
3187	* @param uPass The data pass.
3188	*/
3189	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3190	{
3191	int rc;
3192
3193	LogFlowFunc(("uVersion=%u\n", uVersion));
3194	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3195
3196	/*
3197	* Validate version.
3198	*/
3199	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3200	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3201	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3202	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3203	{
3204	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3205	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3206	}
3207
3208	/*
3209	* Load per-VCPU state.
3210	*/
3211	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3212	{
3213	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3214	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3215	{
3216	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3217	if (pVM->cpum.ro.GuestFeatures.fSvm)
3218	{
3219	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3220	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3221	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3222	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3223	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3224	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3225	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3226	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3227	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3228	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3229	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3230	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3231	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3232	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3233	AssertRCReturn(rc, rc);
3234	}
3235	}
3236	else
3237	{
3238	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3239	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3240	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3241	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3242
3243	/* VMX fWasInRealMode related data. */
3244	uint32_t uDummy;
3245	SSMR3GetU32(pSSM, &uDummy);
3246	SSMR3GetU32(pSSM, &uDummy);
3247	rc = SSMR3GetU32(pSSM, &uDummy);
3248	AssertRCReturn(rc, rc);
3249	}
3250	}
3251
3252	/*
3253	* Load TPR patching data.
3254	*/
3255	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3256	{
3257	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3258	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3259	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3260
3261	/* Fetch all TPR patch records. */
3262	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3263	AssertRCReturn(rc, rc);
3264	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3265	{
3266	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3267	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3268	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3269	SSMR3GetU32(pSSM, &pPatch->cbOp);
3270	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3271	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3272	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3273
3274	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3275	pVM->hm.s.fTPRPatchingActive = true;
3276	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3277
3278	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3279	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3280	SSMR3GetU32(pSSM, &pPatch->cFaults);
3281	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3282	AssertRCReturn(rc, rc);
3283
3284	LogFlow(("hmR3Load: patch %d\n", i));
3285	LogFlow(("Key = %x\n", pPatch->Core.Key));
3286	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3287	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3288	LogFlow(("type = %d\n", pPatch->enmType));
3289	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3290	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3291	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3292	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3293
3294	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3295	AssertRCReturn(rc, rc);
3296	}
3297	}
3298
3299	return VINF_SUCCESS;
3300	}
3301
3302
3303	/**
3304	* Displays HM info.
3305	*
3306	* @param pVM The cross context VM structure.
3307	* @param pHlp The info helper functions.
3308	* @param pszArgs Arguments, ignored.
3309	*/
3310	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3311	{
3312	NOREF(pszArgs);
3313	PVMCPU pVCpu = VMMGetCpu(pVM);
3314	if (!pVCpu)
3315	pVCpu = pVM->apCpusR3[0];
3316
3317	if (HMIsEnabled(pVM))
3318	{
3319	if (pVM->hm.s.vmx.fSupported)
3320	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3321	else
3322	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3323	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3324	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3325	if (pVM->hm.s.vmx.fSupported)
3326	{
3327	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3328	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3329	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3330
3331	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3332	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3333	if (fRealOnV86Active)
3334	{
3335	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3336	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3337	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3338	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3339	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3340	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3341	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3342	}
3343	}
3344	}
3345	else
3346	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3347	}
3348
3349
3350	/**
3351	* Displays the HM Last-Branch-Record info. for the guest.
3352	*
3353	* @param pVM The cross context VM structure.
3354	* @param pHlp The info helper functions.
3355	* @param pszArgs Arguments, ignored.
3356	*/
3357	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3358	{
3359	NOREF(pszArgs);
3360	PVMCPU pVCpu = VMMGetCpu(pVM);
3361	if (!pVCpu)
3362	pVCpu = pVM->apCpusR3[0];
3363
3364	if (!HMIsEnabled(pVM))
3365	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3366
3367	if (HMIsVmxActive(pVM))
3368	{
3369	if (pVM->hm.s.vmx.fLbr)
3370	{
3371	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3372	uint32_t const cLbrStack = pVM->hm.s.vmx.idLbrFromIpMsrLast - pVM->hm.s.vmx.idLbrFromIpMsrFirst + 1;
3373
3374	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3375	* 0xf should cover everything we support thus far. Fix if necessary
3376	* later. */
3377	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3378	if (idxTopOfStack > cLbrStack)
3379	{
3380	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3381	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3382	return;
3383	}
3384
3385	/*
3386	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3387	*/
3388	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3389	uint32_t idxCurrent = idxTopOfStack;
3390	Assert(idxTopOfStack < cLbrStack);
3391	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3392	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3393	for (;;)
3394	{
3395	if (pVM->hm.s.vmx.idLbrToIpMsrFirst)
3396	{
3397	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3398	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3399	}
3400	else
3401	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3402
3403	idxCurrent = (idxCurrent - 1) % cLbrStack;
3404	if (idxCurrent == idxTopOfStack)
3405	break;
3406	}
3407	}
3408	else
3409	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3410	}
3411	else
3412	{
3413	Assert(HMIsSvmActive(pVM));
3414	/** @todo SVM: LBRs (get them from VMCB if possible). */
3415	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented in VM debugger yet\n");
3416	}
3417	}
3418
3419
3420	/**
3421	* Displays the HM pending event.
3422	*
3423	* @param pVM The cross context VM structure.
3424	* @param pHlp The info helper functions.
3425	* @param pszArgs Arguments, ignored.
3426	*/
3427	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3428	{
3429	NOREF(pszArgs);
3430	PVMCPU pVCpu = VMMGetCpu(pVM);
3431	if (!pVCpu)
3432	pVCpu = pVM->apCpusR3[0];
3433
3434	if (HMIsEnabled(pVM))
3435	{
3436	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3437	if (pVCpu->hm.s.Event.fPending)
3438	{
3439	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3440	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3441	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3442	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3443	}
3444	}
3445	else
3446	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3447	}
3448
3449
3450	/**
3451	* Displays the SVM nested-guest VMCB cache.
3452	*
3453	* @param pVM The cross context VM structure.
3454	* @param pHlp The info helper functions.
3455	* @param pszArgs Arguments, ignored.
3456	*/
3457	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3458	{
3459	NOREF(pszArgs);
3460	PVMCPU pVCpu = VMMGetCpu(pVM);
3461	if (!pVCpu)
3462	pVCpu = pVM->apCpusR3[0];
3463
3464	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3465	if ( fSvmEnabled
3466	&& pVM->cpum.ro.GuestFeatures.fSvm)
3467	{
3468	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3469	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3470	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3471	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3472	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3473	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3474	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3475	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3476	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3477	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3478	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3479	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3480	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3481	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3482	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3483	}
3484	else
3485	{
3486	if (!fSvmEnabled)
3487	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3488	else
3489	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3490	}
3491	}
3492

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 87491

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