VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 92479

Last change on this file since 92479 was 91693, checked in by vboxsync, 3 years ago

VMM/hmR3InfoLbr: Don't assert in NEM mode.
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1/* $Id: HM.cpp 91693 2021-10-12 14:07:19Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/em.h>
44#include <VBox/vmm/pdmapi.h>
45#include <VBox/vmm/pgm.h>
46#include <VBox/vmm/ssm.h>
47#include <VBox/vmm/gim.h>
48#include <VBox/vmm/trpm.h>
49#include <VBox/vmm/dbgf.h>
50#include <VBox/vmm/iom.h>
51#include <VBox/vmm/iem.h>
52#include <VBox/vmm/selm.h>
53#include <VBox/vmm/nem.h>
54#include <VBox/vmm/hm_vmx.h>
55#include <VBox/vmm/hm_svm.h>
56#include "HMInternal.h"
57#include <VBox/vmm/vmcc.h>
58#include <VBox/err.h>
59#include <VBox/param.h>
60
61#include <iprt/assert.h>
62#include <VBox/log.h>
63#include <iprt/asm.h>
64#include <iprt/asm-amd64-x86.h>
65#include <iprt/env.h>
66#include <iprt/thread.h>
67
68
69/*********************************************************************************************************************************
70* Defined Constants And Macros *
71*********************************************************************************************************************************/
72/** @def HMVMX_REPORT_FEAT
73 * Reports VT-x feature to the release log.
74 *
75 * @param a_uAllowed1 Mask of allowed-1 feature bits.
76 * @param a_uAllowed0 Mask of allowed-0 feature bits.
77 * @param a_StrDesc The description string to report.
78 * @param a_Featflag Mask of the feature to report.
79 */
80#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
81 do { \
82 if ((a_uAllowed1) & (a_Featflag)) \
83 { \
84 if ((a_uAllowed0) & (a_Featflag)) \
85 LogRel(("HM: " a_StrDesc " (must be set)\n")); \
86 else \
87 LogRel(("HM: " a_StrDesc "\n")); \
88 } \
89 else \
90 LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
91 } while (0)
92
93/** @def HMVMX_REPORT_ALLOWED_FEAT
94 * Reports an allowed VT-x feature to the release log.
95 *
96 * @param a_uAllowed1 Mask of allowed-1 feature bits.
97 * @param a_StrDesc The description string to report.
98 * @param a_FeatFlag Mask of the feature to report.
99 */
100#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
101 do { \
102 if ((a_uAllowed1) & (a_FeatFlag)) \
103 LogRel(("HM: " a_StrDesc "\n")); \
104 else \
105 LogRel(("HM: " a_StrDesc " not supported\n")); \
106 } while (0)
107
108/** @def HMVMX_REPORT_MSR_CAP
109 * Reports MSR feature capability.
110 *
111 * @param a_MsrCaps Mask of MSR feature bits.
112 * @param a_StrDesc The description string to report.
113 * @param a_fCap Mask of the feature to report.
114 */
115#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
116 do { \
117 if ((a_MsrCaps) & (a_fCap)) \
118 LogRel(("HM: " a_StrDesc "\n")); \
119 } while (0)
120
121/** @def HMVMX_LOGREL_FEAT
122 * Dumps a feature flag from a bitmap of features to the release log.
123 *
124 * @param a_fVal The value of all the features.
125 * @param a_fMask The specific bitmask of the feature.
126 */
127#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
128 do { \
129 if ((a_fVal) & (a_fMask)) \
130 LogRel(("HM: %s\n", #a_fMask)); \
131 } while (0)
132
133
134/*********************************************************************************************************************************
135* Internal Functions *
136*********************************************************************************************************************************/
137static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
138static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
139static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
140static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143static int hmR3InitFinalizeR3(PVM pVM);
144static int hmR3InitFinalizeR0(PVM pVM);
145static int hmR3InitFinalizeR0Intel(PVM pVM);
146static int hmR3InitFinalizeR0Amd(PVM pVM);
147static int hmR3TermCPU(PVM pVM);
148
149
150#ifdef VBOX_WITH_STATISTICS
151/**
152 * Returns the name of the hardware exception.
153 *
154 * @returns The name of the hardware exception.
155 * @param uVector The exception vector.
156 */
157static const char *hmR3GetXcptName(uint8_t uVector)
158{
159 switch (uVector)
160 {
161 case X86_XCPT_DE: return "#DE";
162 case X86_XCPT_DB: return "#DB";
163 case X86_XCPT_NMI: return "#NMI";
164 case X86_XCPT_BP: return "#BP";
165 case X86_XCPT_OF: return "#OF";
166 case X86_XCPT_BR: return "#BR";
167 case X86_XCPT_UD: return "#UD";
168 case X86_XCPT_NM: return "#NM";
169 case X86_XCPT_DF: return "#DF";
170 case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
171 case X86_XCPT_TS: return "#TS";
172 case X86_XCPT_NP: return "#NP";
173 case X86_XCPT_SS: return "#SS";
174 case X86_XCPT_GP: return "#GP";
175 case X86_XCPT_PF: return "#PF";
176 case X86_XCPT_MF: return "#MF";
177 case X86_XCPT_AC: return "#AC";
178 case X86_XCPT_MC: return "#MC";
179 case X86_XCPT_XF: return "#XF";
180 case X86_XCPT_VE: return "#VE";
181 case X86_XCPT_CP: return "#CP";
182 case X86_XCPT_VC: return "#VC";
183 case X86_XCPT_SX: return "#SX";
184 }
185 return "Reserved";
186}
187#endif /* VBOX_WITH_STATISTICS */
188
189
190/**
191 * Initializes the HM.
192 *
193 * This is the very first component to really do init after CFGM so that we can
194 * establish the predominant execution engine for the VM prior to initializing
195 * other modules. It takes care of NEM initialization if needed (HM disabled or
196 * not available in HW).
197 *
198 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
199 * hypervisor API via NEM, and then back on raw-mode if that isn't available
200 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
201 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
202 * X, OS/2 and others).
203 *
204 * Note that a lot of the set up work is done in ring-0 and thus postponed till
205 * the ring-3 and ring-0 callback to HMR3InitCompleted.
206 *
207 * @returns VBox status code.
208 * @param pVM The cross context VM structure.
209 *
210 * @remarks Be careful with what we call here, since most of the VMM components
211 * are uninitialized.
212 */
213VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
214{
215 LogFlowFunc(("\n"));
216
217 /*
218 * Assert alignment and sizes.
219 */
220 AssertCompileMemberAlignment(VM, hm.s, 32);
221 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
222
223 /*
224 * Register the saved state data unit.
225 */
226 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
227 NULL, NULL, NULL,
228 NULL, hmR3Save, NULL,
229 NULL, hmR3Load, NULL);
230 if (RT_FAILURE(rc))
231 return rc;
232
233 /*
234 * Register info handlers.
235 */
236 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
237 AssertRCReturn(rc, rc);
238
239 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
240 DBGFINFO_FLAGS_ALL_EMTS);
241 AssertRCReturn(rc, rc);
242
243 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
244 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
245 AssertRCReturn(rc, rc);
246
247 rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
248 AssertRCReturn(rc, rc);
249
250 /*
251 * Read configuration.
252 */
253 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
254
255 /*
256 * Validate the HM settings.
257 */
258 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
259 "HMForced" /* implied 'true' these days */
260 "|UseNEMInstead"
261 "|FallbackToNEM"
262 "|EnableNestedPaging"
263 "|EnableUX"
264 "|EnableLargePages"
265 "|EnableVPID"
266 "|IBPBOnVMExit"
267 "|IBPBOnVMEntry"
268 "|SpecCtrlByHost"
269 "|L1DFlushOnSched"
270 "|L1DFlushOnVMEntry"
271 "|MDSClearOnSched"
272 "|MDSClearOnVMEntry"
273 "|TPRPatchingEnabled"
274 "|64bitEnabled"
275 "|Exclusive"
276 "|MaxResumeLoops"
277 "|VmxPleGap"
278 "|VmxPleWindow"
279 "|VmxLbr"
280 "|UseVmxPreemptTimer"
281 "|SvmPauseFilter"
282 "|SvmPauseFilterThreshold"
283 "|SvmVirtVmsaveVmload"
284 "|SvmVGif"
285 "|LovelyMesaDrvWorkaround",
286 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
287 if (RT_FAILURE(rc))
288 return rc;
289
290 /** @cfgm{/HM/HMForced, bool, false}
291 * Forces hardware virtualization, no falling back on raw-mode. HM must be
292 * enabled, i.e. /HMEnabled must be true. */
293 bool fHMForced;
294 AssertRelease(pVM->fHMEnabled);
295 fHMForced = true;
296
297 /** @cfgm{/HM/UseNEMInstead, bool, true}
298 * Don't use HM, use NEM instead. */
299 bool fUseNEMInstead = false;
300 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
301 AssertRCReturn(rc, rc);
302 if (fUseNEMInstead && pVM->fHMEnabled)
303 {
304 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
305 pVM->fHMEnabled = false;
306 }
307
308 /** @cfgm{/HM/FallbackToNEM, bool, true}
309 * Enables fallback on NEM. */
310 bool fFallbackToNEM = true;
311 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
312 AssertRCReturn(rc, rc);
313
314 /** @cfgm{/HM/EnableNestedPaging, bool, false}
315 * Enables nested paging (aka extended page tables). */
316 bool fAllowNestedPaging = false;
317 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
318 AssertRCReturn(rc, rc);
319
320 /** @cfgm{/HM/EnableUX, bool, true}
321 * Enables the VT-x unrestricted execution feature. */
322 bool fAllowUnrestricted = true;
323 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
324 AssertRCReturn(rc, rc);
325
326 /** @cfgm{/HM/EnableLargePages, bool, false}
327 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
328 * page table walking and maybe better TLB hit rate in some cases. */
329 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
330 AssertRCReturn(rc, rc);
331
332 /** @cfgm{/HM/EnableVPID, bool, false}
333 * Enables the VT-x VPID feature. */
334 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
335 AssertRCReturn(rc, rc);
336
337 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
338 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
339 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
340 AssertRCReturn(rc, rc);
341
342 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
343 * Enables AMD64 cpu features.
344 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
345 * already have the support. */
346#ifdef VBOX_WITH_64_BITS_GUESTS
347 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
348 AssertLogRelRCReturn(rc, rc);
349#else
350 pVM->hm.s.fAllow64BitGuestsCfg = false;
351#endif
352
353 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
354 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
355 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
356 * latest PAUSE instruction to be start of a new PAUSE loop.
357 */
358 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
359 AssertRCReturn(rc, rc);
360
361 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
362 * The pause-filter exiting window in TSC ticks. When the number of ticks
363 * between the current PAUSE instruction and first PAUSE of a loop exceeds
364 * VmxPleWindow, a VM-exit is triggered.
365 *
366 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
367 */
368 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
369 AssertRCReturn(rc, rc);
370
371 /** @cfgm{/HM/VmxLbr, bool, false}
372 * Whether to enable LBR for the guest. This is disabled by default as it's only
373 * useful while debugging and enabling it causes a noticeable performance hit. */
374 rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
375 AssertRCReturn(rc, rc);
376
377 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
378 * A counter that is decrement each time a PAUSE instruction is executed by the
379 * guest. When the counter is 0, a \#VMEXIT is triggered.
380 *
381 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
382 */
383 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
384 AssertRCReturn(rc, rc);
385
386 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
387 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
388 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
389 * PauseFilter count is reset to its initial value. However, if PAUSE is
390 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
391 * be triggered.
392 *
393 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
394 * activated.
395 */
396 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
397 AssertRCReturn(rc, rc);
398
399 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
400 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
401 * available. */
402 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
403 AssertRCReturn(rc, rc);
404
405 /** @cfgm{/HM/SvmVGif, bool, true}
406 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
407 * if it's available. */
408 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
409 AssertRCReturn(rc, rc);
410
411 /** @cfgm{/HM/SvmLbrVirt, bool, false}
412 * Whether to make use of the LBR virtualization feature of the CPU if it's
413 * available. This is disabled by default as it's only useful while debugging
414 * and enabling it causes a small hit to performance. */
415 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
416 AssertRCReturn(rc, rc);
417
418 /** @cfgm{/HM/Exclusive, bool}
419 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
420 * global init for each host CPU. If false, we do local init each time we wish
421 * to execute guest code.
422 *
423 * On Windows, default is false due to the higher risk of conflicts with other
424 * hypervisors.
425 *
426 * On Mac OS X, this setting is ignored since the code does not handle local
427 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
428 */
429#if defined(RT_OS_DARWIN)
430 pVM->hm.s.fGlobalInit = true;
431#else
432 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
433# if defined(RT_OS_WINDOWS)
434 false
435# else
436 true
437# endif
438 );
439 AssertLogRelRCReturn(rc, rc);
440#endif
441
442 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
443 * The number of times to resume guest execution before we forcibly return to
444 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445 * determines the default value. */
446 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
447 AssertLogRelRCReturn(rc, rc);
448
449 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
450 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
451 * available. */
452 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
453 AssertLogRelRCReturn(rc, rc);
454
455 /** @cfgm{/HM/IBPBOnVMExit, bool}
456 * Costly paranoia setting. */
457 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
458 AssertLogRelRCReturn(rc, rc);
459
460 /** @cfgm{/HM/IBPBOnVMEntry, bool}
461 * Costly paranoia setting. */
462 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
463 AssertLogRelRCReturn(rc, rc);
464
465 /** @cfgm{/HM/L1DFlushOnSched, bool, true}
466 * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
467 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
468 AssertLogRelRCReturn(rc, rc);
469
470 /** @cfgm{/HM/L1DFlushOnVMEntry, bool}
471 * CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
472 rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
473 AssertLogRelRCReturn(rc, rc);
474
475 /* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
476 if (pVM->hm.s.fL1dFlushOnVmEntry)
477 pVM->hm.s.fL1dFlushOnSched = false;
478
479 /** @cfgm{/HM/SpecCtrlByHost, bool}
480 * Another expensive paranoia setting. */
481 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
482 AssertLogRelRCReturn(rc, rc);
483
484 /** @cfgm{/HM/MDSClearOnSched, bool, true}
485 * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
486 * ignored on CPUs that aren't affected. */
487 rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
488 AssertLogRelRCReturn(rc, rc);
489
490 /** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
491 * CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
492 * ignored on CPUs that aren't affected. */
493 rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
494 AssertLogRelRCReturn(rc, rc);
495
496 /* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
497 if (pVM->hm.s.fMdsClearOnVmEntry)
498 pVM->hm.s.fMdsClearOnSched = false;
499
500 /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
501 * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
502 * the hypervisor it is running under. */
503 bool fMesaWorkaround;
504 rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
505 AssertLogRelRCReturn(rc, rc);
506 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
507 {
508 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
509 pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
510 }
511
512 /*
513 * Check if VT-x or AMD-v support according to the users wishes.
514 */
515 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
516 * VERR_SVM_IN_USE. */
517 if (pVM->fHMEnabled)
518 {
519 uint32_t fCaps;
520 rc = SUPR3QueryVTCaps(&fCaps);
521 if (RT_SUCCESS(rc))
522 {
523 if (fCaps & SUPVTCAPS_AMD_V)
524 {
525 pVM->hm.s.svm.fSupported = true;
526 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
527 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
528 }
529 else if (fCaps & SUPVTCAPS_VT_X)
530 {
531 const char *pszWhy;
532 rc = SUPR3QueryVTxSupported(&pszWhy);
533 if (RT_SUCCESS(rc))
534 {
535 pVM->hm.s.vmx.fSupported = true;
536 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
537 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
538 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
539 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
540 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
541 }
542 else
543 {
544 /*
545 * Before failing, try fallback to NEM if we're allowed to do that.
546 */
547 pVM->fHMEnabled = false;
548 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
549 if (fFallbackToNEM)
550 {
551 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
552 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
553
554 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
555 if ( RT_SUCCESS(rc2)
556 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
557 rc = VINF_SUCCESS;
558 }
559 if (RT_FAILURE(rc))
560 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
561 }
562 }
563 else
564 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
565 VERR_INTERNAL_ERROR_5);
566
567 /*
568 * Disable nested paging and unrestricted guest execution now if they're
569 * configured so that CPUM can make decisions based on our configuration.
570 */
571 if ( fAllowNestedPaging
572 && (fCaps & SUPVTCAPS_NESTED_PAGING))
573 {
574 pVM->hm.s.fNestedPagingCfg = true;
575 if (fCaps & SUPVTCAPS_VT_X)
576 {
577 if ( fAllowUnrestricted
578 && (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
579 pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
580 else
581 Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
582 }
583 }
584 else
585 Assert(!pVM->hm.s.fNestedPagingCfg);
586 }
587 else
588 {
589 const char *pszMsg;
590 switch (rc)
591 {
592 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
593 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
594 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
595 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
596 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
597 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
598 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
599 default:
600 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
601 }
602
603 /*
604 * Before failing, try fallback to NEM if we're allowed to do that.
605 */
606 pVM->fHMEnabled = false;
607 if (fFallbackToNEM)
608 {
609 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
610 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
611 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
612 if ( RT_SUCCESS(rc2)
613 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
614 rc = VINF_SUCCESS;
615 }
616 if (RT_FAILURE(rc))
617 return VM_SET_ERROR(pVM, rc, pszMsg);
618 }
619 }
620 else
621 {
622 /*
623 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
624 */
625 if (fUseNEMInstead)
626 {
627 rc = NEMR3Init(pVM, false /*fFallback*/, true);
628 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
629 if (RT_FAILURE(rc))
630 return rc;
631 }
632 if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
633 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
634 || pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
635 return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
636 }
637
638 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
639 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
640 return VINF_SUCCESS;
641}
642
643
644/**
645 * Initializes HM components after ring-3 phase has been fully initialized.
646 *
647 * @returns VBox status code.
648 * @param pVM The cross context VM structure.
649 */
650static int hmR3InitFinalizeR3(PVM pVM)
651{
652 LogFlowFunc(("\n"));
653
654 if (!HMIsEnabled(pVM))
655 return VINF_SUCCESS;
656
657 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
658 {
659 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
660 pVCpu->hm.s.fActive = false;
661 pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
662 }
663
664 /*
665 * Check if L1D flush is needed/possible.
666 */
667 if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
668 || pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
669 || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
670 || pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
671 || pVM->cpum.ro.HostFeatures.fArchRdclNo)
672 pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
673
674 /*
675 * Check if MDS flush is needed/possible.
676 * On atoms and knight family CPUs, we will only allow clearing on scheduling.
677 */
678 if ( !pVM->cpum.ro.HostFeatures.fMdsClear
679 || pVM->cpum.ro.HostFeatures.fArchMdsNo)
680 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
681 else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
682 && pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
683 || ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
684 && pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
685 {
686 if (!pVM->hm.s.fMdsClearOnSched)
687 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
688 pVM->hm.s.fMdsClearOnVmEntry = false;
689 }
690 else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
691 || pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
692 pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
693
694 /*
695 * Statistics.
696 */
697#ifdef VBOX_WITH_STATISTICS
698 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
699 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
700 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
701 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
702 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
703#endif
704
705 bool const fCpuSupportsVmx = ASMIsIntelCpu() || ASMIsViaCentaurCpu() || ASMIsShanghaiCpu();
706 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
707 {
708 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
709 PHMCPU pHmCpu = &pVCpu->hm.s;
710 int rc;
711
712# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
713 rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
714 AssertRC(rc); \
715 } while (0)
716# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
717 HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
718
719#ifdef VBOX_WITH_STATISTICS
720
721 HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
722 HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
723 HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
724 HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
725 HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
726 HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
727 HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
728 HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
729 HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
730 HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
731 HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
732 HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
733 HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
734 HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
735# ifdef HM_PROFILE_EXIT_DISPATCH
736 HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
737 "/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
738# endif
739#endif
740# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
741
742#ifdef VBOX_WITH_STATISTICS
743 HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
744 HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
745 HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
746 HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
747 HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
748 HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
749 HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
750 HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
751 HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
752 HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
753 HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
754 HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
755 HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
756 HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
757 HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
758 HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
759#endif
760 HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
761 if (fCpuSupportsVmx)
762 HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
763#ifdef VBOX_WITH_STATISTICS
764 HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
765 HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
766 HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
767 HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
768 HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
769 HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
770 HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
771 HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
772 HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
773 HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
774 HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
775 HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
776 HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
777 HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
778 HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
779 HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
780 HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
781 HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
782 HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
783 HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
784 HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
785 HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
786 HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
787 HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
788 HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
789 HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
790 HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
791 HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
792#endif
793 HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
794 HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
795 HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
796#ifdef VBOX_WITH_STATISTICS
797 HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
798 HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
799 HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
800
801 HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
802 HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
803 HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
804 HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
805 HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
806 HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
807 HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
808 HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
809 HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
810 HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
811 HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
812 HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
813#endif
814 HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
815#ifdef VBOX_WITH_STATISTICS
816 HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
817
818 HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
819 HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
820 HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
821 HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
822 HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
823 HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
824
825 HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
826 HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
827 HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
828 HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
829 HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
830 HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
831 HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
832 HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
833 HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
834 HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
835 HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
836 HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
837 HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
838 HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
839 HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
840
841 HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
842 HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
843 HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
844
845 HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
846 HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
847 HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
848
849 HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
850 HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
851 HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
852 HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
853
854 if (fCpuSupportsVmx)
855 {
856 HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
857 HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
858 HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
859 HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
860 }
861
862 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
863 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
864 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
865
866 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
867 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
868 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
869
870 HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
871 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
872 HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
873 HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
874#endif
875 if (fCpuSupportsVmx)
876 {
877 HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
878 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
879 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
880 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
881 HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
882 }
883#ifdef VBOX_WITH_STATISTICS
884 /*
885 * Guest Exit reason stats.
886 */
887 if (fCpuSupportsVmx)
888 {
889 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
890 {
891 const char *pszExitName = HMGetVmxExitName(j);
892 if (pszExitName)
893 {
894 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
895 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
896 AssertRCReturn(rc, rc);
897 }
898 }
899 }
900 else
901 {
902 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
903 {
904 const char *pszExitName = HMGetSvmExitName(j);
905 if (pszExitName)
906 {
907 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
908 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
909 AssertRC(rc);
910 }
911 }
912 }
913 HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
914
915#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) || defined(VBOX_WITH_NESTED_HWVIRT_VMX)
916 /*
917 * Nested-guest VM-exit reason stats.
918 */
919 if (fCpuSupportsVmx)
920 {
921 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
922 {
923 const char *pszExitName = HMGetVmxExitName(j);
924 if (pszExitName)
925 {
926 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
927 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
928 AssertRC(rc);
929 }
930 }
931 }
932 else
933 {
934 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
935 {
936 const char *pszExitName = HMGetSvmExitName(j);
937 if (pszExitName)
938 {
939 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
940 STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
941 AssertRC(rc);
942 }
943 }
944 }
945 HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
946#endif
947
948 /*
949 * Injected interrupts stats.
950 */
951 char szDesc[64];
952 for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
953 {
954 RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
955 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
956 STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
957 AssertRC(rc);
958 }
959
960 /*
961 * Injected exception stats.
962 */
963 for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
964 {
965 RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
966 rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
967 STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
968 AssertRC(rc);
969 }
970
971#endif /* VBOX_WITH_STATISTICS */
972#undef HM_REG_COUNTER
973#undef HM_REG_PROFILE
974#undef HM_REG_STAT
975 }
976
977 return VINF_SUCCESS;
978}
979
980
981/**
982 * Called when a init phase has completed.
983 *
984 * @returns VBox status code.
985 * @param pVM The cross context VM structure.
986 * @param enmWhat The phase that completed.
987 */
988VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
989{
990 switch (enmWhat)
991 {
992 case VMINITCOMPLETED_RING3:
993 return hmR3InitFinalizeR3(pVM);
994 case VMINITCOMPLETED_RING0:
995 return hmR3InitFinalizeR0(pVM);
996 default:
997 return VINF_SUCCESS;
998 }
999}
1000
1001
1002/**
1003 * Turns off normal raw mode features.
1004 *
1005 * @param pVM The cross context VM structure.
1006 */
1007static void hmR3DisableRawMode(PVM pVM)
1008{
1009/** @todo r=bird: HM shouldn't be doing this crap. */
1010 /* Reinit the paging mode to force the new shadow mode. */
1011 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1012 {
1013 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1014 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1015 }
1016}
1017
1018
1019/**
1020 * Initialize VT-x or AMD-V.
1021 *
1022 * @returns VBox status code.
1023 * @param pVM The cross context VM structure.
1024 */
1025static int hmR3InitFinalizeR0(PVM pVM)
1026{
1027 int rc;
1028
1029 if (!HMIsEnabled(pVM))
1030 return VINF_SUCCESS;
1031
1032 /*
1033 * Hack to allow users to work around broken BIOSes that incorrectly set
1034 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1035 */
1036 if ( !pVM->hm.s.vmx.fSupported
1037 && !pVM->hm.s.svm.fSupported
1038 && pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1039 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1040 {
1041 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1042 pVM->hm.s.svm.fSupported = true;
1043 pVM->hm.s.svm.fIgnoreInUseError = true;
1044 pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1045 }
1046
1047 /*
1048 * Report ring-0 init errors.
1049 */
1050 if ( !pVM->hm.s.vmx.fSupported
1051 && !pVM->hm.s.svm.fSupported)
1052 {
1053 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1054 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1055 switch (pVM->hm.s.ForR3.rcInit)
1056 {
1057 case VERR_VMX_IN_VMX_ROOT_MODE:
1058 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1059 case VERR_VMX_NO_VMX:
1060 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1061 case VERR_VMX_MSR_VMX_DISABLED:
1062 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1063 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1064 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1065 case VERR_VMX_MSR_LOCKING_FAILED:
1066 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1067 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1068 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1069 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1070 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1071
1072 case VERR_SVM_IN_USE:
1073 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1074 case VERR_SVM_NO_SVM:
1075 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1076 case VERR_SVM_DISABLED:
1077 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1078 }
1079 return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1080 }
1081
1082 /*
1083 * Enable VT-x or AMD-V on all host CPUs.
1084 */
1085 rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1086 if (RT_FAILURE(rc))
1087 {
1088 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1089 HMR3CheckError(pVM, rc);
1090 return rc;
1091 }
1092
1093 /*
1094 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1095 * (Main should have taken care of this already)
1096 */
1097 if (!PDMHasIoApic(pVM))
1098 {
1099 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1100 pVM->hm.s.fTprPatchingAllowed = false;
1101 }
1102
1103 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1104 pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1105 pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1106
1107 /*
1108 * Do the vendor specific initialization
1109 *
1110 * Note! We disable release log buffering here since we're doing relatively
1111 * lot of logging and doesn't want to hit the disk with each LogRel
1112 * statement.
1113 */
1114 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1115 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1116 if (pVM->hm.s.vmx.fSupported)
1117 rc = hmR3InitFinalizeR0Intel(pVM);
1118 else
1119 rc = hmR3InitFinalizeR0Amd(pVM);
1120 LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1121 : "HM: VT-x/AMD-V init method: Local\n"));
1122 RTLogRelSetBuffering(fOldBuffered);
1123 pVM->hm.s.fInitialized = true;
1124
1125 return rc;
1126}
1127
1128
1129/**
1130 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1131 */
1132static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1133{
1134 NOREF(pVM);
1135 NOREF(pvAllocation);
1136 NOREF(GCPhysAllocation);
1137}
1138
1139
1140/**
1141 * Returns a description of the VMCS (and associated regions') memory type given the
1142 * IA32_VMX_BASIC MSR.
1143 *
1144 * @returns The descriptive memory type.
1145 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1146 */
1147static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1148{
1149 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1150 switch (uMemType)
1151 {
1152 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1153 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1154 }
1155 return "Unknown";
1156}
1157
1158
1159/**
1160 * Returns a single-line description of all the activity-states supported by the CPU
1161 * given the IA32_VMX_MISC MSR.
1162 *
1163 * @returns All supported activity states.
1164 * @param uMsrMisc IA32_VMX_MISC MSR value.
1165 */
1166static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1167{
1168 static const char * const s_apszActStates[] =
1169 {
1170 "",
1171 " ( HLT )",
1172 " ( SHUTDOWN )",
1173 " ( HLT SHUTDOWN )",
1174 " ( SIPI_WAIT )",
1175 " ( HLT SIPI_WAIT )",
1176 " ( SHUTDOWN SIPI_WAIT )",
1177 " ( HLT SHUTDOWN SIPI_WAIT )"
1178 };
1179 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1180 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1181 return s_apszActStates[idxActStates];
1182}
1183
1184
1185/**
1186 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1187 *
1188 * @param fFeatMsr The feature control MSR value.
1189 */
1190static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1191{
1192 uint64_t const val = fFeatMsr;
1193 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1194 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1195 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1196 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1197 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1198 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1199 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1200 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1201 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1202 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1203 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1204 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1205 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1206 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1207 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1208 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1209 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1210}
1211
1212
1213/**
1214 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1215 *
1216 * @param uBasicMsr The VMX basic MSR value.
1217 */
1218static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1219{
1220 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1221 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1222 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1223 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1224 "< 4 GB" : "None"));
1225 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1226 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1227 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1228 LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1229 LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1230}
1231
1232
1233/**
1234 * Reports MSR_IA32_PINBASED_CTLS to the log.
1235 *
1236 * @param pVmxMsr Pointer to the VMX MSR.
1237 */
1238static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1239{
1240 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1241 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1242 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1243 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1244 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1245 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1246 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1247 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1248}
1249
1250
1251/**
1252 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1253 *
1254 * @param pVmxMsr Pointer to the VMX MSR.
1255 */
1256static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1257{
1258 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1259 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1260 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1261 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1262 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1263 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1264 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1265 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1266 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1267 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1268 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1269 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1270 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1271 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1272 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1273 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1274 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1275 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1276 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1277 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1278 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1279 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1280 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1281 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1282 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1283}
1284
1285
1286/**
1287 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1288 *
1289 * @param pVmxMsr Pointer to the VMX MSR.
1290 */
1291static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1292{
1293 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1294 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1295 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1296 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1297 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1298 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1299 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1300 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1301 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1302 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1303 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1304 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1305 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1306 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1307 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1308 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1309 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1310 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1311 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1312 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1313 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1314 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1315 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1316 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1317 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1318 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1319 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1320 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1321 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1322 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1323}
1324
1325
1326/**
1327 * Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1328 *
1329 * @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1330 */
1331static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1332{
1333 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1334 LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1335}
1336
1337
1338/**
1339 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1340 *
1341 * @param pVmxMsr Pointer to the VMX MSR.
1342 */
1343static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1344{
1345 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1346 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1347 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1348 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1349 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1350 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1351 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1352 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1353 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1354 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1355 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1356 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1357 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1358 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1359 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1360}
1361
1362
1363/**
1364 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1365 *
1366 * @param pVmxMsr Pointer to the VMX MSR.
1367 */
1368static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1369{
1370 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1371 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1372 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1373 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1374 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1375 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1376 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1377 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1378 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1379 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1380 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1381 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1382 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1383 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1384 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1385 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1386 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1387}
1388
1389
1390/**
1391 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1392 *
1393 * @param fCaps The VMX EPT/VPID capability MSR value.
1394 */
1395static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1396{
1397 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1398 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1399 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1400 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1401 HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1402 HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1403 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1404 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1405 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1406 HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1407 HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1408 HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1409 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1410 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1411 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1412 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1413 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1414 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1415 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1416}
1417
1418
1419/**
1420 * Reports MSR_IA32_VMX_MISC MSR to the log.
1421 *
1422 * @param pVM Pointer to the VM.
1423 * @param fMisc The VMX misc. MSR value.
1424 */
1425static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1426{
1427 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1428 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1429 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1430 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1431 else
1432 {
1433 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1434 pVM->hm.s.vmx.cPreemptTimerShift));
1435 }
1436 LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1437 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1438 hmR3VmxGetActivityStateAllDesc(fMisc)));
1439 LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1440 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1441 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1442 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1443 VMX_MISC_MAX_MSRS(fMisc)));
1444 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1445 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1446 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1447 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1448}
1449
1450
1451/**
1452 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1453 *
1454 * @param uVmcsEnum The VMX VMCS enum MSR value.
1455 */
1456static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1457{
1458 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1459 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1460}
1461
1462
1463/**
1464 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1465 *
1466 * @param uVmFunc The VMX VMFUNC MSR value.
1467 */
1468static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1469{
1470 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1471 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1472}
1473
1474
1475/**
1476 * Reports VMX CR0, CR4 fixed MSRs.
1477 *
1478 * @param pMsrs Pointer to the VMX MSRs.
1479 */
1480static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1481{
1482 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1483 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1484 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1485 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1486}
1487
1488
1489/**
1490 * Finish VT-x initialization (after ring-0 init).
1491 *
1492 * @returns VBox status code.
1493 * @param pVM The cross context VM structure.
1494 */
1495static int hmR3InitFinalizeR0Intel(PVM pVM)
1496{
1497 int rc;
1498
1499 LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1500 AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1501
1502 LogRel(("HM: Using VT-x implementation 3.0\n"));
1503 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1504 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1505 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1506 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1507
1508 hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1509 hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1510
1511 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1512 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1513 if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1514 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1515 if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1516 hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1517
1518 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1519 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1520
1521 if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1522 {
1523 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1524 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1525 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1526 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1527 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1528 }
1529
1530 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1531 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1532 if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1533 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1534 if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1535 hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1536 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1537
1538#ifdef TODO_9217_VMCSINFO
1539 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1540 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1541 {
1542 PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1543 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1544 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1545 }
1546#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1547 if (pVM->cpum.ro.GuestFeatures.fVmx)
1548 {
1549 LogRel(("HM: Nested-guest:\n"));
1550 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1551 {
1552 PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1553 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1554 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1555 }
1556 }
1557#endif
1558#endif /* TODO_9217_VMCSINFO */
1559
1560 /*
1561 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1562 */
1563 AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1564 || (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1565 VERR_HM_IPE_1);
1566 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1567 || ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1568 && pVM->hm.s.fNestedPagingCfg),
1569 VERR_HM_IPE_1);
1570
1571 /*
1572 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1573 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1574 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1575 */
1576 if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1577 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1578 {
1579 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1580 LogRel(("HM: Disabled RDTSCP\n"));
1581 }
1582
1583 if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1584 {
1585 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1586 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1587 if (RT_SUCCESS(rc))
1588 {
1589 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1590 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1591 esp. Figure 20-5.*/
1592 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1593 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1594
1595 /* Bit set to 0 means software interrupts are redirected to the
1596 8086 program interrupt handler rather than switching to
1597 protected-mode handler. */
1598 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1599
1600 /* Allow all port IO, so that port IO instructions do not cause
1601 exceptions and would instead cause a VM-exit (based on VT-x's
1602 IO bitmap which we currently configure to always cause an exit). */
1603 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1604 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1605
1606 /*
1607 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1608 * page table used in real and protected mode without paging with EPT.
1609 */
1610 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1611 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1612 {
1613 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1614 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1615 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1616 | X86_PDE4M_G;
1617 }
1618
1619 /* We convert it here every time as PCI regions could be reconfigured. */
1620 if (PDMVmmDevHeapIsEnabled(pVM))
1621 {
1622 RTGCPHYS GCPhys;
1623 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1624 AssertRCReturn(rc, rc);
1625 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1626
1627 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1628 AssertRCReturn(rc, rc);
1629 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1630 }
1631 }
1632 else
1633 {
1634 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1635 pVM->hm.s.vmx.pRealModeTSS = NULL;
1636 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1637 return VMSetError(pVM, rc, RT_SRC_POS,
1638 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1639 }
1640 }
1641
1642 LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1643 : "HM: Guest support: 32-bit only\n"));
1644
1645 /*
1646 * Call ring-0 to set up the VM.
1647 */
1648 rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1649 if (rc != VINF_SUCCESS)
1650 {
1651 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1652 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1653 {
1654 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1655 LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1656 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1657 }
1658 HMR3CheckError(pVM, rc);
1659 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1660 }
1661
1662 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1663 LogRel(("HM: Enabled VMX\n"));
1664 pVM->hm.s.vmx.fEnabled = true;
1665
1666 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1667
1668 /*
1669 * Change the CPU features.
1670 */
1671 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1672 if (pVM->hm.s.fAllow64BitGuestsCfg)
1673 {
1674 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1675 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1676 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1677 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1678 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1679 }
1680 /* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1681 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1682 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1683
1684 /*
1685 * Log configuration details.
1686 */
1687 if (pVM->hm.s.fNestedPagingCfg)
1688 {
1689 LogRel(("HM: Enabled nested paging\n"));
1690 if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1691 LogRel(("HM: EPT flush type = Single context\n"));
1692 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1693 LogRel(("HM: EPT flush type = All contexts\n"));
1694 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1695 LogRel(("HM: EPT flush type = Not supported\n"));
1696 else
1697 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1698
1699 if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1700 LogRel(("HM: Enabled unrestricted guest execution\n"));
1701
1702 if (pVM->hm.s.fLargePages)
1703 {
1704 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1705 PGMSetLargePageUsage(pVM, true);
1706 LogRel(("HM: Enabled large page support\n"));
1707 }
1708 }
1709 else
1710 Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1711
1712 if (pVM->hm.s.ForR3.vmx.fVpid)
1713 {
1714 LogRel(("HM: Enabled VPID\n"));
1715 if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1716 LogRel(("HM: VPID flush type = Individual addresses\n"));
1717 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1718 LogRel(("HM: VPID flush type = Single context\n"));
1719 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1720 LogRel(("HM: VPID flush type = All contexts\n"));
1721 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1722 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1723 else
1724 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1725 }
1726 else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1727 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1728
1729 if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1730 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1731 else
1732 LogRel(("HM: Disabled VMX-preemption timer\n"));
1733
1734 if (pVM->hm.s.fVirtApicRegs)
1735 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1736
1737 if (pVM->hm.s.fPostedIntrs)
1738 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1739
1740 if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1741 {
1742 bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1743 LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1744 }
1745
1746 return VINF_SUCCESS;
1747}
1748
1749
1750/**
1751 * Finish AMD-V initialization (after ring-0 init).
1752 *
1753 * @returns VBox status code.
1754 * @param pVM The cross context VM structure.
1755 */
1756static int hmR3InitFinalizeR0Amd(PVM pVM)
1757{
1758 LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1759
1760 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1761
1762 uint32_t u32Family;
1763 uint32_t u32Model;
1764 uint32_t u32Stepping;
1765 if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1766 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1767 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1768 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1769 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1770 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1771 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1772
1773 /*
1774 * Enumerate AMD-V features.
1775 */
1776 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1777 {
1778#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1779 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1780 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1781 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1782 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1783 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1784 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1785 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1786 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1787 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1788 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1789 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1790 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1791 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1792 HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1793#undef HMSVM_REPORT_FEATURE
1794 };
1795
1796 uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1797 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1798 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1799 {
1800 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1801 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1802 }
1803 if (fSvmFeatures)
1804 for (unsigned iBit = 0; iBit < 32; iBit++)
1805 if (RT_BIT_32(iBit) & fSvmFeatures)
1806 LogRel(("HM: Reserved bit %u\n", iBit));
1807
1808 /*
1809 * Nested paging is determined in HMR3Init, verify the sanity of that.
1810 */
1811 AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1812 || (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1813 VERR_HM_IPE_1);
1814
1815#if 0
1816 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1817 * here. */
1818 if (RTR0IsPostIpiSupport())
1819 pVM->hm.s.fPostedIntrs = true;
1820#endif
1821
1822 /*
1823 * Determine whether we need to intercept #UD in SVM mode for emulating
1824 * intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1825 * when executed in long-mode. This is only really applicable when
1826 * non-default CPU profiles are in effect, i.e. guest vendor differs
1827 * from the host one.
1828 */
1829 if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1830 switch (CPUMGetGuestCpuVendor(pVM))
1831 {
1832 case CPUMCPUVENDOR_INTEL:
1833 case CPUMCPUVENDOR_VIA: /*?*/
1834 case CPUMCPUVENDOR_SHANGHAI: /*?*/
1835 switch (CPUMGetHostCpuVendor(pVM))
1836 {
1837 case CPUMCPUVENDOR_AMD:
1838 case CPUMCPUVENDOR_HYGON:
1839 if (pVM->hm.s.fAllow64BitGuestsCfg)
1840 {
1841 LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1842 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1843 pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1844 }
1845 break;
1846 default: break;
1847 }
1848 default: break;
1849 }
1850
1851 /*
1852 * Call ring-0 to set up the VM.
1853 */
1854 int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1855 if (rc != VINF_SUCCESS)
1856 {
1857 AssertMsgFailed(("%Rrc\n", rc));
1858 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1859 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1860 }
1861
1862 LogRel(("HM: Enabled SVM\n"));
1863 pVM->hm.s.svm.fEnabled = true;
1864
1865 if (pVM->hm.s.fNestedPagingCfg)
1866 {
1867 LogRel(("HM: Enabled nested paging\n"));
1868
1869 /*
1870 * Enable large pages (2 MB) if applicable.
1871 */
1872 if (pVM->hm.s.fLargePages)
1873 {
1874 PGMSetLargePageUsage(pVM, true);
1875 LogRel(("HM: Enabled large page support\n"));
1876 }
1877 }
1878
1879 if (pVM->hm.s.fVirtApicRegs)
1880 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1881
1882 if (pVM->hm.s.fPostedIntrs)
1883 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1884
1885 hmR3DisableRawMode(pVM);
1886
1887 /*
1888 * Change the CPU features.
1889 */
1890 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1891 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1892 if (pVM->hm.s.fAllow64BitGuestsCfg)
1893 {
1894 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1895 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1896 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1897 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1898 }
1899 /* Turn on NXE if PAE has been enabled. */
1900 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1901 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1902
1903 LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1904 : "HM: Disabled TPR patching\n"));
1905
1906 LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1907 : "HM: Guest support: 32-bit only\n"));
1908 return VINF_SUCCESS;
1909}
1910
1911
1912/**
1913 * Applies relocations to data and code managed by this
1914 * component. This function will be called at init and
1915 * whenever the VMM need to relocate it self inside the GC.
1916 *
1917 * @param pVM The cross context VM structure.
1918 */
1919VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1920{
1921 /* Fetch the current paging mode during the relocate callback during state loading. */
1922 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1923 {
1924 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1925 {
1926 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1927 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1928 }
1929 }
1930}
1931
1932
1933/**
1934 * Terminates the HM.
1935 *
1936 * Termination means cleaning up and freeing all resources,
1937 * the VM itself is, at this point, powered off or suspended.
1938 *
1939 * @returns VBox status code.
1940 * @param pVM The cross context VM structure.
1941 */
1942VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1943{
1944 if (pVM->hm.s.vmx.pRealModeTSS)
1945 {
1946 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1947 pVM->hm.s.vmx.pRealModeTSS = 0;
1948 }
1949 hmR3TermCPU(pVM);
1950 return 0;
1951}
1952
1953
1954/**
1955 * Terminates the per-VCPU HM.
1956 *
1957 * @returns VBox status code.
1958 * @param pVM The cross context VM structure.
1959 */
1960static int hmR3TermCPU(PVM pVM)
1961{
1962 RT_NOREF(pVM);
1963 return VINF_SUCCESS;
1964}
1965
1966
1967/**
1968 * Resets a virtual CPU.
1969 *
1970 * Used by HMR3Reset and CPU hot plugging.
1971 *
1972 * @param pVCpu The cross context virtual CPU structure to reset.
1973 */
1974VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1975{
1976 /* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
1977 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1978 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
1979
1980 pVCpu->hm.s.fActive = false;
1981 pVCpu->hm.s.Event.fPending = false;
1982 pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
1983 pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
1984#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1985 if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
1986 pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
1987#endif
1988}
1989
1990
1991/**
1992 * The VM is being reset.
1993 *
1994 * For the HM component this means that any GDT/LDT/TSS monitors
1995 * needs to be removed.
1996 *
1997 * @param pVM The cross context VM structure.
1998 */
1999VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2000{
2001 LogFlow(("HMR3Reset:\n"));
2002
2003 if (HMIsEnabled(pVM))
2004 hmR3DisableRawMode(pVM);
2005
2006 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2007 HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2008
2009 /* Clear all patch information. */
2010 pVM->hm.s.pGuestPatchMem = 0;
2011 pVM->hm.s.pFreeGuestPatchMem = 0;
2012 pVM->hm.s.cbGuestPatchMem = 0;
2013 pVM->hm.s.cPatches = 0;
2014 pVM->hm.s.PatchTree = 0;
2015 pVM->hm.s.fTprPatchingActive = false;
2016 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2017}
2018
2019
2020/**
2021 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2022 *
2023 * @returns VBox strict status code.
2024 * @param pVM The cross context VM structure.
2025 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2026 * @param pvUser Unused.
2027 */
2028static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2029{
2030 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2031
2032 /* Only execute the handler on the VCPU the original patch request was issued. */
2033 if (pVCpu->idCpu != idCpu)
2034 return VINF_SUCCESS;
2035
2036 Log(("hmR3RemovePatches\n"));
2037 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2038 {
2039 uint8_t abInstr[15];
2040 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2041 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2042 int rc;
2043
2044#ifdef LOG_ENABLED
2045 char szOutput[256];
2046 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2047 szOutput, sizeof(szOutput), NULL);
2048 if (RT_SUCCESS(rc))
2049 Log(("Patched instr: %s\n", szOutput));
2050#endif
2051
2052 /* Check if the instruction is still the same. */
2053 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2054 if (rc != VINF_SUCCESS)
2055 {
2056 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2057 continue; /* swapped out or otherwise removed; skip it. */
2058 }
2059
2060 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2061 {
2062 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2063 continue; /* skip it. */
2064 }
2065
2066 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2067 AssertRC(rc);
2068
2069#ifdef LOG_ENABLED
2070 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2071 szOutput, sizeof(szOutput), NULL);
2072 if (RT_SUCCESS(rc))
2073 Log(("Original instr: %s\n", szOutput));
2074#endif
2075 }
2076 pVM->hm.s.cPatches = 0;
2077 pVM->hm.s.PatchTree = 0;
2078 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2079 pVM->hm.s.fTprPatchingActive = false;
2080 return VINF_SUCCESS;
2081}
2082
2083
2084/**
2085 * Worker for enabling patching in a VT-x/AMD-V guest.
2086 *
2087 * @returns VBox status code.
2088 * @param pVM The cross context VM structure.
2089 * @param idCpu VCPU to execute hmR3RemovePatches on.
2090 * @param pPatchMem Patch memory range.
2091 * @param cbPatchMem Size of the memory range.
2092 */
2093static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2094{
2095 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2096 AssertRC(rc);
2097
2098 pVM->hm.s.pGuestPatchMem = pPatchMem;
2099 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2100 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2101 return VINF_SUCCESS;
2102}
2103
2104
2105/**
2106 * Enable patching in a VT-x/AMD-V guest
2107 *
2108 * @returns VBox status code.
2109 * @param pVM The cross context VM structure.
2110 * @param pPatchMem Patch memory range.
2111 * @param cbPatchMem Size of the memory range.
2112 */
2113VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2114{
2115 VM_ASSERT_EMT(pVM);
2116 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2117 if (pVM->cCpus > 1)
2118 {
2119 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2120 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2121 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2122 AssertRC(rc);
2123 return rc;
2124 }
2125 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2126}
2127
2128
2129/**
2130 * Disable patching in a VT-x/AMD-V guest.
2131 *
2132 * @returns VBox status code.
2133 * @param pVM The cross context VM structure.
2134 * @param pPatchMem Patch memory range.
2135 * @param cbPatchMem Size of the memory range.
2136 */
2137VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2138{
2139 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2140 RT_NOREF2(pPatchMem, cbPatchMem);
2141
2142 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2143 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2144
2145 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2146 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2147 (void *)(uintptr_t)VMMGetCpuId(pVM));
2148 AssertRC(rc);
2149
2150 pVM->hm.s.pGuestPatchMem = 0;
2151 pVM->hm.s.pFreeGuestPatchMem = 0;
2152 pVM->hm.s.cbGuestPatchMem = 0;
2153 pVM->hm.s.fTprPatchingActive = false;
2154 return VINF_SUCCESS;
2155}
2156
2157
2158/**
2159 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2160 *
2161 * @returns VBox strict status code.
2162 * @param pVM The cross context VM structure.
2163 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2164 * @param pvUser User specified CPU context.
2165 *
2166 */
2167static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2168{
2169 /*
2170 * Only execute the handler on the VCPU the original patch request was
2171 * issued. (The other CPU(s) might not yet have switched to protected
2172 * mode, nor have the correct memory context.)
2173 */
2174 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2175 if (pVCpu->idCpu != idCpu)
2176 return VINF_SUCCESS;
2177
2178 /*
2179 * We're racing other VCPUs here, so don't try patch the instruction twice
2180 * and make sure there is still room for our patch record.
2181 */
2182 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2183 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2184 if (pPatch)
2185 {
2186 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2187 return VINF_SUCCESS;
2188 }
2189 uint32_t const idx = pVM->hm.s.cPatches;
2190 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2191 {
2192 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2193 return VINF_SUCCESS;
2194 }
2195 pPatch = &pVM->hm.s.aPatches[idx];
2196
2197 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2198
2199 /*
2200 * Disassembler the instruction and get cracking.
2201 */
2202 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2203 DISCPUSTATE Dis;
2204 uint32_t cbOp;
2205 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2206 AssertRC(rc);
2207 if ( rc == VINF_SUCCESS
2208 && Dis.pCurInstr->uOpcode == OP_MOV
2209 && cbOp >= 3)
2210 {
2211 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2212
2213 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2214 AssertRC(rc);
2215
2216 pPatch->cbOp = cbOp;
2217
2218 if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2219 {
2220 /* write. */
2221 if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2222 {
2223 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2224 pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2225 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2226 }
2227 else
2228 {
2229 Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2230 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2231 pPatch->uSrcOperand = Dis.Param2.uValue;
2232 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2233 }
2234 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2235 AssertRC(rc);
2236
2237 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2238 pPatch->cbNewOp = sizeof(s_abVMMCall);
2239 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2240 }
2241 else
2242 {
2243 /*
2244 * TPR Read.
2245 *
2246 * Found:
2247 * mov eax, dword [fffe0080] (5 bytes)
2248 * Check if next instruction is:
2249 * shr eax, 4
2250 */
2251 Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2252
2253 uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2254 uint8_t const cbOpMmio = cbOp;
2255 uint64_t const uSavedRip = pCtx->rip;
2256
2257 pCtx->rip += cbOp;
2258 rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2259 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2260 pCtx->rip = uSavedRip;
2261
2262 if ( rc == VINF_SUCCESS
2263 && Dis.pCurInstr->uOpcode == OP_SHR
2264 && Dis.Param1.fUse == DISUSE_REG_GEN32
2265 && Dis.Param1.Base.idxGenReg == idxMmioReg
2266 && Dis.Param2.fUse == DISUSE_IMMEDIATE8
2267 && Dis.Param2.uValue == 4
2268 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2269 {
2270 uint8_t abInstr[15];
2271
2272 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2273 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2274 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2275 AssertRC(rc);
2276
2277 pPatch->cbOp = cbOpMmio + cbOp;
2278
2279 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2280 abInstr[0] = 0xf0;
2281 abInstr[1] = 0x0f;
2282 abInstr[2] = 0x20;
2283 abInstr[3] = 0xc0 | Dis.Param1.Base.idxGenReg;
2284 for (unsigned i = 4; i < pPatch->cbOp; i++)
2285 abInstr[i] = 0x90; /* nop */
2286
2287 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2288 AssertRC(rc);
2289
2290 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2291 pPatch->cbNewOp = pPatch->cbOp;
2292 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2293
2294 Log(("Acceptable read/shr candidate!\n"));
2295 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2296 }
2297 else
2298 {
2299 pPatch->enmType = HMTPRINSTR_READ;
2300 pPatch->uDstOperand = idxMmioReg;
2301
2302 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2303 AssertRC(rc);
2304
2305 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2306 pPatch->cbNewOp = sizeof(s_abVMMCall);
2307 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2308 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2309 }
2310 }
2311
2312 pPatch->Core.Key = pCtx->eip;
2313 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2314 AssertRC(rc);
2315
2316 pVM->hm.s.cPatches++;
2317 return VINF_SUCCESS;
2318 }
2319
2320 /*
2321 * Save invalid patch, so we will not try again.
2322 */
2323 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2324 pPatch->Core.Key = pCtx->eip;
2325 pPatch->enmType = HMTPRINSTR_INVALID;
2326 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2327 AssertRC(rc);
2328 pVM->hm.s.cPatches++;
2329 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2330 return VINF_SUCCESS;
2331}
2332
2333
2334/**
2335 * Callback to patch a TPR instruction (jump to generated code).
2336 *
2337 * @returns VBox strict status code.
2338 * @param pVM The cross context VM structure.
2339 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2340 * @param pvUser User specified CPU context.
2341 *
2342 */
2343static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2344{
2345 /*
2346 * Only execute the handler on the VCPU the original patch request was
2347 * issued. (The other CPU(s) might not yet have switched to protected
2348 * mode, nor have the correct memory context.)
2349 */
2350 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2351 if (pVCpu->idCpu != idCpu)
2352 return VINF_SUCCESS;
2353
2354 /*
2355 * We're racing other VCPUs here, so don't try patch the instruction twice
2356 * and make sure there is still room for our patch record.
2357 */
2358 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2359 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2360 if (pPatch)
2361 {
2362 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2363 return VINF_SUCCESS;
2364 }
2365 uint32_t const idx = pVM->hm.s.cPatches;
2366 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2367 {
2368 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2369 return VINF_SUCCESS;
2370 }
2371 pPatch = &pVM->hm.s.aPatches[idx];
2372
2373 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2374 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2375
2376 /*
2377 * Disassemble the instruction and get cracking.
2378 */
2379 DISCPUSTATE Dis;
2380 uint32_t cbOp;
2381 int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2382 AssertRC(rc);
2383 if ( rc == VINF_SUCCESS
2384 && Dis.pCurInstr->uOpcode == OP_MOV
2385 && cbOp >= 5)
2386 {
2387 uint8_t aPatch[64];
2388 uint32_t off = 0;
2389
2390 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2391 AssertRC(rc);
2392
2393 pPatch->cbOp = cbOp;
2394 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2395
2396 if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2397 {
2398 /*
2399 * TPR write:
2400 *
2401 * push ECX [51]
2402 * push EDX [52]
2403 * push EAX [50]
2404 * xor EDX,EDX [31 D2]
2405 * mov EAX,EAX [89 C0]
2406 * or
2407 * mov EAX,0000000CCh [B8 CC 00 00 00]
2408 * mov ECX,0C0000082h [B9 82 00 00 C0]
2409 * wrmsr [0F 30]
2410 * pop EAX [58]
2411 * pop EDX [5A]
2412 * pop ECX [59]
2413 * jmp return_address [E9 return_address]
2414 */
2415 bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2416
2417 aPatch[off++] = 0x51; /* push ecx */
2418 aPatch[off++] = 0x52; /* push edx */
2419 if (!fUsesEax)
2420 aPatch[off++] = 0x50; /* push eax */
2421 aPatch[off++] = 0x31; /* xor edx, edx */
2422 aPatch[off++] = 0xd2;
2423 if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2424 {
2425 if (!fUsesEax)
2426 {
2427 aPatch[off++] = 0x89; /* mov eax, src_reg */
2428 aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2429 }
2430 }
2431 else
2432 {
2433 Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2434 aPatch[off++] = 0xb8; /* mov eax, immediate */
2435 *(uint32_t *)&aPatch[off] = Dis.Param2.uValue;
2436 off += sizeof(uint32_t);
2437 }
2438 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2439 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2440 off += sizeof(uint32_t);
2441
2442 aPatch[off++] = 0x0f; /* wrmsr */
2443 aPatch[off++] = 0x30;
2444 if (!fUsesEax)
2445 aPatch[off++] = 0x58; /* pop eax */
2446 aPatch[off++] = 0x5a; /* pop edx */
2447 aPatch[off++] = 0x59; /* pop ecx */
2448 }
2449 else
2450 {
2451 /*
2452 * TPR read:
2453 *
2454 * push ECX [51]
2455 * push EDX [52]
2456 * push EAX [50]
2457 * mov ECX,0C0000082h [B9 82 00 00 C0]
2458 * rdmsr [0F 32]
2459 * mov EAX,EAX [89 C0]
2460 * pop EAX [58]
2461 * pop EDX [5A]
2462 * pop ECX [59]
2463 * jmp return_address [E9 return_address]
2464 */
2465 Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2466
2467 if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2468 aPatch[off++] = 0x51; /* push ecx */
2469 if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2470 aPatch[off++] = 0x52; /* push edx */
2471 if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2472 aPatch[off++] = 0x50; /* push eax */
2473
2474 aPatch[off++] = 0x31; /* xor edx, edx */
2475 aPatch[off++] = 0xd2;
2476
2477 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2478 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2479 off += sizeof(uint32_t);
2480
2481 aPatch[off++] = 0x0f; /* rdmsr */
2482 aPatch[off++] = 0x32;
2483
2484 if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2485 {
2486 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2487 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2488 }
2489
2490 if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2491 aPatch[off++] = 0x58; /* pop eax */
2492 if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2493 aPatch[off++] = 0x5a; /* pop edx */
2494 if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2495 aPatch[off++] = 0x59; /* pop ecx */
2496 }
2497 aPatch[off++] = 0xe9; /* jmp return_address */
2498 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2499 off += sizeof(RTRCUINTPTR);
2500
2501 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2502 {
2503 /* Write new code to the patch buffer. */
2504 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2505 AssertRC(rc);
2506
2507#ifdef LOG_ENABLED
2508 uint32_t cbCurInstr;
2509 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2510 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2511 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2512 {
2513 char szOutput[256];
2514 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2515 szOutput, sizeof(szOutput), &cbCurInstr);
2516 if (RT_SUCCESS(rc))
2517 Log(("Patch instr %s\n", szOutput));
2518 else
2519 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2520 }
2521#endif
2522
2523 pPatch->aNewOpcode[0] = 0xE9;
2524 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2525
2526 /* Overwrite the TPR instruction with a jump. */
2527 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2528 AssertRC(rc);
2529
2530 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2531
2532 pVM->hm.s.pFreeGuestPatchMem += off;
2533 pPatch->cbNewOp = 5;
2534
2535 pPatch->Core.Key = pCtx->eip;
2536 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2537 AssertRC(rc);
2538
2539 pVM->hm.s.cPatches++;
2540 pVM->hm.s.fTprPatchingActive = true;
2541 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2542 return VINF_SUCCESS;
2543 }
2544
2545 Log(("Ran out of space in our patch buffer!\n"));
2546 }
2547 else
2548 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2549
2550
2551 /*
2552 * Save invalid patch, so we will not try again.
2553 */
2554 pPatch = &pVM->hm.s.aPatches[idx];
2555 pPatch->Core.Key = pCtx->eip;
2556 pPatch->enmType = HMTPRINSTR_INVALID;
2557 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2558 AssertRC(rc);
2559 pVM->hm.s.cPatches++;
2560 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2561 return VINF_SUCCESS;
2562}
2563
2564
2565/**
2566 * Attempt to patch TPR mmio instructions.
2567 *
2568 * @returns VBox status code.
2569 * @param pVM The cross context VM structure.
2570 * @param pVCpu The cross context virtual CPU structure.
2571 */
2572VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2573{
2574 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2575 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2576 (void *)(uintptr_t)pVCpu->idCpu);
2577 AssertRC(rc);
2578 return rc;
2579}
2580
2581
2582/**
2583 * Checks if we need to reschedule due to VMM device heap changes.
2584 *
2585 * @returns true if a reschedule is required, otherwise false.
2586 * @param pVM The cross context VM structure.
2587 * @param pCtx VM execution context.
2588 */
2589VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2590{
2591 /*
2592 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2593 * when the unrestricted guest execution feature is missing (VT-x only).
2594 */
2595 if ( pVM->hm.s.vmx.fEnabled
2596 && !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2597 && CPUMIsGuestInRealModeEx(pCtx)
2598 && !PDMVmmDevHeapIsEnabled(pVM))
2599 return true;
2600
2601 return false;
2602}
2603
2604
2605/**
2606 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2607 * event settings changes.
2608 *
2609 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2610 * function is just updating the VM globals.
2611 *
2612 * @param pVM The VM cross context VM structure.
2613 * @thread EMT(0)
2614 */
2615VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2616{
2617 /* Interrupts. */
2618 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2619 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2620
2621 /* CPU Exceptions. */
2622 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2623 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2624 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2625 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2626
2627 /* Common VM exits. */
2628 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2629 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2630 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2631 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2632
2633 /* Vendor specific VM exits. */
2634 if (HMR3IsVmxEnabled(pVM->pUVM))
2635 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2636 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2637 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2638 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2639 else
2640 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2641 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2642 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2643 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2644
2645 /* Done. */
2646 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2647}
2648
2649
2650/**
2651 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2652 *
2653 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2654 * per CPU settings.
2655 *
2656 * @param pVM The VM cross context VM structure.
2657 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2658 */
2659VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2660{
2661 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2662}
2663
2664
2665/**
2666 * Checks if we are currently using hardware acceleration.
2667 *
2668 * @returns true if hardware acceleration is being used, otherwise false.
2669 * @param pVCpu The cross context virtual CPU structure.
2670 */
2671VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2672{
2673 return pVCpu->hm.s.fActive;
2674}
2675
2676
2677/**
2678 * External interface for querying whether hardware acceleration is enabled.
2679 *
2680 * @returns true if VT-x or AMD-V is being used, otherwise false.
2681 * @param pUVM The user mode VM handle.
2682 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2683 */
2684VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2685{
2686 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2687 PVM pVM = pUVM->pVM;
2688 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2689 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2690}
2691
2692
2693/**
2694 * External interface for querying whether VT-x is being used.
2695 *
2696 * @returns true if VT-x is being used, otherwise false.
2697 * @param pUVM The user mode VM handle.
2698 * @sa HMR3IsSvmEnabled, HMIsEnabled
2699 */
2700VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2701{
2702 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2703 PVM pVM = pUVM->pVM;
2704 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2705 return pVM->hm.s.vmx.fEnabled
2706 && pVM->hm.s.vmx.fSupported
2707 && pVM->fHMEnabled;
2708}
2709
2710
2711/**
2712 * External interface for querying whether AMD-V is being used.
2713 *
2714 * @returns true if VT-x is being used, otherwise false.
2715 * @param pUVM The user mode VM handle.
2716 * @sa HMR3IsVmxEnabled, HMIsEnabled
2717 */
2718VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2719{
2720 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2721 PVM pVM = pUVM->pVM;
2722 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2723 return pVM->hm.s.svm.fEnabled
2724 && pVM->hm.s.svm.fSupported
2725 && pVM->fHMEnabled;
2726}
2727
2728
2729/**
2730 * Checks if we are currently using nested paging.
2731 *
2732 * @returns true if nested paging is being used, otherwise false.
2733 * @param pUVM The user mode VM handle.
2734 */
2735VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2736{
2737 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2738 PVM pVM = pUVM->pVM;
2739 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2740 return pVM->hm.s.fNestedPagingCfg;
2741}
2742
2743
2744/**
2745 * Checks if virtualized APIC registers are enabled.
2746 *
2747 * When enabled this feature allows the hardware to access most of the
2748 * APIC registers in the virtual-APIC page without causing VM-exits. See
2749 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2750 *
2751 * @returns true if virtualized APIC registers is enabled, otherwise
2752 * false.
2753 * @param pUVM The user mode VM handle.
2754 */
2755VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2756{
2757 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2758 PVM pVM = pUVM->pVM;
2759 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2760 return pVM->hm.s.fVirtApicRegs;
2761}
2762
2763
2764/**
2765 * Checks if APIC posted-interrupt processing is enabled.
2766 *
2767 * This returns whether we can deliver interrupts to the guest without
2768 * leaving guest-context by updating APIC state from host-context.
2769 *
2770 * @returns true if APIC posted-interrupt processing is enabled,
2771 * otherwise false.
2772 * @param pUVM The user mode VM handle.
2773 */
2774VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2775{
2776 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2777 PVM pVM = pUVM->pVM;
2778 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2779 return pVM->hm.s.fPostedIntrs;
2780}
2781
2782
2783/**
2784 * Checks if we are currently using VPID in VT-x mode.
2785 *
2786 * @returns true if VPID is being used, otherwise false.
2787 * @param pUVM The user mode VM handle.
2788 */
2789VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2790{
2791 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2792 PVM pVM = pUVM->pVM;
2793 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2794 return pVM->hm.s.ForR3.vmx.fVpid;
2795}
2796
2797
2798/**
2799 * Checks if we are currently using VT-x unrestricted execution,
2800 * aka UX.
2801 *
2802 * @returns true if UX is being used, otherwise false.
2803 * @param pUVM The user mode VM handle.
2804 */
2805VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2806{
2807 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2808 PVM pVM = pUVM->pVM;
2809 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2810 return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2811 || pVM->hm.s.svm.fSupported;
2812}
2813
2814
2815/**
2816 * Checks if the VMX-preemption timer is being used.
2817 *
2818 * @returns true if the VMX-preemption timer is being used, otherwise false.
2819 * @param pVM The cross context VM structure.
2820 */
2821VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2822{
2823 return HMIsEnabled(pVM)
2824 && pVM->hm.s.vmx.fEnabled
2825 && pVM->hm.s.vmx.fUsePreemptTimerCfg;
2826}
2827
2828
2829#ifdef TODO_9217_VMCSINFO
2830/**
2831 * Helper for HMR3CheckError to log VMCS controls to the release log.
2832 *
2833 * @param idCpu The Virtual CPU ID.
2834 * @param pVmcsInfo The VMCS info. object.
2835 */
2836static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2837{
2838 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2839 {
2840 uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2841 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2842 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2843 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2844 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2845 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2846 }
2847 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2848 {
2849 uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2850 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2851 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2852 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2853 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2854 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2855 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2856 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2857 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2858 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2859 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2860 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2861 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2862 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2863 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2864 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2865 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2866 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2867 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2868 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2869 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2870 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2871 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2872 }
2873 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2874 {
2875 uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2876 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2877 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2878 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2879 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2880 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2881 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2882 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2883 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2884 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2885 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2886 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2887 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2888 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2889 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2890 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2891 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2892 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2893 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2894 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2895 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2896 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2897 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2898 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2899 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2900 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2901 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2902 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2903 }
2904 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2905 {
2906 uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2907 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2908 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2909 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2910 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2911 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2912 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2913 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2914 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2915 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2916 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2917 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2918 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2919 }
2920 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2921 {
2922 uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2923 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2924 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2925 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2926 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2927 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2928 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2929 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2930 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2931 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2932 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2933 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2934 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2935 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
2936 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
2937 }
2938}
2939#endif
2940
2941
2942/**
2943 * Check fatal VT-x/AMD-V error and produce some meaningful
2944 * log release message.
2945 *
2946 * @param pVM The cross context VM structure.
2947 * @param iStatusCode VBox status code.
2948 */
2949VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2950{
2951 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2952 {
2953 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2954 * might be getting inaccurate values for non-guru'ing EMTs. */
2955 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2956#ifdef TODO_9217_VMCSINFO
2957 PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
2958#endif
2959 bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
2960 switch (iStatusCode)
2961 {
2962 case VERR_VMX_INVALID_VMCS_PTR:
2963 {
2964 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2965 LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2966#ifdef TODO_9217_VMCSINFO
2967 LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2968 pVmcsInfo->HCPhysVmcs));
2969#endif
2970 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2971 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2972 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2973 break;
2974 }
2975
2976 case VERR_VMX_UNABLE_TO_START_VM:
2977 {
2978 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2979 LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2980 LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
2981 LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2982
2983 if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
2984 || pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
2985 {
2986 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2987 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2988 }
2989 else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
2990 {
2991#ifdef TODO_9217_VMCSINFO
2992 hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
2993 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
2994 LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
2995 LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
2996 LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
2997 LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
2998 LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
2999 LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3000#endif
3001 }
3002 /** @todo Log VM-entry event injection control fields
3003 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3004 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3005 break;
3006 }
3007
3008 case VERR_VMX_INVALID_GUEST_STATE:
3009 {
3010 LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3011 LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3012 LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3013#ifdef TODO_9217_VMCSINFO
3014 hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3015#endif
3016 break;
3017 }
3018
3019 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3020 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3021 case VERR_VMX_INVALID_VMXON_PTR:
3022 case VERR_VMX_UNEXPECTED_EXIT:
3023 case VERR_VMX_INVALID_VMCS_FIELD:
3024 case VERR_SVM_UNKNOWN_EXIT:
3025 case VERR_SVM_UNEXPECTED_EXIT:
3026 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3027 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3028 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3029 break;
3030 }
3031 }
3032
3033 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3034 {
3035 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3036 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3037 }
3038 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3039 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3040}
3041
3042
3043/**
3044 * Execute state save operation.
3045 *
3046 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3047 * is because we always save the VM state from ring-3 and thus most HM state
3048 * will be re-synced dynamically at runtime and don't need to be part of the VM
3049 * saved state.
3050 *
3051 * @returns VBox status code.
3052 * @param pVM The cross context VM structure.
3053 * @param pSSM SSM operation handle.
3054 */
3055static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3056{
3057 Log(("hmR3Save:\n"));
3058
3059 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3060 {
3061 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3062 Assert(!pVCpu->hm.s.Event.fPending);
3063 if (pVM->cpum.ro.GuestFeatures.fSvm)
3064 {
3065 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3066 SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3067 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3068 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3069 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3070 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3071 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3072 SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3073 SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3074 SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3075 SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3076 SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3077 SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3078 SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3079 }
3080 }
3081
3082 /* Save the guest patch data. */
3083 SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3084 SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3085 SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3086
3087 /* Store all the guest patch records too. */
3088 int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3089 if (RT_FAILURE(rc))
3090 return rc;
3091
3092 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3093 {
3094 AssertCompileSize(HMTPRINSTR, 4);
3095 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3096 SSMR3PutU32(pSSM, pPatch->Core.Key);
3097 SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3098 SSMR3PutU32(pSSM, pPatch->cbOp);
3099 SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3100 SSMR3PutU32(pSSM, pPatch->cbNewOp);
3101 SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3102 SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3103 SSMR3PutU32(pSSM, pPatch->uDstOperand);
3104 SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3105 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3106 if (RT_FAILURE(rc))
3107 return rc;
3108 }
3109
3110 return VINF_SUCCESS;
3111}
3112
3113
3114/**
3115 * Execute state load operation.
3116 *
3117 * @returns VBox status code.
3118 * @param pVM The cross context VM structure.
3119 * @param pSSM SSM operation handle.
3120 * @param uVersion Data layout version.
3121 * @param uPass The data pass.
3122 */
3123static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3124{
3125 int rc;
3126
3127 LogFlowFunc(("uVersion=%u\n", uVersion));
3128 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3129
3130 /*
3131 * Validate version.
3132 */
3133 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3134 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3135 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3136 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3137 {
3138 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3139 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3140 }
3141
3142 /*
3143 * Load per-VCPU state.
3144 */
3145 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3146 {
3147 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3148 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3149 {
3150 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3151 if (pVM->cpum.ro.GuestFeatures.fSvm)
3152 {
3153 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3154 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3155 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3156 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3157 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3158 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3159 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3160 SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3161 SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3162 SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3163 SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3164 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3165 SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3166 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3167 AssertRCReturn(rc, rc);
3168 }
3169 }
3170 else
3171 {
3172 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3173 SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3174 SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3175 SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3176
3177 /* VMX fWasInRealMode related data. */
3178 uint32_t uDummy;
3179 SSMR3GetU32(pSSM, &uDummy);
3180 SSMR3GetU32(pSSM, &uDummy);
3181 rc = SSMR3GetU32(pSSM, &uDummy);
3182 AssertRCReturn(rc, rc);
3183 }
3184 }
3185
3186 /*
3187 * Load TPR patching data.
3188 */
3189 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3190 {
3191 SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3192 SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3193 SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3194
3195 /* Fetch all TPR patch records. */
3196 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3197 AssertRCReturn(rc, rc);
3198 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3199 {
3200 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3201 SSMR3GetU32(pSSM, &pPatch->Core.Key);
3202 SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3203 SSMR3GetU32(pSSM, &pPatch->cbOp);
3204 SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3205 SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3206 SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3207
3208 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3209 pVM->hm.s.fTprPatchingActive = true;
3210 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTprPatchingActive == false);
3211
3212 SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3213 SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3214 SSMR3GetU32(pSSM, &pPatch->cFaults);
3215 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3216 AssertRCReturn(rc, rc);
3217
3218 LogFlow(("hmR3Load: patch %d\n", i));
3219 LogFlow(("Key = %x\n", pPatch->Core.Key));
3220 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3221 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3222 LogFlow(("type = %d\n", pPatch->enmType));
3223 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3224 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3225 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3226 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3227
3228 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3229 AssertRCReturn(rc, rc);
3230 }
3231 }
3232
3233 return VINF_SUCCESS;
3234}
3235
3236
3237/**
3238 * Displays HM info.
3239 *
3240 * @param pVM The cross context VM structure.
3241 * @param pHlp The info helper functions.
3242 * @param pszArgs Arguments, ignored.
3243 */
3244static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3245{
3246 NOREF(pszArgs);
3247 PVMCPU pVCpu = VMMGetCpu(pVM);
3248 if (!pVCpu)
3249 pVCpu = pVM->apCpusR3[0];
3250
3251 if (HMIsEnabled(pVM))
3252 {
3253 if (pVM->hm.s.vmx.fSupported)
3254 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3255 else
3256 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3257 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3258 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3259 if (pVM->hm.s.vmx.fSupported)
3260 {
3261 PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3262 bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3263 bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3264
3265 pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3266 pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3267 if (fRealOnV86Active)
3268 {
3269 pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3270 pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3271 pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3272 pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3273 pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3274 pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3275 pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3276 }
3277 }
3278 }
3279 else
3280 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3281}
3282
3283
3284/**
3285 * Displays the HM Last-Branch-Record info. for the guest.
3286 *
3287 * @param pVM The cross context VM structure.
3288 * @param pHlp The info helper functions.
3289 * @param pszArgs Arguments, ignored.
3290 */
3291static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3292{
3293 NOREF(pszArgs);
3294 PVMCPU pVCpu = VMMGetCpu(pVM);
3295 if (!pVCpu)
3296 pVCpu = pVM->apCpusR3[0];
3297
3298 if (!HMIsEnabled(pVM))
3299 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3300 else if (HMIsVmxActive(pVM))
3301 {
3302 if (pVM->hm.s.vmx.fLbrCfg)
3303 {
3304 PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3305 uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3306
3307 /** @todo r=ramshankar: The index technically varies depending on the CPU, but
3308 * 0xf should cover everything we support thus far. Fix if necessary
3309 * later. */
3310 uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3311 if (idxTopOfStack > cLbrStack)
3312 {
3313 pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3314 idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3315 return;
3316 }
3317
3318 /*
3319 * Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3320 */
3321 pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3322 uint32_t idxCurrent = idxTopOfStack;
3323 Assert(idxTopOfStack < cLbrStack);
3324 Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3325 Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3326 for (;;)
3327 {
3328 if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3329 pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3330 pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3331 else
3332 pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3333
3334 idxCurrent = (idxCurrent - 1) % cLbrStack;
3335 if (idxCurrent == idxTopOfStack)
3336 break;
3337 }
3338 }
3339 else
3340 pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3341 }
3342 else
3343 {
3344 Assert(HMIsSvmActive(pVM));
3345 /** @todo SVM: LBRs (get them from VMCB if possible). */
3346 pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3347 }
3348}
3349
3350
3351/**
3352 * Displays the HM pending event.
3353 *
3354 * @param pVM The cross context VM structure.
3355 * @param pHlp The info helper functions.
3356 * @param pszArgs Arguments, ignored.
3357 */
3358static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3359{
3360 NOREF(pszArgs);
3361 PVMCPU pVCpu = VMMGetCpu(pVM);
3362 if (!pVCpu)
3363 pVCpu = pVM->apCpusR3[0];
3364
3365 if (HMIsEnabled(pVM))
3366 {
3367 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3368 if (pVCpu->hm.s.Event.fPending)
3369 {
3370 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3371 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3372 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3373 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3374 }
3375 }
3376 else
3377 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3378}
3379
3380
3381/**
3382 * Displays the SVM nested-guest VMCB cache.
3383 *
3384 * @param pVM The cross context VM structure.
3385 * @param pHlp The info helper functions.
3386 * @param pszArgs Arguments, ignored.
3387 */
3388static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3389{
3390 NOREF(pszArgs);
3391 PVMCPU pVCpu = VMMGetCpu(pVM);
3392 if (!pVCpu)
3393 pVCpu = pVM->apCpusR3[0];
3394
3395 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3396 if ( fSvmEnabled
3397 && pVM->cpum.ro.GuestFeatures.fSvm)
3398 {
3399 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3400 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3401 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3402 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3403 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3404 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3405 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3406 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3407 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3408 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3409 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3410 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3411 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3412 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3413 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3414 }
3415 else
3416 {
3417 if (!fSvmEnabled)
3418 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3419 else
3420 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3421 }
3422}
3423
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