HM.cpp@ 92676

Last change on this file since 92676 was 92556, checked in by vboxsync, 3 years ago
SUP,VMM: Added a fFlags parameter to SUPR3PageAlloc so we can indicate a desire for large pages and other things. HM must enable large pages when configred for the NEM code paths too. bugref:9044 bugref:5324
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File size: 155.6 KB

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1	/* $Id: HM.cpp 92556 2021-11-23 01:12:29Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/trpm.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/iom.h>
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#include <VBox/vmm/hm_vmx.h>
55	#include <VBox/vmm/hm_svm.h>
56	#include "HMInternal.h"
57	#include <VBox/vmm/vmcc.h>
58	#include <VBox/err.h>
59	#include <VBox/param.h>
60
61	#include <iprt/assert.h>
62	#include <VBox/log.h>
63	#include <iprt/asm.h>
64	#include <iprt/asm-amd64-x86.h>
65	#include <iprt/env.h>
66	#include <iprt/thread.h>
67
68
69	/*********************************************************************************************************************************
70	* Defined Constants And Macros *
71	*********************************************************************************************************************************/
72	/** @def HMVMX_REPORT_FEAT
73	* Reports VT-x feature to the release log.
74	*
75	* @param a_uAllowed1 Mask of allowed-1 feature bits.
76	* @param a_uAllowed0 Mask of allowed-0 feature bits.
77	* @param a_StrDesc The description string to report.
78	* @param a_Featflag Mask of the feature to report.
79	*/
80	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
81	do { \
82	if ((a_uAllowed1) & (a_Featflag)) \
83	{ \
84	if ((a_uAllowed0) & (a_Featflag)) \
85	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
86	else \
87	LogRel(("HM: " a_StrDesc "\n")); \
88	} \
89	else \
90	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
91	} while (0)
92
93	/** @def HMVMX_REPORT_ALLOWED_FEAT
94	* Reports an allowed VT-x feature to the release log.
95	*
96	* @param a_uAllowed1 Mask of allowed-1 feature bits.
97	* @param a_StrDesc The description string to report.
98	* @param a_FeatFlag Mask of the feature to report.
99	*/
100	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
101	do { \
102	if ((a_uAllowed1) & (a_FeatFlag)) \
103	LogRel(("HM: " a_StrDesc "\n")); \
104	else \
105	LogRel(("HM: " a_StrDesc " not supported\n")); \
106	} while (0)
107
108	/** @def HMVMX_REPORT_MSR_CAP
109	* Reports MSR feature capability.
110	*
111	* @param a_MsrCaps Mask of MSR feature bits.
112	* @param a_StrDesc The description string to report.
113	* @param a_fCap Mask of the feature to report.
114	*/
115	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
116	do { \
117	if ((a_MsrCaps) & (a_fCap)) \
118	LogRel(("HM: " a_StrDesc "\n")); \
119	} while (0)
120
121	/** @def HMVMX_LOGREL_FEAT
122	* Dumps a feature flag from a bitmap of features to the release log.
123	*
124	* @param a_fVal The value of all the features.
125	* @param a_fMask The specific bitmask of the feature.
126	*/
127	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
128	do { \
129	if ((a_fVal) & (a_fMask)) \
130	LogRel(("HM: %s\n", #a_fMask)); \
131	} while (0)
132
133
134	/*********************************************************************************************************************************
135	* Internal Functions *
136	*********************************************************************************************************************************/
137	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
138	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
139	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
140	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
141	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static int hmR3InitFinalizeR3(PVM pVM);
144	static int hmR3InitFinalizeR0(PVM pVM);
145	static int hmR3InitFinalizeR0Intel(PVM pVM);
146	static int hmR3InitFinalizeR0Amd(PVM pVM);
147	static int hmR3TermCPU(PVM pVM);
148
149
150	#ifdef VBOX_WITH_STATISTICS
151	/**
152	* Returns the name of the hardware exception.
153	*
154	* @returns The name of the hardware exception.
155	* @param uVector The exception vector.
156	*/
157	static const char *hmR3GetXcptName(uint8_t uVector)
158	{
159	switch (uVector)
160	{
161	case X86_XCPT_DE: return "#DE";
162	case X86_XCPT_DB: return "#DB";
163	case X86_XCPT_NMI: return "#NMI";
164	case X86_XCPT_BP: return "#BP";
165	case X86_XCPT_OF: return "#OF";
166	case X86_XCPT_BR: return "#BR";
167	case X86_XCPT_UD: return "#UD";
168	case X86_XCPT_NM: return "#NM";
169	case X86_XCPT_DF: return "#DF";
170	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
171	case X86_XCPT_TS: return "#TS";
172	case X86_XCPT_NP: return "#NP";
173	case X86_XCPT_SS: return "#SS";
174	case X86_XCPT_GP: return "#GP";
175	case X86_XCPT_PF: return "#PF";
176	case X86_XCPT_MF: return "#MF";
177	case X86_XCPT_AC: return "#AC";
178	case X86_XCPT_MC: return "#MC";
179	case X86_XCPT_XF: return "#XF";
180	case X86_XCPT_VE: return "#VE";
181	case X86_XCPT_CP: return "#CP";
182	case X86_XCPT_VC: return "#VC";
183	case X86_XCPT_SX: return "#SX";
184	}
185	return "Reserved";
186	}
187	#endif /* VBOX_WITH_STATISTICS */
188
189
190	/**
191	* Initializes the HM.
192	*
193	* This is the very first component to really do init after CFGM so that we can
194	* establish the predominant execution engine for the VM prior to initializing
195	* other modules. It takes care of NEM initialization if needed (HM disabled or
196	* not available in HW).
197	*
198	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
199	* hypervisor API via NEM, and then back on raw-mode if that isn't available
200	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
201	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
202	* X, OS/2 and others).
203	*
204	* Note that a lot of the set up work is done in ring-0 and thus postponed till
205	* the ring-3 and ring-0 callback to HMR3InitCompleted.
206	*
207	* @returns VBox status code.
208	* @param pVM The cross context VM structure.
209	*
210	* @remarks Be careful with what we call here, since most of the VMM components
211	* are uninitialized.
212	*/
213	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
214	{
215	LogFlowFunc(("\n"));
216
217	/*
218	* Assert alignment and sizes.
219	*/
220	AssertCompileMemberAlignment(VM, hm.s, 32);
221	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
222
223	/*
224	* Register the saved state data unit.
225	*/
226	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
227	NULL, NULL, NULL,
228	NULL, hmR3Save, NULL,
229	NULL, hmR3Load, NULL);
230	if (RT_FAILURE(rc))
231	return rc;
232
233	/*
234	* Register info handlers.
235	*/
236	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
237	AssertRCReturn(rc, rc);
238
239	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
240	DBGFINFO_FLAGS_ALL_EMTS);
241	AssertRCReturn(rc, rc);
242
243	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
244	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
245	AssertRCReturn(rc, rc);
246
247	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
248	AssertRCReturn(rc, rc);
249
250	/*
251	* Read configuration.
252	*/
253	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
254
255	/*
256	* Validate the HM settings.
257	*/
258	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
259	"HMForced" /* implied 'true' these days */
260	"\|UseNEMInstead"
261	"\|FallbackToNEM"
262	"\|EnableNestedPaging"
263	"\|EnableUX"
264	"\|EnableLargePages"
265	"\|EnableVPID"
266	"\|IBPBOnVMExit"
267	"\|IBPBOnVMEntry"
268	"\|SpecCtrlByHost"
269	"\|L1DFlushOnSched"
270	"\|L1DFlushOnVMEntry"
271	"\|MDSClearOnSched"
272	"\|MDSClearOnVMEntry"
273	"\|TPRPatchingEnabled"
274	"\|64bitEnabled"
275	"\|Exclusive"
276	"\|MaxResumeLoops"
277	"\|VmxPleGap"
278	"\|VmxPleWindow"
279	"\|VmxLbr"
280	"\|UseVmxPreemptTimer"
281	"\|SvmPauseFilter"
282	"\|SvmPauseFilterThreshold"
283	"\|SvmVirtVmsaveVmload"
284	"\|SvmVGif"
285	"\|LovelyMesaDrvWorkaround",
286	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
287	if (RT_FAILURE(rc))
288	return rc;
289
290	/** @cfgm{/HM/HMForced, bool, false}
291	* Forces hardware virtualization, no falling back on raw-mode. HM must be
292	* enabled, i.e. /HMEnabled must be true. */
293	bool fHMForced;
294	AssertRelease(pVM->fHMEnabled);
295	fHMForced = true;
296
297	/** @cfgm{/HM/UseNEMInstead, bool, true}
298	* Don't use HM, use NEM instead. */
299	bool fUseNEMInstead = false;
300	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
301	AssertRCReturn(rc, rc);
302	if (fUseNEMInstead && pVM->fHMEnabled)
303	{
304	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
305	pVM->fHMEnabled = false;
306	}
307
308	/** @cfgm{/HM/FallbackToNEM, bool, true}
309	* Enables fallback on NEM. */
310	bool fFallbackToNEM = true;
311	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
312	AssertRCReturn(rc, rc);
313
314	/** @cfgm{/HM/EnableNestedPaging, bool, false}
315	* Enables nested paging (aka extended page tables). */
316	bool fAllowNestedPaging = false;
317	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
318	AssertRCReturn(rc, rc);
319
320	/** @cfgm{/HM/EnableUX, bool, true}
321	* Enables the VT-x unrestricted execution feature. */
322	bool fAllowUnrestricted = true;
323	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
324	AssertRCReturn(rc, rc);
325
326	/** @cfgm{/HM/EnableLargePages, bool, false}
327	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
328	* page table walking and maybe better TLB hit rate in some cases. */
329	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
330	AssertRCReturn(rc, rc);
331
332	/** @cfgm{/HM/EnableVPID, bool, false}
333	* Enables the VT-x VPID feature. */
334	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
335	AssertRCReturn(rc, rc);
336
337	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
338	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
339	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
340	AssertRCReturn(rc, rc);
341
342	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
343	* Enables AMD64 cpu features.
344	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
345	* already have the support. */
346	#ifdef VBOX_WITH_64_BITS_GUESTS
347	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
348	AssertLogRelRCReturn(rc, rc);
349	#else
350	pVM->hm.s.fAllow64BitGuestsCfg = false;
351	#endif
352
353	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
354	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
355	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
356	* latest PAUSE instruction to be start of a new PAUSE loop.
357	*/
358	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
359	AssertRCReturn(rc, rc);
360
361	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
362	* The pause-filter exiting window in TSC ticks. When the number of ticks
363	* between the current PAUSE instruction and first PAUSE of a loop exceeds
364	* VmxPleWindow, a VM-exit is triggered.
365	*
366	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
367	*/
368	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
369	AssertRCReturn(rc, rc);
370
371	/** @cfgm{/HM/VmxLbr, bool, false}
372	* Whether to enable LBR for the guest. This is disabled by default as it's only
373	* useful while debugging and enabling it causes a noticeable performance hit. */
374	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
375	AssertRCReturn(rc, rc);
376
377	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
378	* A counter that is decrement each time a PAUSE instruction is executed by the
379	* guest. When the counter is 0, a \#VMEXIT is triggered.
380	*
381	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
382	*/
383	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
384	AssertRCReturn(rc, rc);
385
386	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
387	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
388	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
389	* PauseFilter count is reset to its initial value. However, if PAUSE is
390	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
391	* be triggered.
392	*
393	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
394	* activated.
395	*/
396	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
397	AssertRCReturn(rc, rc);
398
399	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
400	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
401	* available. */
402	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
403	AssertRCReturn(rc, rc);
404
405	/** @cfgm{/HM/SvmVGif, bool, true}
406	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
407	* if it's available. */
408	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
409	AssertRCReturn(rc, rc);
410
411	/** @cfgm{/HM/SvmLbrVirt, bool, false}
412	* Whether to make use of the LBR virtualization feature of the CPU if it's
413	* available. This is disabled by default as it's only useful while debugging
414	* and enabling it causes a small hit to performance. */
415	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
416	AssertRCReturn(rc, rc);
417
418	/** @cfgm{/HM/Exclusive, bool}
419	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
420	* global init for each host CPU. If false, we do local init each time we wish
421	* to execute guest code.
422	*
423	* On Windows, default is false due to the higher risk of conflicts with other
424	* hypervisors.
425	*
426	* On Mac OS X, this setting is ignored since the code does not handle local
427	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
428	*/
429	#if defined(RT_OS_DARWIN)
430	pVM->hm.s.fGlobalInit = true;
431	#else
432	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
433	# if defined(RT_OS_WINDOWS)
434	false
435	# else
436	true
437	# endif
438	);
439	AssertLogRelRCReturn(rc, rc);
440	#endif
441
442	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
443	* The number of times to resume guest execution before we forcibly return to
444	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445	* determines the default value. */
446	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
447	AssertLogRelRCReturn(rc, rc);
448
449	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
450	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
451	* available. */
452	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
453	AssertLogRelRCReturn(rc, rc);
454
455	/** @cfgm{/HM/IBPBOnVMExit, bool}
456	* Costly paranoia setting. */
457	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
458	AssertLogRelRCReturn(rc, rc);
459
460	/** @cfgm{/HM/IBPBOnVMEntry, bool}
461	* Costly paranoia setting. */
462	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
463	AssertLogRelRCReturn(rc, rc);
464
465	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
466	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
467	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
471	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
472	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
473	AssertLogRelRCReturn(rc, rc);
474
475	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
476	if (pVM->hm.s.fL1dFlushOnVmEntry)
477	pVM->hm.s.fL1dFlushOnSched = false;
478
479	/** @cfgm{/HM/SpecCtrlByHost, bool}
480	* Another expensive paranoia setting. */
481	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
482	AssertLogRelRCReturn(rc, rc);
483
484	/** @cfgm{/HM/MDSClearOnSched, bool, true}
485	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
486	* ignored on CPUs that aren't affected. */
487	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
488	AssertLogRelRCReturn(rc, rc);
489
490	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
491	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
492	* ignored on CPUs that aren't affected. */
493	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
494	AssertLogRelRCReturn(rc, rc);
495
496	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
497	if (pVM->hm.s.fMdsClearOnVmEntry)
498	pVM->hm.s.fMdsClearOnSched = false;
499
500	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
501	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
502	* the hypervisor it is running under. */
503	bool fMesaWorkaround;
504	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
505	AssertLogRelRCReturn(rc, rc);
506	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
507	{
508	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
509	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
510	}
511
512	/*
513	* Check if VT-x or AMD-v support according to the users wishes.
514	*/
515	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
516	* VERR_SVM_IN_USE. */
517	if (pVM->fHMEnabled)
518	{
519	uint32_t fCaps;
520	rc = SUPR3QueryVTCaps(&fCaps);
521	if (RT_SUCCESS(rc))
522	{
523	if (fCaps & SUPVTCAPS_AMD_V)
524	{
525	pVM->hm.s.svm.fSupported = true;
526	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
527	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
528	}
529	else if (fCaps & SUPVTCAPS_VT_X)
530	{
531	const char *pszWhy;
532	rc = SUPR3QueryVTxSupported(&pszWhy);
533	if (RT_SUCCESS(rc))
534	{
535	pVM->hm.s.vmx.fSupported = true;
536	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
537	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
538	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
539	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
540	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
541	}
542	else
543	{
544	/*
545	* Before failing, try fallback to NEM if we're allowed to do that.
546	*/
547	pVM->fHMEnabled = false;
548	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
549	if (fFallbackToNEM)
550	{
551	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
552	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
553
554	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
555	if ( RT_SUCCESS(rc2)
556	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
557	rc = VINF_SUCCESS;
558	}
559	if (RT_FAILURE(rc))
560	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
561	}
562	}
563	else
564	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
565	VERR_INTERNAL_ERROR_5);
566
567	/*
568	* Disable nested paging and unrestricted guest execution now if they're
569	* configured so that CPUM can make decisions based on our configuration.
570	*/
571	if ( fAllowNestedPaging
572	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
573	{
574	pVM->hm.s.fNestedPagingCfg = true;
575	if (fCaps & SUPVTCAPS_VT_X)
576	{
577	if ( fAllowUnrestricted
578	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
579	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
580	else
581	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
582	}
583	}
584	else
585	Assert(!pVM->hm.s.fNestedPagingCfg);
586	}
587	else
588	{
589	const char *pszMsg;
590	switch (rc)
591	{
592	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
593	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
594	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
595	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
596	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
597	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
598	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
599	default:
600	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
601	}
602
603	/*
604	* Before failing, try fallback to NEM if we're allowed to do that.
605	*/
606	pVM->fHMEnabled = false;
607	if (fFallbackToNEM)
608	{
609	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
610	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
611	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
612	if ( RT_SUCCESS(rc2)
613	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
614	{
615	rc = VINF_SUCCESS;
616
617	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
618	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
619	}
620	}
621	if (RT_FAILURE(rc))
622	return VM_SET_ERROR(pVM, rc, pszMsg);
623	}
624	}
625	else
626	{
627	/*
628	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
629	*/
630	if (fUseNEMInstead)
631	{
632	rc = NEMR3Init(pVM, false /fFallback/, true);
633	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
634	if (RT_FAILURE(rc))
635	return rc;
636
637	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
638	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
639	}
640	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
641	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
642	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
643	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
644	}
645
646	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
647	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
648	return VINF_SUCCESS;
649	}
650
651
652	/**
653	* Initializes HM components after ring-3 phase has been fully initialized.
654	*
655	* @returns VBox status code.
656	* @param pVM The cross context VM structure.
657	*/
658	static int hmR3InitFinalizeR3(PVM pVM)
659	{
660	LogFlowFunc(("\n"));
661
662	if (!HMIsEnabled(pVM))
663	return VINF_SUCCESS;
664
665	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
666	{
667	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
668	pVCpu->hm.s.fActive = false;
669	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
670	}
671
672	/*
673	* Check if L1D flush is needed/possible.
674	*/
675	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
676	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
677	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
678	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
679	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
680	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
681
682	/*
683	* Check if MDS flush is needed/possible.
684	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
685	*/
686	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
687	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
688	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
689	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
690	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
691	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
692	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
693	{
694	if (!pVM->hm.s.fMdsClearOnSched)
695	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
696	pVM->hm.s.fMdsClearOnVmEntry = false;
697	}
698	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
699	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
700	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
701
702	/*
703	* Statistics.
704	*/
705	#ifdef VBOX_WITH_STATISTICS
706	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
707	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
708	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
709	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
710	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
711	#endif
712
713	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
714	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
715	{
716	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
717	PHMCPU pHmCpu = &pVCpu->hm.s;
718	int rc;
719
720	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
721	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
722	AssertRC(rc); \
723	} while (0)
724	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
725	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
726
727	#ifdef VBOX_WITH_STATISTICS
728
729	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
730	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
731	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
732	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
733	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
734	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
735	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
736	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
737	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
738	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
739	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
740	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
741	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
742	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
743	# ifdef HM_PROFILE_EXIT_DISPATCH
744	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
745	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
746	# endif
747	#endif
748	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
749
750	#ifdef VBOX_WITH_STATISTICS
751	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
752	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
753	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
754	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
755	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
756	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
757	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
758	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
759	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
760	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
761	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
762	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
763	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
764	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
765	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
766	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
767	#endif
768	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
769	if (fCpuSupportsVmx)
770	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
771	#ifdef VBOX_WITH_STATISTICS
772	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
773	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
774	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
775	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
776	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
777	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
778	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
779	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
780	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
781	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
782	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
783	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
784	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
785	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
786	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
787	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
788	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
789	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
790	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
791	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
792	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
793	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
794	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
795	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
796	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
797	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
798	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
799	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
800	#endif
801	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
802	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
803	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
804	#ifdef VBOX_WITH_STATISTICS
805	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
806	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
807	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
808
809	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
810	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
811	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
812	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
813	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
814	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
815	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
816	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
817	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
818	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
819	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
820	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
821	#endif
822	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
823	#ifdef VBOX_WITH_STATISTICS
824	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
825
826	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
827	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
828	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
829	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
830	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
831	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
832
833	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
834	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
835	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
836	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
837	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
838	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
839	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
840	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
841	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
842	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
843	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
844	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
845	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
846	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
847	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
848
849	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
850	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
851	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
852
853	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
854	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
855	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
856
857	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
858	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
859	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
860	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
861
862	if (fCpuSupportsVmx)
863	{
864	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
865	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
866	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
867	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
868	}
869
870	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
871	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
872	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
873
874	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
875	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
876	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
877
878	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
879	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
880	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
881	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
882	#endif
883	if (fCpuSupportsVmx)
884	{
885	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
886	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
887	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
888	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
889	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
890	}
891	#ifdef VBOX_WITH_STATISTICS
892	/*
893	* Guest Exit reason stats.
894	*/
895	if (fCpuSupportsVmx)
896	{
897	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
898	{
899	const char *pszExitName = HMGetVmxExitName(j);
900	if (pszExitName)
901	{
902	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
903	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
904	AssertRCReturn(rc, rc);
905	}
906	}
907	}
908	else
909	{
910	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
911	{
912	const char *pszExitName = HMGetSvmExitName(j);
913	if (pszExitName)
914	{
915	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
916	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
917	AssertRC(rc);
918	}
919	}
920	}
921	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
922
923	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
924	/*
925	* Nested-guest VM-exit reason stats.
926	*/
927	if (fCpuSupportsVmx)
928	{
929	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
930	{
931	const char *pszExitName = HMGetVmxExitName(j);
932	if (pszExitName)
933	{
934	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
935	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
936	AssertRC(rc);
937	}
938	}
939	}
940	else
941	{
942	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
943	{
944	const char *pszExitName = HMGetSvmExitName(j);
945	if (pszExitName)
946	{
947	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
948	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
949	AssertRC(rc);
950	}
951	}
952	}
953	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
954	#endif
955
956	/*
957	* Injected interrupts stats.
958	*/
959	char szDesc[64];
960	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
961	{
962	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
963	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
964	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
965	AssertRC(rc);
966	}
967
968	/*
969	* Injected exception stats.
970	*/
971	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
972	{
973	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
974	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
975	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
976	AssertRC(rc);
977	}
978
979	#endif /* VBOX_WITH_STATISTICS */
980	#undef HM_REG_COUNTER
981	#undef HM_REG_PROFILE
982	#undef HM_REG_STAT
983	}
984
985	return VINF_SUCCESS;
986	}
987
988
989	/**
990	* Called when a init phase has completed.
991	*
992	* @returns VBox status code.
993	* @param pVM The cross context VM structure.
994	* @param enmWhat The phase that completed.
995	*/
996	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
997	{
998	switch (enmWhat)
999	{
1000	case VMINITCOMPLETED_RING3:
1001	return hmR3InitFinalizeR3(pVM);
1002	case VMINITCOMPLETED_RING0:
1003	return hmR3InitFinalizeR0(pVM);
1004	default:
1005	return VINF_SUCCESS;
1006	}
1007	}
1008
1009
1010	/**
1011	* Turns off normal raw mode features.
1012	*
1013	* @param pVM The cross context VM structure.
1014	*/
1015	static void hmR3DisableRawMode(PVM pVM)
1016	{
1017	/** @todo r=bird: HM shouldn't be doing this crap. */
1018	/* Reinit the paging mode to force the new shadow mode. */
1019	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1020	{
1021	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1022	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1023	}
1024	}
1025
1026
1027	/**
1028	* Initialize VT-x or AMD-V.
1029	*
1030	* @returns VBox status code.
1031	* @param pVM The cross context VM structure.
1032	*/
1033	static int hmR3InitFinalizeR0(PVM pVM)
1034	{
1035	int rc;
1036
1037	if (!HMIsEnabled(pVM))
1038	return VINF_SUCCESS;
1039
1040	/*
1041	* Hack to allow users to work around broken BIOSes that incorrectly set
1042	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1043	*/
1044	if ( !pVM->hm.s.vmx.fSupported
1045	&& !pVM->hm.s.svm.fSupported
1046	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1047	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1048	{
1049	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1050	pVM->hm.s.svm.fSupported = true;
1051	pVM->hm.s.svm.fIgnoreInUseError = true;
1052	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1053	}
1054
1055	/*
1056	* Report ring-0 init errors.
1057	*/
1058	if ( !pVM->hm.s.vmx.fSupported
1059	&& !pVM->hm.s.svm.fSupported)
1060	{
1061	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1062	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1063	switch (pVM->hm.s.ForR3.rcInit)
1064	{
1065	case VERR_VMX_IN_VMX_ROOT_MODE:
1066	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1067	case VERR_VMX_NO_VMX:
1068	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1069	case VERR_VMX_MSR_VMX_DISABLED:
1070	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1071	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1072	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1073	case VERR_VMX_MSR_LOCKING_FAILED:
1074	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1075	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1076	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1077	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1078	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1079
1080	case VERR_SVM_IN_USE:
1081	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1082	case VERR_SVM_NO_SVM:
1083	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1084	case VERR_SVM_DISABLED:
1085	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1086	}
1087	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1088	}
1089
1090	/*
1091	* Enable VT-x or AMD-V on all host CPUs.
1092	*/
1093	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1094	if (RT_FAILURE(rc))
1095	{
1096	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1097	HMR3CheckError(pVM, rc);
1098	return rc;
1099	}
1100
1101	/*
1102	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1103	* (Main should have taken care of this already)
1104	*/
1105	if (!PDMHasIoApic(pVM))
1106	{
1107	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1108	pVM->hm.s.fTprPatchingAllowed = false;
1109	}
1110
1111	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1112	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1113	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1114
1115	/*
1116	* Do the vendor specific initialization
1117	*
1118	* Note! We disable release log buffering here since we're doing relatively
1119	* lot of logging and doesn't want to hit the disk with each LogRel
1120	* statement.
1121	*/
1122	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1123	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1124	if (pVM->hm.s.vmx.fSupported)
1125	rc = hmR3InitFinalizeR0Intel(pVM);
1126	else
1127	rc = hmR3InitFinalizeR0Amd(pVM);
1128	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1129	: "HM: VT-x/AMD-V init method: Local\n"));
1130	RTLogRelSetBuffering(fOldBuffered);
1131	pVM->hm.s.fInitialized = true;
1132
1133	return rc;
1134	}
1135
1136
1137	/**
1138	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1139	*/
1140	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1141	{
1142	NOREF(pVM);
1143	NOREF(pvAllocation);
1144	NOREF(GCPhysAllocation);
1145	}
1146
1147
1148	/**
1149	* Returns a description of the VMCS (and associated regions') memory type given the
1150	* IA32_VMX_BASIC MSR.
1151	*
1152	* @returns The descriptive memory type.
1153	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1154	*/
1155	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1156	{
1157	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1158	switch (uMemType)
1159	{
1160	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1161	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1162	}
1163	return "Unknown";
1164	}
1165
1166
1167	/**
1168	* Returns a single-line description of all the activity-states supported by the CPU
1169	* given the IA32_VMX_MISC MSR.
1170	*
1171	* @returns All supported activity states.
1172	* @param uMsrMisc IA32_VMX_MISC MSR value.
1173	*/
1174	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1175	{
1176	static const char * const s_apszActStates[] =
1177	{
1178	"",
1179	" ( HLT )",
1180	" ( SHUTDOWN )",
1181	" ( HLT SHUTDOWN )",
1182	" ( SIPI_WAIT )",
1183	" ( HLT SIPI_WAIT )",
1184	" ( SHUTDOWN SIPI_WAIT )",
1185	" ( HLT SHUTDOWN SIPI_WAIT )"
1186	};
1187	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1188	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1189	return s_apszActStates[idxActStates];
1190	}
1191
1192
1193	/**
1194	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1195	*
1196	* @param fFeatMsr The feature control MSR value.
1197	*/
1198	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1199	{
1200	uint64_t const val = fFeatMsr;
1201	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1202	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1203	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1204	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1205	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1206	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1207	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1208	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1209	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1210	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1211	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1212	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1213	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1214	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1215	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1216	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1217	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1218	}
1219
1220
1221	/**
1222	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1223	*
1224	* @param uBasicMsr The VMX basic MSR value.
1225	*/
1226	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1227	{
1228	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1229	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1230	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1231	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1232	"< 4 GB" : "None"));
1233	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1234	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1235	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1236	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1237	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1238	}
1239
1240
1241	/**
1242	* Reports MSR_IA32_PINBASED_CTLS to the log.
1243	*
1244	* @param pVmxMsr Pointer to the VMX MSR.
1245	*/
1246	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1247	{
1248	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1249	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1250	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1251	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1252	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1253	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1254	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1255	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1256	}
1257
1258
1259	/**
1260	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1261	*
1262	* @param pVmxMsr Pointer to the VMX MSR.
1263	*/
1264	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1265	{
1266	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1267	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1268	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1269	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1270	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1271	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1272	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1273	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1274	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1275	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1276	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1277	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1278	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1279	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1280	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1281	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1282	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1283	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1284	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1285	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1286	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1287	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1288	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1289	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1290	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1291	}
1292
1293
1294	/**
1295	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1296	*
1297	* @param pVmxMsr Pointer to the VMX MSR.
1298	*/
1299	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1300	{
1301	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1302	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1303	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1310	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1316	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1317	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1318	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1320	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1321	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1322	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1323	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1324	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1331	}
1332
1333
1334	/**
1335	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1336	*
1337	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1338	*/
1339	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1340	{
1341	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1342	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1343	}
1344
1345
1346	/**
1347	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1348	*
1349	* @param pVmxMsr Pointer to the VMX MSR.
1350	*/
1351	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1352	{
1353	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1354	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1355	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1356	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1357	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1358	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1359	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1360	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1361	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1362	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1363	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1366	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1367	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1368	}
1369
1370
1371	/**
1372	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1373	*
1374	* @param pVmxMsr Pointer to the VMX MSR.
1375	*/
1376	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1377	{
1378	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1379	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1380	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1389	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1390	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1391	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1392	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1393	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1395	}
1396
1397
1398	/**
1399	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1400	*
1401	* @param fCaps The VMX EPT/VPID capability MSR value.
1402	*/
1403	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1404	{
1405	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1406	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1407	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1408	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1409	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1410	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1411	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1412	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1413	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1414	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1415	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1416	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1417	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1418	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1419	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1420	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1421	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1422	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1423	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1424	}
1425
1426
1427	/**
1428	* Reports MSR_IA32_VMX_MISC MSR to the log.
1429	*
1430	* @param pVM Pointer to the VM.
1431	* @param fMisc The VMX misc. MSR value.
1432	*/
1433	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1434	{
1435	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1436	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1437	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1438	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1439	else
1440	{
1441	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1442	pVM->hm.s.vmx.cPreemptTimerShift));
1443	}
1444	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1445	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1446	hmR3VmxGetActivityStateAllDesc(fMisc)));
1447	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1448	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1449	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1450	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1451	VMX_MISC_MAX_MSRS(fMisc)));
1452	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1453	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1454	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1455	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1456	}
1457
1458
1459	/**
1460	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1461	*
1462	* @param uVmcsEnum The VMX VMCS enum MSR value.
1463	*/
1464	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1465	{
1466	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1467	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1468	}
1469
1470
1471	/**
1472	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1473	*
1474	* @param uVmFunc The VMX VMFUNC MSR value.
1475	*/
1476	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1477	{
1478	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1479	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1480	}
1481
1482
1483	/**
1484	* Reports VMX CR0, CR4 fixed MSRs.
1485	*
1486	* @param pMsrs Pointer to the VMX MSRs.
1487	*/
1488	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1489	{
1490	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1491	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1492	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1493	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1494	}
1495
1496
1497	/**
1498	* Finish VT-x initialization (after ring-0 init).
1499	*
1500	* @returns VBox status code.
1501	* @param pVM The cross context VM structure.
1502	*/
1503	static int hmR3InitFinalizeR0Intel(PVM pVM)
1504	{
1505	int rc;
1506
1507	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1508	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1509
1510	LogRel(("HM: Using VT-x implementation 3.0\n"));
1511	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1512	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1513	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1514	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1515
1516	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1517	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1518
1519	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1520	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1521	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1522	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1523	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1524	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1525
1526	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1527	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1528
1529	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1530	{
1531	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1532	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1533	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1534	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1535	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1536	}
1537
1538	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1539	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1540	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1541	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1542	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1543	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1544	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1545
1546	#ifdef TODO_9217_VMCSINFO
1547	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1548	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1549	{
1550	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1551	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1552	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1553	}
1554	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1555	if (pVM->cpum.ro.GuestFeatures.fVmx)
1556	{
1557	LogRel(("HM: Nested-guest:\n"));
1558	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1559	{
1560	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1561	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1562	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1563	}
1564	}
1565	#endif
1566	#endif /* TODO_9217_VMCSINFO */
1567
1568	/*
1569	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1570	*/
1571	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1572	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1573	VERR_HM_IPE_1);
1574	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1575	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1576	&& pVM->hm.s.fNestedPagingCfg),
1577	VERR_HM_IPE_1);
1578
1579	/*
1580	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1581	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1582	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1583	*/
1584	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1585	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1586	{
1587	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1588	LogRel(("HM: Disabled RDTSCP\n"));
1589	}
1590
1591	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1592	{
1593	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1594	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1595	if (RT_SUCCESS(rc))
1596	{
1597	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1598	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1599	esp. Figure 20-5.*/
1600	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1601	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1602
1603	/* Bit set to 0 means software interrupts are redirected to the
1604	8086 program interrupt handler rather than switching to
1605	protected-mode handler. */
1606	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1607
1608	/* Allow all port IO, so that port IO instructions do not cause
1609	exceptions and would instead cause a VM-exit (based on VT-x's
1610	IO bitmap which we currently configure to always cause an exit). */
1611	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1612	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1613
1614	/*
1615	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1616	* page table used in real and protected mode without paging with EPT.
1617	*/
1618	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1619	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1620	{
1621	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1622	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1623	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1624	\| X86_PDE4M_G;
1625	}
1626
1627	/* We convert it here every time as PCI regions could be reconfigured. */
1628	if (PDMVmmDevHeapIsEnabled(pVM))
1629	{
1630	RTGCPHYS GCPhys;
1631	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1632	AssertRCReturn(rc, rc);
1633	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1634
1635	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1636	AssertRCReturn(rc, rc);
1637	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1638	}
1639	}
1640	else
1641	{
1642	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1643	pVM->hm.s.vmx.pRealModeTSS = NULL;
1644	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1645	return VMSetError(pVM, rc, RT_SRC_POS,
1646	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1647	}
1648	}
1649
1650	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1651	: "HM: Guest support: 32-bit only\n"));
1652
1653	/*
1654	* Call ring-0 to set up the VM.
1655	*/
1656	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1657	if (rc != VINF_SUCCESS)
1658	{
1659	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1660	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1661	{
1662	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1663	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1664	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1665	}
1666	HMR3CheckError(pVM, rc);
1667	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1668	}
1669
1670	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1671	LogRel(("HM: Enabled VMX\n"));
1672	pVM->hm.s.vmx.fEnabled = true;
1673
1674	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1675
1676	/*
1677	* Change the CPU features.
1678	*/
1679	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1680	if (pVM->hm.s.fAllow64BitGuestsCfg)
1681	{
1682	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1683	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1684	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1685	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1686	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1687	}
1688	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1689	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1690	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1691
1692	/*
1693	* Log configuration details.
1694	*/
1695	if (pVM->hm.s.fNestedPagingCfg)
1696	{
1697	LogRel(("HM: Enabled nested paging\n"));
1698	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1699	LogRel(("HM: EPT flush type = Single context\n"));
1700	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1701	LogRel(("HM: EPT flush type = All contexts\n"));
1702	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1703	LogRel(("HM: EPT flush type = Not supported\n"));
1704	else
1705	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1706
1707	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1708	LogRel(("HM: Enabled unrestricted guest execution\n"));
1709
1710	if (pVM->hm.s.fLargePages)
1711	{
1712	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1713	PGMSetLargePageUsage(pVM, true);
1714	LogRel(("HM: Enabled large page support\n"));
1715	}
1716	}
1717	else
1718	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1719
1720	if (pVM->hm.s.ForR3.vmx.fVpid)
1721	{
1722	LogRel(("HM: Enabled VPID\n"));
1723	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1724	LogRel(("HM: VPID flush type = Individual addresses\n"));
1725	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1726	LogRel(("HM: VPID flush type = Single context\n"));
1727	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1728	LogRel(("HM: VPID flush type = All contexts\n"));
1729	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1730	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1731	else
1732	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1733	}
1734	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1735	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1736
1737	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1738	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1739	else
1740	LogRel(("HM: Disabled VMX-preemption timer\n"));
1741
1742	if (pVM->hm.s.fVirtApicRegs)
1743	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1744
1745	if (pVM->hm.s.fPostedIntrs)
1746	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1747
1748	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1749	{
1750	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1751	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1752	}
1753
1754	return VINF_SUCCESS;
1755	}
1756
1757
1758	/**
1759	* Finish AMD-V initialization (after ring-0 init).
1760	*
1761	* @returns VBox status code.
1762	* @param pVM The cross context VM structure.
1763	*/
1764	static int hmR3InitFinalizeR0Amd(PVM pVM)
1765	{
1766	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1767
1768	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1769
1770	uint32_t u32Family;
1771	uint32_t u32Model;
1772	uint32_t u32Stepping;
1773	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1774	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1775	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1776	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1777	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1778	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1779	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1780
1781	/*
1782	* Enumerate AMD-V features.
1783	*/
1784	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1785	{
1786	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1787	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1788	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1789	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1790	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1791	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1792	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1793	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1794	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1795	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1796	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1797	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1798	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1799	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1800	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1801	#undef HMSVM_REPORT_FEATURE
1802	};
1803
1804	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1805	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1806	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1807	{
1808	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1809	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1810	}
1811	if (fSvmFeatures)
1812	for (unsigned iBit = 0; iBit < 32; iBit++)
1813	if (RT_BIT_32(iBit) & fSvmFeatures)
1814	LogRel(("HM: Reserved bit %u\n", iBit));
1815
1816	/*
1817	* Nested paging is determined in HMR3Init, verify the sanity of that.
1818	*/
1819	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1820	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1821	VERR_HM_IPE_1);
1822
1823	#if 0
1824	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1825	* here. */
1826	if (RTR0IsPostIpiSupport())
1827	pVM->hm.s.fPostedIntrs = true;
1828	#endif
1829
1830	/*
1831	* Determine whether we need to intercept #UD in SVM mode for emulating
1832	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1833	* when executed in long-mode. This is only really applicable when
1834	* non-default CPU profiles are in effect, i.e. guest vendor differs
1835	* from the host one.
1836	*/
1837	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1838	switch (CPUMGetGuestCpuVendor(pVM))
1839	{
1840	case CPUMCPUVENDOR_INTEL:
1841	case CPUMCPUVENDOR_VIA: /?/
1842	case CPUMCPUVENDOR_SHANGHAI: /?/
1843	switch (CPUMGetHostCpuVendor(pVM))
1844	{
1845	case CPUMCPUVENDOR_AMD:
1846	case CPUMCPUVENDOR_HYGON:
1847	if (pVM->hm.s.fAllow64BitGuestsCfg)
1848	{
1849	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1850	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1851	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1852	}
1853	break;
1854	default: break;
1855	}
1856	default: break;
1857	}
1858
1859	/*
1860	* Call ring-0 to set up the VM.
1861	*/
1862	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1863	if (rc != VINF_SUCCESS)
1864	{
1865	AssertMsgFailed(("%Rrc\n", rc));
1866	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1867	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1868	}
1869
1870	LogRel(("HM: Enabled SVM\n"));
1871	pVM->hm.s.svm.fEnabled = true;
1872
1873	if (pVM->hm.s.fNestedPagingCfg)
1874	{
1875	LogRel(("HM: Enabled nested paging\n"));
1876
1877	/*
1878	* Enable large pages (2 MB) if applicable.
1879	*/
1880	if (pVM->hm.s.fLargePages)
1881	{
1882	PGMSetLargePageUsage(pVM, true);
1883	LogRel(("HM: Enabled large page support\n"));
1884	}
1885	}
1886
1887	if (pVM->hm.s.fVirtApicRegs)
1888	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1889
1890	if (pVM->hm.s.fPostedIntrs)
1891	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1892
1893	hmR3DisableRawMode(pVM);
1894
1895	/*
1896	* Change the CPU features.
1897	*/
1898	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1899	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1900	if (pVM->hm.s.fAllow64BitGuestsCfg)
1901	{
1902	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1903	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1904	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1905	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1906	}
1907	/* Turn on NXE if PAE has been enabled. */
1908	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1909	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1910
1911	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1912	: "HM: Disabled TPR patching\n"));
1913
1914	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1915	: "HM: Guest support: 32-bit only\n"));
1916	return VINF_SUCCESS;
1917	}
1918
1919
1920	/**
1921	* Applies relocations to data and code managed by this
1922	* component. This function will be called at init and
1923	* whenever the VMM need to relocate it self inside the GC.
1924	*
1925	* @param pVM The cross context VM structure.
1926	*/
1927	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1928	{
1929	/* Fetch the current paging mode during the relocate callback during state loading. */
1930	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1931	{
1932	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1933	{
1934	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1935	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1936	}
1937	}
1938	}
1939
1940
1941	/**
1942	* Terminates the HM.
1943	*
1944	* Termination means cleaning up and freeing all resources,
1945	* the VM itself is, at this point, powered off or suspended.
1946	*
1947	* @returns VBox status code.
1948	* @param pVM The cross context VM structure.
1949	*/
1950	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1951	{
1952	if (pVM->hm.s.vmx.pRealModeTSS)
1953	{
1954	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1955	pVM->hm.s.vmx.pRealModeTSS = 0;
1956	}
1957	hmR3TermCPU(pVM);
1958	return 0;
1959	}
1960
1961
1962	/**
1963	* Terminates the per-VCPU HM.
1964	*
1965	* @returns VBox status code.
1966	* @param pVM The cross context VM structure.
1967	*/
1968	static int hmR3TermCPU(PVM pVM)
1969	{
1970	RT_NOREF(pVM);
1971	return VINF_SUCCESS;
1972	}
1973
1974
1975	/**
1976	* Resets a virtual CPU.
1977	*
1978	* Used by HMR3Reset and CPU hot plugging.
1979	*
1980	* @param pVCpu The cross context virtual CPU structure to reset.
1981	*/
1982	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1983	{
1984	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
1985	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1986	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
1987
1988	pVCpu->hm.s.fActive = false;
1989	pVCpu->hm.s.Event.fPending = false;
1990	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
1991	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
1992	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1993	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
1994	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
1995	#endif
1996	}
1997
1998
1999	/**
2000	* The VM is being reset.
2001	*
2002	* For the HM component this means that any GDT/LDT/TSS monitors
2003	* needs to be removed.
2004	*
2005	* @param pVM The cross context VM structure.
2006	*/
2007	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2008	{
2009	LogFlow(("HMR3Reset:\n"));
2010
2011	if (HMIsEnabled(pVM))
2012	hmR3DisableRawMode(pVM);
2013
2014	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2015	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2016
2017	/* Clear all patch information. */
2018	pVM->hm.s.pGuestPatchMem = 0;
2019	pVM->hm.s.pFreeGuestPatchMem = 0;
2020	pVM->hm.s.cbGuestPatchMem = 0;
2021	pVM->hm.s.cPatches = 0;
2022	pVM->hm.s.PatchTree = 0;
2023	pVM->hm.s.fTprPatchingActive = false;
2024	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2025	}
2026
2027
2028	/**
2029	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2030	*
2031	* @returns VBox strict status code.
2032	* @param pVM The cross context VM structure.
2033	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2034	* @param pvUser Unused.
2035	*/
2036	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2037	{
2038	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2039
2040	/* Only execute the handler on the VCPU the original patch request was issued. */
2041	if (pVCpu->idCpu != idCpu)
2042	return VINF_SUCCESS;
2043
2044	Log(("hmR3RemovePatches\n"));
2045	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2046	{
2047	uint8_t abInstr[15];
2048	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2049	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2050	int rc;
2051
2052	#ifdef LOG_ENABLED
2053	char szOutput[256];
2054	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2055	szOutput, sizeof(szOutput), NULL);
2056	if (RT_SUCCESS(rc))
2057	Log(("Patched instr: %s\n", szOutput));
2058	#endif
2059
2060	/* Check if the instruction is still the same. */
2061	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2062	if (rc != VINF_SUCCESS)
2063	{
2064	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2065	continue; /* swapped out or otherwise removed; skip it. */
2066	}
2067
2068	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2069	{
2070	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2071	continue; /* skip it. */
2072	}
2073
2074	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2075	AssertRC(rc);
2076
2077	#ifdef LOG_ENABLED
2078	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2079	szOutput, sizeof(szOutput), NULL);
2080	if (RT_SUCCESS(rc))
2081	Log(("Original instr: %s\n", szOutput));
2082	#endif
2083	}
2084	pVM->hm.s.cPatches = 0;
2085	pVM->hm.s.PatchTree = 0;
2086	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2087	pVM->hm.s.fTprPatchingActive = false;
2088	return VINF_SUCCESS;
2089	}
2090
2091
2092	/**
2093	* Worker for enabling patching in a VT-x/AMD-V guest.
2094	*
2095	* @returns VBox status code.
2096	* @param pVM The cross context VM structure.
2097	* @param idCpu VCPU to execute hmR3RemovePatches on.
2098	* @param pPatchMem Patch memory range.
2099	* @param cbPatchMem Size of the memory range.
2100	*/
2101	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2102	{
2103	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2104	AssertRC(rc);
2105
2106	pVM->hm.s.pGuestPatchMem = pPatchMem;
2107	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2108	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2109	return VINF_SUCCESS;
2110	}
2111
2112
2113	/**
2114	* Enable patching in a VT-x/AMD-V guest
2115	*
2116	* @returns VBox status code.
2117	* @param pVM The cross context VM structure.
2118	* @param pPatchMem Patch memory range.
2119	* @param cbPatchMem Size of the memory range.
2120	*/
2121	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2122	{
2123	VM_ASSERT_EMT(pVM);
2124	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2125	if (pVM->cCpus > 1)
2126	{
2127	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2128	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2129	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2130	AssertRC(rc);
2131	return rc;
2132	}
2133	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2134	}
2135
2136
2137	/**
2138	* Disable patching in a VT-x/AMD-V guest.
2139	*
2140	* @returns VBox status code.
2141	* @param pVM The cross context VM structure.
2142	* @param pPatchMem Patch memory range.
2143	* @param cbPatchMem Size of the memory range.
2144	*/
2145	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2146	{
2147	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2148	RT_NOREF2(pPatchMem, cbPatchMem);
2149
2150	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2151	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2152
2153	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2154	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2155	(void *)(uintptr_t)VMMGetCpuId(pVM));
2156	AssertRC(rc);
2157
2158	pVM->hm.s.pGuestPatchMem = 0;
2159	pVM->hm.s.pFreeGuestPatchMem = 0;
2160	pVM->hm.s.cbGuestPatchMem = 0;
2161	pVM->hm.s.fTprPatchingActive = false;
2162	return VINF_SUCCESS;
2163	}
2164
2165
2166	/**
2167	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2168	*
2169	* @returns VBox strict status code.
2170	* @param pVM The cross context VM structure.
2171	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2172	* @param pvUser User specified CPU context.
2173	*
2174	*/
2175	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2176	{
2177	/*
2178	* Only execute the handler on the VCPU the original patch request was
2179	* issued. (The other CPU(s) might not yet have switched to protected
2180	* mode, nor have the correct memory context.)
2181	*/
2182	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2183	if (pVCpu->idCpu != idCpu)
2184	return VINF_SUCCESS;
2185
2186	/*
2187	* We're racing other VCPUs here, so don't try patch the instruction twice
2188	* and make sure there is still room for our patch record.
2189	*/
2190	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2191	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2192	if (pPatch)
2193	{
2194	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2195	return VINF_SUCCESS;
2196	}
2197	uint32_t const idx = pVM->hm.s.cPatches;
2198	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2199	{
2200	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2201	return VINF_SUCCESS;
2202	}
2203	pPatch = &pVM->hm.s.aPatches[idx];
2204
2205	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2206
2207	/*
2208	* Disassembler the instruction and get cracking.
2209	*/
2210	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2211	DISCPUSTATE Dis;
2212	uint32_t cbOp;
2213	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2214	AssertRC(rc);
2215	if ( rc == VINF_SUCCESS
2216	&& Dis.pCurInstr->uOpcode == OP_MOV
2217	&& cbOp >= 3)
2218	{
2219	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2220
2221	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2222	AssertRC(rc);
2223
2224	pPatch->cbOp = cbOp;
2225
2226	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2227	{
2228	/* write. */
2229	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2230	{
2231	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2232	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2233	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2234	}
2235	else
2236	{
2237	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2238	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2239	pPatch->uSrcOperand = Dis.Param2.uValue;
2240	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2241	}
2242	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2243	AssertRC(rc);
2244
2245	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2246	pPatch->cbNewOp = sizeof(s_abVMMCall);
2247	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2248	}
2249	else
2250	{
2251	/*
2252	* TPR Read.
2253	*
2254	* Found:
2255	* mov eax, dword [fffe0080] (5 bytes)
2256	* Check if next instruction is:
2257	* shr eax, 4
2258	*/
2259	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2260
2261	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2262	uint8_t const cbOpMmio = cbOp;
2263	uint64_t const uSavedRip = pCtx->rip;
2264
2265	pCtx->rip += cbOp;
2266	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2267	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2268	pCtx->rip = uSavedRip;
2269
2270	if ( rc == VINF_SUCCESS
2271	&& Dis.pCurInstr->uOpcode == OP_SHR
2272	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2273	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2274	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2275	&& Dis.Param2.uValue == 4
2276	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2277	{
2278	uint8_t abInstr[15];
2279
2280	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2281	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2282	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2283	AssertRC(rc);
2284
2285	pPatch->cbOp = cbOpMmio + cbOp;
2286
2287	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2288	abInstr[0] = 0xf0;
2289	abInstr[1] = 0x0f;
2290	abInstr[2] = 0x20;
2291	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2292	for (unsigned i = 4; i < pPatch->cbOp; i++)
2293	abInstr[i] = 0x90; /* nop */
2294
2295	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2296	AssertRC(rc);
2297
2298	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2299	pPatch->cbNewOp = pPatch->cbOp;
2300	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2301
2302	Log(("Acceptable read/shr candidate!\n"));
2303	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2304	}
2305	else
2306	{
2307	pPatch->enmType = HMTPRINSTR_READ;
2308	pPatch->uDstOperand = idxMmioReg;
2309
2310	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2311	AssertRC(rc);
2312
2313	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2314	pPatch->cbNewOp = sizeof(s_abVMMCall);
2315	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2316	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2317	}
2318	}
2319
2320	pPatch->Core.Key = pCtx->eip;
2321	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2322	AssertRC(rc);
2323
2324	pVM->hm.s.cPatches++;
2325	return VINF_SUCCESS;
2326	}
2327
2328	/*
2329	* Save invalid patch, so we will not try again.
2330	*/
2331	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2332	pPatch->Core.Key = pCtx->eip;
2333	pPatch->enmType = HMTPRINSTR_INVALID;
2334	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2335	AssertRC(rc);
2336	pVM->hm.s.cPatches++;
2337	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2338	return VINF_SUCCESS;
2339	}
2340
2341
2342	/**
2343	* Callback to patch a TPR instruction (jump to generated code).
2344	*
2345	* @returns VBox strict status code.
2346	* @param pVM The cross context VM structure.
2347	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2348	* @param pvUser User specified CPU context.
2349	*
2350	*/
2351	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2352	{
2353	/*
2354	* Only execute the handler on the VCPU the original patch request was
2355	* issued. (The other CPU(s) might not yet have switched to protected
2356	* mode, nor have the correct memory context.)
2357	*/
2358	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2359	if (pVCpu->idCpu != idCpu)
2360	return VINF_SUCCESS;
2361
2362	/*
2363	* We're racing other VCPUs here, so don't try patch the instruction twice
2364	* and make sure there is still room for our patch record.
2365	*/
2366	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2367	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2368	if (pPatch)
2369	{
2370	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2371	return VINF_SUCCESS;
2372	}
2373	uint32_t const idx = pVM->hm.s.cPatches;
2374	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2375	{
2376	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2377	return VINF_SUCCESS;
2378	}
2379	pPatch = &pVM->hm.s.aPatches[idx];
2380
2381	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2382	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2383
2384	/*
2385	* Disassemble the instruction and get cracking.
2386	*/
2387	DISCPUSTATE Dis;
2388	uint32_t cbOp;
2389	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2390	AssertRC(rc);
2391	if ( rc == VINF_SUCCESS
2392	&& Dis.pCurInstr->uOpcode == OP_MOV
2393	&& cbOp >= 5)
2394	{
2395	uint8_t aPatch[64];
2396	uint32_t off = 0;
2397
2398	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2399	AssertRC(rc);
2400
2401	pPatch->cbOp = cbOp;
2402	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2403
2404	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2405	{
2406	/*
2407	* TPR write:
2408	*
2409	* push ECX [51]
2410	* push EDX [52]
2411	* push EAX [50]
2412	* xor EDX,EDX [31 D2]
2413	* mov EAX,EAX [89 C0]
2414	* or
2415	* mov EAX,0000000CCh [B8 CC 00 00 00]
2416	* mov ECX,0C0000082h [B9 82 00 00 C0]
2417	* wrmsr [0F 30]
2418	* pop EAX [58]
2419	* pop EDX [5A]
2420	* pop ECX [59]
2421	* jmp return_address [E9 return_address]
2422	*/
2423	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2424
2425	aPatch[off++] = 0x51; /* push ecx */
2426	aPatch[off++] = 0x52; /* push edx */
2427	if (!fUsesEax)
2428	aPatch[off++] = 0x50; /* push eax */
2429	aPatch[off++] = 0x31; /* xor edx, edx */
2430	aPatch[off++] = 0xd2;
2431	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2432	{
2433	if (!fUsesEax)
2434	{
2435	aPatch[off++] = 0x89; /* mov eax, src_reg */
2436	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2437	}
2438	}
2439	else
2440	{
2441	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2442	aPatch[off++] = 0xb8; /* mov eax, immediate */
2443	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2444	off += sizeof(uint32_t);
2445	}
2446	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2447	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2448	off += sizeof(uint32_t);
2449
2450	aPatch[off++] = 0x0f; /* wrmsr */
2451	aPatch[off++] = 0x30;
2452	if (!fUsesEax)
2453	aPatch[off++] = 0x58; /* pop eax */
2454	aPatch[off++] = 0x5a; /* pop edx */
2455	aPatch[off++] = 0x59; /* pop ecx */
2456	}
2457	else
2458	{
2459	/*
2460	* TPR read:
2461	*
2462	* push ECX [51]
2463	* push EDX [52]
2464	* push EAX [50]
2465	* mov ECX,0C0000082h [B9 82 00 00 C0]
2466	* rdmsr [0F 32]
2467	* mov EAX,EAX [89 C0]
2468	* pop EAX [58]
2469	* pop EDX [5A]
2470	* pop ECX [59]
2471	* jmp return_address [E9 return_address]
2472	*/
2473	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2474
2475	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2476	aPatch[off++] = 0x51; /* push ecx */
2477	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2478	aPatch[off++] = 0x52; /* push edx */
2479	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2480	aPatch[off++] = 0x50; /* push eax */
2481
2482	aPatch[off++] = 0x31; /* xor edx, edx */
2483	aPatch[off++] = 0xd2;
2484
2485	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2486	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2487	off += sizeof(uint32_t);
2488
2489	aPatch[off++] = 0x0f; /* rdmsr */
2490	aPatch[off++] = 0x32;
2491
2492	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2493	{
2494	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2495	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2496	}
2497
2498	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2499	aPatch[off++] = 0x58; /* pop eax */
2500	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2501	aPatch[off++] = 0x5a; /* pop edx */
2502	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2503	aPatch[off++] = 0x59; /* pop ecx */
2504	}
2505	aPatch[off++] = 0xe9; /* jmp return_address */
2506	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2507	off += sizeof(RTRCUINTPTR);
2508
2509	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2510	{
2511	/* Write new code to the patch buffer. */
2512	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2513	AssertRC(rc);
2514
2515	#ifdef LOG_ENABLED
2516	uint32_t cbCurInstr;
2517	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2518	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2519	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2520	{
2521	char szOutput[256];
2522	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2523	szOutput, sizeof(szOutput), &cbCurInstr);
2524	if (RT_SUCCESS(rc))
2525	Log(("Patch instr %s\n", szOutput));
2526	else
2527	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2528	}
2529	#endif
2530
2531	pPatch->aNewOpcode[0] = 0xE9;
2532	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2533
2534	/* Overwrite the TPR instruction with a jump. */
2535	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2536	AssertRC(rc);
2537
2538	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2539
2540	pVM->hm.s.pFreeGuestPatchMem += off;
2541	pPatch->cbNewOp = 5;
2542
2543	pPatch->Core.Key = pCtx->eip;
2544	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2545	AssertRC(rc);
2546
2547	pVM->hm.s.cPatches++;
2548	pVM->hm.s.fTprPatchingActive = true;
2549	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2550	return VINF_SUCCESS;
2551	}
2552
2553	Log(("Ran out of space in our patch buffer!\n"));
2554	}
2555	else
2556	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2557
2558
2559	/*
2560	* Save invalid patch, so we will not try again.
2561	*/
2562	pPatch = &pVM->hm.s.aPatches[idx];
2563	pPatch->Core.Key = pCtx->eip;
2564	pPatch->enmType = HMTPRINSTR_INVALID;
2565	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2566	AssertRC(rc);
2567	pVM->hm.s.cPatches++;
2568	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2569	return VINF_SUCCESS;
2570	}
2571
2572
2573	/**
2574	* Attempt to patch TPR mmio instructions.
2575	*
2576	* @returns VBox status code.
2577	* @param pVM The cross context VM structure.
2578	* @param pVCpu The cross context virtual CPU structure.
2579	*/
2580	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2581	{
2582	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2583	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2584	(void *)(uintptr_t)pVCpu->idCpu);
2585	AssertRC(rc);
2586	return rc;
2587	}
2588
2589
2590	/**
2591	* Checks if we need to reschedule due to VMM device heap changes.
2592	*
2593	* @returns true if a reschedule is required, otherwise false.
2594	* @param pVM The cross context VM structure.
2595	* @param pCtx VM execution context.
2596	*/
2597	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2598	{
2599	/*
2600	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2601	* when the unrestricted guest execution feature is missing (VT-x only).
2602	*/
2603	if ( pVM->hm.s.vmx.fEnabled
2604	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2605	&& CPUMIsGuestInRealModeEx(pCtx)
2606	&& !PDMVmmDevHeapIsEnabled(pVM))
2607	return true;
2608
2609	return false;
2610	}
2611
2612
2613	/**
2614	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2615	* event settings changes.
2616	*
2617	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2618	* function is just updating the VM globals.
2619	*
2620	* @param pVM The VM cross context VM structure.
2621	* @thread EMT(0)
2622	*/
2623	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2624	{
2625	/* Interrupts. */
2626	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2627	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2628
2629	/* CPU Exceptions. */
2630	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2631	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2632	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2633	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2634
2635	/* Common VM exits. */
2636	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2637	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2638	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2639	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2640
2641	/* Vendor specific VM exits. */
2642	if (HMR3IsVmxEnabled(pVM->pUVM))
2643	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2644	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2645	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2646	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2647	else
2648	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2649	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2650	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2651	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2652
2653	/* Done. */
2654	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2655	}
2656
2657
2658	/**
2659	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2660	*
2661	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2662	* per CPU settings.
2663	*
2664	* @param pVM The VM cross context VM structure.
2665	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2666	*/
2667	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2668	{
2669	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2670	}
2671
2672
2673	/**
2674	* Checks if we are currently using hardware acceleration.
2675	*
2676	* @returns true if hardware acceleration is being used, otherwise false.
2677	* @param pVCpu The cross context virtual CPU structure.
2678	*/
2679	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2680	{
2681	return pVCpu->hm.s.fActive;
2682	}
2683
2684
2685	/**
2686	* External interface for querying whether hardware acceleration is enabled.
2687	*
2688	* @returns true if VT-x or AMD-V is being used, otherwise false.
2689	* @param pUVM The user mode VM handle.
2690	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2691	*/
2692	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2693	{
2694	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2695	PVM pVM = pUVM->pVM;
2696	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2697	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2698	}
2699
2700
2701	/**
2702	* External interface for querying whether VT-x is being used.
2703	*
2704	* @returns true if VT-x is being used, otherwise false.
2705	* @param pUVM The user mode VM handle.
2706	* @sa HMR3IsSvmEnabled, HMIsEnabled
2707	*/
2708	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2709	{
2710	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2711	PVM pVM = pUVM->pVM;
2712	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2713	return pVM->hm.s.vmx.fEnabled
2714	&& pVM->hm.s.vmx.fSupported
2715	&& pVM->fHMEnabled;
2716	}
2717
2718
2719	/**
2720	* External interface for querying whether AMD-V is being used.
2721	*
2722	* @returns true if VT-x is being used, otherwise false.
2723	* @param pUVM The user mode VM handle.
2724	* @sa HMR3IsVmxEnabled, HMIsEnabled
2725	*/
2726	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2727	{
2728	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2729	PVM pVM = pUVM->pVM;
2730	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2731	return pVM->hm.s.svm.fEnabled
2732	&& pVM->hm.s.svm.fSupported
2733	&& pVM->fHMEnabled;
2734	}
2735
2736
2737	/**
2738	* Checks if we are currently using nested paging.
2739	*
2740	* @returns true if nested paging is being used, otherwise false.
2741	* @param pUVM The user mode VM handle.
2742	*/
2743	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2744	{
2745	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2746	PVM pVM = pUVM->pVM;
2747	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2748	return pVM->hm.s.fNestedPagingCfg;
2749	}
2750
2751
2752	/**
2753	* Checks if virtualized APIC registers are enabled.
2754	*
2755	* When enabled this feature allows the hardware to access most of the
2756	* APIC registers in the virtual-APIC page without causing VM-exits. See
2757	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2758	*
2759	* @returns true if virtualized APIC registers is enabled, otherwise
2760	* false.
2761	* @param pUVM The user mode VM handle.
2762	*/
2763	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2764	{
2765	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2766	PVM pVM = pUVM->pVM;
2767	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2768	return pVM->hm.s.fVirtApicRegs;
2769	}
2770
2771
2772	/**
2773	* Checks if APIC posted-interrupt processing is enabled.
2774	*
2775	* This returns whether we can deliver interrupts to the guest without
2776	* leaving guest-context by updating APIC state from host-context.
2777	*
2778	* @returns true if APIC posted-interrupt processing is enabled,
2779	* otherwise false.
2780	* @param pUVM The user mode VM handle.
2781	*/
2782	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2783	{
2784	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2785	PVM pVM = pUVM->pVM;
2786	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2787	return pVM->hm.s.fPostedIntrs;
2788	}
2789
2790
2791	/**
2792	* Checks if we are currently using VPID in VT-x mode.
2793	*
2794	* @returns true if VPID is being used, otherwise false.
2795	* @param pUVM The user mode VM handle.
2796	*/
2797	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2798	{
2799	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2800	PVM pVM = pUVM->pVM;
2801	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2802	return pVM->hm.s.ForR3.vmx.fVpid;
2803	}
2804
2805
2806	/**
2807	* Checks if we are currently using VT-x unrestricted execution,
2808	* aka UX.
2809	*
2810	* @returns true if UX is being used, otherwise false.
2811	* @param pUVM The user mode VM handle.
2812	*/
2813	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2814	{
2815	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2816	PVM pVM = pUVM->pVM;
2817	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2818	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2819	\|\| pVM->hm.s.svm.fSupported;
2820	}
2821
2822
2823	/**
2824	* Checks if the VMX-preemption timer is being used.
2825	*
2826	* @returns true if the VMX-preemption timer is being used, otherwise false.
2827	* @param pVM The cross context VM structure.
2828	*/
2829	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2830	{
2831	return HMIsEnabled(pVM)
2832	&& pVM->hm.s.vmx.fEnabled
2833	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2834	}
2835
2836
2837	#ifdef TODO_9217_VMCSINFO
2838	/**
2839	* Helper for HMR3CheckError to log VMCS controls to the release log.
2840	*
2841	* @param idCpu The Virtual CPU ID.
2842	* @param pVmcsInfo The VMCS info. object.
2843	*/
2844	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2845	{
2846	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2847	{
2848	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2849	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2850	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2851	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2852	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2853	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2854	}
2855	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2856	{
2857	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2858	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2859	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2860	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2861	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2862	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2863	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2864	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2865	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2866	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2867	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2868	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2869	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2870	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2871	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2872	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2873	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2874	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2875	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2876	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2877	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2878	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2879	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2880	}
2881	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2882	{
2883	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2884	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2885	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2886	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2887	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2888	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2893	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2894	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2895	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2896	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2897	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2898	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2905	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2911	}
2912	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2913	{
2914	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2927	}
2928	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2929	{
2930	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
2945	}
2946	}
2947	#endif
2948
2949
2950	/**
2951	* Check fatal VT-x/AMD-V error and produce some meaningful
2952	* log release message.
2953	*
2954	* @param pVM The cross context VM structure.
2955	* @param iStatusCode VBox status code.
2956	*/
2957	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2958	{
2959	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2960	{
2961	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2962	* might be getting inaccurate values for non-guru'ing EMTs. */
2963	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2964	#ifdef TODO_9217_VMCSINFO
2965	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
2966	#endif
2967	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
2968	switch (iStatusCode)
2969	{
2970	case VERR_VMX_INVALID_VMCS_PTR:
2971	{
2972	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2973	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2974	#ifdef TODO_9217_VMCSINFO
2975	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2976	pVmcsInfo->HCPhysVmcs));
2977	#endif
2978	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2979	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2980	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2981	break;
2982	}
2983
2984	case VERR_VMX_UNABLE_TO_START_VM:
2985	{
2986	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2987	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2988	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
2989	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2990
2991	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
2992	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
2993	{
2994	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2995	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2996	}
2997	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
2998	{
2999	#ifdef TODO_9217_VMCSINFO
3000	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3001	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3002	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3003	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3004	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3005	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3006	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3007	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3008	#endif
3009	}
3010	/** @todo Log VM-entry event injection control fields
3011	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3012	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3013	break;
3014	}
3015
3016	case VERR_VMX_INVALID_GUEST_STATE:
3017	{
3018	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3019	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3020	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3021	#ifdef TODO_9217_VMCSINFO
3022	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3023	#endif
3024	break;
3025	}
3026
3027	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3028	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3029	case VERR_VMX_INVALID_VMXON_PTR:
3030	case VERR_VMX_UNEXPECTED_EXIT:
3031	case VERR_VMX_INVALID_VMCS_FIELD:
3032	case VERR_SVM_UNKNOWN_EXIT:
3033	case VERR_SVM_UNEXPECTED_EXIT:
3034	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3035	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3036	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3037	break;
3038	}
3039	}
3040
3041	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3042	{
3043	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3044	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3045	}
3046	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3047	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3048	}
3049
3050
3051	/**
3052	* Execute state save operation.
3053	*
3054	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3055	* is because we always save the VM state from ring-3 and thus most HM state
3056	* will be re-synced dynamically at runtime and don't need to be part of the VM
3057	* saved state.
3058	*
3059	* @returns VBox status code.
3060	* @param pVM The cross context VM structure.
3061	* @param pSSM SSM operation handle.
3062	*/
3063	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3064	{
3065	Log(("hmR3Save:\n"));
3066
3067	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3068	{
3069	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3070	Assert(!pVCpu->hm.s.Event.fPending);
3071	if (pVM->cpum.ro.GuestFeatures.fSvm)
3072	{
3073	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3074	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3075	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3076	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3077	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3078	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3079	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3080	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3081	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3082	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3083	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3084	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3085	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3086	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3087	}
3088	}
3089
3090	/* Save the guest patch data. */
3091	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3092	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3093	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3094
3095	/* Store all the guest patch records too. */
3096	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3097	if (RT_FAILURE(rc))
3098	return rc;
3099
3100	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3101	{
3102	AssertCompileSize(HMTPRINSTR, 4);
3103	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3104	SSMR3PutU32(pSSM, pPatch->Core.Key);
3105	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3106	SSMR3PutU32(pSSM, pPatch->cbOp);
3107	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3108	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3109	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3110	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3111	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3112	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3113	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3114	if (RT_FAILURE(rc))
3115	return rc;
3116	}
3117
3118	return VINF_SUCCESS;
3119	}
3120
3121
3122	/**
3123	* Execute state load operation.
3124	*
3125	* @returns VBox status code.
3126	* @param pVM The cross context VM structure.
3127	* @param pSSM SSM operation handle.
3128	* @param uVersion Data layout version.
3129	* @param uPass The data pass.
3130	*/
3131	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3132	{
3133	int rc;
3134
3135	LogFlowFunc(("uVersion=%u\n", uVersion));
3136	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3137
3138	/*
3139	* Validate version.
3140	*/
3141	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3142	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3143	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3144	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3145	{
3146	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3147	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3148	}
3149
3150	/*
3151	* Load per-VCPU state.
3152	*/
3153	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3154	{
3155	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3156	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3157	{
3158	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3159	if (pVM->cpum.ro.GuestFeatures.fSvm)
3160	{
3161	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3162	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3163	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3164	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3165	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3166	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3167	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3168	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3169	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3170	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3171	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3172	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3173	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3174	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3175	AssertRCReturn(rc, rc);
3176	}
3177	}
3178	else
3179	{
3180	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3181	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3182	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3183	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3184
3185	/* VMX fWasInRealMode related data. */
3186	uint32_t uDummy;
3187	SSMR3GetU32(pSSM, &uDummy);
3188	SSMR3GetU32(pSSM, &uDummy);
3189	rc = SSMR3GetU32(pSSM, &uDummy);
3190	AssertRCReturn(rc, rc);
3191	}
3192	}
3193
3194	/*
3195	* Load TPR patching data.
3196	*/
3197	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3198	{
3199	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3200	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3201	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3202
3203	/* Fetch all TPR patch records. */
3204	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3205	AssertRCReturn(rc, rc);
3206	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3207	{
3208	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3209	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3210	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3211	SSMR3GetU32(pSSM, &pPatch->cbOp);
3212	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3213	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3214	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3215
3216	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3217	pVM->hm.s.fTprPatchingActive = true;
3218	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3219
3220	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3221	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3222	SSMR3GetU32(pSSM, &pPatch->cFaults);
3223	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3224	AssertRCReturn(rc, rc);
3225
3226	LogFlow(("hmR3Load: patch %d\n", i));
3227	LogFlow(("Key = %x\n", pPatch->Core.Key));
3228	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3229	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3230	LogFlow(("type = %d\n", pPatch->enmType));
3231	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3232	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3233	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3234	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3235
3236	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3237	AssertRCReturn(rc, rc);
3238	}
3239	}
3240
3241	return VINF_SUCCESS;
3242	}
3243
3244
3245	/**
3246	* Displays HM info.
3247	*
3248	* @param pVM The cross context VM structure.
3249	* @param pHlp The info helper functions.
3250	* @param pszArgs Arguments, ignored.
3251	*/
3252	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3253	{
3254	NOREF(pszArgs);
3255	PVMCPU pVCpu = VMMGetCpu(pVM);
3256	if (!pVCpu)
3257	pVCpu = pVM->apCpusR3[0];
3258
3259	if (HMIsEnabled(pVM))
3260	{
3261	if (pVM->hm.s.vmx.fSupported)
3262	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3263	else
3264	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3265	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3266	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3267	if (pVM->hm.s.vmx.fSupported)
3268	{
3269	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3270	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3271	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3272
3273	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3274	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3275	if (fRealOnV86Active)
3276	{
3277	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3278	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3279	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3280	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3281	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3282	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3283	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3284	}
3285	}
3286	}
3287	else
3288	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3289	}
3290
3291
3292	/**
3293	* Displays the HM Last-Branch-Record info. for the guest.
3294	*
3295	* @param pVM The cross context VM structure.
3296	* @param pHlp The info helper functions.
3297	* @param pszArgs Arguments, ignored.
3298	*/
3299	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3300	{
3301	NOREF(pszArgs);
3302	PVMCPU pVCpu = VMMGetCpu(pVM);
3303	if (!pVCpu)
3304	pVCpu = pVM->apCpusR3[0];
3305
3306	if (!HMIsEnabled(pVM))
3307	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3308	else if (HMIsVmxActive(pVM))
3309	{
3310	if (pVM->hm.s.vmx.fLbrCfg)
3311	{
3312	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3313	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3314
3315	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3316	* 0xf should cover everything we support thus far. Fix if necessary
3317	* later. */
3318	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3319	if (idxTopOfStack > cLbrStack)
3320	{
3321	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3322	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3323	return;
3324	}
3325
3326	/*
3327	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3328	*/
3329	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3330	uint32_t idxCurrent = idxTopOfStack;
3331	Assert(idxTopOfStack < cLbrStack);
3332	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3333	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3334	for (;;)
3335	{
3336	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3337	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3338	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3339	else
3340	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3341
3342	idxCurrent = (idxCurrent - 1) % cLbrStack;
3343	if (idxCurrent == idxTopOfStack)
3344	break;
3345	}
3346	}
3347	else
3348	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3349	}
3350	else
3351	{
3352	Assert(HMIsSvmActive(pVM));
3353	/** @todo SVM: LBRs (get them from VMCB if possible). */
3354	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3355	}
3356	}
3357
3358
3359	/**
3360	* Displays the HM pending event.
3361	*
3362	* @param pVM The cross context VM structure.
3363	* @param pHlp The info helper functions.
3364	* @param pszArgs Arguments, ignored.
3365	*/
3366	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3367	{
3368	NOREF(pszArgs);
3369	PVMCPU pVCpu = VMMGetCpu(pVM);
3370	if (!pVCpu)
3371	pVCpu = pVM->apCpusR3[0];
3372
3373	if (HMIsEnabled(pVM))
3374	{
3375	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3376	if (pVCpu->hm.s.Event.fPending)
3377	{
3378	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3379	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3380	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3381	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3382	}
3383	}
3384	else
3385	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3386	}
3387
3388
3389	/**
3390	* Displays the SVM nested-guest VMCB cache.
3391	*
3392	* @param pVM The cross context VM structure.
3393	* @param pHlp The info helper functions.
3394	* @param pszArgs Arguments, ignored.
3395	*/
3396	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3397	{
3398	NOREF(pszArgs);
3399	PVMCPU pVCpu = VMMGetCpu(pVM);
3400	if (!pVCpu)
3401	pVCpu = pVM->apCpusR3[0];
3402
3403	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3404	if ( fSvmEnabled
3405	&& pVM->cpum.ro.GuestFeatures.fSvm)
3406	{
3407	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3408	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3409	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3410	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3411	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3412	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3413	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3414	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3415	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3416	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3417	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3418	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3419	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3420	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3421	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3422	}
3423	else
3424	{
3425	if (!fSvmEnabled)
3426	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3427	else
3428	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3429	}
3430	}
3431

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 92676

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