HM.cpp@ 93732

Last change on this file since 93732 was 93729, checked in by vboxsync, 3 years ago
VMM/HM: Need to postpone registering the debug info handlers further, bugref:9044
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1	/* $Id: HM.cpp 93729 2022-02-14 14:33:32Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/trpm.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/iom.h>
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#include <VBox/vmm/hm_vmx.h>
55	#include <VBox/vmm/hm_svm.h>
56	#include "HMInternal.h"
57	#include <VBox/vmm/vmcc.h>
58	#include <VBox/err.h>
59	#include <VBox/param.h>
60
61	#include <iprt/assert.h>
62	#include <VBox/log.h>
63	#include <iprt/asm.h>
64	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
65	# include <iprt/asm-amd64-x86.h>
66	#endif
67	#include <iprt/env.h>
68	#include <iprt/thread.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74	/** @def HMVMX_REPORT_FEAT
75	* Reports VT-x feature to the release log.
76	*
77	* @param a_uAllowed1 Mask of allowed-1 feature bits.
78	* @param a_uAllowed0 Mask of allowed-0 feature bits.
79	* @param a_StrDesc The description string to report.
80	* @param a_Featflag Mask of the feature to report.
81	*/
82	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
83	do { \
84	if ((a_uAllowed1) & (a_Featflag)) \
85	{ \
86	if ((a_uAllowed0) & (a_Featflag)) \
87	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
88	else \
89	LogRel(("HM: " a_StrDesc "\n")); \
90	} \
91	else \
92	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
93	} while (0)
94
95	/** @def HMVMX_REPORT_ALLOWED_FEAT
96	* Reports an allowed VT-x feature to the release log.
97	*
98	* @param a_uAllowed1 Mask of allowed-1 feature bits.
99	* @param a_StrDesc The description string to report.
100	* @param a_FeatFlag Mask of the feature to report.
101	*/
102	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
103	do { \
104	if ((a_uAllowed1) & (a_FeatFlag)) \
105	LogRel(("HM: " a_StrDesc "\n")); \
106	else \
107	LogRel(("HM: " a_StrDesc " not supported\n")); \
108	} while (0)
109
110	/** @def HMVMX_REPORT_MSR_CAP
111	* Reports MSR feature capability.
112	*
113	* @param a_MsrCaps Mask of MSR feature bits.
114	* @param a_StrDesc The description string to report.
115	* @param a_fCap Mask of the feature to report.
116	*/
117	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
118	do { \
119	if ((a_MsrCaps) & (a_fCap)) \
120	LogRel(("HM: " a_StrDesc "\n")); \
121	} while (0)
122
123	/** @def HMVMX_LOGREL_FEAT
124	* Dumps a feature flag from a bitmap of features to the release log.
125	*
126	* @param a_fVal The value of all the features.
127	* @param a_fMask The specific bitmask of the feature.
128	*/
129	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
130	do { \
131	if ((a_fVal) & (a_fMask)) \
132	LogRel(("HM: %s\n", #a_fMask)); \
133	} while (0)
134
135
136	/*********************************************************************************************************************************
137	* Internal Functions *
138	*********************************************************************************************************************************/
139	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
140	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
141	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
145	static int hmR3InitFinalizeR3(PVM pVM);
146	static int hmR3InitFinalizeR0(PVM pVM);
147	static int hmR3InitFinalizeR0Intel(PVM pVM);
148	static int hmR3InitFinalizeR0Amd(PVM pVM);
149	static int hmR3TermCPU(PVM pVM);
150
151
152	#ifdef VBOX_WITH_STATISTICS
153	/**
154	* Returns the name of the hardware exception.
155	*
156	* @returns The name of the hardware exception.
157	* @param uVector The exception vector.
158	*/
159	static const char *hmR3GetXcptName(uint8_t uVector)
160	{
161	switch (uVector)
162	{
163	case X86_XCPT_DE: return "#DE";
164	case X86_XCPT_DB: return "#DB";
165	case X86_XCPT_NMI: return "#NMI";
166	case X86_XCPT_BP: return "#BP";
167	case X86_XCPT_OF: return "#OF";
168	case X86_XCPT_BR: return "#BR";
169	case X86_XCPT_UD: return "#UD";
170	case X86_XCPT_NM: return "#NM";
171	case X86_XCPT_DF: return "#DF";
172	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
173	case X86_XCPT_TS: return "#TS";
174	case X86_XCPT_NP: return "#NP";
175	case X86_XCPT_SS: return "#SS";
176	case X86_XCPT_GP: return "#GP";
177	case X86_XCPT_PF: return "#PF";
178	case X86_XCPT_MF: return "#MF";
179	case X86_XCPT_AC: return "#AC";
180	case X86_XCPT_MC: return "#MC";
181	case X86_XCPT_XF: return "#XF";
182	case X86_XCPT_VE: return "#VE";
183	case X86_XCPT_CP: return "#CP";
184	case X86_XCPT_VC: return "#VC";
185	case X86_XCPT_SX: return "#SX";
186	}
187	return "Reserved";
188	}
189	#endif /* VBOX_WITH_STATISTICS */
190
191
192	/**
193	* Initializes the HM.
194	*
195	* This is the very first component to really do init after CFGM so that we can
196	* establish the predominant execution engine for the VM prior to initializing
197	* other modules. It takes care of NEM initialization if needed (HM disabled or
198	* not available in HW).
199	*
200	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
201	* hypervisor API via NEM, and then back on raw-mode if that isn't available
202	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
203	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
204	* X, OS/2 and others).
205	*
206	* Note that a lot of the set up work is done in ring-0 and thus postponed till
207	* the ring-3 and ring-0 callback to HMR3InitCompleted.
208	*
209	* @returns VBox status code.
210	* @param pVM The cross context VM structure.
211	*
212	* @remarks Be careful with what we call here, since most of the VMM components
213	* are uninitialized.
214	*/
215	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
216	{
217	LogFlowFunc(("\n"));
218
219	/*
220	* Assert alignment and sizes.
221	*/
222	AssertCompileMemberAlignment(VM, hm.s, 32);
223	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
224
225	/*
226	* Register the saved state data unit.
227	*/
228	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
229	NULL, NULL, NULL,
230	NULL, hmR3Save, NULL,
231	NULL, hmR3Load, NULL);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Read configuration.
237	*/
238	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
239
240	/*
241	* Validate the HM settings.
242	*/
243	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
244	"HMForced" /* implied 'true' these days */
245	"\|UseNEMInstead"
246	"\|FallbackToNEM"
247	"\|EnableNestedPaging"
248	"\|EnableUX"
249	"\|EnableLargePages"
250	"\|EnableVPID"
251	"\|IBPBOnVMExit"
252	"\|IBPBOnVMEntry"
253	"\|SpecCtrlByHost"
254	"\|L1DFlushOnSched"
255	"\|L1DFlushOnVMEntry"
256	"\|MDSClearOnSched"
257	"\|MDSClearOnVMEntry"
258	"\|TPRPatchingEnabled"
259	"\|64bitEnabled"
260	"\|Exclusive"
261	"\|MaxResumeLoops"
262	"\|VmxPleGap"
263	"\|VmxPleWindow"
264	"\|VmxLbr"
265	"\|UseVmxPreemptTimer"
266	"\|SvmPauseFilter"
267	"\|SvmPauseFilterThreshold"
268	"\|SvmVirtVmsaveVmload"
269	"\|SvmVGif"
270	"\|LovelyMesaDrvWorkaround"
271	"\|MissingOS2TlbFlushWorkaround",
272	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
273	if (RT_FAILURE(rc))
274	return rc;
275
276	/** @cfgm{/HM/HMForced, bool, false}
277	* Forces hardware virtualization, no falling back on raw-mode. HM must be
278	* enabled, i.e. /HMEnabled must be true. */
279	bool fHMForced;
280	AssertRelease(pVM->fHMEnabled);
281	fHMForced = true;
282
283	/** @cfgm{/HM/UseNEMInstead, bool, true}
284	* Don't use HM, use NEM instead. */
285	bool fUseNEMInstead = false;
286	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
287	AssertRCReturn(rc, rc);
288	if (fUseNEMInstead && pVM->fHMEnabled)
289	{
290	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
291	pVM->fHMEnabled = false;
292	}
293
294	/** @cfgm{/HM/FallbackToNEM, bool, true}
295	* Enables fallback on NEM. */
296	bool fFallbackToNEM = true;
297	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
298	AssertRCReturn(rc, rc);
299
300	/** @cfgm{/HM/EnableNestedPaging, bool, false}
301	* Enables nested paging (aka extended page tables). */
302	bool fAllowNestedPaging = false;
303	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
304	AssertRCReturn(rc, rc);
305
306	/** @cfgm{/HM/EnableUX, bool, true}
307	* Enables the VT-x unrestricted execution feature. */
308	bool fAllowUnrestricted = true;
309	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
310	AssertRCReturn(rc, rc);
311
312	/** @cfgm{/HM/EnableLargePages, bool, false}
313	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
314	* page table walking and maybe better TLB hit rate in some cases. */
315	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
316	AssertRCReturn(rc, rc);
317
318	/** @cfgm{/HM/EnableVPID, bool, false}
319	* Enables the VT-x VPID feature. */
320	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
321	AssertRCReturn(rc, rc);
322
323	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
324	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
325	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
326	AssertRCReturn(rc, rc);
327
328	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
329	* Enables AMD64 cpu features.
330	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
331	* already have the support. */
332	#ifdef VBOX_WITH_64_BITS_GUESTS
333	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
334	AssertLogRelRCReturn(rc, rc);
335	#else
336	pVM->hm.s.fAllow64BitGuestsCfg = false;
337	#endif
338
339	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
340	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
341	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
342	* latest PAUSE instruction to be start of a new PAUSE loop.
343	*/
344	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
345	AssertRCReturn(rc, rc);
346
347	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
348	* The pause-filter exiting window in TSC ticks. When the number of ticks
349	* between the current PAUSE instruction and first PAUSE of a loop exceeds
350	* VmxPleWindow, a VM-exit is triggered.
351	*
352	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
353	*/
354	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
355	AssertRCReturn(rc, rc);
356
357	/** @cfgm{/HM/VmxLbr, bool, false}
358	* Whether to enable LBR for the guest. This is disabled by default as it's only
359	* useful while debugging and enabling it causes a noticeable performance hit. */
360	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
361	AssertRCReturn(rc, rc);
362
363	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
364	* A counter that is decrement each time a PAUSE instruction is executed by the
365	* guest. When the counter is 0, a \#VMEXIT is triggered.
366	*
367	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
373	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
374	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
375	* PauseFilter count is reset to its initial value. However, if PAUSE is
376	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
377	* be triggered.
378	*
379	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
380	* activated.
381	*/
382	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
383	AssertRCReturn(rc, rc);
384
385	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
386	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
387	* available. */
388	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
389	AssertRCReturn(rc, rc);
390
391	/** @cfgm{/HM/SvmVGif, bool, true}
392	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
393	* if it's available. */
394	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{/HM/SvmLbrVirt, bool, false}
398	* Whether to make use of the LBR virtualization feature of the CPU if it's
399	* available. This is disabled by default as it's only useful while debugging
400	* and enabling it causes a small hit to performance. */
401	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
402	AssertRCReturn(rc, rc);
403
404	/** @cfgm{/HM/Exclusive, bool}
405	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
406	* global init for each host CPU. If false, we do local init each time we wish
407	* to execute guest code.
408	*
409	* On Windows, default is false due to the higher risk of conflicts with other
410	* hypervisors.
411	*
412	* On Mac OS X, this setting is ignored since the code does not handle local
413	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
414	*/
415	#if defined(RT_OS_DARWIN)
416	pVM->hm.s.fGlobalInit = true;
417	#else
418	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
419	# if defined(RT_OS_WINDOWS)
420	false
421	# else
422	true
423	# endif
424	);
425	AssertLogRelRCReturn(rc, rc);
426	#endif
427
428	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
429	* The number of times to resume guest execution before we forcibly return to
430	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
431	* determines the default value. */
432	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
433	AssertLogRelRCReturn(rc, rc);
434
435	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
436	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
437	* available. */
438	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
439	AssertLogRelRCReturn(rc, rc);
440
441	/** @cfgm{/HM/IBPBOnVMExit, bool}
442	* Costly paranoia setting. */
443	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
444	AssertLogRelRCReturn(rc, rc);
445
446	/** @cfgm{/HM/IBPBOnVMEntry, bool}
447	* Costly paranoia setting. */
448	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
449	AssertLogRelRCReturn(rc, rc);
450
451	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
452	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
457	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
462	if (pVM->hm.s.fL1dFlushOnVmEntry)
463	pVM->hm.s.fL1dFlushOnSched = false;
464
465	/** @cfgm{/HM/SpecCtrlByHost, bool}
466	* Another expensive paranoia setting. */
467	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/HM/MDSClearOnSched, bool, true}
471	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
472	* ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
474	AssertLogRelRCReturn(rc, rc);
475
476	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
477	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
478	* ignored on CPUs that aren't affected. */
479	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
480	AssertLogRelRCReturn(rc, rc);
481
482	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
483	if (pVM->hm.s.fMdsClearOnVmEntry)
484	pVM->hm.s.fMdsClearOnSched = false;
485
486	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
487	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
488	* the hypervisor it is running under. */
489	bool fMesaWorkaround;
490	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
491	AssertLogRelRCReturn(rc, rc);
492	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
493	{
494	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
495	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
496	}
497
498	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
499	* Workaround OS/2 not flushing the TLB after page directory and page table
500	* modifications when returning to protected mode from a real mode call
501	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
502	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
503	AssertLogRelRCReturn(rc, rc);
504
505	/*
506	* Check if VT-x or AMD-v support according to the users wishes.
507	*/
508	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
509	* VERR_SVM_IN_USE. */
510	if (pVM->fHMEnabled)
511	{
512	uint32_t fCaps;
513	rc = SUPR3QueryVTCaps(&fCaps);
514	if (RT_SUCCESS(rc))
515	{
516	if (fCaps & SUPVTCAPS_AMD_V)
517	{
518	pVM->hm.s.svm.fSupported = true;
519	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
520	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
521	}
522	else if (fCaps & SUPVTCAPS_VT_X)
523	{
524	const char *pszWhy;
525	rc = SUPR3QueryVTxSupported(&pszWhy);
526	if (RT_SUCCESS(rc))
527	{
528	pVM->hm.s.vmx.fSupported = true;
529	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
530	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
531	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
532	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
533	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
534	}
535	else
536	{
537	/*
538	* Before failing, try fallback to NEM if we're allowed to do that.
539	*/
540	pVM->fHMEnabled = false;
541	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
542	if (fFallbackToNEM)
543	{
544	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
545	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
546
547	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
548	if ( RT_SUCCESS(rc2)
549	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
550	rc = VINF_SUCCESS;
551	}
552	if (RT_FAILURE(rc))
553	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
554	}
555	}
556	else
557	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
558	VERR_INTERNAL_ERROR_5);
559
560	/*
561	* Disable nested paging and unrestricted guest execution now if they're
562	* configured so that CPUM can make decisions based on our configuration.
563	*/
564	if ( fAllowNestedPaging
565	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
566	{
567	pVM->hm.s.fNestedPagingCfg = true;
568	if (fCaps & SUPVTCAPS_VT_X)
569	{
570	if ( fAllowUnrestricted
571	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
572	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
573	else
574	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
575	}
576	}
577	else
578	Assert(!pVM->hm.s.fNestedPagingCfg);
579	}
580	else
581	{
582	const char *pszMsg;
583	switch (rc)
584	{
585	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
586	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
587	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
588	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
589	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
590	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
591	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
592	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
593	default:
594	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
595	}
596
597	/*
598	* Before failing, try fallback to NEM if we're allowed to do that.
599	*/
600	pVM->fHMEnabled = false;
601	if (fFallbackToNEM)
602	{
603	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
604	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
605	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
606	if ( RT_SUCCESS(rc2)
607	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
608	{
609	rc = VINF_SUCCESS;
610
611	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
612	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
613	}
614	}
615	if (RT_FAILURE(rc))
616	return VM_SET_ERROR(pVM, rc, pszMsg);
617	}
618	}
619	else
620	{
621	/*
622	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
623	*/
624	if (fUseNEMInstead)
625	{
626	rc = NEMR3Init(pVM, false /fFallback/, true);
627	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
628	if (RT_FAILURE(rc))
629	return rc;
630
631	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
632	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
633	}
634	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
635	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
636	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
637	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
638	}
639
640	if (pVM->fHMEnabled)
641	{
642	/*
643	* Register info handlers now that HM is used for sure.
644	*/
645	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
646	AssertRCReturn(rc, rc);
647
648	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
649	DBGFINFO_FLAGS_ALL_EMTS);
650	AssertRCReturn(rc, rc);
651
652	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
653	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
654	AssertRCReturn(rc, rc);
655
656	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
657	AssertRCReturn(rc, rc);
658	}
659
660	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
661	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
662	return VINF_SUCCESS;
663	}
664
665
666	/**
667	* Initializes HM components after ring-3 phase has been fully initialized.
668	*
669	* @returns VBox status code.
670	* @param pVM The cross context VM structure.
671	*/
672	static int hmR3InitFinalizeR3(PVM pVM)
673	{
674	LogFlowFunc(("\n"));
675
676	if (!HMIsEnabled(pVM))
677	return VINF_SUCCESS;
678
679	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
680	{
681	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
682	pVCpu->hm.s.fActive = false;
683	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
684	}
685
686	/*
687	* Check if L1D flush is needed/possible.
688	*/
689	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
690	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
691	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
692	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
693	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
694	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
695
696	/*
697	* Check if MDS flush is needed/possible.
698	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
699	*/
700	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
701	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
702	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
703	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
704	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
705	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
706	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
707	{
708	if (!pVM->hm.s.fMdsClearOnSched)
709	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
710	pVM->hm.s.fMdsClearOnVmEntry = false;
711	}
712	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
713	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
714	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
715
716	/*
717	* Statistics.
718	*/
719	#ifdef VBOX_WITH_STATISTICS
720	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
721	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
722	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
723	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
724	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
725	#endif
726
727	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
728	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
729	{
730	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
731	PHMCPU pHmCpu = &pVCpu->hm.s;
732	int rc;
733
734	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
735	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
736	AssertRC(rc); \
737	} while (0)
738	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
739	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
740
741	#ifdef VBOX_WITH_STATISTICS
742
743	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
744	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
745	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
746	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
747	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
748	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
749	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
750	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
751	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
752	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
753	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
754	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
755	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
756	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
757	# ifdef HM_PROFILE_EXIT_DISPATCH
758	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
759	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
760	# endif
761	#endif
762	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
763
764	#ifdef VBOX_WITH_STATISTICS
765	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
766	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
767	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
768	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
769	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
770	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
771	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
772	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
773	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
774	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
775	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
776	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
777	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
778	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
779	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
780	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
781	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
782	#endif
783	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
784	if (fCpuSupportsVmx)
785	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
786	#ifdef VBOX_WITH_STATISTICS
787	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
788	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
789	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
790	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
791	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
792	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
793	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
794	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
795	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
796	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
797	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
798	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
799	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
800	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
801	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
802	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
803	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
804	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
805	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
806	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
807	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
808	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
809	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
810	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
811	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
812	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
813	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
814	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
815	#endif
816	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
817	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
818	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
819	#ifdef VBOX_WITH_STATISTICS
820	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
821	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
822	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
823
824	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
825	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
826	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
827	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
828	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
829	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
830	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
831	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
832	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
833	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
834	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
835	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
836	#endif
837	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
838	#ifdef VBOX_WITH_STATISTICS
839	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
840
841	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
842	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
843	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
844	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
845	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
846	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
847
848	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
849	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
850	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
851	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
852	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
853	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
854	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
855	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
856	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
857	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
858	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
859	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
860	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
861	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
862	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
863
864	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
865	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
866	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
867
868	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
869	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
870	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
871
872	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
873	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
874	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
875	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
876
877	if (fCpuSupportsVmx)
878	{
879	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
880	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
881	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
882	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
883	}
884
885	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
886	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
887	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
888
889	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
890	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
891	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
892
893	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
894	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
895	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
896	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
897	#endif
898	if (fCpuSupportsVmx)
899	{
900	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
901	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
902	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
903	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
904	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
905	}
906	#ifdef VBOX_WITH_STATISTICS
907	/*
908	* Guest Exit reason stats.
909	*/
910	if (fCpuSupportsVmx)
911	{
912	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
913	{
914	const char *pszExitName = HMGetVmxExitName(j);
915	if (pszExitName)
916	{
917	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
918	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
919	AssertRCReturn(rc, rc);
920	}
921	}
922	}
923	else
924	{
925	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
926	{
927	const char *pszExitName = HMGetSvmExitName(j);
928	if (pszExitName)
929	{
930	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
931	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
932	AssertRC(rc);
933	}
934	}
935	}
936	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
937
938	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
939	/*
940	* Nested-guest VM-exit reason stats.
941	*/
942	if (fCpuSupportsVmx)
943	{
944	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
945	{
946	const char *pszExitName = HMGetVmxExitName(j);
947	if (pszExitName)
948	{
949	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
950	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
951	AssertRC(rc);
952	}
953	}
954	}
955	else
956	{
957	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
958	{
959	const char *pszExitName = HMGetSvmExitName(j);
960	if (pszExitName)
961	{
962	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
963	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
964	AssertRC(rc);
965	}
966	}
967	}
968	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
969	#endif
970
971	/*
972	* Injected interrupts stats.
973	*/
974	char szDesc[64];
975	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
976	{
977	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
978	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
979	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
980	AssertRC(rc);
981	}
982
983	/*
984	* Injected exception stats.
985	*/
986	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
987	{
988	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
989	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
990	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
991	AssertRC(rc);
992	}
993
994	#endif /* VBOX_WITH_STATISTICS */
995	#undef HM_REG_COUNTER
996	#undef HM_REG_PROFILE
997	#undef HM_REG_STAT
998	}
999
1000	return VINF_SUCCESS;
1001	}
1002
1003
1004	/**
1005	* Called when a init phase has completed.
1006	*
1007	* @returns VBox status code.
1008	* @param pVM The cross context VM structure.
1009	* @param enmWhat The phase that completed.
1010	*/
1011	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1012	{
1013	switch (enmWhat)
1014	{
1015	case VMINITCOMPLETED_RING3:
1016	return hmR3InitFinalizeR3(pVM);
1017	case VMINITCOMPLETED_RING0:
1018	return hmR3InitFinalizeR0(pVM);
1019	default:
1020	return VINF_SUCCESS;
1021	}
1022	}
1023
1024
1025	/**
1026	* Turns off normal raw mode features.
1027	*
1028	* @param pVM The cross context VM structure.
1029	*/
1030	static void hmR3DisableRawMode(PVM pVM)
1031	{
1032	/** @todo r=bird: HM shouldn't be doing this crap. */
1033	/* Reinit the paging mode to force the new shadow mode. */
1034	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1035	{
1036	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1037	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1038	}
1039	}
1040
1041
1042	/**
1043	* Initialize VT-x or AMD-V.
1044	*
1045	* @returns VBox status code.
1046	* @param pVM The cross context VM structure.
1047	*/
1048	static int hmR3InitFinalizeR0(PVM pVM)
1049	{
1050	int rc;
1051
1052	if (!HMIsEnabled(pVM))
1053	return VINF_SUCCESS;
1054
1055	/*
1056	* Hack to allow users to work around broken BIOSes that incorrectly set
1057	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1058	*/
1059	if ( !pVM->hm.s.vmx.fSupported
1060	&& !pVM->hm.s.svm.fSupported
1061	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1062	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1063	{
1064	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1065	pVM->hm.s.svm.fSupported = true;
1066	pVM->hm.s.svm.fIgnoreInUseError = true;
1067	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1068	}
1069
1070	/*
1071	* Report ring-0 init errors.
1072	*/
1073	if ( !pVM->hm.s.vmx.fSupported
1074	&& !pVM->hm.s.svm.fSupported)
1075	{
1076	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1077	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1078	switch (pVM->hm.s.ForR3.rcInit)
1079	{
1080	case VERR_VMX_IN_VMX_ROOT_MODE:
1081	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1082	case VERR_VMX_NO_VMX:
1083	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1084	case VERR_VMX_MSR_VMX_DISABLED:
1085	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1086	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1087	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1088	case VERR_VMX_MSR_LOCKING_FAILED:
1089	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1090	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1091	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1092	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1093	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1094
1095	case VERR_SVM_IN_USE:
1096	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1097	case VERR_SVM_NO_SVM:
1098	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1099	case VERR_SVM_DISABLED:
1100	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1101	}
1102	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1103	}
1104
1105	/*
1106	* Enable VT-x or AMD-V on all host CPUs.
1107	*/
1108	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1109	if (RT_FAILURE(rc))
1110	{
1111	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1112	HMR3CheckError(pVM, rc);
1113	return rc;
1114	}
1115
1116	/*
1117	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1118	* (Main should have taken care of this already)
1119	*/
1120	if (!PDMHasIoApic(pVM))
1121	{
1122	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1123	pVM->hm.s.fTprPatchingAllowed = false;
1124	}
1125
1126	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1127	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1128	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1129
1130	/*
1131	* Do the vendor specific initialization
1132	*
1133	* Note! We disable release log buffering here since we're doing relatively
1134	* lot of logging and doesn't want to hit the disk with each LogRel
1135	* statement.
1136	*/
1137	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1138	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1139	if (pVM->hm.s.vmx.fSupported)
1140	rc = hmR3InitFinalizeR0Intel(pVM);
1141	else
1142	rc = hmR3InitFinalizeR0Amd(pVM);
1143	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1144	: "HM: VT-x/AMD-V init method: Local\n"));
1145	RTLogRelSetBuffering(fOldBuffered);
1146	pVM->hm.s.fInitialized = true;
1147
1148	return rc;
1149	}
1150
1151
1152	/**
1153	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1154	*/
1155	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1156	{
1157	NOREF(pVM);
1158	NOREF(pvAllocation);
1159	NOREF(GCPhysAllocation);
1160	}
1161
1162
1163	/**
1164	* Returns a description of the VMCS (and associated regions') memory type given the
1165	* IA32_VMX_BASIC MSR.
1166	*
1167	* @returns The descriptive memory type.
1168	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1169	*/
1170	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1171	{
1172	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1173	switch (uMemType)
1174	{
1175	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1176	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1177	}
1178	return "Unknown";
1179	}
1180
1181
1182	/**
1183	* Returns a single-line description of all the activity-states supported by the CPU
1184	* given the IA32_VMX_MISC MSR.
1185	*
1186	* @returns All supported activity states.
1187	* @param uMsrMisc IA32_VMX_MISC MSR value.
1188	*/
1189	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1190	{
1191	static const char * const s_apszActStates[] =
1192	{
1193	"",
1194	" ( HLT )",
1195	" ( SHUTDOWN )",
1196	" ( HLT SHUTDOWN )",
1197	" ( SIPI_WAIT )",
1198	" ( HLT SIPI_WAIT )",
1199	" ( SHUTDOWN SIPI_WAIT )",
1200	" ( HLT SHUTDOWN SIPI_WAIT )"
1201	};
1202	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1203	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1204	return s_apszActStates[idxActStates];
1205	}
1206
1207
1208	/**
1209	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1210	*
1211	* @param fFeatMsr The feature control MSR value.
1212	*/
1213	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1214	{
1215	uint64_t const val = fFeatMsr;
1216	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1217	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1218	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1219	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1220	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1221	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1222	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1223	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1224	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1225	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1226	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1227	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1228	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1229	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1230	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1231	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1232	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1233	}
1234
1235
1236	/**
1237	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1238	*
1239	* @param uBasicMsr The VMX basic MSR value.
1240	*/
1241	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1242	{
1243	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1244	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1245	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1246	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1247	"< 4 GB" : "None"));
1248	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1249	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1250	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1251	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1252	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1253	}
1254
1255
1256	/**
1257	* Reports MSR_IA32_PINBASED_CTLS to the log.
1258	*
1259	* @param pVmxMsr Pointer to the VMX MSR.
1260	*/
1261	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1262	{
1263	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1264	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1265	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1266	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1267	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1268	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1269	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1270	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1271	}
1272
1273
1274	/**
1275	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1276	*
1277	* @param pVmxMsr Pointer to the VMX MSR.
1278	*/
1279	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1280	{
1281	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1282	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1283	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1284	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1285	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1286	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1287	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1288	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1289	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1290	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1291	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1292	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1293	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1294	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1295	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1296	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1297	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1298	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1299	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1306	}
1307
1308
1309	/**
1310	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1311	*
1312	* @param pVmxMsr Pointer to the VMX MSR.
1313	*/
1314	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1315	{
1316	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1317	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1318	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1320	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1321	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1322	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1323	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1324	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1346	}
1347
1348
1349	/**
1350	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1351	*
1352	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1353	*/
1354	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1355	{
1356	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1357	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1358	}
1359
1360
1361	/**
1362	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1363	*
1364	* @param pVmxMsr Pointer to the VMX MSR.
1365	*/
1366	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1367	{
1368	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1369	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1370	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1383	}
1384
1385
1386	/**
1387	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1388	*
1389	* @param pVmxMsr Pointer to the VMX MSR.
1390	*/
1391	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1392	{
1393	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1394	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1395	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1409	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1410	}
1411
1412
1413	/**
1414	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1415	*
1416	* @param fCaps The VMX EPT/VPID capability MSR value.
1417	*/
1418	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1419	{
1420	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1421	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1422	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1423	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1424	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1425	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1431	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1432	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1433	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1434	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1435	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1436	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1437	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1438	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1439	}
1440
1441
1442	/**
1443	* Reports MSR_IA32_VMX_MISC MSR to the log.
1444	*
1445	* @param pVM Pointer to the VM.
1446	* @param fMisc The VMX misc. MSR value.
1447	*/
1448	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1449	{
1450	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1451	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1452	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1453	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1454	else
1455	{
1456	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1457	pVM->hm.s.vmx.cPreemptTimerShift));
1458	}
1459	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1460	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1461	hmR3VmxGetActivityStateAllDesc(fMisc)));
1462	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1463	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1464	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1465	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1466	VMX_MISC_MAX_MSRS(fMisc)));
1467	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1468	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1469	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1470	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1471	}
1472
1473
1474	/**
1475	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1476	*
1477	* @param uVmcsEnum The VMX VMCS enum MSR value.
1478	*/
1479	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1480	{
1481	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1482	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1483	}
1484
1485
1486	/**
1487	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1488	*
1489	* @param uVmFunc The VMX VMFUNC MSR value.
1490	*/
1491	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1492	{
1493	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1494	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1495	}
1496
1497
1498	/**
1499	* Reports VMX CR0, CR4 fixed MSRs.
1500	*
1501	* @param pMsrs Pointer to the VMX MSRs.
1502	*/
1503	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1504	{
1505	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1506	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1507	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1508	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1509	}
1510
1511
1512	/**
1513	* Finish VT-x initialization (after ring-0 init).
1514	*
1515	* @returns VBox status code.
1516	* @param pVM The cross context VM structure.
1517	*/
1518	static int hmR3InitFinalizeR0Intel(PVM pVM)
1519	{
1520	int rc;
1521
1522	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1523	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1524
1525	LogRel(("HM: Using VT-x implementation 3.0\n"));
1526	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1527	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1528	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1529	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1530
1531	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1532	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1533
1534	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1535	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1536	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1537	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1538	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1539	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1540
1541	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1542	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1543
1544	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1545	{
1546	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1547	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1548	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1549	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1550	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1551	}
1552
1553	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1554	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1555	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1556	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1557	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1558	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1559	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1560
1561	#ifdef TODO_9217_VMCSINFO
1562	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1563	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1564	{
1565	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1566	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1567	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1568	}
1569	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1570	if (pVM->cpum.ro.GuestFeatures.fVmx)
1571	{
1572	LogRel(("HM: Nested-guest:\n"));
1573	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1574	{
1575	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1576	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1577	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1578	}
1579	}
1580	#endif
1581	#endif /* TODO_9217_VMCSINFO */
1582
1583	/*
1584	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1585	*/
1586	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1587	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1588	VERR_HM_IPE_1);
1589	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1590	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1591	&& pVM->hm.s.fNestedPagingCfg),
1592	VERR_HM_IPE_1);
1593
1594	/*
1595	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1596	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1597	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1598	*/
1599	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1600	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1601	{
1602	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1603	LogRel(("HM: Disabled RDTSCP\n"));
1604	}
1605
1606	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1607	{
1608	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1609	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1610	if (RT_SUCCESS(rc))
1611	{
1612	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1613	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1614	esp. Figure 20-5.*/
1615	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1616	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1617
1618	/* Bit set to 0 means software interrupts are redirected to the
1619	8086 program interrupt handler rather than switching to
1620	protected-mode handler. */
1621	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1622
1623	/* Allow all port IO, so that port IO instructions do not cause
1624	exceptions and would instead cause a VM-exit (based on VT-x's
1625	IO bitmap which we currently configure to always cause an exit). */
1626	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1627	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1628
1629	/*
1630	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1631	* page table used in real and protected mode without paging with EPT.
1632	*/
1633	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1634	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1635	{
1636	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1637	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1638	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1639	\| X86_PDE4M_G;
1640	}
1641
1642	/* We convert it here every time as PCI regions could be reconfigured. */
1643	if (PDMVmmDevHeapIsEnabled(pVM))
1644	{
1645	RTGCPHYS GCPhys;
1646	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1647	AssertRCReturn(rc, rc);
1648	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1649
1650	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1651	AssertRCReturn(rc, rc);
1652	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1653	}
1654	}
1655	else
1656	{
1657	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1658	pVM->hm.s.vmx.pRealModeTSS = NULL;
1659	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1660	return VMSetError(pVM, rc, RT_SRC_POS,
1661	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1662	}
1663	}
1664
1665	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1666	: "HM: Guest support: 32-bit only\n"));
1667
1668	/*
1669	* Call ring-0 to set up the VM.
1670	*/
1671	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1672	if (rc != VINF_SUCCESS)
1673	{
1674	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1675	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1676	{
1677	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1678	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1679	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1680	}
1681	HMR3CheckError(pVM, rc);
1682	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1683	}
1684
1685	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1686	LogRel(("HM: Enabled VMX\n"));
1687	pVM->hm.s.vmx.fEnabled = true;
1688
1689	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1690
1691	/*
1692	* Change the CPU features.
1693	*/
1694	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1695	if (pVM->hm.s.fAllow64BitGuestsCfg)
1696	{
1697	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1698	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1699	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1700	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1701	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1702	}
1703	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1704	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1705	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1706
1707	/*
1708	* Log configuration details.
1709	*/
1710	if (pVM->hm.s.fNestedPagingCfg)
1711	{
1712	LogRel(("HM: Enabled nested paging\n"));
1713	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1714	LogRel(("HM: EPT flush type = Single context\n"));
1715	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1716	LogRel(("HM: EPT flush type = All contexts\n"));
1717	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1718	LogRel(("HM: EPT flush type = Not supported\n"));
1719	else
1720	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1721
1722	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1723	LogRel(("HM: Enabled unrestricted guest execution\n"));
1724
1725	if (pVM->hm.s.fLargePages)
1726	{
1727	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1728	PGMSetLargePageUsage(pVM, true);
1729	LogRel(("HM: Enabled large page support\n"));
1730	}
1731	}
1732	else
1733	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1734
1735	if (pVM->hm.s.ForR3.vmx.fVpid)
1736	{
1737	LogRel(("HM: Enabled VPID\n"));
1738	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1739	LogRel(("HM: VPID flush type = Individual addresses\n"));
1740	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1741	LogRel(("HM: VPID flush type = Single context\n"));
1742	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1743	LogRel(("HM: VPID flush type = All contexts\n"));
1744	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1745	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1746	else
1747	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1748	}
1749	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1750	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1751
1752	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1753	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1754	else
1755	LogRel(("HM: Disabled VMX-preemption timer\n"));
1756
1757	if (pVM->hm.s.fVirtApicRegs)
1758	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1759
1760	if (pVM->hm.s.fPostedIntrs)
1761	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1762
1763	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1764	{
1765	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1766	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1767	}
1768
1769	return VINF_SUCCESS;
1770	}
1771
1772
1773	/**
1774	* Finish AMD-V initialization (after ring-0 init).
1775	*
1776	* @returns VBox status code.
1777	* @param pVM The cross context VM structure.
1778	*/
1779	static int hmR3InitFinalizeR0Amd(PVM pVM)
1780	{
1781	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1782
1783	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1784
1785	uint32_t u32Family;
1786	uint32_t u32Model;
1787	uint32_t u32Stepping;
1788	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1789	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1790	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1791	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1792	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1793	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1794	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1795
1796	/*
1797	* Enumerate AMD-V features.
1798	*/
1799	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1800	{
1801	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1802	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1803	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1804	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1805	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1806	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1807	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1808	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1809	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1810	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1811	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1812	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1813	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1814	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1815	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1816	#undef HMSVM_REPORT_FEATURE
1817	};
1818
1819	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1820	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1821	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1822	{
1823	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1824	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1825	}
1826	if (fSvmFeatures)
1827	for (unsigned iBit = 0; iBit < 32; iBit++)
1828	if (RT_BIT_32(iBit) & fSvmFeatures)
1829	LogRel(("HM: Reserved bit %u\n", iBit));
1830
1831	/*
1832	* Nested paging is determined in HMR3Init, verify the sanity of that.
1833	*/
1834	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1835	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1836	VERR_HM_IPE_1);
1837
1838	#if 0
1839	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1840	* here. */
1841	if (RTR0IsPostIpiSupport())
1842	pVM->hm.s.fPostedIntrs = true;
1843	#endif
1844
1845	/*
1846	* Determine whether we need to intercept #UD in SVM mode for emulating
1847	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1848	* when executed in long-mode. This is only really applicable when
1849	* non-default CPU profiles are in effect, i.e. guest vendor differs
1850	* from the host one.
1851	*/
1852	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1853	switch (CPUMGetGuestCpuVendor(pVM))
1854	{
1855	case CPUMCPUVENDOR_INTEL:
1856	case CPUMCPUVENDOR_VIA: /?/
1857	case CPUMCPUVENDOR_SHANGHAI: /?/
1858	switch (CPUMGetHostCpuVendor(pVM))
1859	{
1860	case CPUMCPUVENDOR_AMD:
1861	case CPUMCPUVENDOR_HYGON:
1862	if (pVM->hm.s.fAllow64BitGuestsCfg)
1863	{
1864	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1865	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1866	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1867	}
1868	break;
1869	default: break;
1870	}
1871	default: break;
1872	}
1873
1874	/*
1875	* Call ring-0 to set up the VM.
1876	*/
1877	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1878	if (rc != VINF_SUCCESS)
1879	{
1880	AssertMsgFailed(("%Rrc\n", rc));
1881	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1882	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1883	}
1884
1885	LogRel(("HM: Enabled SVM\n"));
1886	pVM->hm.s.svm.fEnabled = true;
1887
1888	if (pVM->hm.s.fNestedPagingCfg)
1889	{
1890	LogRel(("HM: Enabled nested paging\n"));
1891
1892	/*
1893	* Enable large pages (2 MB) if applicable.
1894	*/
1895	if (pVM->hm.s.fLargePages)
1896	{
1897	PGMSetLargePageUsage(pVM, true);
1898	LogRel(("HM: Enabled large page support\n"));
1899	}
1900	}
1901
1902	if (pVM->hm.s.fVirtApicRegs)
1903	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1904
1905	if (pVM->hm.s.fPostedIntrs)
1906	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1907
1908	hmR3DisableRawMode(pVM);
1909
1910	/*
1911	* Change the CPU features.
1912	*/
1913	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1914	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1915	if (pVM->hm.s.fAllow64BitGuestsCfg)
1916	{
1917	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1918	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1919	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1920	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1921	}
1922	/* Turn on NXE if PAE has been enabled. */
1923	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1924	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1925
1926	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1927	: "HM: Disabled TPR patching\n"));
1928
1929	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1930	: "HM: Guest support: 32-bit only\n"));
1931	return VINF_SUCCESS;
1932	}
1933
1934
1935	/**
1936	* Applies relocations to data and code managed by this
1937	* component. This function will be called at init and
1938	* whenever the VMM need to relocate it self inside the GC.
1939	*
1940	* @param pVM The cross context VM structure.
1941	*/
1942	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1943	{
1944	/* Fetch the current paging mode during the relocate callback during state loading. */
1945	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1946	{
1947	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1948	{
1949	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1950	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1951	}
1952	}
1953	}
1954
1955
1956	/**
1957	* Terminates the HM.
1958	*
1959	* Termination means cleaning up and freeing all resources,
1960	* the VM itself is, at this point, powered off or suspended.
1961	*
1962	* @returns VBox status code.
1963	* @param pVM The cross context VM structure.
1964	*/
1965	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1966	{
1967	if (pVM->hm.s.vmx.pRealModeTSS)
1968	{
1969	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1970	pVM->hm.s.vmx.pRealModeTSS = 0;
1971	}
1972	hmR3TermCPU(pVM);
1973	return 0;
1974	}
1975
1976
1977	/**
1978	* Terminates the per-VCPU HM.
1979	*
1980	* @returns VBox status code.
1981	* @param pVM The cross context VM structure.
1982	*/
1983	static int hmR3TermCPU(PVM pVM)
1984	{
1985	RT_NOREF(pVM);
1986	return VINF_SUCCESS;
1987	}
1988
1989
1990	/**
1991	* Resets a virtual CPU.
1992	*
1993	* Used by HMR3Reset and CPU hot plugging.
1994	*
1995	* @param pVCpu The cross context virtual CPU structure to reset.
1996	*/
1997	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1998	{
1999	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2000	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2001	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2002
2003	pVCpu->hm.s.fActive = false;
2004	pVCpu->hm.s.Event.fPending = false;
2005	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2006	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2007	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2008	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2009	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2010	#endif
2011	}
2012
2013
2014	/**
2015	* The VM is being reset.
2016	*
2017	* For the HM component this means that any GDT/LDT/TSS monitors
2018	* needs to be removed.
2019	*
2020	* @param pVM The cross context VM structure.
2021	*/
2022	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2023	{
2024	LogFlow(("HMR3Reset:\n"));
2025
2026	if (HMIsEnabled(pVM))
2027	hmR3DisableRawMode(pVM);
2028
2029	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2030	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2031
2032	/* Clear all patch information. */
2033	pVM->hm.s.pGuestPatchMem = 0;
2034	pVM->hm.s.pFreeGuestPatchMem = 0;
2035	pVM->hm.s.cbGuestPatchMem = 0;
2036	pVM->hm.s.cPatches = 0;
2037	pVM->hm.s.PatchTree = 0;
2038	pVM->hm.s.fTprPatchingActive = false;
2039	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2040	}
2041
2042
2043	/**
2044	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2045	*
2046	* @returns VBox strict status code.
2047	* @param pVM The cross context VM structure.
2048	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2049	* @param pvUser Unused.
2050	*/
2051	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2052	{
2053	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2054
2055	/* Only execute the handler on the VCPU the original patch request was issued. */
2056	if (pVCpu->idCpu != idCpu)
2057	return VINF_SUCCESS;
2058
2059	Log(("hmR3RemovePatches\n"));
2060	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2061	{
2062	uint8_t abInstr[15];
2063	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2064	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2065	int rc;
2066
2067	#ifdef LOG_ENABLED
2068	char szOutput[256];
2069	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2070	szOutput, sizeof(szOutput), NULL);
2071	if (RT_SUCCESS(rc))
2072	Log(("Patched instr: %s\n", szOutput));
2073	#endif
2074
2075	/* Check if the instruction is still the same. */
2076	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2077	if (rc != VINF_SUCCESS)
2078	{
2079	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2080	continue; /* swapped out or otherwise removed; skip it. */
2081	}
2082
2083	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2084	{
2085	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2086	continue; /* skip it. */
2087	}
2088
2089	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2090	AssertRC(rc);
2091
2092	#ifdef LOG_ENABLED
2093	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2094	szOutput, sizeof(szOutput), NULL);
2095	if (RT_SUCCESS(rc))
2096	Log(("Original instr: %s\n", szOutput));
2097	#endif
2098	}
2099	pVM->hm.s.cPatches = 0;
2100	pVM->hm.s.PatchTree = 0;
2101	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2102	pVM->hm.s.fTprPatchingActive = false;
2103	return VINF_SUCCESS;
2104	}
2105
2106
2107	/**
2108	* Worker for enabling patching in a VT-x/AMD-V guest.
2109	*
2110	* @returns VBox status code.
2111	* @param pVM The cross context VM structure.
2112	* @param idCpu VCPU to execute hmR3RemovePatches on.
2113	* @param pPatchMem Patch memory range.
2114	* @param cbPatchMem Size of the memory range.
2115	*/
2116	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2117	{
2118	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2119	AssertRC(rc);
2120
2121	pVM->hm.s.pGuestPatchMem = pPatchMem;
2122	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2123	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2124	return VINF_SUCCESS;
2125	}
2126
2127
2128	/**
2129	* Enable patching in a VT-x/AMD-V guest
2130	*
2131	* @returns VBox status code.
2132	* @param pVM The cross context VM structure.
2133	* @param pPatchMem Patch memory range.
2134	* @param cbPatchMem Size of the memory range.
2135	*/
2136	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2137	{
2138	VM_ASSERT_EMT(pVM);
2139	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2140	if (pVM->cCpus > 1)
2141	{
2142	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2143	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2144	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2145	AssertRC(rc);
2146	return rc;
2147	}
2148	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2149	}
2150
2151
2152	/**
2153	* Disable patching in a VT-x/AMD-V guest.
2154	*
2155	* @returns VBox status code.
2156	* @param pVM The cross context VM structure.
2157	* @param pPatchMem Patch memory range.
2158	* @param cbPatchMem Size of the memory range.
2159	*/
2160	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2161	{
2162	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2163	RT_NOREF2(pPatchMem, cbPatchMem);
2164
2165	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2166	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2167
2168	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2169	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2170	(void *)(uintptr_t)VMMGetCpuId(pVM));
2171	AssertRC(rc);
2172
2173	pVM->hm.s.pGuestPatchMem = 0;
2174	pVM->hm.s.pFreeGuestPatchMem = 0;
2175	pVM->hm.s.cbGuestPatchMem = 0;
2176	pVM->hm.s.fTprPatchingActive = false;
2177	return VINF_SUCCESS;
2178	}
2179
2180
2181	/**
2182	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2183	*
2184	* @returns VBox strict status code.
2185	* @param pVM The cross context VM structure.
2186	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2187	* @param pvUser User specified CPU context.
2188	*
2189	*/
2190	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2191	{
2192	/*
2193	* Only execute the handler on the VCPU the original patch request was
2194	* issued. (The other CPU(s) might not yet have switched to protected
2195	* mode, nor have the correct memory context.)
2196	*/
2197	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2198	if (pVCpu->idCpu != idCpu)
2199	return VINF_SUCCESS;
2200
2201	/*
2202	* We're racing other VCPUs here, so don't try patch the instruction twice
2203	* and make sure there is still room for our patch record.
2204	*/
2205	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2206	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2207	if (pPatch)
2208	{
2209	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2210	return VINF_SUCCESS;
2211	}
2212	uint32_t const idx = pVM->hm.s.cPatches;
2213	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2214	{
2215	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2216	return VINF_SUCCESS;
2217	}
2218	pPatch = &pVM->hm.s.aPatches[idx];
2219
2220	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2221
2222	/*
2223	* Disassembler the instruction and get cracking.
2224	*/
2225	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2226	DISCPUSTATE Dis;
2227	uint32_t cbOp;
2228	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2229	AssertRC(rc);
2230	if ( rc == VINF_SUCCESS
2231	&& Dis.pCurInstr->uOpcode == OP_MOV
2232	&& cbOp >= 3)
2233	{
2234	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2235
2236	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2237	AssertRC(rc);
2238
2239	pPatch->cbOp = cbOp;
2240
2241	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2242	{
2243	/* write. */
2244	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2245	{
2246	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2247	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2248	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2249	}
2250	else
2251	{
2252	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2253	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2254	pPatch->uSrcOperand = Dis.Param2.uValue;
2255	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2256	}
2257	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2258	AssertRC(rc);
2259
2260	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2261	pPatch->cbNewOp = sizeof(s_abVMMCall);
2262	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2263	}
2264	else
2265	{
2266	/*
2267	* TPR Read.
2268	*
2269	* Found:
2270	* mov eax, dword [fffe0080] (5 bytes)
2271	* Check if next instruction is:
2272	* shr eax, 4
2273	*/
2274	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2275
2276	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2277	uint8_t const cbOpMmio = cbOp;
2278	uint64_t const uSavedRip = pCtx->rip;
2279
2280	pCtx->rip += cbOp;
2281	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2282	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2283	pCtx->rip = uSavedRip;
2284
2285	if ( rc == VINF_SUCCESS
2286	&& Dis.pCurInstr->uOpcode == OP_SHR
2287	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2288	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2289	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2290	&& Dis.Param2.uValue == 4
2291	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2292	{
2293	uint8_t abInstr[15];
2294
2295	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2296	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2297	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2298	AssertRC(rc);
2299
2300	pPatch->cbOp = cbOpMmio + cbOp;
2301
2302	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2303	abInstr[0] = 0xf0;
2304	abInstr[1] = 0x0f;
2305	abInstr[2] = 0x20;
2306	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2307	for (unsigned i = 4; i < pPatch->cbOp; i++)
2308	abInstr[i] = 0x90; /* nop */
2309
2310	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2311	AssertRC(rc);
2312
2313	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2314	pPatch->cbNewOp = pPatch->cbOp;
2315	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2316
2317	Log(("Acceptable read/shr candidate!\n"));
2318	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2319	}
2320	else
2321	{
2322	pPatch->enmType = HMTPRINSTR_READ;
2323	pPatch->uDstOperand = idxMmioReg;
2324
2325	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2326	AssertRC(rc);
2327
2328	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2329	pPatch->cbNewOp = sizeof(s_abVMMCall);
2330	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2331	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2332	}
2333	}
2334
2335	pPatch->Core.Key = pCtx->eip;
2336	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2337	AssertRC(rc);
2338
2339	pVM->hm.s.cPatches++;
2340	return VINF_SUCCESS;
2341	}
2342
2343	/*
2344	* Save invalid patch, so we will not try again.
2345	*/
2346	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2347	pPatch->Core.Key = pCtx->eip;
2348	pPatch->enmType = HMTPRINSTR_INVALID;
2349	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2350	AssertRC(rc);
2351	pVM->hm.s.cPatches++;
2352	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2353	return VINF_SUCCESS;
2354	}
2355
2356
2357	/**
2358	* Callback to patch a TPR instruction (jump to generated code).
2359	*
2360	* @returns VBox strict status code.
2361	* @param pVM The cross context VM structure.
2362	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2363	* @param pvUser User specified CPU context.
2364	*
2365	*/
2366	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2367	{
2368	/*
2369	* Only execute the handler on the VCPU the original patch request was
2370	* issued. (The other CPU(s) might not yet have switched to protected
2371	* mode, nor have the correct memory context.)
2372	*/
2373	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2374	if (pVCpu->idCpu != idCpu)
2375	return VINF_SUCCESS;
2376
2377	/*
2378	* We're racing other VCPUs here, so don't try patch the instruction twice
2379	* and make sure there is still room for our patch record.
2380	*/
2381	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2382	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2383	if (pPatch)
2384	{
2385	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2386	return VINF_SUCCESS;
2387	}
2388	uint32_t const idx = pVM->hm.s.cPatches;
2389	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2390	{
2391	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2392	return VINF_SUCCESS;
2393	}
2394	pPatch = &pVM->hm.s.aPatches[idx];
2395
2396	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2397	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2398
2399	/*
2400	* Disassemble the instruction and get cracking.
2401	*/
2402	DISCPUSTATE Dis;
2403	uint32_t cbOp;
2404	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2405	AssertRC(rc);
2406	if ( rc == VINF_SUCCESS
2407	&& Dis.pCurInstr->uOpcode == OP_MOV
2408	&& cbOp >= 5)
2409	{
2410	uint8_t aPatch[64];
2411	uint32_t off = 0;
2412
2413	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2414	AssertRC(rc);
2415
2416	pPatch->cbOp = cbOp;
2417	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2418
2419	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2420	{
2421	/*
2422	* TPR write:
2423	*
2424	* push ECX [51]
2425	* push EDX [52]
2426	* push EAX [50]
2427	* xor EDX,EDX [31 D2]
2428	* mov EAX,EAX [89 C0]
2429	* or
2430	* mov EAX,0000000CCh [B8 CC 00 00 00]
2431	* mov ECX,0C0000082h [B9 82 00 00 C0]
2432	* wrmsr [0F 30]
2433	* pop EAX [58]
2434	* pop EDX [5A]
2435	* pop ECX [59]
2436	* jmp return_address [E9 return_address]
2437	*/
2438	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2439
2440	aPatch[off++] = 0x51; /* push ecx */
2441	aPatch[off++] = 0x52; /* push edx */
2442	if (!fUsesEax)
2443	aPatch[off++] = 0x50; /* push eax */
2444	aPatch[off++] = 0x31; /* xor edx, edx */
2445	aPatch[off++] = 0xd2;
2446	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2447	{
2448	if (!fUsesEax)
2449	{
2450	aPatch[off++] = 0x89; /* mov eax, src_reg */
2451	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2452	}
2453	}
2454	else
2455	{
2456	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2457	aPatch[off++] = 0xb8; /* mov eax, immediate */
2458	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2459	off += sizeof(uint32_t);
2460	}
2461	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2462	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2463	off += sizeof(uint32_t);
2464
2465	aPatch[off++] = 0x0f; /* wrmsr */
2466	aPatch[off++] = 0x30;
2467	if (!fUsesEax)
2468	aPatch[off++] = 0x58; /* pop eax */
2469	aPatch[off++] = 0x5a; /* pop edx */
2470	aPatch[off++] = 0x59; /* pop ecx */
2471	}
2472	else
2473	{
2474	/*
2475	* TPR read:
2476	*
2477	* push ECX [51]
2478	* push EDX [52]
2479	* push EAX [50]
2480	* mov ECX,0C0000082h [B9 82 00 00 C0]
2481	* rdmsr [0F 32]
2482	* mov EAX,EAX [89 C0]
2483	* pop EAX [58]
2484	* pop EDX [5A]
2485	* pop ECX [59]
2486	* jmp return_address [E9 return_address]
2487	*/
2488	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2489
2490	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2491	aPatch[off++] = 0x51; /* push ecx */
2492	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2493	aPatch[off++] = 0x52; /* push edx */
2494	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2495	aPatch[off++] = 0x50; /* push eax */
2496
2497	aPatch[off++] = 0x31; /* xor edx, edx */
2498	aPatch[off++] = 0xd2;
2499
2500	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2501	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2502	off += sizeof(uint32_t);
2503
2504	aPatch[off++] = 0x0f; /* rdmsr */
2505	aPatch[off++] = 0x32;
2506
2507	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2508	{
2509	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2510	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2511	}
2512
2513	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2514	aPatch[off++] = 0x58; /* pop eax */
2515	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2516	aPatch[off++] = 0x5a; /* pop edx */
2517	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2518	aPatch[off++] = 0x59; /* pop ecx */
2519	}
2520	aPatch[off++] = 0xe9; /* jmp return_address */
2521	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2522	off += sizeof(RTRCUINTPTR);
2523
2524	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2525	{
2526	/* Write new code to the patch buffer. */
2527	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2528	AssertRC(rc);
2529
2530	#ifdef LOG_ENABLED
2531	uint32_t cbCurInstr;
2532	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2533	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2534	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2535	{
2536	char szOutput[256];
2537	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2538	szOutput, sizeof(szOutput), &cbCurInstr);
2539	if (RT_SUCCESS(rc))
2540	Log(("Patch instr %s\n", szOutput));
2541	else
2542	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2543	}
2544	#endif
2545
2546	pPatch->aNewOpcode[0] = 0xE9;
2547	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2548
2549	/* Overwrite the TPR instruction with a jump. */
2550	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2551	AssertRC(rc);
2552
2553	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2554
2555	pVM->hm.s.pFreeGuestPatchMem += off;
2556	pPatch->cbNewOp = 5;
2557
2558	pPatch->Core.Key = pCtx->eip;
2559	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2560	AssertRC(rc);
2561
2562	pVM->hm.s.cPatches++;
2563	pVM->hm.s.fTprPatchingActive = true;
2564	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2565	return VINF_SUCCESS;
2566	}
2567
2568	Log(("Ran out of space in our patch buffer!\n"));
2569	}
2570	else
2571	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2572
2573
2574	/*
2575	* Save invalid patch, so we will not try again.
2576	*/
2577	pPatch = &pVM->hm.s.aPatches[idx];
2578	pPatch->Core.Key = pCtx->eip;
2579	pPatch->enmType = HMTPRINSTR_INVALID;
2580	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2581	AssertRC(rc);
2582	pVM->hm.s.cPatches++;
2583	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2584	return VINF_SUCCESS;
2585	}
2586
2587
2588	/**
2589	* Attempt to patch TPR mmio instructions.
2590	*
2591	* @returns VBox status code.
2592	* @param pVM The cross context VM structure.
2593	* @param pVCpu The cross context virtual CPU structure.
2594	*/
2595	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2596	{
2597	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2598	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2599	(void *)(uintptr_t)pVCpu->idCpu);
2600	AssertRC(rc);
2601	return rc;
2602	}
2603
2604
2605	/**
2606	* Checks if we need to reschedule due to VMM device heap changes.
2607	*
2608	* @returns true if a reschedule is required, otherwise false.
2609	* @param pVM The cross context VM structure.
2610	* @param pCtx VM execution context.
2611	*/
2612	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2613	{
2614	/*
2615	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2616	* when the unrestricted guest execution feature is missing (VT-x only).
2617	*/
2618	if ( pVM->hm.s.vmx.fEnabled
2619	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2620	&& CPUMIsGuestInRealModeEx(pCtx)
2621	&& !PDMVmmDevHeapIsEnabled(pVM))
2622	return true;
2623
2624	return false;
2625	}
2626
2627
2628	/**
2629	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2630	* event settings changes.
2631	*
2632	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2633	* function is just updating the VM globals.
2634	*
2635	* @param pVM The VM cross context VM structure.
2636	* @thread EMT(0)
2637	*/
2638	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2639	{
2640	/* Interrupts. */
2641	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2642	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2643
2644	/* CPU Exceptions. */
2645	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2646	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2647	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2648	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2649
2650	/* Common VM exits. */
2651	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2652	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2653	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2654	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2655
2656	/* Vendor specific VM exits. */
2657	if (HMR3IsVmxEnabled(pVM->pUVM))
2658	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2659	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2660	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2661	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2662	else
2663	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2664	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2665	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2666	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2667
2668	/* Done. */
2669	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2670	}
2671
2672
2673	/**
2674	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2675	*
2676	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2677	* per CPU settings.
2678	*
2679	* @param pVM The VM cross context VM structure.
2680	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2681	*/
2682	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2683	{
2684	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2685	}
2686
2687
2688	/**
2689	* Checks if we are currently using hardware acceleration.
2690	*
2691	* @returns true if hardware acceleration is being used, otherwise false.
2692	* @param pVCpu The cross context virtual CPU structure.
2693	*/
2694	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2695	{
2696	return pVCpu->hm.s.fActive;
2697	}
2698
2699
2700	/**
2701	* External interface for querying whether hardware acceleration is enabled.
2702	*
2703	* @returns true if VT-x or AMD-V is being used, otherwise false.
2704	* @param pUVM The user mode VM handle.
2705	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2706	*/
2707	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2708	{
2709	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2710	PVM pVM = pUVM->pVM;
2711	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2712	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2713	}
2714
2715
2716	/**
2717	* External interface for querying whether VT-x is being used.
2718	*
2719	* @returns true if VT-x is being used, otherwise false.
2720	* @param pUVM The user mode VM handle.
2721	* @sa HMR3IsSvmEnabled, HMIsEnabled
2722	*/
2723	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2724	{
2725	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2726	PVM pVM = pUVM->pVM;
2727	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2728	return pVM->hm.s.vmx.fEnabled
2729	&& pVM->hm.s.vmx.fSupported
2730	&& pVM->fHMEnabled;
2731	}
2732
2733
2734	/**
2735	* External interface for querying whether AMD-V is being used.
2736	*
2737	* @returns true if VT-x is being used, otherwise false.
2738	* @param pUVM The user mode VM handle.
2739	* @sa HMR3IsVmxEnabled, HMIsEnabled
2740	*/
2741	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2742	{
2743	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2744	PVM pVM = pUVM->pVM;
2745	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2746	return pVM->hm.s.svm.fEnabled
2747	&& pVM->hm.s.svm.fSupported
2748	&& pVM->fHMEnabled;
2749	}
2750
2751
2752	/**
2753	* Checks if we are currently using nested paging.
2754	*
2755	* @returns true if nested paging is being used, otherwise false.
2756	* @param pUVM The user mode VM handle.
2757	*/
2758	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2759	{
2760	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2761	PVM pVM = pUVM->pVM;
2762	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2763	return pVM->hm.s.fNestedPagingCfg;
2764	}
2765
2766
2767	/**
2768	* Checks if virtualized APIC registers are enabled.
2769	*
2770	* When enabled this feature allows the hardware to access most of the
2771	* APIC registers in the virtual-APIC page without causing VM-exits. See
2772	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2773	*
2774	* @returns true if virtualized APIC registers is enabled, otherwise
2775	* false.
2776	* @param pUVM The user mode VM handle.
2777	*/
2778	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2779	{
2780	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2781	PVM pVM = pUVM->pVM;
2782	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2783	return pVM->hm.s.fVirtApicRegs;
2784	}
2785
2786
2787	/**
2788	* Checks if APIC posted-interrupt processing is enabled.
2789	*
2790	* This returns whether we can deliver interrupts to the guest without
2791	* leaving guest-context by updating APIC state from host-context.
2792	*
2793	* @returns true if APIC posted-interrupt processing is enabled,
2794	* otherwise false.
2795	* @param pUVM The user mode VM handle.
2796	*/
2797	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2798	{
2799	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2800	PVM pVM = pUVM->pVM;
2801	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2802	return pVM->hm.s.fPostedIntrs;
2803	}
2804
2805
2806	/**
2807	* Checks if we are currently using VPID in VT-x mode.
2808	*
2809	* @returns true if VPID is being used, otherwise false.
2810	* @param pUVM The user mode VM handle.
2811	*/
2812	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2813	{
2814	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2815	PVM pVM = pUVM->pVM;
2816	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2817	return pVM->hm.s.ForR3.vmx.fVpid;
2818	}
2819
2820
2821	/**
2822	* Checks if we are currently using VT-x unrestricted execution,
2823	* aka UX.
2824	*
2825	* @returns true if UX is being used, otherwise false.
2826	* @param pUVM The user mode VM handle.
2827	*/
2828	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2829	{
2830	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2831	PVM pVM = pUVM->pVM;
2832	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2833	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2834	\|\| pVM->hm.s.svm.fSupported;
2835	}
2836
2837
2838	/**
2839	* Checks if the VMX-preemption timer is being used.
2840	*
2841	* @returns true if the VMX-preemption timer is being used, otherwise false.
2842	* @param pVM The cross context VM structure.
2843	*/
2844	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2845	{
2846	return HMIsEnabled(pVM)
2847	&& pVM->hm.s.vmx.fEnabled
2848	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2849	}
2850
2851
2852	#ifdef TODO_9217_VMCSINFO
2853	/**
2854	* Helper for HMR3CheckError to log VMCS controls to the release log.
2855	*
2856	* @param idCpu The Virtual CPU ID.
2857	* @param pVmcsInfo The VMCS info. object.
2858	*/
2859	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2860	{
2861	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2862	{
2863	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2864	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2865	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2866	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2867	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2868	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2869	}
2870	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2871	{
2872	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2873	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2874	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2875	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2876	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2877	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2878	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2879	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2880	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2881	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2882	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2883	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2884	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2885	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2886	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2887	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2888	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2893	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2894	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2895	}
2896	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2897	{
2898	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2905	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2926	}
2927	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2928	{
2929	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2942	}
2943	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2944	{
2945	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
2960	}
2961	}
2962	#endif
2963
2964
2965	/**
2966	* Check fatal VT-x/AMD-V error and produce some meaningful
2967	* log release message.
2968	*
2969	* @param pVM The cross context VM structure.
2970	* @param iStatusCode VBox status code.
2971	*/
2972	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2973	{
2974	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2975	{
2976	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2977	* might be getting inaccurate values for non-guru'ing EMTs. */
2978	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2979	#ifdef TODO_9217_VMCSINFO
2980	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
2981	#endif
2982	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
2983	switch (iStatusCode)
2984	{
2985	case VERR_VMX_INVALID_VMCS_PTR:
2986	{
2987	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2988	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2989	#ifdef TODO_9217_VMCSINFO
2990	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2991	pVmcsInfo->HCPhysVmcs));
2992	#endif
2993	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2994	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2995	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2996	break;
2997	}
2998
2999	case VERR_VMX_UNABLE_TO_START_VM:
3000	{
3001	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3002	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3003	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3004	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3005
3006	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3007	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3008	{
3009	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3010	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3011	}
3012	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3013	{
3014	#ifdef TODO_9217_VMCSINFO
3015	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3016	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3017	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3018	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3019	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3020	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3021	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3022	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3023	#endif
3024	}
3025	/** @todo Log VM-entry event injection control fields
3026	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3027	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3028	break;
3029	}
3030
3031	case VERR_VMX_INVALID_GUEST_STATE:
3032	{
3033	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3034	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3035	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3036	#ifdef TODO_9217_VMCSINFO
3037	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3038	#endif
3039	break;
3040	}
3041
3042	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3043	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3044	case VERR_VMX_INVALID_VMXON_PTR:
3045	case VERR_VMX_UNEXPECTED_EXIT:
3046	case VERR_VMX_INVALID_VMCS_FIELD:
3047	case VERR_SVM_UNKNOWN_EXIT:
3048	case VERR_SVM_UNEXPECTED_EXIT:
3049	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3050	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3051	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3052	break;
3053	}
3054	}
3055
3056	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3057	{
3058	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3059	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3060	}
3061	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3062	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3063	}
3064
3065
3066	/**
3067	* Execute state save operation.
3068	*
3069	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3070	* is because we always save the VM state from ring-3 and thus most HM state
3071	* will be re-synced dynamically at runtime and don't need to be part of the VM
3072	* saved state.
3073	*
3074	* @returns VBox status code.
3075	* @param pVM The cross context VM structure.
3076	* @param pSSM SSM operation handle.
3077	*/
3078	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3079	{
3080	Log(("hmR3Save:\n"));
3081
3082	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3083	{
3084	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3085	Assert(!pVCpu->hm.s.Event.fPending);
3086	if (pVM->cpum.ro.GuestFeatures.fSvm)
3087	{
3088	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3089	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3090	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3091	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3092	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3093	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3094	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3095	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3096	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3097	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3098	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3099	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3100	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3101	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3102	}
3103	}
3104
3105	/* Save the guest patch data. */
3106	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3107	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3108	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3109
3110	/* Store all the guest patch records too. */
3111	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3112	if (RT_FAILURE(rc))
3113	return rc;
3114
3115	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3116	{
3117	AssertCompileSize(HMTPRINSTR, 4);
3118	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3119	SSMR3PutU32(pSSM, pPatch->Core.Key);
3120	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3121	SSMR3PutU32(pSSM, pPatch->cbOp);
3122	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3123	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3124	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3125	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3126	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3127	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3128	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3129	if (RT_FAILURE(rc))
3130	return rc;
3131	}
3132
3133	return VINF_SUCCESS;
3134	}
3135
3136
3137	/**
3138	* Execute state load operation.
3139	*
3140	* @returns VBox status code.
3141	* @param pVM The cross context VM structure.
3142	* @param pSSM SSM operation handle.
3143	* @param uVersion Data layout version.
3144	* @param uPass The data pass.
3145	*/
3146	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3147	{
3148	int rc;
3149
3150	LogFlowFunc(("uVersion=%u\n", uVersion));
3151	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3152
3153	/*
3154	* Validate version.
3155	*/
3156	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3157	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3158	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3159	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3160	{
3161	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3162	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3163	}
3164
3165	/*
3166	* Load per-VCPU state.
3167	*/
3168	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3169	{
3170	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3171	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3172	{
3173	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3174	if (pVM->cpum.ro.GuestFeatures.fSvm)
3175	{
3176	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3177	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3178	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3179	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3180	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3181	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3182	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3183	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3184	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3185	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3186	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3187	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3188	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3189	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3190	AssertRCReturn(rc, rc);
3191	}
3192	}
3193	else
3194	{
3195	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3196	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3197	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3198	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3199
3200	/* VMX fWasInRealMode related data. */
3201	uint32_t uDummy;
3202	SSMR3GetU32(pSSM, &uDummy);
3203	SSMR3GetU32(pSSM, &uDummy);
3204	rc = SSMR3GetU32(pSSM, &uDummy);
3205	AssertRCReturn(rc, rc);
3206	}
3207	}
3208
3209	/*
3210	* Load TPR patching data.
3211	*/
3212	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3213	{
3214	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3215	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3216	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3217
3218	/* Fetch all TPR patch records. */
3219	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3220	AssertRCReturn(rc, rc);
3221	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3222	{
3223	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3224	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3225	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3226	SSMR3GetU32(pSSM, &pPatch->cbOp);
3227	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3228	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3229	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3230
3231	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3232	pVM->hm.s.fTprPatchingActive = true;
3233	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3234
3235	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3236	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3237	SSMR3GetU32(pSSM, &pPatch->cFaults);
3238	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3239	AssertRCReturn(rc, rc);
3240
3241	LogFlow(("hmR3Load: patch %d\n", i));
3242	LogFlow(("Key = %x\n", pPatch->Core.Key));
3243	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3244	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3245	LogFlow(("type = %d\n", pPatch->enmType));
3246	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3247	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3248	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3249	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3250
3251	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3252	AssertRCReturn(rc, rc);
3253	}
3254	}
3255
3256	return VINF_SUCCESS;
3257	}
3258
3259
3260	/**
3261	* Displays HM info.
3262	*
3263	* @param pVM The cross context VM structure.
3264	* @param pHlp The info helper functions.
3265	* @param pszArgs Arguments, ignored.
3266	*/
3267	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3268	{
3269	NOREF(pszArgs);
3270	PVMCPU pVCpu = VMMGetCpu(pVM);
3271	if (!pVCpu)
3272	pVCpu = pVM->apCpusR3[0];
3273
3274	if (HMIsEnabled(pVM))
3275	{
3276	if (pVM->hm.s.vmx.fSupported)
3277	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3278	else
3279	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3280	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3281	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3282	if (pVM->hm.s.vmx.fSupported)
3283	{
3284	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3285	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3286	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3287
3288	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3289	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3290	if (fRealOnV86Active)
3291	{
3292	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3293	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3294	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3295	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3296	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3297	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3298	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3299	}
3300	}
3301	}
3302	else
3303	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3304	}
3305
3306
3307	/**
3308	* Displays the HM Last-Branch-Record info. for the guest.
3309	*
3310	* @param pVM The cross context VM structure.
3311	* @param pHlp The info helper functions.
3312	* @param pszArgs Arguments, ignored.
3313	*/
3314	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3315	{
3316	NOREF(pszArgs);
3317	PVMCPU pVCpu = VMMGetCpu(pVM);
3318	if (!pVCpu)
3319	pVCpu = pVM->apCpusR3[0];
3320
3321	if (!HMIsEnabled(pVM))
3322	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3323	else if (HMIsVmxActive(pVM))
3324	{
3325	if (pVM->hm.s.vmx.fLbrCfg)
3326	{
3327	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3328	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3329
3330	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3331	* 0xf should cover everything we support thus far. Fix if necessary
3332	* later. */
3333	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3334	if (idxTopOfStack > cLbrStack)
3335	{
3336	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3337	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3338	return;
3339	}
3340
3341	/*
3342	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3343	*/
3344	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3345	uint32_t idxCurrent = idxTopOfStack;
3346	Assert(idxTopOfStack < cLbrStack);
3347	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3348	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3349	for (;;)
3350	{
3351	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3352	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3353	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3354	else
3355	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3356
3357	idxCurrent = (idxCurrent - 1) % cLbrStack;
3358	if (idxCurrent == idxTopOfStack)
3359	break;
3360	}
3361	}
3362	else
3363	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3364	}
3365	else
3366	{
3367	Assert(HMIsSvmActive(pVM));
3368	/** @todo SVM: LBRs (get them from VMCB if possible). */
3369	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3370	}
3371	}
3372
3373
3374	/**
3375	* Displays the HM pending event.
3376	*
3377	* @param pVM The cross context VM structure.
3378	* @param pHlp The info helper functions.
3379	* @param pszArgs Arguments, ignored.
3380	*/
3381	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3382	{
3383	NOREF(pszArgs);
3384	PVMCPU pVCpu = VMMGetCpu(pVM);
3385	if (!pVCpu)
3386	pVCpu = pVM->apCpusR3[0];
3387
3388	if (HMIsEnabled(pVM))
3389	{
3390	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3391	if (pVCpu->hm.s.Event.fPending)
3392	{
3393	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3394	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3395	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3396	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3397	}
3398	}
3399	else
3400	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3401	}
3402
3403
3404	/**
3405	* Displays the SVM nested-guest VMCB cache.
3406	*
3407	* @param pVM The cross context VM structure.
3408	* @param pHlp The info helper functions.
3409	* @param pszArgs Arguments, ignored.
3410	*/
3411	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3412	{
3413	NOREF(pszArgs);
3414	PVMCPU pVCpu = VMMGetCpu(pVM);
3415	if (!pVCpu)
3416	pVCpu = pVM->apCpusR3[0];
3417
3418	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3419	if ( fSvmEnabled
3420	&& pVM->cpum.ro.GuestFeatures.fSvm)
3421	{
3422	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3423	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3424	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3425	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3426	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3427	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3428	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3429	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3430	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3431	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3432	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3433	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3434	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3435	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3436	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3437	}
3438	else
3439	{
3440	if (!fSvmEnabled)
3441	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3442	else
3443	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3444	}
3445	}
3446

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 93732

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