HM.cpp@ 93857

Last change on this file since 93857 was 93744, checked in by vboxsync, 3 years ago
VMM: More arm64 adjustments. bugref:9898
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 156.6 KB

Line
1	/* $Id: HM.cpp 93744 2022-02-14 21:00:26Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/trpm.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/iom.h>
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#include <VBox/vmm/hm_vmx.h>
55	#include <VBox/vmm/hm_svm.h>
56	#include "HMInternal.h"
57	#include <VBox/vmm/vmcc.h>
58	#include <VBox/err.h>
59	#include <VBox/param.h>
60
61	#include <iprt/assert.h>
62	#include <VBox/log.h>
63	#include <iprt/asm.h>
64	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
65	# include <iprt/asm-amd64-x86.h>
66	#endif
67	#include <iprt/env.h>
68	#include <iprt/thread.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74	/** @def HMVMX_REPORT_FEAT
75	* Reports VT-x feature to the release log.
76	*
77	* @param a_uAllowed1 Mask of allowed-1 feature bits.
78	* @param a_uAllowed0 Mask of allowed-0 feature bits.
79	* @param a_StrDesc The description string to report.
80	* @param a_Featflag Mask of the feature to report.
81	*/
82	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
83	do { \
84	if ((a_uAllowed1) & (a_Featflag)) \
85	{ \
86	if ((a_uAllowed0) & (a_Featflag)) \
87	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
88	else \
89	LogRel(("HM: " a_StrDesc "\n")); \
90	} \
91	else \
92	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
93	} while (0)
94
95	/** @def HMVMX_REPORT_ALLOWED_FEAT
96	* Reports an allowed VT-x feature to the release log.
97	*
98	* @param a_uAllowed1 Mask of allowed-1 feature bits.
99	* @param a_StrDesc The description string to report.
100	* @param a_FeatFlag Mask of the feature to report.
101	*/
102	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
103	do { \
104	if ((a_uAllowed1) & (a_FeatFlag)) \
105	LogRel(("HM: " a_StrDesc "\n")); \
106	else \
107	LogRel(("HM: " a_StrDesc " not supported\n")); \
108	} while (0)
109
110	/** @def HMVMX_REPORT_MSR_CAP
111	* Reports MSR feature capability.
112	*
113	* @param a_MsrCaps Mask of MSR feature bits.
114	* @param a_StrDesc The description string to report.
115	* @param a_fCap Mask of the feature to report.
116	*/
117	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
118	do { \
119	if ((a_MsrCaps) & (a_fCap)) \
120	LogRel(("HM: " a_StrDesc "\n")); \
121	} while (0)
122
123	/** @def HMVMX_LOGREL_FEAT
124	* Dumps a feature flag from a bitmap of features to the release log.
125	*
126	* @param a_fVal The value of all the features.
127	* @param a_fMask The specific bitmask of the feature.
128	*/
129	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
130	do { \
131	if ((a_fVal) & (a_fMask)) \
132	LogRel(("HM: %s\n", #a_fMask)); \
133	} while (0)
134
135
136	/*********************************************************************************************************************************
137	* Internal Functions *
138	*********************************************************************************************************************************/
139	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
140	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
141	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
145	static int hmR3InitFinalizeR3(PVM pVM);
146	static int hmR3InitFinalizeR0(PVM pVM);
147	static int hmR3InitFinalizeR0Intel(PVM pVM);
148	static int hmR3InitFinalizeR0Amd(PVM pVM);
149	static int hmR3TermCPU(PVM pVM);
150
151
152	#ifdef VBOX_WITH_STATISTICS
153	/**
154	* Returns the name of the hardware exception.
155	*
156	* @returns The name of the hardware exception.
157	* @param uVector The exception vector.
158	*/
159	static const char *hmR3GetXcptName(uint8_t uVector)
160	{
161	switch (uVector)
162	{
163	case X86_XCPT_DE: return "#DE";
164	case X86_XCPT_DB: return "#DB";
165	case X86_XCPT_NMI: return "#NMI";
166	case X86_XCPT_BP: return "#BP";
167	case X86_XCPT_OF: return "#OF";
168	case X86_XCPT_BR: return "#BR";
169	case X86_XCPT_UD: return "#UD";
170	case X86_XCPT_NM: return "#NM";
171	case X86_XCPT_DF: return "#DF";
172	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
173	case X86_XCPT_TS: return "#TS";
174	case X86_XCPT_NP: return "#NP";
175	case X86_XCPT_SS: return "#SS";
176	case X86_XCPT_GP: return "#GP";
177	case X86_XCPT_PF: return "#PF";
178	case X86_XCPT_MF: return "#MF";
179	case X86_XCPT_AC: return "#AC";
180	case X86_XCPT_MC: return "#MC";
181	case X86_XCPT_XF: return "#XF";
182	case X86_XCPT_VE: return "#VE";
183	case X86_XCPT_CP: return "#CP";
184	case X86_XCPT_VC: return "#VC";
185	case X86_XCPT_SX: return "#SX";
186	}
187	return "Reserved";
188	}
189	#endif /* VBOX_WITH_STATISTICS */
190
191
192	/**
193	* Initializes the HM.
194	*
195	* This is the very first component to really do init after CFGM so that we can
196	* establish the predominant execution engine for the VM prior to initializing
197	* other modules. It takes care of NEM initialization if needed (HM disabled or
198	* not available in HW).
199	*
200	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
201	* hypervisor API via NEM, and then back on raw-mode if that isn't available
202	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
203	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
204	* X, OS/2 and others).
205	*
206	* Note that a lot of the set up work is done in ring-0 and thus postponed till
207	* the ring-3 and ring-0 callback to HMR3InitCompleted.
208	*
209	* @returns VBox status code.
210	* @param pVM The cross context VM structure.
211	*
212	* @remarks Be careful with what we call here, since most of the VMM components
213	* are uninitialized.
214	*/
215	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
216	{
217	LogFlowFunc(("\n"));
218
219	/*
220	* Assert alignment and sizes.
221	*/
222	AssertCompileMemberAlignment(VM, hm.s, 32);
223	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
224
225	/*
226	* Register the saved state data unit.
227	*/
228	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
229	NULL, NULL, NULL,
230	NULL, hmR3Save, NULL,
231	NULL, hmR3Load, NULL);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Read configuration.
237	*/
238	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
239
240	/*
241	* Validate the HM settings.
242	*/
243	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
244	"HMForced" /* implied 'true' these days */
245	"\|UseNEMInstead"
246	"\|FallbackToNEM"
247	"\|EnableNestedPaging"
248	"\|EnableUX"
249	"\|EnableLargePages"
250	"\|EnableVPID"
251	"\|IBPBOnVMExit"
252	"\|IBPBOnVMEntry"
253	"\|SpecCtrlByHost"
254	"\|L1DFlushOnSched"
255	"\|L1DFlushOnVMEntry"
256	"\|MDSClearOnSched"
257	"\|MDSClearOnVMEntry"
258	"\|TPRPatchingEnabled"
259	"\|64bitEnabled"
260	"\|Exclusive"
261	"\|MaxResumeLoops"
262	"\|VmxPleGap"
263	"\|VmxPleWindow"
264	"\|VmxLbr"
265	"\|UseVmxPreemptTimer"
266	"\|SvmPauseFilter"
267	"\|SvmPauseFilterThreshold"
268	"\|SvmVirtVmsaveVmload"
269	"\|SvmVGif"
270	"\|LovelyMesaDrvWorkaround"
271	"\|MissingOS2TlbFlushWorkaround",
272	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
273	if (RT_FAILURE(rc))
274	return rc;
275
276	/** @cfgm{/HM/HMForced, bool, false}
277	* Forces hardware virtualization, no falling back on raw-mode. HM must be
278	* enabled, i.e. /HMEnabled must be true. */
279	bool fHMForced;
280	AssertRelease(pVM->fHMEnabled);
281	fHMForced = true;
282
283	/** @cfgm{/HM/UseNEMInstead, bool, true}
284	* Don't use HM, use NEM instead. */
285	bool fUseNEMInstead = false;
286	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
287	AssertRCReturn(rc, rc);
288	if (fUseNEMInstead && pVM->fHMEnabled)
289	{
290	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
291	pVM->fHMEnabled = false;
292	}
293
294	/** @cfgm{/HM/FallbackToNEM, bool, true}
295	* Enables fallback on NEM. */
296	bool fFallbackToNEM = true;
297	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
298	AssertRCReturn(rc, rc);
299
300	/** @cfgm{/HM/EnableNestedPaging, bool, false}
301	* Enables nested paging (aka extended page tables). */
302	bool fAllowNestedPaging = false;
303	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
304	AssertRCReturn(rc, rc);
305
306	/** @cfgm{/HM/EnableUX, bool, true}
307	* Enables the VT-x unrestricted execution feature. */
308	bool fAllowUnrestricted = true;
309	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
310	AssertRCReturn(rc, rc);
311
312	/** @cfgm{/HM/EnableLargePages, bool, false}
313	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
314	* page table walking and maybe better TLB hit rate in some cases. */
315	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
316	AssertRCReturn(rc, rc);
317
318	/** @cfgm{/HM/EnableVPID, bool, false}
319	* Enables the VT-x VPID feature. */
320	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
321	AssertRCReturn(rc, rc);
322
323	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
324	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
325	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
326	AssertRCReturn(rc, rc);
327
328	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
329	* Enables AMD64 cpu features.
330	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
331	* already have the support. */
332	#ifdef VBOX_WITH_64_BITS_GUESTS
333	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
334	AssertLogRelRCReturn(rc, rc);
335	#else
336	pVM->hm.s.fAllow64BitGuestsCfg = false;
337	#endif
338
339	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
340	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
341	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
342	* latest PAUSE instruction to be start of a new PAUSE loop.
343	*/
344	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
345	AssertRCReturn(rc, rc);
346
347	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
348	* The pause-filter exiting window in TSC ticks. When the number of ticks
349	* between the current PAUSE instruction and first PAUSE of a loop exceeds
350	* VmxPleWindow, a VM-exit is triggered.
351	*
352	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
353	*/
354	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
355	AssertRCReturn(rc, rc);
356
357	/** @cfgm{/HM/VmxLbr, bool, false}
358	* Whether to enable LBR for the guest. This is disabled by default as it's only
359	* useful while debugging and enabling it causes a noticeable performance hit. */
360	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
361	AssertRCReturn(rc, rc);
362
363	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
364	* A counter that is decrement each time a PAUSE instruction is executed by the
365	* guest. When the counter is 0, a \#VMEXIT is triggered.
366	*
367	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
373	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
374	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
375	* PauseFilter count is reset to its initial value. However, if PAUSE is
376	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
377	* be triggered.
378	*
379	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
380	* activated.
381	*/
382	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
383	AssertRCReturn(rc, rc);
384
385	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
386	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
387	* available. */
388	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
389	AssertRCReturn(rc, rc);
390
391	/** @cfgm{/HM/SvmVGif, bool, true}
392	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
393	* if it's available. */
394	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{/HM/SvmLbrVirt, bool, false}
398	* Whether to make use of the LBR virtualization feature of the CPU if it's
399	* available. This is disabled by default as it's only useful while debugging
400	* and enabling it causes a small hit to performance. */
401	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
402	AssertRCReturn(rc, rc);
403
404	/** @cfgm{/HM/Exclusive, bool}
405	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
406	* global init for each host CPU. If false, we do local init each time we wish
407	* to execute guest code.
408	*
409	* On Windows, default is false due to the higher risk of conflicts with other
410	* hypervisors.
411	*
412	* On Mac OS X, this setting is ignored since the code does not handle local
413	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
414	*/
415	#if defined(RT_OS_DARWIN)
416	pVM->hm.s.fGlobalInit = true;
417	#else
418	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
419	# if defined(RT_OS_WINDOWS)
420	false
421	# else
422	true
423	# endif
424	);
425	AssertLogRelRCReturn(rc, rc);
426	#endif
427
428	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
429	* The number of times to resume guest execution before we forcibly return to
430	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
431	* determines the default value. */
432	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
433	AssertLogRelRCReturn(rc, rc);
434
435	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
436	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
437	* available. */
438	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
439	AssertLogRelRCReturn(rc, rc);
440
441	/** @cfgm{/HM/IBPBOnVMExit, bool}
442	* Costly paranoia setting. */
443	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
444	AssertLogRelRCReturn(rc, rc);
445
446	/** @cfgm{/HM/IBPBOnVMEntry, bool}
447	* Costly paranoia setting. */
448	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
449	AssertLogRelRCReturn(rc, rc);
450
451	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
452	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
457	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
462	if (pVM->hm.s.fL1dFlushOnVmEntry)
463	pVM->hm.s.fL1dFlushOnSched = false;
464
465	/** @cfgm{/HM/SpecCtrlByHost, bool}
466	* Another expensive paranoia setting. */
467	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/HM/MDSClearOnSched, bool, true}
471	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
472	* ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
474	AssertLogRelRCReturn(rc, rc);
475
476	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
477	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
478	* ignored on CPUs that aren't affected. */
479	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
480	AssertLogRelRCReturn(rc, rc);
481
482	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
483	if (pVM->hm.s.fMdsClearOnVmEntry)
484	pVM->hm.s.fMdsClearOnSched = false;
485
486	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
487	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
488	* the hypervisor it is running under. */
489	bool fMesaWorkaround;
490	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
491	AssertLogRelRCReturn(rc, rc);
492	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
493	{
494	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
495	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
496	}
497
498	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
499	* Workaround OS/2 not flushing the TLB after page directory and page table
500	* modifications when returning to protected mode from a real mode call
501	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
502	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
503	AssertLogRelRCReturn(rc, rc);
504
505	/*
506	* Check if VT-x or AMD-v support according to the users wishes.
507	*/
508	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
509	* VERR_SVM_IN_USE. */
510	if (pVM->fHMEnabled)
511	{
512	uint32_t fCaps;
513	rc = SUPR3QueryVTCaps(&fCaps);
514	if (RT_SUCCESS(rc))
515	{
516	if (fCaps & SUPVTCAPS_AMD_V)
517	{
518	pVM->hm.s.svm.fSupported = true;
519	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
520	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
521	}
522	else if (fCaps & SUPVTCAPS_VT_X)
523	{
524	const char *pszWhy;
525	rc = SUPR3QueryVTxSupported(&pszWhy);
526	if (RT_SUCCESS(rc))
527	{
528	pVM->hm.s.vmx.fSupported = true;
529	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
530	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
531	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
532	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
533	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
534	}
535	else
536	{
537	/*
538	* Before failing, try fallback to NEM if we're allowed to do that.
539	*/
540	pVM->fHMEnabled = false;
541	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
542	if (fFallbackToNEM)
543	{
544	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
545	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
546
547	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
548	if ( RT_SUCCESS(rc2)
549	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
550	rc = VINF_SUCCESS;
551	}
552	if (RT_FAILURE(rc))
553	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
554	}
555	}
556	else
557	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
558	VERR_INTERNAL_ERROR_5);
559
560	/*
561	* Disable nested paging and unrestricted guest execution now if they're
562	* configured so that CPUM can make decisions based on our configuration.
563	*/
564	if ( fAllowNestedPaging
565	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
566	{
567	pVM->hm.s.fNestedPagingCfg = true;
568	if (fCaps & SUPVTCAPS_VT_X)
569	{
570	if ( fAllowUnrestricted
571	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
572	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
573	else
574	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
575	}
576	}
577	else
578	Assert(!pVM->hm.s.fNestedPagingCfg);
579	}
580	else
581	{
582	const char *pszMsg;
583	switch (rc)
584	{
585	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
586	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
587	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
588	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
589	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
590	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
591	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
592	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
593	default:
594	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
595	}
596
597	/*
598	* Before failing, try fallback to NEM if we're allowed to do that.
599	*/
600	pVM->fHMEnabled = false;
601	if (fFallbackToNEM)
602	{
603	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
604	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
605	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
606	if ( RT_SUCCESS(rc2)
607	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
608	{
609	rc = VINF_SUCCESS;
610
611	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
612	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
613	}
614	}
615	if (RT_FAILURE(rc))
616	return VM_SET_ERROR(pVM, rc, pszMsg);
617	}
618	}
619	else
620	{
621	/*
622	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
623	*/
624	if (fUseNEMInstead)
625	{
626	rc = NEMR3Init(pVM, false /fFallback/, true);
627	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
628	if (RT_FAILURE(rc))
629	return rc;
630
631	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
632	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
633	}
634	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
635	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
636	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
637	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
638	}
639
640	if (pVM->fHMEnabled)
641	{
642	/*
643	* Register info handlers now that HM is used for sure.
644	*/
645	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
646	AssertRCReturn(rc, rc);
647
648	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
649	DBGFINFO_FLAGS_ALL_EMTS);
650	AssertRCReturn(rc, rc);
651
652	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
653	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
654	AssertRCReturn(rc, rc);
655
656	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
657	AssertRCReturn(rc, rc);
658	}
659
660	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
661	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
662	return VINF_SUCCESS;
663	}
664
665
666	/**
667	* Initializes HM components after ring-3 phase has been fully initialized.
668	*
669	* @returns VBox status code.
670	* @param pVM The cross context VM structure.
671	*/
672	static int hmR3InitFinalizeR3(PVM pVM)
673	{
674	LogFlowFunc(("\n"));
675
676	if (!HMIsEnabled(pVM))
677	return VINF_SUCCESS;
678
679	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
680	{
681	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
682	pVCpu->hm.s.fActive = false;
683	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
684	}
685
686	/*
687	* Check if L1D flush is needed/possible.
688	*/
689	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
690	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
691	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
692	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
693	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
694	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
695
696	/*
697	* Check if MDS flush is needed/possible.
698	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
699	*/
700	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
701	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
702	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
703	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
704	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
705	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
706	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
707	{
708	if (!pVM->hm.s.fMdsClearOnSched)
709	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
710	pVM->hm.s.fMdsClearOnVmEntry = false;
711	}
712	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
713	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
714	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
715
716	/*
717	* Statistics.
718	*/
719	#ifdef VBOX_WITH_STATISTICS
720	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
721	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
722	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
723	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
724	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
725	#endif
726
727	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
728	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
729	#else
730	bool const fCpuSupportsVmx = false;
731	#endif
732	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
733	{
734	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
735	PHMCPU pHmCpu = &pVCpu->hm.s;
736	int rc;
737
738	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
739	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
740	AssertRC(rc); \
741	} while (0)
742	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
743	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
744
745	#ifdef VBOX_WITH_STATISTICS
746
747	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
748	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
749	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
750	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
751	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
752	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
753	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
754	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
755	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
756	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
757	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
758	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
759	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
760	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
761	# ifdef HM_PROFILE_EXIT_DISPATCH
762	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
763	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
764	# endif
765	#endif
766	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
767
768	#ifdef VBOX_WITH_STATISTICS
769	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
770	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
771	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
772	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
773	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
774	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
775	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
776	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
777	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
778	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
779	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
780	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
781	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
782	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
783	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
784	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
785	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
786	#endif
787	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
788	if (fCpuSupportsVmx)
789	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
790	#ifdef VBOX_WITH_STATISTICS
791	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
792	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
793	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
794	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
795	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
796	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
797	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
798	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
799	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
800	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
801	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
802	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
803	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
804	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
805	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
806	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
807	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
808	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
809	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
810	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
811	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
812	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
813	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
814	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
815	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
816	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
817	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
818	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
819	#endif
820	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
821	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
822	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
823	#ifdef VBOX_WITH_STATISTICS
824	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
825	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
826	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
827
828	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
829	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
830	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
831	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
832	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
833	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
834	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
835	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
836	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
837	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
838	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
839	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
840	#endif
841	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
842	#ifdef VBOX_WITH_STATISTICS
843	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
844
845	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
846	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
847	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
848	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
849	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
850	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
851
852	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
853	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
854	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
855	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
856	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
857	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
858	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
859	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
860	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
861	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
862	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
863	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
864	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
865	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
866	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
867
868	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
869	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
870	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
871
872	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
873	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
874	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
875
876	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
877	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
878	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
879	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
880
881	if (fCpuSupportsVmx)
882	{
883	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
884	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
885	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
886	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
887	}
888
889	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
890	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
891	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
892
893	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
894	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
895	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
896
897	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
898	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
899	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
900	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
901	#endif
902	if (fCpuSupportsVmx)
903	{
904	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
905	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
906	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
907	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
908	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
909	}
910	#ifdef VBOX_WITH_STATISTICS
911	/*
912	* Guest Exit reason stats.
913	*/
914	if (fCpuSupportsVmx)
915	{
916	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
917	{
918	const char *pszExitName = HMGetVmxExitName(j);
919	if (pszExitName)
920	{
921	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
922	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
923	AssertRCReturn(rc, rc);
924	}
925	}
926	}
927	else
928	{
929	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
930	{
931	const char *pszExitName = HMGetSvmExitName(j);
932	if (pszExitName)
933	{
934	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
935	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
936	AssertRC(rc);
937	}
938	}
939	}
940	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
941
942	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
943	/*
944	* Nested-guest VM-exit reason stats.
945	*/
946	if (fCpuSupportsVmx)
947	{
948	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
949	{
950	const char *pszExitName = HMGetVmxExitName(j);
951	if (pszExitName)
952	{
953	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
954	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
955	AssertRC(rc);
956	}
957	}
958	}
959	else
960	{
961	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
962	{
963	const char *pszExitName = HMGetSvmExitName(j);
964	if (pszExitName)
965	{
966	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
967	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
968	AssertRC(rc);
969	}
970	}
971	}
972	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
973	#endif
974
975	/*
976	* Injected interrupts stats.
977	*/
978	char szDesc[64];
979	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
980	{
981	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
982	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
983	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
984	AssertRC(rc);
985	}
986
987	/*
988	* Injected exception stats.
989	*/
990	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
991	{
992	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
993	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
994	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
995	AssertRC(rc);
996	}
997
998	#endif /* VBOX_WITH_STATISTICS */
999	#undef HM_REG_COUNTER
1000	#undef HM_REG_PROFILE
1001	#undef HM_REG_STAT
1002	}
1003
1004	return VINF_SUCCESS;
1005	}
1006
1007
1008	/**
1009	* Called when a init phase has completed.
1010	*
1011	* @returns VBox status code.
1012	* @param pVM The cross context VM structure.
1013	* @param enmWhat The phase that completed.
1014	*/
1015	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1016	{
1017	switch (enmWhat)
1018	{
1019	case VMINITCOMPLETED_RING3:
1020	return hmR3InitFinalizeR3(pVM);
1021	case VMINITCOMPLETED_RING0:
1022	return hmR3InitFinalizeR0(pVM);
1023	default:
1024	return VINF_SUCCESS;
1025	}
1026	}
1027
1028
1029	/**
1030	* Turns off normal raw mode features.
1031	*
1032	* @param pVM The cross context VM structure.
1033	*/
1034	static void hmR3DisableRawMode(PVM pVM)
1035	{
1036	/** @todo r=bird: HM shouldn't be doing this crap. */
1037	/* Reinit the paging mode to force the new shadow mode. */
1038	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1039	{
1040	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1041	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1042	}
1043	}
1044
1045
1046	/**
1047	* Initialize VT-x or AMD-V.
1048	*
1049	* @returns VBox status code.
1050	* @param pVM The cross context VM structure.
1051	*/
1052	static int hmR3InitFinalizeR0(PVM pVM)
1053	{
1054	int rc;
1055
1056	if (!HMIsEnabled(pVM))
1057	return VINF_SUCCESS;
1058
1059	/*
1060	* Hack to allow users to work around broken BIOSes that incorrectly set
1061	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1062	*/
1063	if ( !pVM->hm.s.vmx.fSupported
1064	&& !pVM->hm.s.svm.fSupported
1065	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1066	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1067	{
1068	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1069	pVM->hm.s.svm.fSupported = true;
1070	pVM->hm.s.svm.fIgnoreInUseError = true;
1071	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1072	}
1073
1074	/*
1075	* Report ring-0 init errors.
1076	*/
1077	if ( !pVM->hm.s.vmx.fSupported
1078	&& !pVM->hm.s.svm.fSupported)
1079	{
1080	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1081	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1082	switch (pVM->hm.s.ForR3.rcInit)
1083	{
1084	case VERR_VMX_IN_VMX_ROOT_MODE:
1085	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1086	case VERR_VMX_NO_VMX:
1087	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1088	case VERR_VMX_MSR_VMX_DISABLED:
1089	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1090	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1091	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1092	case VERR_VMX_MSR_LOCKING_FAILED:
1093	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1094	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1095	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1096	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1097	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1098
1099	case VERR_SVM_IN_USE:
1100	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1101	case VERR_SVM_NO_SVM:
1102	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1103	case VERR_SVM_DISABLED:
1104	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1105	}
1106	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1107	}
1108
1109	/*
1110	* Enable VT-x or AMD-V on all host CPUs.
1111	*/
1112	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1113	if (RT_FAILURE(rc))
1114	{
1115	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1116	HMR3CheckError(pVM, rc);
1117	return rc;
1118	}
1119
1120	/*
1121	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1122	* (Main should have taken care of this already)
1123	*/
1124	if (!PDMHasIoApic(pVM))
1125	{
1126	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1127	pVM->hm.s.fTprPatchingAllowed = false;
1128	}
1129
1130	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1131	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1132	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1133
1134	/*
1135	* Do the vendor specific initialization
1136	*
1137	* Note! We disable release log buffering here since we're doing relatively
1138	* lot of logging and doesn't want to hit the disk with each LogRel
1139	* statement.
1140	*/
1141	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1142	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1143	if (pVM->hm.s.vmx.fSupported)
1144	rc = hmR3InitFinalizeR0Intel(pVM);
1145	else
1146	rc = hmR3InitFinalizeR0Amd(pVM);
1147	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1148	: "HM: VT-x/AMD-V init method: Local\n"));
1149	RTLogRelSetBuffering(fOldBuffered);
1150	pVM->hm.s.fInitialized = true;
1151
1152	return rc;
1153	}
1154
1155
1156	/**
1157	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1158	*/
1159	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1160	{
1161	NOREF(pVM);
1162	NOREF(pvAllocation);
1163	NOREF(GCPhysAllocation);
1164	}
1165
1166
1167	/**
1168	* Returns a description of the VMCS (and associated regions') memory type given the
1169	* IA32_VMX_BASIC MSR.
1170	*
1171	* @returns The descriptive memory type.
1172	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1173	*/
1174	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1175	{
1176	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1177	switch (uMemType)
1178	{
1179	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1180	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1181	}
1182	return "Unknown";
1183	}
1184
1185
1186	/**
1187	* Returns a single-line description of all the activity-states supported by the CPU
1188	* given the IA32_VMX_MISC MSR.
1189	*
1190	* @returns All supported activity states.
1191	* @param uMsrMisc IA32_VMX_MISC MSR value.
1192	*/
1193	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1194	{
1195	static const char * const s_apszActStates[] =
1196	{
1197	"",
1198	" ( HLT )",
1199	" ( SHUTDOWN )",
1200	" ( HLT SHUTDOWN )",
1201	" ( SIPI_WAIT )",
1202	" ( HLT SIPI_WAIT )",
1203	" ( SHUTDOWN SIPI_WAIT )",
1204	" ( HLT SHUTDOWN SIPI_WAIT )"
1205	};
1206	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1207	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1208	return s_apszActStates[idxActStates];
1209	}
1210
1211
1212	/**
1213	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1214	*
1215	* @param fFeatMsr The feature control MSR value.
1216	*/
1217	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1218	{
1219	uint64_t const val = fFeatMsr;
1220	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1221	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1222	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1223	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1224	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1225	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1226	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1227	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1228	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1229	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1230	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1231	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1232	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1233	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1234	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1235	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1236	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1237	}
1238
1239
1240	/**
1241	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1242	*
1243	* @param uBasicMsr The VMX basic MSR value.
1244	*/
1245	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1246	{
1247	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1248	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1249	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1250	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1251	"< 4 GB" : "None"));
1252	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1253	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1254	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1255	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1256	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1257	}
1258
1259
1260	/**
1261	* Reports MSR_IA32_PINBASED_CTLS to the log.
1262	*
1263	* @param pVmxMsr Pointer to the VMX MSR.
1264	*/
1265	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1266	{
1267	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1268	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1269	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1270	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1271	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1272	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1273	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1274	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1275	}
1276
1277
1278	/**
1279	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1280	*
1281	* @param pVmxMsr Pointer to the VMX MSR.
1282	*/
1283	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1284	{
1285	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1286	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1287	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1288	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1289	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1290	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1291	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1292	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1293	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1294	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1295	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1296	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1297	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1298	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1299	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1304	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1305	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1306	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1307	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1308	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1309	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1310	}
1311
1312
1313	/**
1314	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1315	*
1316	* @param pVmxMsr Pointer to the VMX MSR.
1317	*/
1318	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1319	{
1320	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1321	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1322	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1323	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1324	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1350	}
1351
1352
1353	/**
1354	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1355	*
1356	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1357	*/
1358	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1359	{
1360	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1361	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1362	}
1363
1364
1365	/**
1366	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1367	*
1368	* @param pVmxMsr Pointer to the VMX MSR.
1369	*/
1370	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1371	{
1372	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1373	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1374	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1387	}
1388
1389
1390	/**
1391	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1392	*
1393	* @param pVmxMsr Pointer to the VMX MSR.
1394	*/
1395	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1396	{
1397	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1398	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1399	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1408	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1409	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1410	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1411	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1412	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1413	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1414	}
1415
1416
1417	/**
1418	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1419	*
1420	* @param fCaps The VMX EPT/VPID capability MSR value.
1421	*/
1422	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1423	{
1424	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1425	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1431	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1432	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1433	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1434	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1435	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1436	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1437	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1438	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1439	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1440	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1441	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1442	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1443	}
1444
1445
1446	/**
1447	* Reports MSR_IA32_VMX_MISC MSR to the log.
1448	*
1449	* @param pVM Pointer to the VM.
1450	* @param fMisc The VMX misc. MSR value.
1451	*/
1452	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1453	{
1454	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1455	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1456	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1457	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1458	else
1459	{
1460	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1461	pVM->hm.s.vmx.cPreemptTimerShift));
1462	}
1463	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1464	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1465	hmR3VmxGetActivityStateAllDesc(fMisc)));
1466	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1467	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1468	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1469	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1470	VMX_MISC_MAX_MSRS(fMisc)));
1471	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1472	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1473	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1474	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1475	}
1476
1477
1478	/**
1479	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1480	*
1481	* @param uVmcsEnum The VMX VMCS enum MSR value.
1482	*/
1483	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1484	{
1485	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1486	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1487	}
1488
1489
1490	/**
1491	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1492	*
1493	* @param uVmFunc The VMX VMFUNC MSR value.
1494	*/
1495	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1496	{
1497	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1498	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1499	}
1500
1501
1502	/**
1503	* Reports VMX CR0, CR4 fixed MSRs.
1504	*
1505	* @param pMsrs Pointer to the VMX MSRs.
1506	*/
1507	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1508	{
1509	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1510	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1511	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1512	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1513	}
1514
1515
1516	/**
1517	* Finish VT-x initialization (after ring-0 init).
1518	*
1519	* @returns VBox status code.
1520	* @param pVM The cross context VM structure.
1521	*/
1522	static int hmR3InitFinalizeR0Intel(PVM pVM)
1523	{
1524	int rc;
1525
1526	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1527	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1528
1529	LogRel(("HM: Using VT-x implementation 3.0\n"));
1530	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1531	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1532	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1533	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1534
1535	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1536	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1537
1538	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1539	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1540	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1541	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1542	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1543	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1544
1545	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1546	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1547
1548	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1549	{
1550	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1551	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1552	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1553	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1554	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1555	}
1556
1557	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1558	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1559	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1560	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1561	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1562	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1563	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1564
1565	#ifdef TODO_9217_VMCSINFO
1566	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1567	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1568	{
1569	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1570	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1571	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1572	}
1573	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1574	if (pVM->cpum.ro.GuestFeatures.fVmx)
1575	{
1576	LogRel(("HM: Nested-guest:\n"));
1577	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1578	{
1579	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1580	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1581	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1582	}
1583	}
1584	#endif
1585	#endif /* TODO_9217_VMCSINFO */
1586
1587	/*
1588	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1589	*/
1590	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1591	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1592	VERR_HM_IPE_1);
1593	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1594	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1595	&& pVM->hm.s.fNestedPagingCfg),
1596	VERR_HM_IPE_1);
1597
1598	/*
1599	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1600	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1601	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1602	*/
1603	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1604	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1605	{
1606	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1607	LogRel(("HM: Disabled RDTSCP\n"));
1608	}
1609
1610	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1611	{
1612	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1613	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1614	if (RT_SUCCESS(rc))
1615	{
1616	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1617	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1618	esp. Figure 20-5.*/
1619	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1620	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1621
1622	/* Bit set to 0 means software interrupts are redirected to the
1623	8086 program interrupt handler rather than switching to
1624	protected-mode handler. */
1625	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1626
1627	/* Allow all port IO, so that port IO instructions do not cause
1628	exceptions and would instead cause a VM-exit (based on VT-x's
1629	IO bitmap which we currently configure to always cause an exit). */
1630	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1631	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1632
1633	/*
1634	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1635	* page table used in real and protected mode without paging with EPT.
1636	*/
1637	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1638	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1639	{
1640	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1641	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1642	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1643	\| X86_PDE4M_G;
1644	}
1645
1646	/* We convert it here every time as PCI regions could be reconfigured. */
1647	if (PDMVmmDevHeapIsEnabled(pVM))
1648	{
1649	RTGCPHYS GCPhys;
1650	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1651	AssertRCReturn(rc, rc);
1652	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1653
1654	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1655	AssertRCReturn(rc, rc);
1656	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1657	}
1658	}
1659	else
1660	{
1661	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1662	pVM->hm.s.vmx.pRealModeTSS = NULL;
1663	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1664	return VMSetError(pVM, rc, RT_SRC_POS,
1665	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1666	}
1667	}
1668
1669	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1670	: "HM: Guest support: 32-bit only\n"));
1671
1672	/*
1673	* Call ring-0 to set up the VM.
1674	*/
1675	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1676	if (rc != VINF_SUCCESS)
1677	{
1678	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1679	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1680	{
1681	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1682	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1683	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1684	}
1685	HMR3CheckError(pVM, rc);
1686	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1687	}
1688
1689	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1690	LogRel(("HM: Enabled VMX\n"));
1691	pVM->hm.s.vmx.fEnabled = true;
1692
1693	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1694
1695	/*
1696	* Change the CPU features.
1697	*/
1698	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1699	if (pVM->hm.s.fAllow64BitGuestsCfg)
1700	{
1701	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1702	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1703	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1704	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1705	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1706	}
1707	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1708	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1709	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1710
1711	/*
1712	* Log configuration details.
1713	*/
1714	if (pVM->hm.s.fNestedPagingCfg)
1715	{
1716	LogRel(("HM: Enabled nested paging\n"));
1717	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1718	LogRel(("HM: EPT flush type = Single context\n"));
1719	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1720	LogRel(("HM: EPT flush type = All contexts\n"));
1721	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1722	LogRel(("HM: EPT flush type = Not supported\n"));
1723	else
1724	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1725
1726	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1727	LogRel(("HM: Enabled unrestricted guest execution\n"));
1728
1729	if (pVM->hm.s.fLargePages)
1730	{
1731	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1732	PGMSetLargePageUsage(pVM, true);
1733	LogRel(("HM: Enabled large page support\n"));
1734	}
1735	}
1736	else
1737	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1738
1739	if (pVM->hm.s.ForR3.vmx.fVpid)
1740	{
1741	LogRel(("HM: Enabled VPID\n"));
1742	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1743	LogRel(("HM: VPID flush type = Individual addresses\n"));
1744	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1745	LogRel(("HM: VPID flush type = Single context\n"));
1746	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1747	LogRel(("HM: VPID flush type = All contexts\n"));
1748	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1749	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1750	else
1751	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1752	}
1753	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1754	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1755
1756	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1757	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1758	else
1759	LogRel(("HM: Disabled VMX-preemption timer\n"));
1760
1761	if (pVM->hm.s.fVirtApicRegs)
1762	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1763
1764	if (pVM->hm.s.fPostedIntrs)
1765	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1766
1767	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1768	{
1769	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1770	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1771	}
1772
1773	return VINF_SUCCESS;
1774	}
1775
1776
1777	/**
1778	* Finish AMD-V initialization (after ring-0 init).
1779	*
1780	* @returns VBox status code.
1781	* @param pVM The cross context VM structure.
1782	*/
1783	static int hmR3InitFinalizeR0Amd(PVM pVM)
1784	{
1785	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1786
1787	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1788
1789	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1790	uint32_t u32Family;
1791	uint32_t u32Model;
1792	uint32_t u32Stepping;
1793	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1794	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1795	#endif
1796	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1797	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1798	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1799	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1800	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1801
1802	/*
1803	* Enumerate AMD-V features.
1804	*/
1805	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1806	{
1807	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1808	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1809	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1810	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1811	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1812	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1813	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1814	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1815	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1816	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1817	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1818	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1819	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1820	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1821	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1822	#undef HMSVM_REPORT_FEATURE
1823	};
1824
1825	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1826	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1827	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1828	{
1829	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1830	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1831	}
1832	if (fSvmFeatures)
1833	for (unsigned iBit = 0; iBit < 32; iBit++)
1834	if (RT_BIT_32(iBit) & fSvmFeatures)
1835	LogRel(("HM: Reserved bit %u\n", iBit));
1836
1837	/*
1838	* Nested paging is determined in HMR3Init, verify the sanity of that.
1839	*/
1840	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1841	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1842	VERR_HM_IPE_1);
1843
1844	#if 0
1845	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1846	* here. */
1847	if (RTR0IsPostIpiSupport())
1848	pVM->hm.s.fPostedIntrs = true;
1849	#endif
1850
1851	/*
1852	* Determine whether we need to intercept #UD in SVM mode for emulating
1853	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1854	* when executed in long-mode. This is only really applicable when
1855	* non-default CPU profiles are in effect, i.e. guest vendor differs
1856	* from the host one.
1857	*/
1858	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1859	switch (CPUMGetGuestCpuVendor(pVM))
1860	{
1861	case CPUMCPUVENDOR_INTEL:
1862	case CPUMCPUVENDOR_VIA: /?/
1863	case CPUMCPUVENDOR_SHANGHAI: /?/
1864	switch (CPUMGetHostCpuVendor(pVM))
1865	{
1866	case CPUMCPUVENDOR_AMD:
1867	case CPUMCPUVENDOR_HYGON:
1868	if (pVM->hm.s.fAllow64BitGuestsCfg)
1869	{
1870	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1871	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1872	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1873	}
1874	break;
1875	default: break;
1876	}
1877	default: break;
1878	}
1879
1880	/*
1881	* Call ring-0 to set up the VM.
1882	*/
1883	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1884	if (rc != VINF_SUCCESS)
1885	{
1886	AssertMsgFailed(("%Rrc\n", rc));
1887	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1888	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1889	}
1890
1891	LogRel(("HM: Enabled SVM\n"));
1892	pVM->hm.s.svm.fEnabled = true;
1893
1894	if (pVM->hm.s.fNestedPagingCfg)
1895	{
1896	LogRel(("HM: Enabled nested paging\n"));
1897
1898	/*
1899	* Enable large pages (2 MB) if applicable.
1900	*/
1901	if (pVM->hm.s.fLargePages)
1902	{
1903	PGMSetLargePageUsage(pVM, true);
1904	LogRel(("HM: Enabled large page support\n"));
1905	}
1906	}
1907
1908	if (pVM->hm.s.fVirtApicRegs)
1909	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1910
1911	if (pVM->hm.s.fPostedIntrs)
1912	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1913
1914	hmR3DisableRawMode(pVM);
1915
1916	/*
1917	* Change the CPU features.
1918	*/
1919	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1920	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1921	if (pVM->hm.s.fAllow64BitGuestsCfg)
1922	{
1923	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1924	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1925	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1926	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1927	}
1928	/* Turn on NXE if PAE has been enabled. */
1929	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1930	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1931
1932	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1933	: "HM: Disabled TPR patching\n"));
1934
1935	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1936	: "HM: Guest support: 32-bit only\n"));
1937	return VINF_SUCCESS;
1938	}
1939
1940
1941	/**
1942	* Applies relocations to data and code managed by this
1943	* component. This function will be called at init and
1944	* whenever the VMM need to relocate it self inside the GC.
1945	*
1946	* @param pVM The cross context VM structure.
1947	*/
1948	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1949	{
1950	/* Fetch the current paging mode during the relocate callback during state loading. */
1951	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1952	{
1953	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1954	{
1955	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1956	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1957	}
1958	}
1959	}
1960
1961
1962	/**
1963	* Terminates the HM.
1964	*
1965	* Termination means cleaning up and freeing all resources,
1966	* the VM itself is, at this point, powered off or suspended.
1967	*
1968	* @returns VBox status code.
1969	* @param pVM The cross context VM structure.
1970	*/
1971	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1972	{
1973	if (pVM->hm.s.vmx.pRealModeTSS)
1974	{
1975	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1976	pVM->hm.s.vmx.pRealModeTSS = 0;
1977	}
1978	hmR3TermCPU(pVM);
1979	return 0;
1980	}
1981
1982
1983	/**
1984	* Terminates the per-VCPU HM.
1985	*
1986	* @returns VBox status code.
1987	* @param pVM The cross context VM structure.
1988	*/
1989	static int hmR3TermCPU(PVM pVM)
1990	{
1991	RT_NOREF(pVM);
1992	return VINF_SUCCESS;
1993	}
1994
1995
1996	/**
1997	* Resets a virtual CPU.
1998	*
1999	* Used by HMR3Reset and CPU hot plugging.
2000	*
2001	* @param pVCpu The cross context virtual CPU structure to reset.
2002	*/
2003	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2004	{
2005	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2006	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2007	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2008
2009	pVCpu->hm.s.fActive = false;
2010	pVCpu->hm.s.Event.fPending = false;
2011	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2012	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2013	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2014	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2015	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2016	#endif
2017	}
2018
2019
2020	/**
2021	* The VM is being reset.
2022	*
2023	* For the HM component this means that any GDT/LDT/TSS monitors
2024	* needs to be removed.
2025	*
2026	* @param pVM The cross context VM structure.
2027	*/
2028	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2029	{
2030	LogFlow(("HMR3Reset:\n"));
2031
2032	if (HMIsEnabled(pVM))
2033	hmR3DisableRawMode(pVM);
2034
2035	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2036	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2037
2038	/* Clear all patch information. */
2039	pVM->hm.s.pGuestPatchMem = 0;
2040	pVM->hm.s.pFreeGuestPatchMem = 0;
2041	pVM->hm.s.cbGuestPatchMem = 0;
2042	pVM->hm.s.cPatches = 0;
2043	pVM->hm.s.PatchTree = 0;
2044	pVM->hm.s.fTprPatchingActive = false;
2045	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2046	}
2047
2048
2049	/**
2050	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2051	*
2052	* @returns VBox strict status code.
2053	* @param pVM The cross context VM structure.
2054	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2055	* @param pvUser Unused.
2056	*/
2057	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2058	{
2059	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2060
2061	/* Only execute the handler on the VCPU the original patch request was issued. */
2062	if (pVCpu->idCpu != idCpu)
2063	return VINF_SUCCESS;
2064
2065	Log(("hmR3RemovePatches\n"));
2066	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2067	{
2068	uint8_t abInstr[15];
2069	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2070	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2071	int rc;
2072
2073	#ifdef LOG_ENABLED
2074	char szOutput[256];
2075	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2076	szOutput, sizeof(szOutput), NULL);
2077	if (RT_SUCCESS(rc))
2078	Log(("Patched instr: %s\n", szOutput));
2079	#endif
2080
2081	/* Check if the instruction is still the same. */
2082	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2083	if (rc != VINF_SUCCESS)
2084	{
2085	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2086	continue; /* swapped out or otherwise removed; skip it. */
2087	}
2088
2089	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2090	{
2091	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2092	continue; /* skip it. */
2093	}
2094
2095	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2096	AssertRC(rc);
2097
2098	#ifdef LOG_ENABLED
2099	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2100	szOutput, sizeof(szOutput), NULL);
2101	if (RT_SUCCESS(rc))
2102	Log(("Original instr: %s\n", szOutput));
2103	#endif
2104	}
2105	pVM->hm.s.cPatches = 0;
2106	pVM->hm.s.PatchTree = 0;
2107	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2108	pVM->hm.s.fTprPatchingActive = false;
2109	return VINF_SUCCESS;
2110	}
2111
2112
2113	/**
2114	* Worker for enabling patching in a VT-x/AMD-V guest.
2115	*
2116	* @returns VBox status code.
2117	* @param pVM The cross context VM structure.
2118	* @param idCpu VCPU to execute hmR3RemovePatches on.
2119	* @param pPatchMem Patch memory range.
2120	* @param cbPatchMem Size of the memory range.
2121	*/
2122	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2123	{
2124	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2125	AssertRC(rc);
2126
2127	pVM->hm.s.pGuestPatchMem = pPatchMem;
2128	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2129	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2130	return VINF_SUCCESS;
2131	}
2132
2133
2134	/**
2135	* Enable patching in a VT-x/AMD-V guest
2136	*
2137	* @returns VBox status code.
2138	* @param pVM The cross context VM structure.
2139	* @param pPatchMem Patch memory range.
2140	* @param cbPatchMem Size of the memory range.
2141	*/
2142	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2143	{
2144	VM_ASSERT_EMT(pVM);
2145	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2146	if (pVM->cCpus > 1)
2147	{
2148	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2149	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2150	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2151	AssertRC(rc);
2152	return rc;
2153	}
2154	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2155	}
2156
2157
2158	/**
2159	* Disable patching in a VT-x/AMD-V guest.
2160	*
2161	* @returns VBox status code.
2162	* @param pVM The cross context VM structure.
2163	* @param pPatchMem Patch memory range.
2164	* @param cbPatchMem Size of the memory range.
2165	*/
2166	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2167	{
2168	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2169	RT_NOREF2(pPatchMem, cbPatchMem);
2170
2171	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2172	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2173
2174	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2175	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2176	(void *)(uintptr_t)VMMGetCpuId(pVM));
2177	AssertRC(rc);
2178
2179	pVM->hm.s.pGuestPatchMem = 0;
2180	pVM->hm.s.pFreeGuestPatchMem = 0;
2181	pVM->hm.s.cbGuestPatchMem = 0;
2182	pVM->hm.s.fTprPatchingActive = false;
2183	return VINF_SUCCESS;
2184	}
2185
2186
2187	/**
2188	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2189	*
2190	* @returns VBox strict status code.
2191	* @param pVM The cross context VM structure.
2192	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2193	* @param pvUser User specified CPU context.
2194	*
2195	*/
2196	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2197	{
2198	/*
2199	* Only execute the handler on the VCPU the original patch request was
2200	* issued. (The other CPU(s) might not yet have switched to protected
2201	* mode, nor have the correct memory context.)
2202	*/
2203	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2204	if (pVCpu->idCpu != idCpu)
2205	return VINF_SUCCESS;
2206
2207	/*
2208	* We're racing other VCPUs here, so don't try patch the instruction twice
2209	* and make sure there is still room for our patch record.
2210	*/
2211	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2212	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2213	if (pPatch)
2214	{
2215	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2216	return VINF_SUCCESS;
2217	}
2218	uint32_t const idx = pVM->hm.s.cPatches;
2219	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2220	{
2221	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2222	return VINF_SUCCESS;
2223	}
2224	pPatch = &pVM->hm.s.aPatches[idx];
2225
2226	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2227
2228	/*
2229	* Disassembler the instruction and get cracking.
2230	*/
2231	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2232	DISCPUSTATE Dis;
2233	uint32_t cbOp;
2234	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2235	AssertRC(rc);
2236	if ( rc == VINF_SUCCESS
2237	&& Dis.pCurInstr->uOpcode == OP_MOV
2238	&& cbOp >= 3)
2239	{
2240	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2241
2242	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2243	AssertRC(rc);
2244
2245	pPatch->cbOp = cbOp;
2246
2247	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2248	{
2249	/* write. */
2250	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2251	{
2252	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2253	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2254	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2255	}
2256	else
2257	{
2258	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2259	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2260	pPatch->uSrcOperand = Dis.Param2.uValue;
2261	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2262	}
2263	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2264	AssertRC(rc);
2265
2266	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2267	pPatch->cbNewOp = sizeof(s_abVMMCall);
2268	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2269	}
2270	else
2271	{
2272	/*
2273	* TPR Read.
2274	*
2275	* Found:
2276	* mov eax, dword [fffe0080] (5 bytes)
2277	* Check if next instruction is:
2278	* shr eax, 4
2279	*/
2280	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2281
2282	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2283	uint8_t const cbOpMmio = cbOp;
2284	uint64_t const uSavedRip = pCtx->rip;
2285
2286	pCtx->rip += cbOp;
2287	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2288	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2289	pCtx->rip = uSavedRip;
2290
2291	if ( rc == VINF_SUCCESS
2292	&& Dis.pCurInstr->uOpcode == OP_SHR
2293	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2294	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2295	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2296	&& Dis.Param2.uValue == 4
2297	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2298	{
2299	uint8_t abInstr[15];
2300
2301	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2302	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2303	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2304	AssertRC(rc);
2305
2306	pPatch->cbOp = cbOpMmio + cbOp;
2307
2308	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2309	abInstr[0] = 0xf0;
2310	abInstr[1] = 0x0f;
2311	abInstr[2] = 0x20;
2312	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2313	for (unsigned i = 4; i < pPatch->cbOp; i++)
2314	abInstr[i] = 0x90; /* nop */
2315
2316	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2317	AssertRC(rc);
2318
2319	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2320	pPatch->cbNewOp = pPatch->cbOp;
2321	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2322
2323	Log(("Acceptable read/shr candidate!\n"));
2324	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2325	}
2326	else
2327	{
2328	pPatch->enmType = HMTPRINSTR_READ;
2329	pPatch->uDstOperand = idxMmioReg;
2330
2331	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2332	AssertRC(rc);
2333
2334	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2335	pPatch->cbNewOp = sizeof(s_abVMMCall);
2336	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2337	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2338	}
2339	}
2340
2341	pPatch->Core.Key = pCtx->eip;
2342	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2343	AssertRC(rc);
2344
2345	pVM->hm.s.cPatches++;
2346	return VINF_SUCCESS;
2347	}
2348
2349	/*
2350	* Save invalid patch, so we will not try again.
2351	*/
2352	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2353	pPatch->Core.Key = pCtx->eip;
2354	pPatch->enmType = HMTPRINSTR_INVALID;
2355	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2356	AssertRC(rc);
2357	pVM->hm.s.cPatches++;
2358	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2359	return VINF_SUCCESS;
2360	}
2361
2362
2363	/**
2364	* Callback to patch a TPR instruction (jump to generated code).
2365	*
2366	* @returns VBox strict status code.
2367	* @param pVM The cross context VM structure.
2368	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2369	* @param pvUser User specified CPU context.
2370	*
2371	*/
2372	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2373	{
2374	/*
2375	* Only execute the handler on the VCPU the original patch request was
2376	* issued. (The other CPU(s) might not yet have switched to protected
2377	* mode, nor have the correct memory context.)
2378	*/
2379	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2380	if (pVCpu->idCpu != idCpu)
2381	return VINF_SUCCESS;
2382
2383	/*
2384	* We're racing other VCPUs here, so don't try patch the instruction twice
2385	* and make sure there is still room for our patch record.
2386	*/
2387	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2388	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2389	if (pPatch)
2390	{
2391	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2392	return VINF_SUCCESS;
2393	}
2394	uint32_t const idx = pVM->hm.s.cPatches;
2395	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2396	{
2397	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2398	return VINF_SUCCESS;
2399	}
2400	pPatch = &pVM->hm.s.aPatches[idx];
2401
2402	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2403	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2404
2405	/*
2406	* Disassemble the instruction and get cracking.
2407	*/
2408	DISCPUSTATE Dis;
2409	uint32_t cbOp;
2410	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2411	AssertRC(rc);
2412	if ( rc == VINF_SUCCESS
2413	&& Dis.pCurInstr->uOpcode == OP_MOV
2414	&& cbOp >= 5)
2415	{
2416	uint8_t aPatch[64];
2417	uint32_t off = 0;
2418
2419	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2420	AssertRC(rc);
2421
2422	pPatch->cbOp = cbOp;
2423	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2424
2425	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2426	{
2427	/*
2428	* TPR write:
2429	*
2430	* push ECX [51]
2431	* push EDX [52]
2432	* push EAX [50]
2433	* xor EDX,EDX [31 D2]
2434	* mov EAX,EAX [89 C0]
2435	* or
2436	* mov EAX,0000000CCh [B8 CC 00 00 00]
2437	* mov ECX,0C0000082h [B9 82 00 00 C0]
2438	* wrmsr [0F 30]
2439	* pop EAX [58]
2440	* pop EDX [5A]
2441	* pop ECX [59]
2442	* jmp return_address [E9 return_address]
2443	*/
2444	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2445
2446	aPatch[off++] = 0x51; /* push ecx */
2447	aPatch[off++] = 0x52; /* push edx */
2448	if (!fUsesEax)
2449	aPatch[off++] = 0x50; /* push eax */
2450	aPatch[off++] = 0x31; /* xor edx, edx */
2451	aPatch[off++] = 0xd2;
2452	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2453	{
2454	if (!fUsesEax)
2455	{
2456	aPatch[off++] = 0x89; /* mov eax, src_reg */
2457	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2458	}
2459	}
2460	else
2461	{
2462	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2463	aPatch[off++] = 0xb8; /* mov eax, immediate */
2464	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2465	off += sizeof(uint32_t);
2466	}
2467	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2468	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2469	off += sizeof(uint32_t);
2470
2471	aPatch[off++] = 0x0f; /* wrmsr */
2472	aPatch[off++] = 0x30;
2473	if (!fUsesEax)
2474	aPatch[off++] = 0x58; /* pop eax */
2475	aPatch[off++] = 0x5a; /* pop edx */
2476	aPatch[off++] = 0x59; /* pop ecx */
2477	}
2478	else
2479	{
2480	/*
2481	* TPR read:
2482	*
2483	* push ECX [51]
2484	* push EDX [52]
2485	* push EAX [50]
2486	* mov ECX,0C0000082h [B9 82 00 00 C0]
2487	* rdmsr [0F 32]
2488	* mov EAX,EAX [89 C0]
2489	* pop EAX [58]
2490	* pop EDX [5A]
2491	* pop ECX [59]
2492	* jmp return_address [E9 return_address]
2493	*/
2494	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2495
2496	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2497	aPatch[off++] = 0x51; /* push ecx */
2498	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2499	aPatch[off++] = 0x52; /* push edx */
2500	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2501	aPatch[off++] = 0x50; /* push eax */
2502
2503	aPatch[off++] = 0x31; /* xor edx, edx */
2504	aPatch[off++] = 0xd2;
2505
2506	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2507	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2508	off += sizeof(uint32_t);
2509
2510	aPatch[off++] = 0x0f; /* rdmsr */
2511	aPatch[off++] = 0x32;
2512
2513	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2514	{
2515	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2516	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2517	}
2518
2519	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2520	aPatch[off++] = 0x58; /* pop eax */
2521	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2522	aPatch[off++] = 0x5a; /* pop edx */
2523	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2524	aPatch[off++] = 0x59; /* pop ecx */
2525	}
2526	aPatch[off++] = 0xe9; /* jmp return_address */
2527	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2528	off += sizeof(RTRCUINTPTR);
2529
2530	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2531	{
2532	/* Write new code to the patch buffer. */
2533	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2534	AssertRC(rc);
2535
2536	#ifdef LOG_ENABLED
2537	uint32_t cbCurInstr;
2538	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2539	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2540	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2541	{
2542	char szOutput[256];
2543	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2544	szOutput, sizeof(szOutput), &cbCurInstr);
2545	if (RT_SUCCESS(rc))
2546	Log(("Patch instr %s\n", szOutput));
2547	else
2548	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2549	}
2550	#endif
2551
2552	pPatch->aNewOpcode[0] = 0xE9;
2553	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2554
2555	/* Overwrite the TPR instruction with a jump. */
2556	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2557	AssertRC(rc);
2558
2559	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2560
2561	pVM->hm.s.pFreeGuestPatchMem += off;
2562	pPatch->cbNewOp = 5;
2563
2564	pPatch->Core.Key = pCtx->eip;
2565	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2566	AssertRC(rc);
2567
2568	pVM->hm.s.cPatches++;
2569	pVM->hm.s.fTprPatchingActive = true;
2570	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2571	return VINF_SUCCESS;
2572	}
2573
2574	Log(("Ran out of space in our patch buffer!\n"));
2575	}
2576	else
2577	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2578
2579
2580	/*
2581	* Save invalid patch, so we will not try again.
2582	*/
2583	pPatch = &pVM->hm.s.aPatches[idx];
2584	pPatch->Core.Key = pCtx->eip;
2585	pPatch->enmType = HMTPRINSTR_INVALID;
2586	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2587	AssertRC(rc);
2588	pVM->hm.s.cPatches++;
2589	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2590	return VINF_SUCCESS;
2591	}
2592
2593
2594	/**
2595	* Attempt to patch TPR mmio instructions.
2596	*
2597	* @returns VBox status code.
2598	* @param pVM The cross context VM structure.
2599	* @param pVCpu The cross context virtual CPU structure.
2600	*/
2601	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2602	{
2603	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2604	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2605	(void *)(uintptr_t)pVCpu->idCpu);
2606	AssertRC(rc);
2607	return rc;
2608	}
2609
2610
2611	/**
2612	* Checks if we need to reschedule due to VMM device heap changes.
2613	*
2614	* @returns true if a reschedule is required, otherwise false.
2615	* @param pVM The cross context VM structure.
2616	* @param pCtx VM execution context.
2617	*/
2618	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2619	{
2620	/*
2621	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2622	* when the unrestricted guest execution feature is missing (VT-x only).
2623	*/
2624	if ( pVM->hm.s.vmx.fEnabled
2625	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2626	&& CPUMIsGuestInRealModeEx(pCtx)
2627	&& !PDMVmmDevHeapIsEnabled(pVM))
2628	return true;
2629
2630	return false;
2631	}
2632
2633
2634	/**
2635	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2636	* event settings changes.
2637	*
2638	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2639	* function is just updating the VM globals.
2640	*
2641	* @param pVM The VM cross context VM structure.
2642	* @thread EMT(0)
2643	*/
2644	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2645	{
2646	/* Interrupts. */
2647	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2648	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2649
2650	/* CPU Exceptions. */
2651	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2652	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2653	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2654	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2655
2656	/* Common VM exits. */
2657	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2658	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2659	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2660	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2661
2662	/* Vendor specific VM exits. */
2663	if (HMR3IsVmxEnabled(pVM->pUVM))
2664	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2665	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2666	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2667	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2668	else
2669	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2670	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2671	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2672	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2673
2674	/* Done. */
2675	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2676	}
2677
2678
2679	/**
2680	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2681	*
2682	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2683	* per CPU settings.
2684	*
2685	* @param pVM The VM cross context VM structure.
2686	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2687	*/
2688	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2689	{
2690	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2691	}
2692
2693
2694	/**
2695	* Checks if we are currently using hardware acceleration.
2696	*
2697	* @returns true if hardware acceleration is being used, otherwise false.
2698	* @param pVCpu The cross context virtual CPU structure.
2699	*/
2700	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2701	{
2702	return pVCpu->hm.s.fActive;
2703	}
2704
2705
2706	/**
2707	* External interface for querying whether hardware acceleration is enabled.
2708	*
2709	* @returns true if VT-x or AMD-V is being used, otherwise false.
2710	* @param pUVM The user mode VM handle.
2711	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2712	*/
2713	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2714	{
2715	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2716	PVM pVM = pUVM->pVM;
2717	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2718	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2719	}
2720
2721
2722	/**
2723	* External interface for querying whether VT-x is being used.
2724	*
2725	* @returns true if VT-x is being used, otherwise false.
2726	* @param pUVM The user mode VM handle.
2727	* @sa HMR3IsSvmEnabled, HMIsEnabled
2728	*/
2729	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2730	{
2731	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2732	PVM pVM = pUVM->pVM;
2733	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2734	return pVM->hm.s.vmx.fEnabled
2735	&& pVM->hm.s.vmx.fSupported
2736	&& pVM->fHMEnabled;
2737	}
2738
2739
2740	/**
2741	* External interface for querying whether AMD-V is being used.
2742	*
2743	* @returns true if VT-x is being used, otherwise false.
2744	* @param pUVM The user mode VM handle.
2745	* @sa HMR3IsVmxEnabled, HMIsEnabled
2746	*/
2747	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2748	{
2749	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2750	PVM pVM = pUVM->pVM;
2751	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2752	return pVM->hm.s.svm.fEnabled
2753	&& pVM->hm.s.svm.fSupported
2754	&& pVM->fHMEnabled;
2755	}
2756
2757
2758	/**
2759	* Checks if we are currently using nested paging.
2760	*
2761	* @returns true if nested paging is being used, otherwise false.
2762	* @param pUVM The user mode VM handle.
2763	*/
2764	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2765	{
2766	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2767	PVM pVM = pUVM->pVM;
2768	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2769	return pVM->hm.s.fNestedPagingCfg;
2770	}
2771
2772
2773	/**
2774	* Checks if virtualized APIC registers are enabled.
2775	*
2776	* When enabled this feature allows the hardware to access most of the
2777	* APIC registers in the virtual-APIC page without causing VM-exits. See
2778	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2779	*
2780	* @returns true if virtualized APIC registers is enabled, otherwise
2781	* false.
2782	* @param pUVM The user mode VM handle.
2783	*/
2784	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2785	{
2786	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2787	PVM pVM = pUVM->pVM;
2788	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2789	return pVM->hm.s.fVirtApicRegs;
2790	}
2791
2792
2793	/**
2794	* Checks if APIC posted-interrupt processing is enabled.
2795	*
2796	* This returns whether we can deliver interrupts to the guest without
2797	* leaving guest-context by updating APIC state from host-context.
2798	*
2799	* @returns true if APIC posted-interrupt processing is enabled,
2800	* otherwise false.
2801	* @param pUVM The user mode VM handle.
2802	*/
2803	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2804	{
2805	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2806	PVM pVM = pUVM->pVM;
2807	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2808	return pVM->hm.s.fPostedIntrs;
2809	}
2810
2811
2812	/**
2813	* Checks if we are currently using VPID in VT-x mode.
2814	*
2815	* @returns true if VPID is being used, otherwise false.
2816	* @param pUVM The user mode VM handle.
2817	*/
2818	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2819	{
2820	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2821	PVM pVM = pUVM->pVM;
2822	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2823	return pVM->hm.s.ForR3.vmx.fVpid;
2824	}
2825
2826
2827	/**
2828	* Checks if we are currently using VT-x unrestricted execution,
2829	* aka UX.
2830	*
2831	* @returns true if UX is being used, otherwise false.
2832	* @param pUVM The user mode VM handle.
2833	*/
2834	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2835	{
2836	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2837	PVM pVM = pUVM->pVM;
2838	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2839	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2840	\|\| pVM->hm.s.svm.fSupported;
2841	}
2842
2843
2844	/**
2845	* Checks if the VMX-preemption timer is being used.
2846	*
2847	* @returns true if the VMX-preemption timer is being used, otherwise false.
2848	* @param pVM The cross context VM structure.
2849	*/
2850	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2851	{
2852	return HMIsEnabled(pVM)
2853	&& pVM->hm.s.vmx.fEnabled
2854	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2855	}
2856
2857
2858	#ifdef TODO_9217_VMCSINFO
2859	/**
2860	* Helper for HMR3CheckError to log VMCS controls to the release log.
2861	*
2862	* @param idCpu The Virtual CPU ID.
2863	* @param pVmcsInfo The VMCS info. object.
2864	*/
2865	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2866	{
2867	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2868	{
2869	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2870	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2871	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2872	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2873	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2874	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2875	}
2876	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2877	{
2878	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2879	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2880	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2881	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2882	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2883	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2884	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2885	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2886	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2887	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2888	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2893	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2894	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2895	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2896	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2897	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2898	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2901	}
2902	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2903	{
2904	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2905	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2932	}
2933	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2934	{
2935	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2942	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2943	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2948	}
2949	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2950	{
2951	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
2966	}
2967	}
2968	#endif
2969
2970
2971	/**
2972	* Check fatal VT-x/AMD-V error and produce some meaningful
2973	* log release message.
2974	*
2975	* @param pVM The cross context VM structure.
2976	* @param iStatusCode VBox status code.
2977	*/
2978	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2979	{
2980	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2981	{
2982	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2983	* might be getting inaccurate values for non-guru'ing EMTs. */
2984	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2985	#ifdef TODO_9217_VMCSINFO
2986	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
2987	#endif
2988	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
2989	switch (iStatusCode)
2990	{
2991	case VERR_VMX_INVALID_VMCS_PTR:
2992	{
2993	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2994	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2995	#ifdef TODO_9217_VMCSINFO
2996	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2997	pVmcsInfo->HCPhysVmcs));
2998	#endif
2999	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3000	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3001	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3002	break;
3003	}
3004
3005	case VERR_VMX_UNABLE_TO_START_VM:
3006	{
3007	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3008	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3009	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3010	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3011
3012	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3013	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3014	{
3015	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3016	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3017	}
3018	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3019	{
3020	#ifdef TODO_9217_VMCSINFO
3021	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3022	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3023	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3024	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3025	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3026	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3027	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3028	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3029	#endif
3030	}
3031	/** @todo Log VM-entry event injection control fields
3032	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3033	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3034	break;
3035	}
3036
3037	case VERR_VMX_INVALID_GUEST_STATE:
3038	{
3039	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3040	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3041	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3042	#ifdef TODO_9217_VMCSINFO
3043	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3044	#endif
3045	break;
3046	}
3047
3048	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3049	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3050	case VERR_VMX_INVALID_VMXON_PTR:
3051	case VERR_VMX_UNEXPECTED_EXIT:
3052	case VERR_VMX_INVALID_VMCS_FIELD:
3053	case VERR_SVM_UNKNOWN_EXIT:
3054	case VERR_SVM_UNEXPECTED_EXIT:
3055	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3056	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3057	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3058	break;
3059	}
3060	}
3061
3062	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3063	{
3064	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3065	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3066	}
3067	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3068	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3069	}
3070
3071
3072	/**
3073	* Execute state save operation.
3074	*
3075	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3076	* is because we always save the VM state from ring-3 and thus most HM state
3077	* will be re-synced dynamically at runtime and don't need to be part of the VM
3078	* saved state.
3079	*
3080	* @returns VBox status code.
3081	* @param pVM The cross context VM structure.
3082	* @param pSSM SSM operation handle.
3083	*/
3084	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3085	{
3086	Log(("hmR3Save:\n"));
3087
3088	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3089	{
3090	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3091	Assert(!pVCpu->hm.s.Event.fPending);
3092	if (pVM->cpum.ro.GuestFeatures.fSvm)
3093	{
3094	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3095	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3096	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3097	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3098	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3099	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3100	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3101	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3102	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3103	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3104	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3105	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3106	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3107	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3108	}
3109	}
3110
3111	/* Save the guest patch data. */
3112	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3113	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3114	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3115
3116	/* Store all the guest patch records too. */
3117	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3118	if (RT_FAILURE(rc))
3119	return rc;
3120
3121	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3122	{
3123	AssertCompileSize(HMTPRINSTR, 4);
3124	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3125	SSMR3PutU32(pSSM, pPatch->Core.Key);
3126	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3127	SSMR3PutU32(pSSM, pPatch->cbOp);
3128	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3129	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3130	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3131	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3132	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3133	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3134	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3135	if (RT_FAILURE(rc))
3136	return rc;
3137	}
3138
3139	return VINF_SUCCESS;
3140	}
3141
3142
3143	/**
3144	* Execute state load operation.
3145	*
3146	* @returns VBox status code.
3147	* @param pVM The cross context VM structure.
3148	* @param pSSM SSM operation handle.
3149	* @param uVersion Data layout version.
3150	* @param uPass The data pass.
3151	*/
3152	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3153	{
3154	int rc;
3155
3156	LogFlowFunc(("uVersion=%u\n", uVersion));
3157	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3158
3159	/*
3160	* Validate version.
3161	*/
3162	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3163	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3164	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3165	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3166	{
3167	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3168	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3169	}
3170
3171	/*
3172	* Load per-VCPU state.
3173	*/
3174	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3175	{
3176	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3177	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3178	{
3179	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3180	if (pVM->cpum.ro.GuestFeatures.fSvm)
3181	{
3182	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3183	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3184	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3185	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3186	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3187	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3188	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3189	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3190	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3191	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3192	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3193	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3194	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3195	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3196	AssertRCReturn(rc, rc);
3197	}
3198	}
3199	else
3200	{
3201	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3202	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3203	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3204	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3205
3206	/* VMX fWasInRealMode related data. */
3207	uint32_t uDummy;
3208	SSMR3GetU32(pSSM, &uDummy);
3209	SSMR3GetU32(pSSM, &uDummy);
3210	rc = SSMR3GetU32(pSSM, &uDummy);
3211	AssertRCReturn(rc, rc);
3212	}
3213	}
3214
3215	/*
3216	* Load TPR patching data.
3217	*/
3218	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3219	{
3220	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3221	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3222	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3223
3224	/* Fetch all TPR patch records. */
3225	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3226	AssertRCReturn(rc, rc);
3227	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3228	{
3229	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3230	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3231	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3232	SSMR3GetU32(pSSM, &pPatch->cbOp);
3233	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3234	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3235	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3236
3237	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3238	pVM->hm.s.fTprPatchingActive = true;
3239	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3240
3241	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3242	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3243	SSMR3GetU32(pSSM, &pPatch->cFaults);
3244	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3245	AssertRCReturn(rc, rc);
3246
3247	LogFlow(("hmR3Load: patch %d\n", i));
3248	LogFlow(("Key = %x\n", pPatch->Core.Key));
3249	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3250	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3251	LogFlow(("type = %d\n", pPatch->enmType));
3252	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3253	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3254	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3255	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3256
3257	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3258	AssertRCReturn(rc, rc);
3259	}
3260	}
3261
3262	return VINF_SUCCESS;
3263	}
3264
3265
3266	/**
3267	* Displays HM info.
3268	*
3269	* @param pVM The cross context VM structure.
3270	* @param pHlp The info helper functions.
3271	* @param pszArgs Arguments, ignored.
3272	*/
3273	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3274	{
3275	NOREF(pszArgs);
3276	PVMCPU pVCpu = VMMGetCpu(pVM);
3277	if (!pVCpu)
3278	pVCpu = pVM->apCpusR3[0];
3279
3280	if (HMIsEnabled(pVM))
3281	{
3282	if (pVM->hm.s.vmx.fSupported)
3283	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3284	else
3285	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3286	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3287	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3288	if (pVM->hm.s.vmx.fSupported)
3289	{
3290	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3291	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3292	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3293
3294	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3295	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3296	if (fRealOnV86Active)
3297	{
3298	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3299	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3300	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3301	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3302	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3303	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3304	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3305	}
3306	}
3307	}
3308	else
3309	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3310	}
3311
3312
3313	/**
3314	* Displays the HM Last-Branch-Record info. for the guest.
3315	*
3316	* @param pVM The cross context VM structure.
3317	* @param pHlp The info helper functions.
3318	* @param pszArgs Arguments, ignored.
3319	*/
3320	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3321	{
3322	NOREF(pszArgs);
3323	PVMCPU pVCpu = VMMGetCpu(pVM);
3324	if (!pVCpu)
3325	pVCpu = pVM->apCpusR3[0];
3326
3327	if (!HMIsEnabled(pVM))
3328	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3329	else if (HMIsVmxActive(pVM))
3330	{
3331	if (pVM->hm.s.vmx.fLbrCfg)
3332	{
3333	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3334	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3335
3336	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3337	* 0xf should cover everything we support thus far. Fix if necessary
3338	* later. */
3339	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3340	if (idxTopOfStack > cLbrStack)
3341	{
3342	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3343	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3344	return;
3345	}
3346
3347	/*
3348	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3349	*/
3350	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3351	uint32_t idxCurrent = idxTopOfStack;
3352	Assert(idxTopOfStack < cLbrStack);
3353	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3354	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3355	for (;;)
3356	{
3357	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3358	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3359	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3360	else
3361	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3362
3363	idxCurrent = (idxCurrent - 1) % cLbrStack;
3364	if (idxCurrent == idxTopOfStack)
3365	break;
3366	}
3367	}
3368	else
3369	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3370	}
3371	else
3372	{
3373	Assert(HMIsSvmActive(pVM));
3374	/** @todo SVM: LBRs (get them from VMCB if possible). */
3375	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3376	}
3377	}
3378
3379
3380	/**
3381	* Displays the HM pending event.
3382	*
3383	* @param pVM The cross context VM structure.
3384	* @param pHlp The info helper functions.
3385	* @param pszArgs Arguments, ignored.
3386	*/
3387	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3388	{
3389	NOREF(pszArgs);
3390	PVMCPU pVCpu = VMMGetCpu(pVM);
3391	if (!pVCpu)
3392	pVCpu = pVM->apCpusR3[0];
3393
3394	if (HMIsEnabled(pVM))
3395	{
3396	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3397	if (pVCpu->hm.s.Event.fPending)
3398	{
3399	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3400	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3401	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3402	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3403	}
3404	}
3405	else
3406	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3407	}
3408
3409
3410	/**
3411	* Displays the SVM nested-guest VMCB cache.
3412	*
3413	* @param pVM The cross context VM structure.
3414	* @param pHlp The info helper functions.
3415	* @param pszArgs Arguments, ignored.
3416	*/
3417	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3418	{
3419	NOREF(pszArgs);
3420	PVMCPU pVCpu = VMMGetCpu(pVM);
3421	if (!pVCpu)
3422	pVCpu = pVM->apCpusR3[0];
3423
3424	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3425	if ( fSvmEnabled
3426	&& pVM->cpum.ro.GuestFeatures.fSvm)
3427	{
3428	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3429	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3430	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3431	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3432	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3433	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3434	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3435	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3436	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3437	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3438	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3439	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3440	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3441	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3442	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3443	}
3444	else
3445	{
3446	if (!fSvmEnabled)
3447	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3448	else
3449	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3450	}
3451	}
3452

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 93857

Download in other formats: