HM.cpp@ 93922

Last change on this file since 93922 was 93922, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 EPT VM-exit handling with HM ring-0 code.
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1	/* $Id: HM.cpp 93922 2022-02-24 15:14:31Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/trpm.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/iom.h>
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#include <VBox/vmm/hm_vmx.h>
55	#include <VBox/vmm/hm_svm.h>
56	#include "HMInternal.h"
57	#include <VBox/vmm/vmcc.h>
58	#include <VBox/err.h>
59	#include <VBox/param.h>
60
61	#include <iprt/assert.h>
62	#include <VBox/log.h>
63	#include <iprt/asm.h>
64	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
65	# include <iprt/asm-amd64-x86.h>
66	#endif
67	#include <iprt/env.h>
68	#include <iprt/thread.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74	/** @def HMVMX_REPORT_FEAT
75	* Reports VT-x feature to the release log.
76	*
77	* @param a_uAllowed1 Mask of allowed-1 feature bits.
78	* @param a_uAllowed0 Mask of allowed-0 feature bits.
79	* @param a_StrDesc The description string to report.
80	* @param a_Featflag Mask of the feature to report.
81	*/
82	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
83	do { \
84	if ((a_uAllowed1) & (a_Featflag)) \
85	{ \
86	if ((a_uAllowed0) & (a_Featflag)) \
87	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
88	else \
89	LogRel(("HM: " a_StrDesc "\n")); \
90	} \
91	else \
92	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
93	} while (0)
94
95	/** @def HMVMX_REPORT_ALLOWED_FEAT
96	* Reports an allowed VT-x feature to the release log.
97	*
98	* @param a_uAllowed1 Mask of allowed-1 feature bits.
99	* @param a_StrDesc The description string to report.
100	* @param a_FeatFlag Mask of the feature to report.
101	*/
102	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
103	do { \
104	if ((a_uAllowed1) & (a_FeatFlag)) \
105	LogRel(("HM: " a_StrDesc "\n")); \
106	else \
107	LogRel(("HM: " a_StrDesc " not supported\n")); \
108	} while (0)
109
110	/** @def HMVMX_REPORT_MSR_CAP
111	* Reports MSR feature capability.
112	*
113	* @param a_MsrCaps Mask of MSR feature bits.
114	* @param a_StrDesc The description string to report.
115	* @param a_fCap Mask of the feature to report.
116	*/
117	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
118	do { \
119	if ((a_MsrCaps) & (a_fCap)) \
120	LogRel(("HM: " a_StrDesc "\n")); \
121	} while (0)
122
123	/** @def HMVMX_LOGREL_FEAT
124	* Dumps a feature flag from a bitmap of features to the release log.
125	*
126	* @param a_fVal The value of all the features.
127	* @param a_fMask The specific bitmask of the feature.
128	*/
129	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
130	do { \
131	if ((a_fVal) & (a_fMask)) \
132	LogRel(("HM: %s\n", #a_fMask)); \
133	} while (0)
134
135
136	/*********************************************************************************************************************************
137	* Internal Functions *
138	*********************************************************************************************************************************/
139	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
140	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
141	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
145	static int hmR3InitFinalizeR3(PVM pVM);
146	static int hmR3InitFinalizeR0(PVM pVM);
147	static int hmR3InitFinalizeR0Intel(PVM pVM);
148	static int hmR3InitFinalizeR0Amd(PVM pVM);
149	static int hmR3TermCPU(PVM pVM);
150
151
152	#ifdef VBOX_WITH_STATISTICS
153	/**
154	* Returns the name of the hardware exception.
155	*
156	* @returns The name of the hardware exception.
157	* @param uVector The exception vector.
158	*/
159	static const char *hmR3GetXcptName(uint8_t uVector)
160	{
161	switch (uVector)
162	{
163	case X86_XCPT_DE: return "#DE";
164	case X86_XCPT_DB: return "#DB";
165	case X86_XCPT_NMI: return "#NMI";
166	case X86_XCPT_BP: return "#BP";
167	case X86_XCPT_OF: return "#OF";
168	case X86_XCPT_BR: return "#BR";
169	case X86_XCPT_UD: return "#UD";
170	case X86_XCPT_NM: return "#NM";
171	case X86_XCPT_DF: return "#DF";
172	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
173	case X86_XCPT_TS: return "#TS";
174	case X86_XCPT_NP: return "#NP";
175	case X86_XCPT_SS: return "#SS";
176	case X86_XCPT_GP: return "#GP";
177	case X86_XCPT_PF: return "#PF";
178	case X86_XCPT_MF: return "#MF";
179	case X86_XCPT_AC: return "#AC";
180	case X86_XCPT_MC: return "#MC";
181	case X86_XCPT_XF: return "#XF";
182	case X86_XCPT_VE: return "#VE";
183	case X86_XCPT_CP: return "#CP";
184	case X86_XCPT_VC: return "#VC";
185	case X86_XCPT_SX: return "#SX";
186	}
187	return "Reserved";
188	}
189	#endif /* VBOX_WITH_STATISTICS */
190
191
192	/**
193	* Initializes the HM.
194	*
195	* This is the very first component to really do init after CFGM so that we can
196	* establish the predominant execution engine for the VM prior to initializing
197	* other modules. It takes care of NEM initialization if needed (HM disabled or
198	* not available in HW).
199	*
200	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
201	* hypervisor API via NEM, and then back on raw-mode if that isn't available
202	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
203	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
204	* X, OS/2 and others).
205	*
206	* Note that a lot of the set up work is done in ring-0 and thus postponed till
207	* the ring-3 and ring-0 callback to HMR3InitCompleted.
208	*
209	* @returns VBox status code.
210	* @param pVM The cross context VM structure.
211	*
212	* @remarks Be careful with what we call here, since most of the VMM components
213	* are uninitialized.
214	*/
215	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
216	{
217	LogFlowFunc(("\n"));
218
219	/*
220	* Assert alignment and sizes.
221	*/
222	AssertCompileMemberAlignment(VM, hm.s, 32);
223	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
224
225	/*
226	* Register the saved state data unit.
227	*/
228	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
229	NULL, NULL, NULL,
230	NULL, hmR3Save, NULL,
231	NULL, hmR3Load, NULL);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Read configuration.
237	*/
238	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
239
240	/*
241	* Validate the HM settings.
242	*/
243	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
244	"HMForced" /* implied 'true' these days */
245	"\|UseNEMInstead"
246	"\|FallbackToNEM"
247	"\|FallbackToIEM"
248	"\|EnableNestedPaging"
249	"\|EnableUX"
250	"\|EnableLargePages"
251	"\|EnableVPID"
252	"\|IBPBOnVMExit"
253	"\|IBPBOnVMEntry"
254	"\|SpecCtrlByHost"
255	"\|L1DFlushOnSched"
256	"\|L1DFlushOnVMEntry"
257	"\|MDSClearOnSched"
258	"\|MDSClearOnVMEntry"
259	"\|TPRPatchingEnabled"
260	"\|64bitEnabled"
261	"\|Exclusive"
262	"\|MaxResumeLoops"
263	"\|VmxPleGap"
264	"\|VmxPleWindow"
265	"\|VmxLbr"
266	"\|UseVmxPreemptTimer"
267	"\|SvmPauseFilter"
268	"\|SvmPauseFilterThreshold"
269	"\|SvmVirtVmsaveVmload"
270	"\|SvmVGif"
271	"\|LovelyMesaDrvWorkaround"
272	"\|MissingOS2TlbFlushWorkaround",
273	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
274	if (RT_FAILURE(rc))
275	return rc;
276
277	/** @cfgm{/HM/HMForced, bool, false}
278	* Forces hardware virtualization, no falling back on raw-mode. HM must be
279	* enabled, i.e. /HMEnabled must be true. */
280	bool const fHMForced = true;
281	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
282	AssertRelease(pVM->fHMEnabled);
283	#else
284	AssertRelease(!pVM->fHMEnabled);
285	#endif
286
287	/** @cfgm{/HM/UseNEMInstead, bool, true}
288	* Don't use HM, use NEM instead. */
289	bool fUseNEMInstead = false;
290	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
291	AssertRCReturn(rc, rc);
292	if (fUseNEMInstead && pVM->fHMEnabled)
293	{
294	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
295	pVM->fHMEnabled = false;
296	}
297
298	/** @cfgm{/HM/FallbackToNEM, bool, true}
299	* Enables fallback on NEM. */
300	bool fFallbackToNEM = true;
301	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
302	AssertRCReturn(rc, rc);
303
304	/** @cfgm{/HM/FallbackToIEM, bool, false on AMD64 else true }
305	* Enables fallback on NEM. */
306	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
307	bool fFallbackToIEM = false;
308	#else
309	bool fFallbackToIEM = true;
310	#endif
311	rc = CFGMR3QueryBoolDef(pCfgHm, "fFallbackToIEM", &fFallbackToIEM, fFallbackToIEM);
312	AssertRCReturn(rc, rc);
313
314	/** @cfgm{/HM/EnableNestedPaging, bool, false}
315	* Enables nested paging (aka extended page tables). */
316	bool fAllowNestedPaging = false;
317	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
318	AssertRCReturn(rc, rc);
319
320	/** @cfgm{/HM/EnableUX, bool, true}
321	* Enables the VT-x unrestricted execution feature. */
322	bool fAllowUnrestricted = true;
323	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
324	AssertRCReturn(rc, rc);
325
326	/** @cfgm{/HM/EnableLargePages, bool, false}
327	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
328	* page table walking and maybe better TLB hit rate in some cases. */
329	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
330	AssertRCReturn(rc, rc);
331
332	/** @cfgm{/HM/EnableVPID, bool, false}
333	* Enables the VT-x VPID feature. */
334	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
335	AssertRCReturn(rc, rc);
336
337	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
338	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
339	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
340	AssertRCReturn(rc, rc);
341
342	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
343	* Enables AMD64 cpu features.
344	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
345	* already have the support. */
346	#ifdef VBOX_WITH_64_BITS_GUESTS
347	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
348	AssertLogRelRCReturn(rc, rc);
349	#else
350	pVM->hm.s.fAllow64BitGuestsCfg = false;
351	#endif
352
353	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
354	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
355	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
356	* latest PAUSE instruction to be start of a new PAUSE loop.
357	*/
358	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
359	AssertRCReturn(rc, rc);
360
361	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
362	* The pause-filter exiting window in TSC ticks. When the number of ticks
363	* between the current PAUSE instruction and first PAUSE of a loop exceeds
364	* VmxPleWindow, a VM-exit is triggered.
365	*
366	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
367	*/
368	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
369	AssertRCReturn(rc, rc);
370
371	/** @cfgm{/HM/VmxLbr, bool, false}
372	* Whether to enable LBR for the guest. This is disabled by default as it's only
373	* useful while debugging and enabling it causes a noticeable performance hit. */
374	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
375	AssertRCReturn(rc, rc);
376
377	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
378	* A counter that is decrement each time a PAUSE instruction is executed by the
379	* guest. When the counter is 0, a \#VMEXIT is triggered.
380	*
381	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
382	*/
383	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
384	AssertRCReturn(rc, rc);
385
386	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
387	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
388	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
389	* PauseFilter count is reset to its initial value. However, if PAUSE is
390	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
391	* be triggered.
392	*
393	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
394	* activated.
395	*/
396	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
397	AssertRCReturn(rc, rc);
398
399	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
400	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
401	* available. */
402	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
403	AssertRCReturn(rc, rc);
404
405	/** @cfgm{/HM/SvmVGif, bool, true}
406	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
407	* if it's available. */
408	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
409	AssertRCReturn(rc, rc);
410
411	/** @cfgm{/HM/SvmLbrVirt, bool, false}
412	* Whether to make use of the LBR virtualization feature of the CPU if it's
413	* available. This is disabled by default as it's only useful while debugging
414	* and enabling it causes a small hit to performance. */
415	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
416	AssertRCReturn(rc, rc);
417
418	/** @cfgm{/HM/Exclusive, bool}
419	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
420	* global init for each host CPU. If false, we do local init each time we wish
421	* to execute guest code.
422	*
423	* On Windows, default is false due to the higher risk of conflicts with other
424	* hypervisors.
425	*
426	* On Mac OS X, this setting is ignored since the code does not handle local
427	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
428	*/
429	#if defined(RT_OS_DARWIN)
430	pVM->hm.s.fGlobalInit = true;
431	#else
432	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
433	# if defined(RT_OS_WINDOWS)
434	false
435	# else
436	true
437	# endif
438	);
439	AssertLogRelRCReturn(rc, rc);
440	#endif
441
442	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
443	* The number of times to resume guest execution before we forcibly return to
444	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445	* determines the default value. */
446	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
447	AssertLogRelRCReturn(rc, rc);
448
449	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
450	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
451	* available. */
452	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
453	AssertLogRelRCReturn(rc, rc);
454
455	/** @cfgm{/HM/IBPBOnVMExit, bool}
456	* Costly paranoia setting. */
457	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
458	AssertLogRelRCReturn(rc, rc);
459
460	/** @cfgm{/HM/IBPBOnVMEntry, bool}
461	* Costly paranoia setting. */
462	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
463	AssertLogRelRCReturn(rc, rc);
464
465	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
466	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
467	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
471	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
472	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
473	AssertLogRelRCReturn(rc, rc);
474
475	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
476	if (pVM->hm.s.fL1dFlushOnVmEntry)
477	pVM->hm.s.fL1dFlushOnSched = false;
478
479	/** @cfgm{/HM/SpecCtrlByHost, bool}
480	* Another expensive paranoia setting. */
481	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
482	AssertLogRelRCReturn(rc, rc);
483
484	/** @cfgm{/HM/MDSClearOnSched, bool, true}
485	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
486	* ignored on CPUs that aren't affected. */
487	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
488	AssertLogRelRCReturn(rc, rc);
489
490	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
491	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
492	* ignored on CPUs that aren't affected. */
493	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
494	AssertLogRelRCReturn(rc, rc);
495
496	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
497	if (pVM->hm.s.fMdsClearOnVmEntry)
498	pVM->hm.s.fMdsClearOnSched = false;
499
500	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
501	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
502	* the hypervisor it is running under. */
503	bool fMesaWorkaround;
504	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
505	AssertLogRelRCReturn(rc, rc);
506	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
507	{
508	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
509	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
510	}
511
512	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
513	* Workaround OS/2 not flushing the TLB after page directory and page table
514	* modifications when returning to protected mode from a real mode call
515	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
516	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
517	AssertLogRelRCReturn(rc, rc);
518
519	/*
520	* Check if VT-x or AMD-v support according to the users wishes.
521	*/
522	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
523	* VERR_SVM_IN_USE. */
524	if (pVM->fHMEnabled)
525	{
526	uint32_t fCaps;
527	rc = SUPR3QueryVTCaps(&fCaps);
528	if (RT_SUCCESS(rc))
529	{
530	if (fCaps & SUPVTCAPS_AMD_V)
531	{
532	pVM->hm.s.svm.fSupported = true;
533	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
534	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
535	}
536	else if (fCaps & SUPVTCAPS_VT_X)
537	{
538	const char *pszWhy;
539	rc = SUPR3QueryVTxSupported(&pszWhy);
540	if (RT_SUCCESS(rc))
541	{
542	pVM->hm.s.vmx.fSupported = true;
543	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
544	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
545	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
546	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
547	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
548	}
549	else
550	{
551	/*
552	* Before failing, try fallback to NEM if we're allowed to do that.
553	*/
554	pVM->fHMEnabled = false;
555	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
556	if (fFallbackToNEM)
557	{
558	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
559	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
560
561	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
562	if ( RT_SUCCESS(rc2)
563	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
564	rc = VINF_SUCCESS;
565	}
566	if (RT_FAILURE(rc))
567	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
568	}
569	}
570	else
571	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
572	VERR_INTERNAL_ERROR_5);
573
574	/*
575	* Disable nested paging and unrestricted guest execution now if they're
576	* configured so that CPUM can make decisions based on our configuration.
577	*/
578	if ( fAllowNestedPaging
579	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
580	{
581	pVM->hm.s.fNestedPagingCfg = true;
582	if (fCaps & SUPVTCAPS_VT_X)
583	{
584	if ( fAllowUnrestricted
585	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
586	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
587	else
588	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
589	}
590	}
591	else
592	Assert(!pVM->hm.s.fNestedPagingCfg);
593	}
594	else
595	{
596	const char *pszMsg;
597	switch (rc)
598	{
599	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
600	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
601	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
602	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
603	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
604	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
605	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
606	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
607	default:
608	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
609	}
610
611	/*
612	* Before failing, try fallback to NEM if we're allowed to do that.
613	*/
614	pVM->fHMEnabled = false;
615	if (fFallbackToNEM)
616	{
617	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
618	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
619	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
620	if ( RT_SUCCESS(rc2)
621	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
622	{
623	rc = VINF_SUCCESS;
624
625	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
626	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
627	}
628	}
629
630	/*
631	* Then try fall back on IEM if NEM isn't available and we're allowed to.
632	*/
633	if (RT_FAILURE(rc))
634	{
635	if ( fFallbackToIEM
636	&& (!fFallbackToNEM \|\| rc == VERR_NEM_NOT_AVAILABLE))
637	{
638	LogRel(("HM: HMR3Init: Falling back on IEM: %s\n", !fFallbackToNEM ? pszMsg : "NEM not available"));
639	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
640	#ifdef VBOX_WITH_PGM_NEM_MODE
641	PGMR3EnableNemMode(pVM);
642	#endif
643	}
644	else
645	return VM_SET_ERROR(pVM, rc, pszMsg);
646	}
647	}
648	}
649	else
650	{
651	/*
652	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
653	*/
654	rc = VERR_NEM_NOT_AVAILABLE;
655	if (fUseNEMInstead)
656	{
657	rc = NEMR3Init(pVM, false /fFallback/, true);
658	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
659	if (RT_SUCCESS(rc))
660	{
661	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
662	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
663	}
664	else if (!fFallbackToIEM \|\| rc != VERR_NEM_NOT_AVAILABLE)
665	return rc;
666	}
667
668	if (fFallbackToIEM && rc == VERR_NEM_NOT_AVAILABLE)
669	{
670	LogRel(("HM: HMR3Init: Falling back on IEM%s\n", fUseNEMInstead ? ": NEM not available" : ""));
671	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_IEM);
672	#ifdef VBOX_WITH_PGM_NEM_MODE
673	PGMR3EnableNemMode(pVM);
674	#endif
675	}
676
677	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
678	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
679	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
680	}
681
682	if (pVM->fHMEnabled)
683	{
684	/*
685	* Register info handlers now that HM is used for sure.
686	*/
687	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
688	AssertRCReturn(rc, rc);
689
690	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
691	DBGFINFO_FLAGS_ALL_EMTS);
692	AssertRCReturn(rc, rc);
693
694	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
695	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
696	AssertRCReturn(rc, rc);
697
698	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
699	AssertRCReturn(rc, rc);
700	}
701
702	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
703	return VINF_SUCCESS;
704	}
705
706
707	/**
708	* Initializes HM components after ring-3 phase has been fully initialized.
709	*
710	* @returns VBox status code.
711	* @param pVM The cross context VM structure.
712	*/
713	static int hmR3InitFinalizeR3(PVM pVM)
714	{
715	LogFlowFunc(("\n"));
716
717	if (!HMIsEnabled(pVM))
718	return VINF_SUCCESS;
719
720	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
721	{
722	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
723	pVCpu->hm.s.fActive = false;
724	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
725	}
726
727	/*
728	* Check if L1D flush is needed/possible.
729	*/
730	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
731	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
732	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
733	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
734	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
735	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
736
737	/*
738	* Check if MDS flush is needed/possible.
739	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
740	*/
741	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
742	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
743	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
744	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
745	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
746	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
747	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
748	{
749	if (!pVM->hm.s.fMdsClearOnSched)
750	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
751	pVM->hm.s.fMdsClearOnVmEntry = false;
752	}
753	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
754	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
755	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
756
757	/*
758	* Statistics.
759	*/
760	#ifdef VBOX_WITH_STATISTICS
761	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
762	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
763	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
764	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
765	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
766	#endif
767
768	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
769	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
770	#else
771	bool const fCpuSupportsVmx = false;
772	#endif
773	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
774	{
775	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
776	PHMCPU pHmCpu = &pVCpu->hm.s;
777	int rc;
778
779	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
780	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
781	AssertRC(rc); \
782	} while (0)
783	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
784	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
785
786	#ifdef VBOX_WITH_STATISTICS
787
788	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
789	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
790	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
791	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
792	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
793	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
794	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
795	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
796	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
797	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
798	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
799	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
800	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
801	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
802	# ifdef HM_PROFILE_EXIT_DISPATCH
803	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
804	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
805	# endif
806	#endif
807	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
808
809	#ifdef VBOX_WITH_STATISTICS
810	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
811	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
812	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
813	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
814	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
815	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
816	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
817	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
818	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
819	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
820	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
821	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
822	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
823	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
824	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
825	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
826	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
827	#endif
828	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
829	if (fCpuSupportsVmx)
830	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
831	#ifdef VBOX_WITH_STATISTICS
832	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
833	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
834	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
835	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
836	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
837	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
838	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
839	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
840	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
841	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
842	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
843	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
844	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
845	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
846	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
847	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
848	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
849	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
850	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
851	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
852	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
853	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
854	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
855	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
856	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
857	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
858	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
859	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
860	#endif
861	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
862	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
863	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
864	#ifdef VBOX_WITH_STATISTICS
865	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
866	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
867	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
868
869	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
870	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
871	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
872	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
873	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
874	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
875	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
876	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
877	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
878	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
879	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
880	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
881	#endif
882	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
883	#ifdef VBOX_WITH_STATISTICS
884	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
885
886	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
887	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
888	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
889	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
890	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
891	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
892
893	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
894	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
895	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
896	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
897	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
898	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
899	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
900	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
901	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
902	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
903	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
904	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
905	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
906	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
907	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
908
909	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
910	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
911	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
912
913	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
914	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
915	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
916
917	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
918	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
919	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
920	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
921
922	if (fCpuSupportsVmx)
923	{
924	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
925	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
926	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
927	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
928	}
929
930	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
931	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
932	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
933
934	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
935	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
936	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
937
938	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
939	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
940	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
941	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
942	#endif
943	if (fCpuSupportsVmx)
944	{
945	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
946	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
947	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
948	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
949	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
950	}
951	#ifdef VBOX_WITH_STATISTICS
952	/*
953	* Guest Exit reason stats.
954	*/
955	if (fCpuSupportsVmx)
956	{
957	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
958	{
959	const char *pszExitName = HMGetVmxExitName(j);
960	if (pszExitName)
961	{
962	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
963	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
964	AssertRCReturn(rc, rc);
965	}
966	}
967	}
968	else
969	{
970	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
971	{
972	const char *pszExitName = HMGetSvmExitName(j);
973	if (pszExitName)
974	{
975	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
976	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
977	AssertRC(rc);
978	}
979	}
980	}
981	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
982
983	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
984	/*
985	* Nested-guest VM-exit reason stats.
986	*/
987	if (fCpuSupportsVmx)
988	{
989	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
990	{
991	const char *pszExitName = HMGetVmxExitName(j);
992	if (pszExitName)
993	{
994	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
995	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
996	AssertRC(rc);
997	}
998	}
999	}
1000	else
1001	{
1002	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1003	{
1004	const char *pszExitName = HMGetSvmExitName(j);
1005	if (pszExitName)
1006	{
1007	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1008	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
1009	AssertRC(rc);
1010	}
1011	}
1012	}
1013	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
1014	#endif
1015
1016	/*
1017	* Injected interrupts stats.
1018	*/
1019	char szDesc[64];
1020	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
1021	{
1022	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
1023	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1024	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
1025	AssertRC(rc);
1026	}
1027
1028	/*
1029	* Injected exception stats.
1030	*/
1031	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
1032	{
1033	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
1034	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1035	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
1036	AssertRC(rc);
1037	}
1038
1039	#endif /* VBOX_WITH_STATISTICS */
1040	#undef HM_REG_COUNTER
1041	#undef HM_REG_PROFILE
1042	#undef HM_REG_STAT
1043	}
1044
1045	return VINF_SUCCESS;
1046	}
1047
1048
1049	/**
1050	* Called when a init phase has completed.
1051	*
1052	* @returns VBox status code.
1053	* @param pVM The cross context VM structure.
1054	* @param enmWhat The phase that completed.
1055	*/
1056	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1057	{
1058	switch (enmWhat)
1059	{
1060	case VMINITCOMPLETED_RING3:
1061	return hmR3InitFinalizeR3(pVM);
1062	case VMINITCOMPLETED_RING0:
1063	return hmR3InitFinalizeR0(pVM);
1064	default:
1065	return VINF_SUCCESS;
1066	}
1067	}
1068
1069
1070	/**
1071	* Turns off normal raw mode features.
1072	*
1073	* @param pVM The cross context VM structure.
1074	*/
1075	static void hmR3DisableRawMode(PVM pVM)
1076	{
1077	/** @todo r=bird: HM shouldn't be doing this crap. */
1078	/* Reinit the paging mode to force the new shadow mode. */
1079	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1080	{
1081	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1082	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL, false /* fForce */);
1083	}
1084	}
1085
1086
1087	/**
1088	* Initialize VT-x or AMD-V.
1089	*
1090	* @returns VBox status code.
1091	* @param pVM The cross context VM structure.
1092	*/
1093	static int hmR3InitFinalizeR0(PVM pVM)
1094	{
1095	int rc;
1096
1097	if (!HMIsEnabled(pVM))
1098	return VINF_SUCCESS;
1099
1100	/*
1101	* Hack to allow users to work around broken BIOSes that incorrectly set
1102	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1103	*/
1104	if ( !pVM->hm.s.vmx.fSupported
1105	&& !pVM->hm.s.svm.fSupported
1106	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1107	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1108	{
1109	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1110	pVM->hm.s.svm.fSupported = true;
1111	pVM->hm.s.svm.fIgnoreInUseError = true;
1112	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1113	}
1114
1115	/*
1116	* Report ring-0 init errors.
1117	*/
1118	if ( !pVM->hm.s.vmx.fSupported
1119	&& !pVM->hm.s.svm.fSupported)
1120	{
1121	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1122	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1123	switch (pVM->hm.s.ForR3.rcInit)
1124	{
1125	case VERR_VMX_IN_VMX_ROOT_MODE:
1126	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1127	case VERR_VMX_NO_VMX:
1128	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1129	case VERR_VMX_MSR_VMX_DISABLED:
1130	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1131	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1132	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1133	case VERR_VMX_MSR_LOCKING_FAILED:
1134	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1135	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1136	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1137	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1138	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1139
1140	case VERR_SVM_IN_USE:
1141	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1142	case VERR_SVM_NO_SVM:
1143	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1144	case VERR_SVM_DISABLED:
1145	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1146	}
1147	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1148	}
1149
1150	/*
1151	* Enable VT-x or AMD-V on all host CPUs.
1152	*/
1153	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1154	if (RT_FAILURE(rc))
1155	{
1156	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1157	HMR3CheckError(pVM, rc);
1158	return rc;
1159	}
1160
1161	/*
1162	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1163	* (Main should have taken care of this already)
1164	*/
1165	if (!PDMHasIoApic(pVM))
1166	{
1167	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1168	pVM->hm.s.fTprPatchingAllowed = false;
1169	}
1170
1171	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1172	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1173	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1174
1175	/*
1176	* Do the vendor specific initialization
1177	*
1178	* Note! We disable release log buffering here since we're doing relatively
1179	* lot of logging and doesn't want to hit the disk with each LogRel
1180	* statement.
1181	*/
1182	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1183	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1184	if (pVM->hm.s.vmx.fSupported)
1185	rc = hmR3InitFinalizeR0Intel(pVM);
1186	else
1187	rc = hmR3InitFinalizeR0Amd(pVM);
1188	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1189	: "HM: VT-x/AMD-V init method: Local\n"));
1190	RTLogRelSetBuffering(fOldBuffered);
1191	pVM->hm.s.fInitialized = true;
1192
1193	return rc;
1194	}
1195
1196
1197	/**
1198	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1199	*/
1200	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1201	{
1202	NOREF(pVM);
1203	NOREF(pvAllocation);
1204	NOREF(GCPhysAllocation);
1205	}
1206
1207
1208	/**
1209	* Returns a description of the VMCS (and associated regions') memory type given the
1210	* IA32_VMX_BASIC MSR.
1211	*
1212	* @returns The descriptive memory type.
1213	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1214	*/
1215	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1216	{
1217	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1218	switch (uMemType)
1219	{
1220	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1221	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1222	}
1223	return "Unknown";
1224	}
1225
1226
1227	/**
1228	* Returns a single-line description of all the activity-states supported by the CPU
1229	* given the IA32_VMX_MISC MSR.
1230	*
1231	* @returns All supported activity states.
1232	* @param uMsrMisc IA32_VMX_MISC MSR value.
1233	*/
1234	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1235	{
1236	static const char * const s_apszActStates[] =
1237	{
1238	"",
1239	" ( HLT )",
1240	" ( SHUTDOWN )",
1241	" ( HLT SHUTDOWN )",
1242	" ( SIPI_WAIT )",
1243	" ( HLT SIPI_WAIT )",
1244	" ( SHUTDOWN SIPI_WAIT )",
1245	" ( HLT SHUTDOWN SIPI_WAIT )"
1246	};
1247	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1248	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1249	return s_apszActStates[idxActStates];
1250	}
1251
1252
1253	/**
1254	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1255	*
1256	* @param fFeatMsr The feature control MSR value.
1257	*/
1258	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1259	{
1260	uint64_t const val = fFeatMsr;
1261	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1262	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1263	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1264	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1265	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1266	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1267	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1268	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1269	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1270	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1271	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1272	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1273	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1274	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1275	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1276	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1277	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1278	}
1279
1280
1281	/**
1282	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1283	*
1284	* @param uBasicMsr The VMX basic MSR value.
1285	*/
1286	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1287	{
1288	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1289	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1290	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1291	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1292	"< 4 GB" : "None"));
1293	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1294	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1295	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1296	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1297	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1298	}
1299
1300
1301	/**
1302	* Reports MSR_IA32_PINBASED_CTLS to the log.
1303	*
1304	* @param pVmxMsr Pointer to the VMX MSR.
1305	*/
1306	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1307	{
1308	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1309	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1310	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1311	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1312	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1313	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1314	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1315	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1316	}
1317
1318
1319	/**
1320	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1321	*
1322	* @param pVmxMsr Pointer to the VMX MSR.
1323	*/
1324	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1325	{
1326	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1327	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1328	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1344	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1345	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1346	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1347	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1348	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1349	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1350	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1351	}
1352
1353
1354	/**
1355	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1356	*
1357	* @param pVmxMsr Pointer to the VMX MSR.
1358	*/
1359	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1360	{
1361	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1362	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1363	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1364	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1365	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1366	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1367	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1368	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1381	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1382	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1383	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1384	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1385	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1386	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1387	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1388	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1389	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1390	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1391	}
1392
1393
1394	/**
1395	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1396	*
1397	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1398	*/
1399	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1400	{
1401	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1402	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1403	}
1404
1405
1406	/**
1407	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1408	*
1409	* @param pVmxMsr Pointer to the VMX MSR.
1410	*/
1411	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1412	{
1413	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1414	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1415	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1416	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1417	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1418	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1419	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1420	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1421	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1422	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1423	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1424	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1425	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1426	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1427	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1428	}
1429
1430
1431	/**
1432	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1433	*
1434	* @param pVmxMsr Pointer to the VMX MSR.
1435	*/
1436	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1437	{
1438	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1439	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1440	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1441	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1442	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1443	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1444	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1445	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1446	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1447	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1448	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1449	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1450	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1451	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1452	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1453	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1454	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1455	}
1456
1457
1458	/**
1459	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1460	*
1461	* @param fCaps The VMX EPT/VPID capability MSR value.
1462	*/
1463	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1464	{
1465	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1466	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1467	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1468	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1469	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1470	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1471	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1472	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1473	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1474	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1475	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1476	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1477	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1478	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1479	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1480	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1481	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1482	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1483	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1484	}
1485
1486
1487	/**
1488	* Reports MSR_IA32_VMX_MISC MSR to the log.
1489	*
1490	* @param pVM Pointer to the VM.
1491	* @param fMisc The VMX misc. MSR value.
1492	*/
1493	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1494	{
1495	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1496	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1497	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1498	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1499	else
1500	{
1501	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1502	pVM->hm.s.vmx.cPreemptTimerShift));
1503	}
1504	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1505	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1506	hmR3VmxGetActivityStateAllDesc(fMisc)));
1507	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1508	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1509	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1510	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1511	VMX_MISC_MAX_MSRS(fMisc)));
1512	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1513	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1514	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1515	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1516	}
1517
1518
1519	/**
1520	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1521	*
1522	* @param uVmcsEnum The VMX VMCS enum MSR value.
1523	*/
1524	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1525	{
1526	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1527	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1528	}
1529
1530
1531	/**
1532	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1533	*
1534	* @param uVmFunc The VMX VMFUNC MSR value.
1535	*/
1536	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1537	{
1538	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1539	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1540	}
1541
1542
1543	/**
1544	* Reports VMX CR0, CR4 fixed MSRs.
1545	*
1546	* @param pMsrs Pointer to the VMX MSRs.
1547	*/
1548	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1549	{
1550	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1551	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1552	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1553	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1554	}
1555
1556
1557	/**
1558	* Finish VT-x initialization (after ring-0 init).
1559	*
1560	* @returns VBox status code.
1561	* @param pVM The cross context VM structure.
1562	*/
1563	static int hmR3InitFinalizeR0Intel(PVM pVM)
1564	{
1565	int rc;
1566
1567	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1568	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1569
1570	LogRel(("HM: Using VT-x implementation 3.0\n"));
1571	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1572	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1573	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1574	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1575
1576	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1577	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1578
1579	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1580	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1581	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1582	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1583	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1584	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1585
1586	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1587	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1588
1589	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1590	{
1591	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1592	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1593	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1594	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1595	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1596	}
1597
1598	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1599	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1600	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1601	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1602	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1603	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1604	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1605
1606	#ifdef TODO_9217_VMCSINFO
1607	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1608	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1609	{
1610	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1611	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1612	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1613	}
1614	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1615	if (pVM->cpum.ro.GuestFeatures.fVmx)
1616	{
1617	LogRel(("HM: Nested-guest:\n"));
1618	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1619	{
1620	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1621	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1622	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1623	}
1624	}
1625	#endif
1626	#endif /* TODO_9217_VMCSINFO */
1627
1628	/*
1629	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1630	*/
1631	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1632	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1633	VERR_HM_IPE_1);
1634	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1635	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1636	&& pVM->hm.s.fNestedPagingCfg),
1637	VERR_HM_IPE_1);
1638
1639	/*
1640	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1641	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1642	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1643	*/
1644	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1645	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1646	{
1647	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1648	LogRel(("HM: Disabled RDTSCP\n"));
1649	}
1650
1651	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1652	{
1653	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1654	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1655	if (RT_SUCCESS(rc))
1656	{
1657	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1658	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1659	esp. Figure 20-5.*/
1660	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1661	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1662
1663	/* Bit set to 0 means software interrupts are redirected to the
1664	8086 program interrupt handler rather than switching to
1665	protected-mode handler. */
1666	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1667
1668	/* Allow all port IO, so that port IO instructions do not cause
1669	exceptions and would instead cause a VM-exit (based on VT-x's
1670	IO bitmap which we currently configure to always cause an exit). */
1671	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1672	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1673
1674	/*
1675	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1676	* page table used in real and protected mode without paging with EPT.
1677	*/
1678	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1679	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1680	{
1681	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1682	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1683	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1684	\| X86_PDE4M_G;
1685	}
1686
1687	/* We convert it here every time as PCI regions could be reconfigured. */
1688	if (PDMVmmDevHeapIsEnabled(pVM))
1689	{
1690	RTGCPHYS GCPhys;
1691	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1692	AssertRCReturn(rc, rc);
1693	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1694
1695	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1696	AssertRCReturn(rc, rc);
1697	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1698	}
1699	}
1700	else
1701	{
1702	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1703	pVM->hm.s.vmx.pRealModeTSS = NULL;
1704	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1705	return VMSetError(pVM, rc, RT_SRC_POS,
1706	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1707	}
1708	}
1709
1710	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1711	: "HM: Guest support: 32-bit only\n"));
1712
1713	/*
1714	* Call ring-0 to set up the VM.
1715	*/
1716	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1717	if (rc != VINF_SUCCESS)
1718	{
1719	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1720	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1721	{
1722	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1723	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1724	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1725	}
1726	HMR3CheckError(pVM, rc);
1727	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1728	}
1729
1730	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1731	LogRel(("HM: Enabled VMX\n"));
1732	pVM->hm.s.vmx.fEnabled = true;
1733
1734	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1735
1736	/*
1737	* Change the CPU features.
1738	*/
1739	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1740	if (pVM->hm.s.fAllow64BitGuestsCfg)
1741	{
1742	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1743	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1744	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1745	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1746	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1747	}
1748	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1749	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1750	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1751
1752	/*
1753	* Log configuration details.
1754	*/
1755	if (pVM->hm.s.fNestedPagingCfg)
1756	{
1757	LogRel(("HM: Enabled nested paging\n"));
1758	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1759	LogRel(("HM: EPT flush type = Single context\n"));
1760	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1761	LogRel(("HM: EPT flush type = All contexts\n"));
1762	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1763	LogRel(("HM: EPT flush type = Not supported\n"));
1764	else
1765	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1766
1767	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1768	LogRel(("HM: Enabled unrestricted guest execution\n"));
1769
1770	if (pVM->hm.s.fLargePages)
1771	{
1772	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1773	PGMSetLargePageUsage(pVM, true);
1774	LogRel(("HM: Enabled large page support\n"));
1775	}
1776	}
1777	else
1778	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1779
1780	if (pVM->hm.s.ForR3.vmx.fVpid)
1781	{
1782	LogRel(("HM: Enabled VPID\n"));
1783	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1784	LogRel(("HM: VPID flush type = Individual addresses\n"));
1785	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1786	LogRel(("HM: VPID flush type = Single context\n"));
1787	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1788	LogRel(("HM: VPID flush type = All contexts\n"));
1789	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1790	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1791	else
1792	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1793	}
1794	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1795	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1796
1797	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1798	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1799	else
1800	LogRel(("HM: Disabled VMX-preemption timer\n"));
1801
1802	if (pVM->hm.s.fVirtApicRegs)
1803	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1804
1805	if (pVM->hm.s.fPostedIntrs)
1806	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1807
1808	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1809	{
1810	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1811	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1812	}
1813
1814	return VINF_SUCCESS;
1815	}
1816
1817
1818	/**
1819	* Finish AMD-V initialization (after ring-0 init).
1820	*
1821	* @returns VBox status code.
1822	* @param pVM The cross context VM structure.
1823	*/
1824	static int hmR3InitFinalizeR0Amd(PVM pVM)
1825	{
1826	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1827
1828	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1829
1830	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
1831	uint32_t u32Family;
1832	uint32_t u32Model;
1833	uint32_t u32Stepping;
1834	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1835	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1836	#endif
1837	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1838	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1839	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1840	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1841	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1842
1843	/*
1844	* Enumerate AMD-V features.
1845	*/
1846	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1847	{
1848	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1849	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1850	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1851	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1852	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1853	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1854	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1855	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1856	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1857	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1858	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1859	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1860	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1861	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1862	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1863	#undef HMSVM_REPORT_FEATURE
1864	};
1865
1866	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1867	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1868	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1869	{
1870	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1871	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1872	}
1873	if (fSvmFeatures)
1874	for (unsigned iBit = 0; iBit < 32; iBit++)
1875	if (RT_BIT_32(iBit) & fSvmFeatures)
1876	LogRel(("HM: Reserved bit %u\n", iBit));
1877
1878	/*
1879	* Nested paging is determined in HMR3Init, verify the sanity of that.
1880	*/
1881	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1882	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1883	VERR_HM_IPE_1);
1884
1885	#if 0
1886	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1887	* here. */
1888	if (RTR0IsPostIpiSupport())
1889	pVM->hm.s.fPostedIntrs = true;
1890	#endif
1891
1892	/*
1893	* Determine whether we need to intercept #UD in SVM mode for emulating
1894	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1895	* when executed in long-mode. This is only really applicable when
1896	* non-default CPU profiles are in effect, i.e. guest vendor differs
1897	* from the host one.
1898	*/
1899	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1900	switch (CPUMGetGuestCpuVendor(pVM))
1901	{
1902	case CPUMCPUVENDOR_INTEL:
1903	case CPUMCPUVENDOR_VIA: /?/
1904	case CPUMCPUVENDOR_SHANGHAI: /?/
1905	switch (CPUMGetHostCpuVendor(pVM))
1906	{
1907	case CPUMCPUVENDOR_AMD:
1908	case CPUMCPUVENDOR_HYGON:
1909	if (pVM->hm.s.fAllow64BitGuestsCfg)
1910	{
1911	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1912	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1913	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1914	}
1915	break;
1916	default: break;
1917	}
1918	default: break;
1919	}
1920
1921	/*
1922	* Call ring-0 to set up the VM.
1923	*/
1924	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1925	if (rc != VINF_SUCCESS)
1926	{
1927	AssertMsgFailed(("%Rrc\n", rc));
1928	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1929	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1930	}
1931
1932	LogRel(("HM: Enabled SVM\n"));
1933	pVM->hm.s.svm.fEnabled = true;
1934
1935	if (pVM->hm.s.fNestedPagingCfg)
1936	{
1937	LogRel(("HM: Enabled nested paging\n"));
1938
1939	/*
1940	* Enable large pages (2 MB) if applicable.
1941	*/
1942	if (pVM->hm.s.fLargePages)
1943	{
1944	PGMSetLargePageUsage(pVM, true);
1945	LogRel(("HM: Enabled large page support\n"));
1946	}
1947	}
1948
1949	if (pVM->hm.s.fVirtApicRegs)
1950	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1951
1952	if (pVM->hm.s.fPostedIntrs)
1953	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1954
1955	hmR3DisableRawMode(pVM);
1956
1957	/*
1958	* Change the CPU features.
1959	*/
1960	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1961	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1962	if (pVM->hm.s.fAllow64BitGuestsCfg)
1963	{
1964	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1965	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1966	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1967	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1968	}
1969	/* Turn on NXE if PAE has been enabled. */
1970	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1971	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1972
1973	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1974	: "HM: Disabled TPR patching\n"));
1975
1976	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1977	: "HM: Guest support: 32-bit only\n"));
1978	return VINF_SUCCESS;
1979	}
1980
1981
1982	/**
1983	* Applies relocations to data and code managed by this
1984	* component. This function will be called at init and
1985	* whenever the VMM need to relocate it self inside the GC.
1986	*
1987	* @param pVM The cross context VM structure.
1988	*/
1989	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1990	{
1991	/* Fetch the current paging mode during the relocate callback during state loading. */
1992	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1993	{
1994	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1995	{
1996	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1997	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1998	}
1999	}
2000	}
2001
2002
2003	/**
2004	* Terminates the HM.
2005	*
2006	* Termination means cleaning up and freeing all resources,
2007	* the VM itself is, at this point, powered off or suspended.
2008	*
2009	* @returns VBox status code.
2010	* @param pVM The cross context VM structure.
2011	*/
2012	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2013	{
2014	if (pVM->hm.s.vmx.pRealModeTSS)
2015	{
2016	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2017	pVM->hm.s.vmx.pRealModeTSS = 0;
2018	}
2019	hmR3TermCPU(pVM);
2020	return 0;
2021	}
2022
2023
2024	/**
2025	* Terminates the per-VCPU HM.
2026	*
2027	* @returns VBox status code.
2028	* @param pVM The cross context VM structure.
2029	*/
2030	static int hmR3TermCPU(PVM pVM)
2031	{
2032	RT_NOREF(pVM);
2033	return VINF_SUCCESS;
2034	}
2035
2036
2037	/**
2038	* Resets a virtual CPU.
2039	*
2040	* Used by HMR3Reset and CPU hot plugging.
2041	*
2042	* @param pVCpu The cross context virtual CPU structure to reset.
2043	*/
2044	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2045	{
2046	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
2047	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2048	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2049
2050	pVCpu->hm.s.fActive = false;
2051	pVCpu->hm.s.Event.fPending = false;
2052	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2053	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2054	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2055	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2056	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2057	#endif
2058	}
2059
2060
2061	/**
2062	* The VM is being reset.
2063	*
2064	* For the HM component this means that any GDT/LDT/TSS monitors
2065	* needs to be removed.
2066	*
2067	* @param pVM The cross context VM structure.
2068	*/
2069	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2070	{
2071	LogFlow(("HMR3Reset:\n"));
2072
2073	if (HMIsEnabled(pVM))
2074	hmR3DisableRawMode(pVM);
2075
2076	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2077	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2078
2079	/* Clear all patch information. */
2080	pVM->hm.s.pGuestPatchMem = 0;
2081	pVM->hm.s.pFreeGuestPatchMem = 0;
2082	pVM->hm.s.cbGuestPatchMem = 0;
2083	pVM->hm.s.cPatches = 0;
2084	pVM->hm.s.PatchTree = 0;
2085	pVM->hm.s.fTprPatchingActive = false;
2086	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2087	}
2088
2089
2090	/**
2091	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2092	*
2093	* @returns VBox strict status code.
2094	* @param pVM The cross context VM structure.
2095	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2096	* @param pvUser Unused.
2097	*/
2098	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2099	{
2100	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2101
2102	/* Only execute the handler on the VCPU the original patch request was issued. */
2103	if (pVCpu->idCpu != idCpu)
2104	return VINF_SUCCESS;
2105
2106	Log(("hmR3RemovePatches\n"));
2107	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2108	{
2109	uint8_t abInstr[15];
2110	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2111	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2112	int rc;
2113
2114	#ifdef LOG_ENABLED
2115	char szOutput[256];
2116	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2117	szOutput, sizeof(szOutput), NULL);
2118	if (RT_SUCCESS(rc))
2119	Log(("Patched instr: %s\n", szOutput));
2120	#endif
2121
2122	/* Check if the instruction is still the same. */
2123	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2124	if (rc != VINF_SUCCESS)
2125	{
2126	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2127	continue; /* swapped out or otherwise removed; skip it. */
2128	}
2129
2130	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2131	{
2132	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2133	continue; /* skip it. */
2134	}
2135
2136	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2137	AssertRC(rc);
2138
2139	#ifdef LOG_ENABLED
2140	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2141	szOutput, sizeof(szOutput), NULL);
2142	if (RT_SUCCESS(rc))
2143	Log(("Original instr: %s\n", szOutput));
2144	#endif
2145	}
2146	pVM->hm.s.cPatches = 0;
2147	pVM->hm.s.PatchTree = 0;
2148	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2149	pVM->hm.s.fTprPatchingActive = false;
2150	return VINF_SUCCESS;
2151	}
2152
2153
2154	/**
2155	* Worker for enabling patching in a VT-x/AMD-V guest.
2156	*
2157	* @returns VBox status code.
2158	* @param pVM The cross context VM structure.
2159	* @param idCpu VCPU to execute hmR3RemovePatches on.
2160	* @param pPatchMem Patch memory range.
2161	* @param cbPatchMem Size of the memory range.
2162	*/
2163	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2164	{
2165	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2166	AssertRC(rc);
2167
2168	pVM->hm.s.pGuestPatchMem = pPatchMem;
2169	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2170	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2171	return VINF_SUCCESS;
2172	}
2173
2174
2175	/**
2176	* Enable patching in a VT-x/AMD-V guest
2177	*
2178	* @returns VBox status code.
2179	* @param pVM The cross context VM structure.
2180	* @param pPatchMem Patch memory range.
2181	* @param cbPatchMem Size of the memory range.
2182	*/
2183	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2184	{
2185	VM_ASSERT_EMT(pVM);
2186	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2187	if (pVM->cCpus > 1)
2188	{
2189	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2190	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2191	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2192	AssertRC(rc);
2193	return rc;
2194	}
2195	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2196	}
2197
2198
2199	/**
2200	* Disable patching in a VT-x/AMD-V guest.
2201	*
2202	* @returns VBox status code.
2203	* @param pVM The cross context VM structure.
2204	* @param pPatchMem Patch memory range.
2205	* @param cbPatchMem Size of the memory range.
2206	*/
2207	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2208	{
2209	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2210	RT_NOREF2(pPatchMem, cbPatchMem);
2211
2212	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2213	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2214
2215	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2216	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2217	(void *)(uintptr_t)VMMGetCpuId(pVM));
2218	AssertRC(rc);
2219
2220	pVM->hm.s.pGuestPatchMem = 0;
2221	pVM->hm.s.pFreeGuestPatchMem = 0;
2222	pVM->hm.s.cbGuestPatchMem = 0;
2223	pVM->hm.s.fTprPatchingActive = false;
2224	return VINF_SUCCESS;
2225	}
2226
2227
2228	/**
2229	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2230	*
2231	* @returns VBox strict status code.
2232	* @param pVM The cross context VM structure.
2233	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2234	* @param pvUser User specified CPU context.
2235	*
2236	*/
2237	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2238	{
2239	/*
2240	* Only execute the handler on the VCPU the original patch request was
2241	* issued. (The other CPU(s) might not yet have switched to protected
2242	* mode, nor have the correct memory context.)
2243	*/
2244	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2245	if (pVCpu->idCpu != idCpu)
2246	return VINF_SUCCESS;
2247
2248	/*
2249	* We're racing other VCPUs here, so don't try patch the instruction twice
2250	* and make sure there is still room for our patch record.
2251	*/
2252	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2253	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2254	if (pPatch)
2255	{
2256	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2257	return VINF_SUCCESS;
2258	}
2259	uint32_t const idx = pVM->hm.s.cPatches;
2260	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2261	{
2262	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2263	return VINF_SUCCESS;
2264	}
2265	pPatch = &pVM->hm.s.aPatches[idx];
2266
2267	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2268
2269	/*
2270	* Disassembler the instruction and get cracking.
2271	*/
2272	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2273	DISCPUSTATE Dis;
2274	uint32_t cbOp;
2275	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2276	AssertRC(rc);
2277	if ( rc == VINF_SUCCESS
2278	&& Dis.pCurInstr->uOpcode == OP_MOV
2279	&& cbOp >= 3)
2280	{
2281	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2282
2283	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2284	AssertRC(rc);
2285
2286	pPatch->cbOp = cbOp;
2287
2288	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2289	{
2290	/* write. */
2291	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2292	{
2293	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2294	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2295	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2296	}
2297	else
2298	{
2299	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2300	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2301	pPatch->uSrcOperand = Dis.Param2.uValue;
2302	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2303	}
2304	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2305	AssertRC(rc);
2306
2307	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2308	pPatch->cbNewOp = sizeof(s_abVMMCall);
2309	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2310	}
2311	else
2312	{
2313	/*
2314	* TPR Read.
2315	*
2316	* Found:
2317	* mov eax, dword [fffe0080] (5 bytes)
2318	* Check if next instruction is:
2319	* shr eax, 4
2320	*/
2321	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2322
2323	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2324	uint8_t const cbOpMmio = cbOp;
2325	uint64_t const uSavedRip = pCtx->rip;
2326
2327	pCtx->rip += cbOp;
2328	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2329	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2330	pCtx->rip = uSavedRip;
2331
2332	if ( rc == VINF_SUCCESS
2333	&& Dis.pCurInstr->uOpcode == OP_SHR
2334	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2335	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2336	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2337	&& Dis.Param2.uValue == 4
2338	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2339	{
2340	uint8_t abInstr[15];
2341
2342	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2343	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2344	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2345	AssertRC(rc);
2346
2347	pPatch->cbOp = cbOpMmio + cbOp;
2348
2349	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2350	abInstr[0] = 0xf0;
2351	abInstr[1] = 0x0f;
2352	abInstr[2] = 0x20;
2353	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2354	for (unsigned i = 4; i < pPatch->cbOp; i++)
2355	abInstr[i] = 0x90; /* nop */
2356
2357	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2358	AssertRC(rc);
2359
2360	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2361	pPatch->cbNewOp = pPatch->cbOp;
2362	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2363
2364	Log(("Acceptable read/shr candidate!\n"));
2365	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2366	}
2367	else
2368	{
2369	pPatch->enmType = HMTPRINSTR_READ;
2370	pPatch->uDstOperand = idxMmioReg;
2371
2372	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2373	AssertRC(rc);
2374
2375	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2376	pPatch->cbNewOp = sizeof(s_abVMMCall);
2377	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2378	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2379	}
2380	}
2381
2382	pPatch->Core.Key = pCtx->eip;
2383	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2384	AssertRC(rc);
2385
2386	pVM->hm.s.cPatches++;
2387	return VINF_SUCCESS;
2388	}
2389
2390	/*
2391	* Save invalid patch, so we will not try again.
2392	*/
2393	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2394	pPatch->Core.Key = pCtx->eip;
2395	pPatch->enmType = HMTPRINSTR_INVALID;
2396	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2397	AssertRC(rc);
2398	pVM->hm.s.cPatches++;
2399	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2400	return VINF_SUCCESS;
2401	}
2402
2403
2404	/**
2405	* Callback to patch a TPR instruction (jump to generated code).
2406	*
2407	* @returns VBox strict status code.
2408	* @param pVM The cross context VM structure.
2409	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2410	* @param pvUser User specified CPU context.
2411	*
2412	*/
2413	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2414	{
2415	/*
2416	* Only execute the handler on the VCPU the original patch request was
2417	* issued. (The other CPU(s) might not yet have switched to protected
2418	* mode, nor have the correct memory context.)
2419	*/
2420	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2421	if (pVCpu->idCpu != idCpu)
2422	return VINF_SUCCESS;
2423
2424	/*
2425	* We're racing other VCPUs here, so don't try patch the instruction twice
2426	* and make sure there is still room for our patch record.
2427	*/
2428	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2429	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2430	if (pPatch)
2431	{
2432	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2433	return VINF_SUCCESS;
2434	}
2435	uint32_t const idx = pVM->hm.s.cPatches;
2436	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2437	{
2438	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2439	return VINF_SUCCESS;
2440	}
2441	pPatch = &pVM->hm.s.aPatches[idx];
2442
2443	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2444	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2445
2446	/*
2447	* Disassemble the instruction and get cracking.
2448	*/
2449	DISCPUSTATE Dis;
2450	uint32_t cbOp;
2451	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2452	AssertRC(rc);
2453	if ( rc == VINF_SUCCESS
2454	&& Dis.pCurInstr->uOpcode == OP_MOV
2455	&& cbOp >= 5)
2456	{
2457	uint8_t aPatch[64];
2458	uint32_t off = 0;
2459
2460	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2461	AssertRC(rc);
2462
2463	pPatch->cbOp = cbOp;
2464	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2465
2466	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2467	{
2468	/*
2469	* TPR write:
2470	*
2471	* push ECX [51]
2472	* push EDX [52]
2473	* push EAX [50]
2474	* xor EDX,EDX [31 D2]
2475	* mov EAX,EAX [89 C0]
2476	* or
2477	* mov EAX,0000000CCh [B8 CC 00 00 00]
2478	* mov ECX,0C0000082h [B9 82 00 00 C0]
2479	* wrmsr [0F 30]
2480	* pop EAX [58]
2481	* pop EDX [5A]
2482	* pop ECX [59]
2483	* jmp return_address [E9 return_address]
2484	*/
2485	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2486
2487	aPatch[off++] = 0x51; /* push ecx */
2488	aPatch[off++] = 0x52; /* push edx */
2489	if (!fUsesEax)
2490	aPatch[off++] = 0x50; /* push eax */
2491	aPatch[off++] = 0x31; /* xor edx, edx */
2492	aPatch[off++] = 0xd2;
2493	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2494	{
2495	if (!fUsesEax)
2496	{
2497	aPatch[off++] = 0x89; /* mov eax, src_reg */
2498	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2499	}
2500	}
2501	else
2502	{
2503	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2504	aPatch[off++] = 0xb8; /* mov eax, immediate */
2505	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2506	off += sizeof(uint32_t);
2507	}
2508	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2509	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2510	off += sizeof(uint32_t);
2511
2512	aPatch[off++] = 0x0f; /* wrmsr */
2513	aPatch[off++] = 0x30;
2514	if (!fUsesEax)
2515	aPatch[off++] = 0x58; /* pop eax */
2516	aPatch[off++] = 0x5a; /* pop edx */
2517	aPatch[off++] = 0x59; /* pop ecx */
2518	}
2519	else
2520	{
2521	/*
2522	* TPR read:
2523	*
2524	* push ECX [51]
2525	* push EDX [52]
2526	* push EAX [50]
2527	* mov ECX,0C0000082h [B9 82 00 00 C0]
2528	* rdmsr [0F 32]
2529	* mov EAX,EAX [89 C0]
2530	* pop EAX [58]
2531	* pop EDX [5A]
2532	* pop ECX [59]
2533	* jmp return_address [E9 return_address]
2534	*/
2535	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2536
2537	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2538	aPatch[off++] = 0x51; /* push ecx */
2539	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2540	aPatch[off++] = 0x52; /* push edx */
2541	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2542	aPatch[off++] = 0x50; /* push eax */
2543
2544	aPatch[off++] = 0x31; /* xor edx, edx */
2545	aPatch[off++] = 0xd2;
2546
2547	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2548	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2549	off += sizeof(uint32_t);
2550
2551	aPatch[off++] = 0x0f; /* rdmsr */
2552	aPatch[off++] = 0x32;
2553
2554	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2555	{
2556	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2557	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2558	}
2559
2560	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2561	aPatch[off++] = 0x58; /* pop eax */
2562	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2563	aPatch[off++] = 0x5a; /* pop edx */
2564	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2565	aPatch[off++] = 0x59; /* pop ecx */
2566	}
2567	aPatch[off++] = 0xe9; /* jmp return_address */
2568	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2569	off += sizeof(RTRCUINTPTR);
2570
2571	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2572	{
2573	/* Write new code to the patch buffer. */
2574	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2575	AssertRC(rc);
2576
2577	#ifdef LOG_ENABLED
2578	uint32_t cbCurInstr;
2579	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2580	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2581	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2582	{
2583	char szOutput[256];
2584	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2585	szOutput, sizeof(szOutput), &cbCurInstr);
2586	if (RT_SUCCESS(rc))
2587	Log(("Patch instr %s\n", szOutput));
2588	else
2589	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2590	}
2591	#endif
2592
2593	pPatch->aNewOpcode[0] = 0xE9;
2594	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2595
2596	/* Overwrite the TPR instruction with a jump. */
2597	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2598	AssertRC(rc);
2599
2600	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2601
2602	pVM->hm.s.pFreeGuestPatchMem += off;
2603	pPatch->cbNewOp = 5;
2604
2605	pPatch->Core.Key = pCtx->eip;
2606	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2607	AssertRC(rc);
2608
2609	pVM->hm.s.cPatches++;
2610	pVM->hm.s.fTprPatchingActive = true;
2611	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2612	return VINF_SUCCESS;
2613	}
2614
2615	Log(("Ran out of space in our patch buffer!\n"));
2616	}
2617	else
2618	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2619
2620
2621	/*
2622	* Save invalid patch, so we will not try again.
2623	*/
2624	pPatch = &pVM->hm.s.aPatches[idx];
2625	pPatch->Core.Key = pCtx->eip;
2626	pPatch->enmType = HMTPRINSTR_INVALID;
2627	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2628	AssertRC(rc);
2629	pVM->hm.s.cPatches++;
2630	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2631	return VINF_SUCCESS;
2632	}
2633
2634
2635	/**
2636	* Attempt to patch TPR mmio instructions.
2637	*
2638	* @returns VBox status code.
2639	* @param pVM The cross context VM structure.
2640	* @param pVCpu The cross context virtual CPU structure.
2641	*/
2642	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2643	{
2644	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2645	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2646	(void *)(uintptr_t)pVCpu->idCpu);
2647	AssertRC(rc);
2648	return rc;
2649	}
2650
2651
2652	/**
2653	* Checks if we need to reschedule due to VMM device heap changes.
2654	*
2655	* @returns true if a reschedule is required, otherwise false.
2656	* @param pVM The cross context VM structure.
2657	* @param pCtx VM execution context.
2658	*/
2659	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2660	{
2661	/*
2662	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2663	* when the unrestricted guest execution feature is missing (VT-x only).
2664	*/
2665	if ( pVM->hm.s.vmx.fEnabled
2666	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2667	&& CPUMIsGuestInRealModeEx(pCtx)
2668	&& !PDMVmmDevHeapIsEnabled(pVM))
2669	return true;
2670
2671	return false;
2672	}
2673
2674
2675	/**
2676	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2677	* event settings changes.
2678	*
2679	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2680	* function is just updating the VM globals.
2681	*
2682	* @param pVM The VM cross context VM structure.
2683	* @thread EMT(0)
2684	*/
2685	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2686	{
2687	/* Interrupts. */
2688	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2689	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2690
2691	/* CPU Exceptions. */
2692	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2693	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2694	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2695	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2696
2697	/* Common VM exits. */
2698	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2699	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2700	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2701	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2702
2703	/* Vendor specific VM exits. */
2704	if (HMR3IsVmxEnabled(pVM->pUVM))
2705	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2706	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2707	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2708	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2709	else
2710	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2711	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2712	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2713	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2714
2715	/* Done. */
2716	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2717	}
2718
2719
2720	/**
2721	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2722	*
2723	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2724	* per CPU settings.
2725	*
2726	* @param pVM The VM cross context VM structure.
2727	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2728	*/
2729	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2730	{
2731	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2732	}
2733
2734
2735	/**
2736	* Checks if we are currently using hardware acceleration.
2737	*
2738	* @returns true if hardware acceleration is being used, otherwise false.
2739	* @param pVCpu The cross context virtual CPU structure.
2740	*/
2741	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2742	{
2743	return pVCpu->hm.s.fActive;
2744	}
2745
2746
2747	/**
2748	* External interface for querying whether hardware acceleration is enabled.
2749	*
2750	* @returns true if VT-x or AMD-V is being used, otherwise false.
2751	* @param pUVM The user mode VM handle.
2752	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2753	*/
2754	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2755	{
2756	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2757	PVM pVM = pUVM->pVM;
2758	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2759	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2760	}
2761
2762
2763	/**
2764	* External interface for querying whether VT-x is being used.
2765	*
2766	* @returns true if VT-x is being used, otherwise false.
2767	* @param pUVM The user mode VM handle.
2768	* @sa HMR3IsSvmEnabled, HMIsEnabled
2769	*/
2770	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2771	{
2772	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2773	PVM pVM = pUVM->pVM;
2774	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2775	return pVM->hm.s.vmx.fEnabled
2776	&& pVM->hm.s.vmx.fSupported
2777	&& pVM->fHMEnabled;
2778	}
2779
2780
2781	/**
2782	* External interface for querying whether AMD-V is being used.
2783	*
2784	* @returns true if VT-x is being used, otherwise false.
2785	* @param pUVM The user mode VM handle.
2786	* @sa HMR3IsVmxEnabled, HMIsEnabled
2787	*/
2788	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2789	{
2790	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2791	PVM pVM = pUVM->pVM;
2792	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2793	return pVM->hm.s.svm.fEnabled
2794	&& pVM->hm.s.svm.fSupported
2795	&& pVM->fHMEnabled;
2796	}
2797
2798
2799	/**
2800	* Checks if we are currently using nested paging.
2801	*
2802	* @returns true if nested paging is being used, otherwise false.
2803	* @param pUVM The user mode VM handle.
2804	*/
2805	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2806	{
2807	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2808	PVM pVM = pUVM->pVM;
2809	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2810	return pVM->hm.s.fNestedPagingCfg;
2811	}
2812
2813
2814	/**
2815	* Checks if virtualized APIC registers are enabled.
2816	*
2817	* When enabled this feature allows the hardware to access most of the
2818	* APIC registers in the virtual-APIC page without causing VM-exits. See
2819	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2820	*
2821	* @returns true if virtualized APIC registers is enabled, otherwise
2822	* false.
2823	* @param pUVM The user mode VM handle.
2824	*/
2825	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2826	{
2827	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2828	PVM pVM = pUVM->pVM;
2829	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2830	return pVM->hm.s.fVirtApicRegs;
2831	}
2832
2833
2834	/**
2835	* Checks if APIC posted-interrupt processing is enabled.
2836	*
2837	* This returns whether we can deliver interrupts to the guest without
2838	* leaving guest-context by updating APIC state from host-context.
2839	*
2840	* @returns true if APIC posted-interrupt processing is enabled,
2841	* otherwise false.
2842	* @param pUVM The user mode VM handle.
2843	*/
2844	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2845	{
2846	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2847	PVM pVM = pUVM->pVM;
2848	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2849	return pVM->hm.s.fPostedIntrs;
2850	}
2851
2852
2853	/**
2854	* Checks if we are currently using VPID in VT-x mode.
2855	*
2856	* @returns true if VPID is being used, otherwise false.
2857	* @param pUVM The user mode VM handle.
2858	*/
2859	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2860	{
2861	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2862	PVM pVM = pUVM->pVM;
2863	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2864	return pVM->hm.s.ForR3.vmx.fVpid;
2865	}
2866
2867
2868	/**
2869	* Checks if we are currently using VT-x unrestricted execution,
2870	* aka UX.
2871	*
2872	* @returns true if UX is being used, otherwise false.
2873	* @param pUVM The user mode VM handle.
2874	*/
2875	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2876	{
2877	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2878	PVM pVM = pUVM->pVM;
2879	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2880	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2881	\|\| pVM->hm.s.svm.fSupported;
2882	}
2883
2884
2885	/**
2886	* Checks if the VMX-preemption timer is being used.
2887	*
2888	* @returns true if the VMX-preemption timer is being used, otherwise false.
2889	* @param pVM The cross context VM structure.
2890	*/
2891	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2892	{
2893	return HMIsEnabled(pVM)
2894	&& pVM->hm.s.vmx.fEnabled
2895	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2896	}
2897
2898
2899	#ifdef TODO_9217_VMCSINFO
2900	/**
2901	* Helper for HMR3CheckError to log VMCS controls to the release log.
2902	*
2903	* @param idCpu The Virtual CPU ID.
2904	* @param pVmcsInfo The VMCS info. object.
2905	*/
2906	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2907	{
2908	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2909	{
2910	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2916	}
2917	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2918	{
2919	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2924	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2925	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2926	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2927	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2940	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2941	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2942	}
2943	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2944	{
2945	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2958	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2959	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2960	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2961	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2962	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2963	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2964	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2965	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2966	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2967	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2968	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2969	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2970	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2971	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2972	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2973	}
2974	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2975	{
2976	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2977	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2978	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2979	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2980	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2981	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2982	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2983	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2984	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2985	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2986	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2987	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2988	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2989	}
2990	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2991	{
2992	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2993	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2994	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2995	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2996	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2997	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2998	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2999	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3000	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3001	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3002	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
3003	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
3004	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
3005	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
3006	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
3007	}
3008	}
3009	#endif
3010
3011
3012	/**
3013	* Check fatal VT-x/AMD-V error and produce some meaningful
3014	* log release message.
3015	*
3016	* @param pVM The cross context VM structure.
3017	* @param iStatusCode VBox status code.
3018	*/
3019	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3020	{
3021	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3022	{
3023	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3024	* might be getting inaccurate values for non-guru'ing EMTs. */
3025	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3026	#ifdef TODO_9217_VMCSINFO
3027	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
3028	#endif
3029	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3030	switch (iStatusCode)
3031	{
3032	case VERR_VMX_INVALID_VMCS_PTR:
3033	{
3034	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3035	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3036	#ifdef TODO_9217_VMCSINFO
3037	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
3038	pVmcsInfo->HCPhysVmcs));
3039	#endif
3040	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
3041	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3042	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3043	break;
3044	}
3045
3046	case VERR_VMX_UNABLE_TO_START_VM:
3047	{
3048	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3049	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3050	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3051	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3052
3053	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3054	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3055	{
3056	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3057	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3058	}
3059	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3060	{
3061	#ifdef TODO_9217_VMCSINFO
3062	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3063	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3064	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3065	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3066	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3067	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3068	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3069	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3070	#endif
3071	}
3072	/** @todo Log VM-entry event injection control fields
3073	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3074	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3075	break;
3076	}
3077
3078	case VERR_VMX_INVALID_GUEST_STATE:
3079	{
3080	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3081	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3082	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3083	#ifdef TODO_9217_VMCSINFO
3084	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3085	#endif
3086	break;
3087	}
3088
3089	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3090	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3091	case VERR_VMX_INVALID_VMXON_PTR:
3092	case VERR_VMX_UNEXPECTED_EXIT:
3093	case VERR_VMX_INVALID_VMCS_FIELD:
3094	case VERR_SVM_UNKNOWN_EXIT:
3095	case VERR_SVM_UNEXPECTED_EXIT:
3096	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3097	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3098	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3099	break;
3100	}
3101	}
3102
3103	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3104	{
3105	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3106	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3107	}
3108	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3109	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3110	}
3111
3112
3113	/**
3114	* Execute state save operation.
3115	*
3116	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3117	* is because we always save the VM state from ring-3 and thus most HM state
3118	* will be re-synced dynamically at runtime and don't need to be part of the VM
3119	* saved state.
3120	*
3121	* @returns VBox status code.
3122	* @param pVM The cross context VM structure.
3123	* @param pSSM SSM operation handle.
3124	*/
3125	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3126	{
3127	Log(("hmR3Save:\n"));
3128
3129	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3130	{
3131	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3132	Assert(!pVCpu->hm.s.Event.fPending);
3133	if (pVM->cpum.ro.GuestFeatures.fSvm)
3134	{
3135	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3136	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3137	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3138	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3139	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3140	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3141	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3142	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3143	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3144	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3145	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3146	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3147	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3148	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3149	}
3150	}
3151
3152	/* Save the guest patch data. */
3153	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3154	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3155	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3156
3157	/* Store all the guest patch records too. */
3158	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3159	if (RT_FAILURE(rc))
3160	return rc;
3161
3162	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3163	{
3164	AssertCompileSize(HMTPRINSTR, 4);
3165	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3166	SSMR3PutU32(pSSM, pPatch->Core.Key);
3167	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3168	SSMR3PutU32(pSSM, pPatch->cbOp);
3169	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3170	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3171	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3172	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3173	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3174	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3175	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3176	if (RT_FAILURE(rc))
3177	return rc;
3178	}
3179
3180	return VINF_SUCCESS;
3181	}
3182
3183
3184	/**
3185	* Execute state load operation.
3186	*
3187	* @returns VBox status code.
3188	* @param pVM The cross context VM structure.
3189	* @param pSSM SSM operation handle.
3190	* @param uVersion Data layout version.
3191	* @param uPass The data pass.
3192	*/
3193	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3194	{
3195	int rc;
3196
3197	LogFlowFunc(("uVersion=%u\n", uVersion));
3198	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3199
3200	/*
3201	* Validate version.
3202	*/
3203	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3204	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3205	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3206	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3207	{
3208	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3209	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3210	}
3211
3212	/*
3213	* Load per-VCPU state.
3214	*/
3215	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3216	{
3217	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3218	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3219	{
3220	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3221	if (pVM->cpum.ro.GuestFeatures.fSvm)
3222	{
3223	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3224	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3225	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3226	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3227	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3228	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3229	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3230	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3231	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3232	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3233	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3234	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3235	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3236	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3237	AssertRCReturn(rc, rc);
3238	}
3239	}
3240	else
3241	{
3242	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3243	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3244	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3245	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3246
3247	/* VMX fWasInRealMode related data. */
3248	uint32_t uDummy;
3249	SSMR3GetU32(pSSM, &uDummy);
3250	SSMR3GetU32(pSSM, &uDummy);
3251	rc = SSMR3GetU32(pSSM, &uDummy);
3252	AssertRCReturn(rc, rc);
3253	}
3254	}
3255
3256	/*
3257	* Load TPR patching data.
3258	*/
3259	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3260	{
3261	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3262	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3263	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3264
3265	/* Fetch all TPR patch records. */
3266	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3267	AssertRCReturn(rc, rc);
3268	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3269	{
3270	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3271	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3272	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3273	SSMR3GetU32(pSSM, &pPatch->cbOp);
3274	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3275	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3276	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3277
3278	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3279	pVM->hm.s.fTprPatchingActive = true;
3280	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3281
3282	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3283	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3284	SSMR3GetU32(pSSM, &pPatch->cFaults);
3285	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3286	AssertRCReturn(rc, rc);
3287
3288	LogFlow(("hmR3Load: patch %d\n", i));
3289	LogFlow(("Key = %x\n", pPatch->Core.Key));
3290	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3291	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3292	LogFlow(("type = %d\n", pPatch->enmType));
3293	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3294	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3295	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3296	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3297
3298	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3299	AssertRCReturn(rc, rc);
3300	}
3301	}
3302
3303	return VINF_SUCCESS;
3304	}
3305
3306
3307	/**
3308	* Displays HM info.
3309	*
3310	* @param pVM The cross context VM structure.
3311	* @param pHlp The info helper functions.
3312	* @param pszArgs Arguments, ignored.
3313	*/
3314	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3315	{
3316	NOREF(pszArgs);
3317	PVMCPU pVCpu = VMMGetCpu(pVM);
3318	if (!pVCpu)
3319	pVCpu = pVM->apCpusR3[0];
3320
3321	if (HMIsEnabled(pVM))
3322	{
3323	if (pVM->hm.s.vmx.fSupported)
3324	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3325	else
3326	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3327	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3328	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3329	if (pVM->hm.s.vmx.fSupported)
3330	{
3331	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3332	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3333	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3334
3335	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3336	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3337	if (fRealOnV86Active)
3338	{
3339	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3340	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3341	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3342	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3343	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3344	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3345	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3346	}
3347	}
3348	}
3349	else
3350	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3351	}
3352
3353
3354	/**
3355	* Displays the HM Last-Branch-Record info. for the guest.
3356	*
3357	* @param pVM The cross context VM structure.
3358	* @param pHlp The info helper functions.
3359	* @param pszArgs Arguments, ignored.
3360	*/
3361	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3362	{
3363	NOREF(pszArgs);
3364	PVMCPU pVCpu = VMMGetCpu(pVM);
3365	if (!pVCpu)
3366	pVCpu = pVM->apCpusR3[0];
3367
3368	if (!HMIsEnabled(pVM))
3369	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3370	else if (HMIsVmxActive(pVM))
3371	{
3372	if (pVM->hm.s.vmx.fLbrCfg)
3373	{
3374	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3375	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3376
3377	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3378	* 0xf should cover everything we support thus far. Fix if necessary
3379	* later. */
3380	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3381	if (idxTopOfStack > cLbrStack)
3382	{
3383	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3384	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3385	return;
3386	}
3387
3388	/*
3389	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3390	*/
3391	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3392	uint32_t idxCurrent = idxTopOfStack;
3393	Assert(idxTopOfStack < cLbrStack);
3394	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3395	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3396	for (;;)
3397	{
3398	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3399	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3400	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3401	else
3402	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3403
3404	idxCurrent = (idxCurrent - 1) % cLbrStack;
3405	if (idxCurrent == idxTopOfStack)
3406	break;
3407	}
3408	}
3409	else
3410	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3411	}
3412	else
3413	{
3414	Assert(HMIsSvmActive(pVM));
3415	/** @todo SVM: LBRs (get them from VMCB if possible). */
3416	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3417	}
3418	}
3419
3420
3421	/**
3422	* Displays the HM pending event.
3423	*
3424	* @param pVM The cross context VM structure.
3425	* @param pHlp The info helper functions.
3426	* @param pszArgs Arguments, ignored.
3427	*/
3428	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3429	{
3430	NOREF(pszArgs);
3431	PVMCPU pVCpu = VMMGetCpu(pVM);
3432	if (!pVCpu)
3433	pVCpu = pVM->apCpusR3[0];
3434
3435	if (HMIsEnabled(pVM))
3436	{
3437	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3438	if (pVCpu->hm.s.Event.fPending)
3439	{
3440	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3441	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3442	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3443	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3444	}
3445	}
3446	else
3447	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3448	}
3449
3450
3451	/**
3452	* Displays the SVM nested-guest VMCB cache.
3453	*
3454	* @param pVM The cross context VM structure.
3455	* @param pHlp The info helper functions.
3456	* @param pszArgs Arguments, ignored.
3457	*/
3458	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3459	{
3460	NOREF(pszArgs);
3461	PVMCPU pVCpu = VMMGetCpu(pVM);
3462	if (!pVCpu)
3463	pVCpu = pVM->apCpusR3[0];
3464
3465	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3466	if ( fSvmEnabled
3467	&& pVM->cpum.ro.GuestFeatures.fSvm)
3468	{
3469	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3470	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3471	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3472	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3473	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3474	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3475	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3476	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3477	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3478	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3479	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3480	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3481	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3482	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3483	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3484	}
3485	else
3486	{
3487	if (!fSvmEnabled)
3488	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3489	else
3490	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3491	}
3492	}
3493

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 93922

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