VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HWACCM.cpp@ 40274

Last change on this file since 40274 was 40274, checked in by vboxsync, 13 years ago

Introduced VBOX_WITH_REM in Config.kmk and the VMM.
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  • Property svn:keywords set to Id
File size: 134.6 KB
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1/* $Id: HWACCM.cpp 40274 2012-02-28 13:17:35Z vboxsync $ */
2/** @file
3 * HWACCM - Intel/AMD VM Hardware Support Manager
4 */
5
6/*
7 * Copyright (C) 2006-2007 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HWACCM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hwacc_vmx.h>
38#include <VBox/vmm/hwacc_svm.h>
39#include "HWACCMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/asm-amd64-x86.h>
48#include <iprt/string.h>
49#include <iprt/env.h>
50#include <iprt/thread.h>
51
52/*******************************************************************************
53* Global Variables *
54*******************************************************************************/
55#ifdef VBOX_WITH_STATISTICS
56# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57# define EXIT_REASON_NIL() NULL
58/** Exit reason descriptions for VT-x, used to describe statistics. */
59static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60{
61 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
62 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
63 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75 EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
76 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98 EXIT_REASON_NIL(),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112 EXIT_REASON_NIL(),
113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117 EXIT_REASON_NIL()
118};
119/** Exit reason descriptions for AMD-V, used to describe statistics. */
120static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121{
122 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264 EXIT_REASON_NIL()
265};
266# undef EXIT_REASON
267# undef EXIT_REASON_NIL
268#endif /* VBOX_WITH_STATISTICS */
269
270/*******************************************************************************
271* Internal Functions *
272*******************************************************************************/
273static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
274static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275static int hwaccmR3InitCPU(PVM pVM);
276static int hwaccmR3InitFinalizeR0(PVM pVM);
277static int hwaccmR3TermCPU(PVM pVM);
278
279
280/**
281 * Initializes the HWACCM.
282 *
283 * @returns VBox status code.
284 * @param pVM The VM to operate on.
285 */
286VMMR3DECL(int) HWACCMR3Init(PVM pVM)
287{
288 LogFlow(("HWACCMR3Init\n"));
289
290 /*
291 * Assert alignment and sizes.
292 */
293 AssertCompileMemberAlignment(VM, hwaccm.s, 32);
294 AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
295
296 /* Some structure checks. */
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313
314 /*
315 * Register the saved state data unit.
316 */
317 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
318 NULL, NULL, NULL,
319 NULL, hwaccmR3Save, NULL,
320 NULL, hwaccmR3Load, NULL);
321 if (RT_FAILURE(rc))
322 return rc;
323
324 /* Misc initialisation. */
325 pVM->hwaccm.s.vmx.fSupported = false;
326 pVM->hwaccm.s.svm.fSupported = false;
327 pVM->hwaccm.s.vmx.fEnabled = false;
328 pVM->hwaccm.s.svm.fEnabled = false;
329
330 pVM->hwaccm.s.fNestedPaging = false;
331 pVM->hwaccm.s.fLargePages = false;
332
333 /* Disabled by default. */
334 pVM->fHWACCMEnabled = false;
335
336 /*
337 * Check CFGM options.
338 */
339 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
340 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
341 /* Nested paging: disabled by default. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
343 AssertRC(rc);
344
345 /* Large pages: disabled by default. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
347 AssertRC(rc);
348
349 /* VT-x VPID: disabled by default. */
350 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
351 AssertRC(rc);
352
353 /* HWACCM support must be explicitely enabled in the configuration file. */
354 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
355 AssertRC(rc);
356
357 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
358 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
359 AssertRC(rc);
360
361#ifdef RT_OS_DARWIN
362 if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
363#else
364 if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
365#endif
366 {
367 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
368 VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
369 return VERR_HWACCM_CONFIG_MISMATCH;
370 }
371
372 if (VMMIsHwVirtExtForced(pVM))
373 pVM->fHWACCMEnabled = true;
374
375#if HC_ARCH_BITS == 32
376 /* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
377 * (To use the default, don't set 64bitEnabled in CFGM.) */
378 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
379 AssertLogRelRCReturn(rc, rc);
380 if (pVM->hwaccm.s.fAllow64BitGuests)
381 {
382# ifdef RT_OS_DARWIN
383 if (!VMMIsHwVirtExtForced(pVM))
384# else
385 if (!pVM->hwaccm.s.fAllowed)
386# endif
387 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
388 }
389#else
390 /* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
391 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
392 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
393 AssertLogRelRCReturn(rc, rc);
394#endif
395
396
397 /** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
398 * or local init each time we wish to execute guest code.
399 *
400 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
401 */
402 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
403#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
404 false
405#else
406 true
407#endif
408 );
409
410 /* Max number of resume loops. */
411 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
412 AssertRC(rc);
413
414 return rc;
415}
416
417/**
418 * Initializes the per-VCPU HWACCM.
419 *
420 * @returns VBox status code.
421 * @param pVM The VM to operate on.
422 */
423static int hwaccmR3InitCPU(PVM pVM)
424{
425 LogFlow(("HWACCMR3InitCPU\n"));
426
427 for (VMCPUID i = 0; i < pVM->cCpus; i++)
428 {
429 PVMCPU pVCpu = &pVM->aCpus[i];
430
431 pVCpu->hwaccm.s.fActive = false;
432 }
433
434#ifdef VBOX_WITH_STATISTICS
435 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
436 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
437 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
438 STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
439
440 /*
441 * Statistics.
442 */
443 for (VMCPUID i = 0; i < pVM->cCpus; i++)
444 {
445 PVMCPU pVCpu = &pVM->aCpus[i];
446 int rc;
447
448 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
449 "/PROF/HWACCM/CPU%d/Poke", i);
450 AssertRC(rc);
451 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
452 "/PROF/HWACCM/CPU%d/PokeWait", i);
453 AssertRC(rc);
454 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
455 "/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
458 "/PROF/HWACCM/CPU%d/SwitchToGC", i);
459 AssertRC(rc);
460 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
461 "/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
462 AssertRC(rc);
463 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
464 "/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
465 AssertRC(rc);
466# if 1 /* temporary for tracking down darwin holdup. */
467 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
468 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
469 AssertRC(rc);
470 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
471 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
472 AssertRC(rc);
473 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
474 "/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
475 AssertRC(rc);
476# endif
477 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
478 "/PROF/HWACCM/CPU%d/InGC", i);
479 AssertRC(rc);
480
481# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
482 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
483 "/PROF/HWACCM/CPU%d/Switcher3264", i);
484 AssertRC(rc);
485# endif
486
487# define HWACCM_REG_COUNTER(a, b) \
488 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
489 AssertRC(rc);
490
491 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
492 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
493 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
494 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
495 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
496 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
497 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
498 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
499 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
500 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
501 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
502 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
503 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
504 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
505 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
506 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
507 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
508 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
509 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
510 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
511 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
512 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
513 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
514 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
515 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
516 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
517 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
518 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
519 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
520 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
521 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
522 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
523 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
524 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
525 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
526 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
527 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
528 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
529
530 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
531 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
532
533 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
534 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
535 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
536
537 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
538 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
539 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
540 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
541 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
542 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
543 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
544 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
545 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
546 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
547 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
548 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
549 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
550
551 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
552 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
553 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
554
555 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
556 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
557 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
558
559 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadMinimal, "/HWACCM/CPU%d/Load/Minimal");
560 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadFull, "/HWACCM/CPU%d/Load/Full");
561
562#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
563 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
564 HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
565#endif
566
567 for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
568 {
569 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
570 "/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
571 AssertRC(rc);
572 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
573 "/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
574 AssertRC(rc);
575 }
576
577#undef HWACCM_REG_COUNTER
578
579 pVCpu->hwaccm.s.paStatExitReason = NULL;
580
581 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
582 AssertRC(rc);
583 if (RT_SUCCESS(rc))
584 {
585 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
586 for (int j=0;j<MAX_EXITREASON_STAT;j++)
587 {
588 if (papszDesc[j])
589 {
590 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
591 papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
592 AssertRC(rc);
593 }
594 }
595 rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
596 AssertRC(rc);
597 }
598 pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
599# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
600 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
601# else
602 Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
603# endif
604
605 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
606 AssertRCReturn(rc, rc);
607 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
608# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
609 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
610# else
611 Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
612# endif
613 for (unsigned j = 0; j < 255; j++)
614 STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
615 (j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
616
617 }
618#endif /* VBOX_WITH_STATISTICS */
619
620#ifdef VBOX_WITH_CRASHDUMP_MAGIC
621 /* Magic marker for searching in crash dumps. */
622 for (VMCPUID i = 0; i < pVM->cCpus; i++)
623 {
624 PVMCPU pVCpu = &pVM->aCpus[i];
625
626 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
627 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
628 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
629 }
630#endif
631 return VINF_SUCCESS;
632}
633
634/**
635 * Called when a init phase has completed.
636 *
637 * @returns VBox status code.
638 * @param pVM The VM.
639 * @param enmWhat The phase that completed.
640 */
641VMMR3_INT_DECL(int) HWACCMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
642{
643 switch (enmWhat)
644 {
645 case VMINITCOMPLETED_RING3:
646 return hwaccmR3InitCPU(pVM);
647 case VMINITCOMPLETED_RING0:
648 return hwaccmR3InitFinalizeR0(pVM);
649 default:
650 return VINF_SUCCESS;
651 }
652}
653
654/**
655 * Turns off normal raw mode features
656 *
657 * @param pVM The VM to operate on.
658 */
659static void hwaccmR3DisableRawMode(PVM pVM)
660{
661 /* Disable PATM & CSAM. */
662 PATMR3AllowPatching(pVM, false);
663 CSAMDisableScanning(pVM);
664
665 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
666 SELMR3DisableMonitoring(pVM);
667 TRPMR3DisableMonitoring(pVM);
668
669 /* Disable the switcher code (safety precaution). */
670 VMMR3DisableSwitcher(pVM);
671
672 /* Disable mapping of the hypervisor into the shadow page table. */
673 PGMR3MappingsDisable(pVM);
674
675 /* Disable the switcher */
676 VMMR3DisableSwitcher(pVM);
677
678 /* Reinit the paging mode to force the new shadow mode. */
679 for (VMCPUID i = 0; i < pVM->cCpus; i++)
680 {
681 PVMCPU pVCpu = &pVM->aCpus[i];
682
683 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
684 }
685}
686
687/**
688 * Initialize VT-x or AMD-V.
689 *
690 * @returns VBox status code.
691 * @param pVM The VM handle.
692 */
693static int hwaccmR3InitFinalizeR0(PVM pVM)
694{
695 int rc;
696
697 /* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
698 * is already using AMD-V.
699 */
700 if ( !pVM->hwaccm.s.vmx.fSupported
701 && !pVM->hwaccm.s.svm.fSupported
702 && pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
703 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
704 {
705 LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
706 pVM->hwaccm.s.svm.fSupported = true;
707 pVM->hwaccm.s.svm.fIgnoreInUseError = true;
708 }
709 else
710 if ( !pVM->hwaccm.s.vmx.fSupported
711 && !pVM->hwaccm.s.svm.fSupported)
712 {
713 LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
714 LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
715
716 if (VMMIsHwVirtExtForced(pVM))
717 {
718 switch (pVM->hwaccm.s.lLastError)
719 {
720 case VERR_VMX_NO_VMX:
721 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
722 case VERR_VMX_IN_VMX_ROOT_MODE:
723 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
724 case VERR_SVM_IN_USE:
725 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
726 case VERR_SVM_NO_SVM:
727 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
728 case VERR_SVM_DISABLED:
729 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
730 default:
731 return pVM->hwaccm.s.lLastError;
732 }
733 }
734 return VINF_SUCCESS;
735 }
736
737 if (pVM->hwaccm.s.vmx.fSupported)
738 {
739 rc = SUPR3QueryVTxSupported();
740 if (RT_FAILURE(rc))
741 {
742#ifdef RT_OS_LINUX
743 LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
744#else
745 LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
746#endif
747 if ( pVM->cCpus > 1
748 || VMMIsHwVirtExtForced(pVM))
749 return rc;
750
751 /* silently fall back to raw mode */
752 return VINF_SUCCESS;
753 }
754 }
755
756 if (!pVM->hwaccm.s.fAllowed)
757 return VINF_SUCCESS; /* nothing to do */
758
759 /* Enable VT-x or AMD-V on all host CPUs. */
760 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
761 if (RT_FAILURE(rc))
762 {
763 LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
764 return rc;
765 }
766 Assert(!pVM->fHWACCMEnabled || VMMIsHwVirtExtForced(pVM));
767
768 pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
769 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
770 if (!pVM->hwaccm.s.fHasIoApic)
771 {
772 Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
773 pVM->hwaccm.s.fTRPPatchingAllowed = false;
774 }
775
776 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
777 if (pVM->hwaccm.s.vmx.fSupported)
778 {
779 Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
780
781 if ( pVM->hwaccm.s.fInitialized == false
782 && pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
783 {
784 uint64_t val;
785 RTGCPHYS GCPhys = 0;
786
787 LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
788 LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
789 LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
790 LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
791 LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
792 LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
793 LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
794 LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
795
796 LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
797 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
798 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
799 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
800 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
801 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
802 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
803 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
804 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
805 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
806 val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
807 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
808 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
809 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
810 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
811 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
812 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
813 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
814 LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
815
816 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
817 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
818 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
819 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
820 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
821 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
822 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
823 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
824 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
825 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
826 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
827 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
828 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
829 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
830 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
831 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
832 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
833 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
834 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
835 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
836 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
837 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
838 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
839 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
840 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
841 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
842 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
843 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
844 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
845 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
846 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
847 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
848 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
849 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
850 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
851 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
852 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
853 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
854 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
855 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
856 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
857 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
858 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
859 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
860
861 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
862 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
863 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
864 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
865 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
866 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
867 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
868 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
869 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
870 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
871 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
872 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
873 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
874 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
875 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
876 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
877 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
878 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
879 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
880 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
881 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
882 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
883 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
884 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
885 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
886 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
887 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
888 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
889 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
890 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
891 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
892 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
893 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
894 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
895 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
896 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
897 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
898 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
899 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
900 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
901 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
902 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
903 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
904
905 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
906 {
907 LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
908 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
909 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
910 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
911 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
912 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
913 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
914 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
915 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
916 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
917 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
918 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
919 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
920 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
921 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
922 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
923 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
924 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
925 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
926 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
927
928 val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
929 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
930 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
931 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
932 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
933 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
934 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT *must* be set\n"));
935 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
936 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
937 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
938 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
939 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
940 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
941 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
942 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
943 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
944 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
945 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
946 LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
947 }
948
949 LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
950 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
951 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
952 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
953 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
954 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
955 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
956 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
957 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
958 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
959 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
960 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
961 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
962 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
963 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
964 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
965 val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
966 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
967 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
968 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
969 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
970 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
971 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
972 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
973 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
974 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
975 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
976 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
977 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
978 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
979 LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
980
981 LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
982 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
983 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
984 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
985 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
986 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
987 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
988 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
989 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
990 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
991 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
992 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
993 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
994 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
995 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
996 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
997 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
998 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
999 val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1000 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1001 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1002 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1003 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
1004 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1005 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
1006 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1007 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1008 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1009 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1010 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1011 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1012 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1013 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1014 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1015 LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1016
1017 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
1018 {
1019 LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
1020
1021 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
1022 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
1023 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
1024 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1025 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1026 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1027 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1028 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1029 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1030 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1031 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1032 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1033 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1034 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1035 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1036 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1037 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1038 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1039 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1040 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1041 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1042 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1043 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1044 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1045 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1046 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1047 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1048 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1049 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1050 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1051 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1052 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1053 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1054 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1055 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1056 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1057 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV)
1058 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_INDIV\n"));
1059 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT)
1060 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_CONTEXT\n"));
1061 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL)
1062 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL\n"));
1063 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1064 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1065 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV)
1066 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV\n"));
1067 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT)
1068 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT\n"));
1069 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL)
1070 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL\n"));
1071 if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL)
1072 LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_CONTEXT_GLOBAL\n"));
1073 }
1074
1075 LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1076 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc) == pVM->hwaccm.s.vmx.cPreemptTimerShift)
1077 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1078 else
1079 LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift));
1080 LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1081 LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1082 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1083 LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1084
1085 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1086 LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1087 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1088 LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1089 LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1090
1091 LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1092
1093 /* Paranoia */
1094 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1095
1096 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1097 {
1098 LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1099 LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
1100 }
1101
1102#ifdef HWACCM_VTX_WITH_EPT
1103 if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1104 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1105#endif /* HWACCM_VTX_WITH_EPT */
1106#ifdef HWACCM_VTX_WITH_VPID
1107 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1108 && !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1109 pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1110#endif /* HWACCM_VTX_WITH_VPID */
1111
1112 /* Unrestricted guest execution relies on EPT. */
1113 if ( pVM->hwaccm.s.fNestedPaging
1114 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1115 {
1116 pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1117 }
1118
1119 /* Only try once. */
1120 pVM->hwaccm.s.fInitialized = true;
1121
1122 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1123 {
1124 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1125 rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1126 if (RT_SUCCESS(rc))
1127 {
1128 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1129 ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1130 pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1131 /* Bit set to 0 means redirection enabled. */
1132 memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1133 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1134 memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1135 *((unsigned char *)pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1136
1137 /* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1138 * real and protected mode without paging with EPT.
1139 */
1140 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1141 for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1142 {
1143 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1144 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1145 }
1146
1147 /* We convert it here every time as pci regions could be reconfigured. */
1148 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1149 AssertRC(rc);
1150 LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1151
1152 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1153 AssertRC(rc);
1154 LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1155 }
1156 else
1157 {
1158 LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1159 pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1160 pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1161 }
1162 }
1163
1164 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1165 AssertRC(rc);
1166 if (rc == VINF_SUCCESS)
1167 {
1168 pVM->fHWACCMEnabled = true;
1169 pVM->hwaccm.s.vmx.fEnabled = true;
1170 hwaccmR3DisableRawMode(pVM);
1171
1172 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1173#ifdef VBOX_ENABLE_64_BITS_GUESTS
1174 if (pVM->hwaccm.s.fAllow64BitGuests)
1175 {
1176 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1177 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1178 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1179 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1180 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1181 }
1182 else
1183 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1184 /* Todo: this needs to be fixed properly!! */
1185 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1186 && (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1187 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1188
1189 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1190 ? "HWACCM: 32-bit and 64-bit guests supported.\n"
1191 : "HWACCM: 32-bit guests supported.\n"));
1192#else
1193 LogRel(("HWACCM: 32-bit guests supported.\n"));
1194#endif
1195 LogRel(("HWACCM: VMX enabled!\n"));
1196 if (pVM->hwaccm.s.fNestedPaging)
1197 {
1198 LogRel(("HWACCM: Enabled nested paging\n"));
1199 LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1200 if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1201 LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1202
1203#if HC_ARCH_BITS == 64
1204 if (pVM->hwaccm.s.fLargePages)
1205 {
1206 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1207 PGMSetLargePageUsage(pVM, true);
1208 LogRel(("HWACCM: Large page support enabled!\n"));
1209 }
1210#endif
1211 }
1212 else
1213 Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1214
1215 if (pVM->hwaccm.s.vmx.fVPID)
1216 LogRel(("HWACCM: Enabled VPID\n"));
1217
1218 if ( pVM->hwaccm.s.fNestedPaging
1219 || pVM->hwaccm.s.vmx.fVPID)
1220 {
1221 LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1222 LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1223 }
1224
1225 /* TPR patching status logging. */
1226 if (pVM->hwaccm.s.fTRPPatchingAllowed)
1227 {
1228 if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1229 && (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1230 {
1231 pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1232 LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1233 }
1234 else
1235 {
1236 uint32_t u32Eax, u32Dummy;
1237
1238 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1239 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1240 if ( u32Eax < 0x80000001
1241 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1242 {
1243 pVM->hwaccm.s.fTRPPatchingAllowed = false;
1244 LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1245 }
1246 }
1247 }
1248 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1249
1250 /*
1251 * Check for preemption timer config override and log the state of it.
1252 */
1253 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1254 {
1255 PCFGMNODE pCfgHwAccM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWACCM");
1256 int rc2 = CFGMR3QueryBoolDef(pCfgHwAccM, "UsePreemptTimer", &pVM->hwaccm.s.vmx.fUsePreemptTimer, true);
1257 AssertLogRelRC(rc2);
1258 }
1259 if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1260 LogRel(("HWACCM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hwaccm.s.vmx.cPreemptTimerShift));
1261 }
1262 else
1263 {
1264 LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1265 LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1266 pVM->fHWACCMEnabled = false;
1267 }
1268 }
1269 }
1270 else
1271 if (pVM->hwaccm.s.svm.fSupported)
1272 {
1273 Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1274
1275 if (pVM->hwaccm.s.fInitialized == false)
1276 {
1277 /* Erratum 170 which requires a forced TLB flush for each world switch:
1278 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1279 *
1280 * All BH-G1/2 and DH-G1/2 models include a fix:
1281 * Athlon X2: 0x6b 1/2
1282 * 0x68 1/2
1283 * Athlon 64: 0x7f 1
1284 * 0x6f 2
1285 * Sempron: 0x7f 1/2
1286 * 0x6f 2
1287 * 0x6c 2
1288 * 0x7c 2
1289 * Turion 64: 0x68 2
1290 *
1291 */
1292 uint32_t u32Dummy;
1293 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1294 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1295 u32BaseFamily= (u32Version >> 8) & 0xf;
1296 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1297 u32Model = ((u32Version >> 4) & 0xf);
1298 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1299 u32Stepping = u32Version & 0xf;
1300 if ( u32Family == 0xf
1301 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1302 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1303 {
1304 LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1305 }
1306
1307 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1308 LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1309 LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1310 LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1311 LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1312 LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1313 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1314 {
1315#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1316 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1317 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1318 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1319 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1320 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1321 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1322 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1323 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1324 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1325 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1326 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1327#undef FLAG_NAME
1328 };
1329 uint32_t fSvmFeatures = pVM->hwaccm.s.svm.u32Features;
1330 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1331 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1332 {
1333 LogRel(("HWACCM: %s\n", s_aSvmFeatures[i].pszName));
1334 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1335 }
1336 if (fSvmFeatures)
1337 for (unsigned iBit = 0; iBit < 32; iBit++)
1338 if (RT_BIT_32(iBit) & fSvmFeatures)
1339 LogRel(("HWACCM: Reserved bit %u\n", iBit));
1340
1341 /* Only try once. */
1342 pVM->hwaccm.s.fInitialized = true;
1343
1344 if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1345 pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1346
1347 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1348 AssertRC(rc);
1349 if (rc == VINF_SUCCESS)
1350 {
1351 pVM->fHWACCMEnabled = true;
1352 pVM->hwaccm.s.svm.fEnabled = true;
1353
1354 if (pVM->hwaccm.s.fNestedPaging)
1355 {
1356 LogRel(("HWACCM: Enabled nested paging\n"));
1357#if HC_ARCH_BITS == 64
1358 if (pVM->hwaccm.s.fLargePages)
1359 {
1360 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1361 PGMSetLargePageUsage(pVM, true);
1362 LogRel(("HWACCM: Large page support enabled!\n"));
1363 }
1364#endif
1365 }
1366
1367 hwaccmR3DisableRawMode(pVM);
1368 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1369 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1370 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1371#ifdef VBOX_ENABLE_64_BITS_GUESTS
1372 if (pVM->hwaccm.s.fAllow64BitGuests)
1373 {
1374 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1375 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1376 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1377 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1378 }
1379 else
1380 /* Turn on NXE if PAE has been enabled. */
1381 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1382 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1383#endif
1384
1385 LogRel((pVM->hwaccm.s.fAllow64BitGuests
1386 ? "HWACCM: 32-bit and 64-bit guest supported.\n"
1387 : "HWACCM: 32-bit guest supported.\n"));
1388
1389 LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1390 }
1391 else
1392 {
1393 pVM->fHWACCMEnabled = false;
1394 }
1395 }
1396 }
1397 if (pVM->fHWACCMEnabled)
1398 LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1399 RTLogRelSetBuffering(fOldBuffered);
1400 return VINF_SUCCESS;
1401}
1402
1403/**
1404 * Applies relocations to data and code managed by this
1405 * component. This function will be called at init and
1406 * whenever the VMM need to relocate it self inside the GC.
1407 *
1408 * @param pVM The VM.
1409 */
1410VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1411{
1412 Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1413
1414 /* Fetch the current paging mode during the relocate callback during state loading. */
1415 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1416 {
1417 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1418 {
1419 PVMCPU pVCpu = &pVM->aCpus[i];
1420
1421 pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1422 Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1423 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1424 }
1425 }
1426#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1427 if (pVM->fHWACCMEnabled)
1428 {
1429 int rc;
1430
1431 switch(PGMGetHostMode(pVM))
1432 {
1433 case PGMMODE_32_BIT:
1434 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1435 break;
1436
1437 case PGMMODE_PAE:
1438 case PGMMODE_PAE_NX:
1439 pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1440 break;
1441
1442 default:
1443 AssertFailed();
1444 break;
1445 }
1446 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1447 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1448
1449 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1450 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1451
1452 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1453 AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1454
1455 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1456 AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1457
1458# ifdef DEBUG
1459 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1460 AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1461# endif
1462 }
1463#endif
1464 return;
1465}
1466
1467/**
1468 * Checks hardware accelerated raw mode is allowed.
1469 *
1470 * @returns boolean
1471 * @param pVM The VM to operate on.
1472 */
1473VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1474{
1475 return pVM->hwaccm.s.fAllowed;
1476}
1477
1478/**
1479 * Notification callback which is called whenever there is a chance that a CR3
1480 * value might have changed.
1481 *
1482 * This is called by PGM.
1483 *
1484 * @param pVM The VM to operate on.
1485 * @param pVCpu The VMCPU to operate on.
1486 * @param enmShadowMode New shadow paging mode.
1487 * @param enmGuestMode New guest paging mode.
1488 */
1489VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1490{
1491 /* Ignore page mode changes during state loading. */
1492 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1493 return;
1494
1495 pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1496
1497 if ( pVM->hwaccm.s.vmx.fEnabled
1498 && pVM->fHWACCMEnabled)
1499 {
1500 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1501 && enmGuestMode >= PGMMODE_PROTECTED)
1502 {
1503 PCPUMCTX pCtx;
1504
1505 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1506
1507 /* After a real mode switch to protected mode we must force
1508 * CPL to 0. Our real mode emulation had to set it to 3.
1509 */
1510 pCtx->ssHid.Attr.n.u2Dpl = 0;
1511 }
1512 }
1513
1514 if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1515 {
1516 /* Keep track of paging mode changes. */
1517 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1518 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1519
1520 /* Did we miss a change, because all code was executed in the recompiler? */
1521 if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1522 {
1523 Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1524 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1525 }
1526 }
1527
1528 /* Reset the contents of the read cache. */
1529 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1530 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1531 pCache->Read.aFieldVal[j] = 0;
1532}
1533
1534/**
1535 * Terminates the HWACCM.
1536 *
1537 * Termination means cleaning up and freeing all resources,
1538 * the VM it self is at this point powered off or suspended.
1539 *
1540 * @returns VBox status code.
1541 * @param pVM The VM to operate on.
1542 */
1543VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1544{
1545 if (pVM->hwaccm.s.vmx.pRealModeTSS)
1546 {
1547 PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1548 pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1549 }
1550 hwaccmR3TermCPU(pVM);
1551 return 0;
1552}
1553
1554/**
1555 * Terminates the per-VCPU HWACCM.
1556 *
1557 * @returns VBox status code.
1558 * @param pVM The VM to operate on.
1559 */
1560static int hwaccmR3TermCPU(PVM pVM)
1561{
1562 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1563 {
1564 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1565
1566#ifdef VBOX_WITH_STATISTICS
1567 if (pVCpu->hwaccm.s.paStatExitReason)
1568 {
1569 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1570 pVCpu->hwaccm.s.paStatExitReason = NULL;
1571 pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1572 }
1573 if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1574 {
1575 MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1576 pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1577 pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1578 }
1579#endif
1580
1581#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1582 memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1583 pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1584 pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1585#endif
1586 }
1587 return 0;
1588}
1589
1590/**
1591 * Resets a virtual CPU.
1592 *
1593 * Used by HWACCMR3Reset and CPU hot plugging.
1594 *
1595 * @param pVCpu The CPU to reset.
1596 */
1597VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1598{
1599 /* On first entry we'll sync everything. */
1600 pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1601
1602 pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1603 pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1604
1605 pVCpu->hwaccm.s.fActive = false;
1606 pVCpu->hwaccm.s.Event.fPending = false;
1607
1608 /* Reset state information for real-mode emulation in VT-x. */
1609 pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1610 pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1611 pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1612
1613 /* Reset the contents of the read cache. */
1614 PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1615 for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1616 pCache->Read.aFieldVal[j] = 0;
1617
1618#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1619 /* Magic marker for searching in crash dumps. */
1620 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1621 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1622#endif
1623}
1624
1625/**
1626 * The VM is being reset.
1627 *
1628 * For the HWACCM component this means that any GDT/LDT/TSS monitors
1629 * needs to be removed.
1630 *
1631 * @param pVM VM handle.
1632 */
1633VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1634{
1635 LogFlow(("HWACCMR3Reset:\n"));
1636
1637 if (pVM->fHWACCMEnabled)
1638 hwaccmR3DisableRawMode(pVM);
1639
1640 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1641 {
1642 PVMCPU pVCpu = &pVM->aCpus[i];
1643
1644 HWACCMR3ResetCpu(pVCpu);
1645 }
1646
1647 /* Clear all patch information. */
1648 pVM->hwaccm.s.pGuestPatchMem = 0;
1649 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1650 pVM->hwaccm.s.cbGuestPatchMem = 0;
1651 pVM->hwaccm.s.cPatches = 0;
1652 pVM->hwaccm.s.PatchTree = 0;
1653 pVM->hwaccm.s.fTPRPatchingActive = false;
1654 ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1655}
1656
1657/**
1658 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1659 *
1660 * @returns VBox strict status code.
1661 * @param pVM The VM handle.
1662 * @param pVCpu The VMCPU for the EMT we're being called on.
1663 * @param pvUser Unused
1664 *
1665 */
1666DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1667{
1668 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1669
1670 /* Only execute the handler on the VCPU the original patch request was issued. */
1671 if (pVCpu->idCpu != idCpu)
1672 return VINF_SUCCESS;
1673
1674 Log(("hwaccmR3RemovePatches\n"));
1675 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1676 {
1677 uint8_t szInstr[15];
1678 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1679 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1680 int rc;
1681
1682#ifdef LOG_ENABLED
1683 char szOutput[256];
1684
1685 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1686 szOutput, sizeof(szOutput), NULL);
1687 if (RT_SUCCESS(rc))
1688 Log(("Patched instr: %s\n", szOutput));
1689#endif
1690
1691 /* Check if the instruction is still the same. */
1692 rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1693 if (rc != VINF_SUCCESS)
1694 {
1695 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1696 continue; /* swapped out or otherwise removed; skip it. */
1697 }
1698
1699 if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1700 {
1701 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1702 continue; /* skip it. */
1703 }
1704
1705 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1706 AssertRC(rc);
1707
1708#ifdef LOG_ENABLED
1709 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1710 szOutput, sizeof(szOutput), NULL);
1711 if (RT_SUCCESS(rc))
1712 Log(("Original instr: %s\n", szOutput));
1713#endif
1714 }
1715 pVM->hwaccm.s.cPatches = 0;
1716 pVM->hwaccm.s.PatchTree = 0;
1717 pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1718 pVM->hwaccm.s.fTPRPatchingActive = false;
1719 return VINF_SUCCESS;
1720}
1721
1722/**
1723 * Enable patching in a VT-x/AMD-V guest
1724 *
1725 * @returns VBox status code.
1726 * @param pVM The VM to operate on.
1727 * @param idCpu VCPU to execute hwaccmR3RemovePatches on
1728 * @param pPatchMem Patch memory range
1729 * @param cbPatchMem Size of the memory range
1730 */
1731int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1732{
1733 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)idCpu);
1734 AssertRC(rc);
1735
1736 pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1737 pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1738 pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1739 return VINF_SUCCESS;
1740}
1741
1742/**
1743 * Enable patching in a VT-x/AMD-V guest
1744 *
1745 * @returns VBox status code.
1746 * @param pVM The VM to operate on.
1747 * @param pPatchMem Patch memory range
1748 * @param cbPatchMem Size of the memory range
1749 */
1750VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1751{
1752 VM_ASSERT_EMT(pVM);
1753 Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1754 if (pVM->cCpus > 1)
1755 {
1756 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1757 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1758 (PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1759 AssertRC(rc);
1760 return rc;
1761 }
1762 return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1763}
1764
1765/**
1766 * Disable patching in a VT-x/AMD-V guest
1767 *
1768 * @returns VBox status code.
1769 * @param pVM The VM to operate on.
1770 * @param pPatchMem Patch memory range
1771 * @param cbPatchMem Size of the memory range
1772 */
1773VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1774{
1775 Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1776
1777 Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1778 Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1779
1780 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1781 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)VMMGetCpuId(pVM));
1782 AssertRC(rc);
1783
1784 pVM->hwaccm.s.pGuestPatchMem = 0;
1785 pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1786 pVM->hwaccm.s.cbGuestPatchMem = 0;
1787 pVM->hwaccm.s.fTPRPatchingActive = false;
1788 return VINF_SUCCESS;
1789}
1790
1791
1792/**
1793 * Callback to patch a TPR instruction (vmmcall or mov cr8)
1794 *
1795 * @returns VBox strict status code.
1796 * @param pVM The VM handle.
1797 * @param pVCpu The VMCPU for the EMT we're being called on.
1798 * @param pvUser User specified CPU context
1799 *
1800 */
1801DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1802{
1803 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1804 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1805 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1806 unsigned cbOp;
1807
1808 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1809 if (pVCpu->idCpu != idCpu)
1810 return VINF_SUCCESS;
1811
1812 Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1813
1814 /* Two or more VCPUs were racing to patch this instruction. */
1815 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1816 if (pPatch)
1817 return VINF_SUCCESS;
1818
1819 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1820
1821 int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1822 AssertRC(rc);
1823 if ( rc == VINF_SUCCESS
1824 && pDis->pCurInstr->opcode == OP_MOV
1825 && cbOp >= 3)
1826 {
1827 uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1828 uint32_t idx = pVM->hwaccm.s.cPatches;
1829
1830 pPatch = &pVM->hwaccm.s.aPatches[idx];
1831
1832 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1833 AssertRC(rc);
1834
1835 pPatch->cbOp = cbOp;
1836
1837 if (pDis->param1.flags == USE_DISPLACEMENT32)
1838 {
1839 /* write. */
1840 if (pDis->param2.flags == USE_REG_GEN32)
1841 {
1842 pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1843 pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1844 }
1845 else
1846 {
1847 Assert(pDis->param2.flags == USE_IMMEDIATE32);
1848 pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1849 pPatch->uSrcOperand = pDis->param2.parval;
1850 }
1851 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1852 AssertRC(rc);
1853
1854 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1855 pPatch->cbNewOp = sizeof(aVMMCall);
1856 }
1857 else
1858 {
1859 RTGCPTR oldrip = pCtx->rip;
1860 uint32_t oldcbOp = cbOp;
1861 uint32_t uMmioReg = pDis->param1.base.reg_gen;
1862
1863 /* read */
1864 Assert(pDis->param1.flags == USE_REG_GEN32);
1865
1866 /* Found:
1867 * mov eax, dword [fffe0080] (5 bytes)
1868 * Check if next instruction is:
1869 * shr eax, 4
1870 */
1871 pCtx->rip += cbOp;
1872 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1873 pCtx->rip = oldrip;
1874 if ( rc == VINF_SUCCESS
1875 && pDis->pCurInstr->opcode == OP_SHR
1876 && pDis->param1.flags == USE_REG_GEN32
1877 && pDis->param1.base.reg_gen == uMmioReg
1878 && pDis->param2.flags == USE_IMMEDIATE8
1879 && pDis->param2.parval == 4
1880 && oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1881 {
1882 uint8_t szInstr[15];
1883
1884 /* Replacing two instructions now. */
1885 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1886 AssertRC(rc);
1887
1888 pPatch->cbOp = oldcbOp + cbOp;
1889
1890 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1891 szInstr[0] = 0xF0;
1892 szInstr[1] = 0x0F;
1893 szInstr[2] = 0x20;
1894 szInstr[3] = 0xC0 | pDis->param1.base.reg_gen;
1895 for (unsigned i = 4; i < pPatch->cbOp; i++)
1896 szInstr[i] = 0x90; /* nop */
1897
1898 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1899 AssertRC(rc);
1900
1901 memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1902 pPatch->cbNewOp = pPatch->cbOp;
1903
1904 Log(("Acceptable read/shr candidate!\n"));
1905 pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1906 }
1907 else
1908 {
1909 pPatch->enmType = HWACCMTPRINSTR_READ;
1910 pPatch->uDstOperand = pDis->param1.base.reg_gen;
1911
1912 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1913 AssertRC(rc);
1914
1915 memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1916 pPatch->cbNewOp = sizeof(aVMMCall);
1917 }
1918 }
1919
1920 pPatch->Core.Key = pCtx->eip;
1921 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1922 AssertRC(rc);
1923
1924 pVM->hwaccm.s.cPatches++;
1925 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1926 return VINF_SUCCESS;
1927 }
1928
1929 /* Save invalid patch, so we will not try again. */
1930 uint32_t idx = pVM->hwaccm.s.cPatches;
1931
1932#ifdef LOG_ENABLED
1933 char szOutput[256];
1934 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1935 szOutput, sizeof(szOutput), NULL);
1936 if (RT_SUCCESS(rc))
1937 Log(("Failed to patch instr: %s\n", szOutput));
1938#endif
1939
1940 pPatch = &pVM->hwaccm.s.aPatches[idx];
1941 pPatch->Core.Key = pCtx->eip;
1942 pPatch->enmType = HWACCMTPRINSTR_INVALID;
1943 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1944 AssertRC(rc);
1945 pVM->hwaccm.s.cPatches++;
1946 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1947 return VINF_SUCCESS;
1948}
1949
1950/**
1951 * Callback to patch a TPR instruction (jump to generated code)
1952 *
1953 * @returns VBox strict status code.
1954 * @param pVM The VM handle.
1955 * @param pVCpu The VMCPU for the EMT we're being called on.
1956 * @param pvUser User specified CPU context
1957 *
1958 */
1959DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1960{
1961 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1962 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1963 PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1964 unsigned cbOp;
1965 int rc;
1966#ifdef LOG_ENABLED
1967 RTGCPTR pInstr;
1968 char szOutput[256];
1969#endif
1970
1971 /* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1972 if (pVCpu->idCpu != idCpu)
1973 return VINF_SUCCESS;
1974
1975 Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1976
1977 /* Two or more VCPUs were racing to patch this instruction. */
1978 PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1979 if (pPatch)
1980 {
1981 Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1982 return VINF_SUCCESS;
1983 }
1984
1985 Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1986
1987 rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1988 AssertRC(rc);
1989 if ( rc == VINF_SUCCESS
1990 && pDis->pCurInstr->opcode == OP_MOV
1991 && cbOp >= 5)
1992 {
1993 uint32_t idx = pVM->hwaccm.s.cPatches;
1994 uint8_t aPatch[64];
1995 uint32_t off = 0;
1996
1997 pPatch = &pVM->hwaccm.s.aPatches[idx];
1998
1999#ifdef LOG_ENABLED
2000 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2001 szOutput, sizeof(szOutput), NULL);
2002 if (RT_SUCCESS(rc))
2003 Log(("Original instr: %s\n", szOutput));
2004#endif
2005
2006 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2007 AssertRC(rc);
2008
2009 pPatch->cbOp = cbOp;
2010 pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
2011
2012 if (pDis->param1.flags == USE_DISPLACEMENT32)
2013 {
2014 /*
2015 * TPR write:
2016 *
2017 * push ECX [51]
2018 * push EDX [52]
2019 * push EAX [50]
2020 * xor EDX,EDX [31 D2]
2021 * mov EAX,EAX [89 C0]
2022 * or
2023 * mov EAX,0000000CCh [B8 CC 00 00 00]
2024 * mov ECX,0C0000082h [B9 82 00 00 C0]
2025 * wrmsr [0F 30]
2026 * pop EAX [58]
2027 * pop EDX [5A]
2028 * pop ECX [59]
2029 * jmp return_address [E9 return_address]
2030 *
2031 */
2032 bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
2033
2034 aPatch[off++] = 0x51; /* push ecx */
2035 aPatch[off++] = 0x52; /* push edx */
2036 if (!fUsesEax)
2037 aPatch[off++] = 0x50; /* push eax */
2038 aPatch[off++] = 0x31; /* xor edx, edx */
2039 aPatch[off++] = 0xD2;
2040 if (pDis->param2.flags == USE_REG_GEN32)
2041 {
2042 if (!fUsesEax)
2043 {
2044 aPatch[off++] = 0x89; /* mov eax, src_reg */
2045 aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
2046 }
2047 }
2048 else
2049 {
2050 Assert(pDis->param2.flags == USE_IMMEDIATE32);
2051 aPatch[off++] = 0xB8; /* mov eax, immediate */
2052 *(uint32_t *)&aPatch[off] = pDis->param2.parval;
2053 off += sizeof(uint32_t);
2054 }
2055 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2056 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2057 off += sizeof(uint32_t);
2058
2059 aPatch[off++] = 0x0F; /* wrmsr */
2060 aPatch[off++] = 0x30;
2061 if (!fUsesEax)
2062 aPatch[off++] = 0x58; /* pop eax */
2063 aPatch[off++] = 0x5A; /* pop edx */
2064 aPatch[off++] = 0x59; /* pop ecx */
2065 }
2066 else
2067 {
2068 /*
2069 * TPR read:
2070 *
2071 * push ECX [51]
2072 * push EDX [52]
2073 * push EAX [50]
2074 * mov ECX,0C0000082h [B9 82 00 00 C0]
2075 * rdmsr [0F 32]
2076 * mov EAX,EAX [89 C0]
2077 * pop EAX [58]
2078 * pop EDX [5A]
2079 * pop ECX [59]
2080 * jmp return_address [E9 return_address]
2081 *
2082 */
2083 Assert(pDis->param1.flags == USE_REG_GEN32);
2084
2085 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2086 aPatch[off++] = 0x51; /* push ecx */
2087 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2088 aPatch[off++] = 0x52; /* push edx */
2089 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2090 aPatch[off++] = 0x50; /* push eax */
2091
2092 aPatch[off++] = 0x31; /* xor edx, edx */
2093 aPatch[off++] = 0xD2;
2094
2095 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2096 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2097 off += sizeof(uint32_t);
2098
2099 aPatch[off++] = 0x0F; /* rdmsr */
2100 aPatch[off++] = 0x32;
2101
2102 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2103 {
2104 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2105 aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2106 }
2107
2108 if (pDis->param1.base.reg_gen != USE_REG_EAX)
2109 aPatch[off++] = 0x58; /* pop eax */
2110 if (pDis->param1.base.reg_gen != USE_REG_EDX)
2111 aPatch[off++] = 0x5A; /* pop edx */
2112 if (pDis->param1.base.reg_gen != USE_REG_ECX)
2113 aPatch[off++] = 0x59; /* pop ecx */
2114 }
2115 aPatch[off++] = 0xE9; /* jmp return_address */
2116 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2117 off += sizeof(RTRCUINTPTR);
2118
2119 if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2120 {
2121 /* Write new code to the patch buffer. */
2122 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2123 AssertRC(rc);
2124
2125#ifdef LOG_ENABLED
2126 pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2127 while (true)
2128 {
2129 uint32_t cb;
2130
2131 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2132 szOutput, sizeof(szOutput), &cb);
2133 if (RT_SUCCESS(rc))
2134 Log(("Patch instr %s\n", szOutput));
2135
2136 pInstr += cb;
2137
2138 if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2139 break;
2140 }
2141#endif
2142
2143 pPatch->aNewOpcode[0] = 0xE9;
2144 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2145
2146 /* Overwrite the TPR instruction with a jump. */
2147 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2148 AssertRC(rc);
2149
2150#ifdef LOG_ENABLED
2151 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2152 szOutput, sizeof(szOutput), NULL);
2153 if (RT_SUCCESS(rc))
2154 Log(("Jump: %s\n", szOutput));
2155#endif
2156 pVM->hwaccm.s.pFreeGuestPatchMem += off;
2157 pPatch->cbNewOp = 5;
2158
2159 pPatch->Core.Key = pCtx->eip;
2160 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2161 AssertRC(rc);
2162
2163 pVM->hwaccm.s.cPatches++;
2164 pVM->hwaccm.s.fTPRPatchingActive = true;
2165 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2166 return VINF_SUCCESS;
2167 }
2168 else
2169 Log(("Ran out of space in our patch buffer!\n"));
2170 }
2171
2172 /* Save invalid patch, so we will not try again. */
2173 uint32_t idx = pVM->hwaccm.s.cPatches;
2174
2175#ifdef LOG_ENABLED
2176 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2177 szOutput, sizeof(szOutput), NULL);
2178 if (RT_SUCCESS(rc))
2179 Log(("Failed to patch instr: %s\n", szOutput));
2180#endif
2181
2182 pPatch = &pVM->hwaccm.s.aPatches[idx];
2183 pPatch->Core.Key = pCtx->eip;
2184 pPatch->enmType = HWACCMTPRINSTR_INVALID;
2185 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2186 AssertRC(rc);
2187 pVM->hwaccm.s.cPatches++;
2188 STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2189 return VINF_SUCCESS;
2190}
2191
2192/**
2193 * Attempt to patch TPR mmio instructions
2194 *
2195 * @returns VBox status code.
2196 * @param pVM The VM to operate on.
2197 * @param pVCpu The VM CPU to operate on.
2198 * @param pCtx CPU context
2199 */
2200VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2201{
2202 NOREF(pCtx);
2203 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2204 pVM->hwaccm.s.pGuestPatchMem ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr,
2205 (void *)(uintptr_t)pVCpu->idCpu);
2206 AssertRC(rc);
2207 return rc;
2208}
2209
2210/**
2211 * Force execution of the current IO code in the recompiler
2212 *
2213 * @returns VBox status code.
2214 * @param pVM The VM to operate on.
2215 * @param pCtx Partial VM execution context
2216 */
2217VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2218{
2219 PVMCPU pVCpu = VMMGetCpu(pVM);
2220
2221 Assert(pVM->fHWACCMEnabled);
2222 Log(("HWACCMR3EmulateIoBlock\n"));
2223
2224 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2225 if (HWACCMCanEmulateIoBlockEx(pCtx))
2226 {
2227 Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2228 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2229 pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2230 pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2231 return VINF_EM_RESCHEDULE_REM;
2232 }
2233 return VINF_SUCCESS;
2234}
2235
2236/**
2237 * Checks if we can currently use hardware accelerated raw mode.
2238 *
2239 * @returns boolean
2240 * @param pVM The VM to operate on.
2241 * @param pCtx Partial VM execution context
2242 */
2243VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2244{
2245 PVMCPU pVCpu = VMMGetCpu(pVM);
2246
2247 Assert(pVM->fHWACCMEnabled);
2248
2249 /* If we're still executing the IO code, then return false. */
2250 if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2251 && pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2252 && pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2253 && pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2254 return false;
2255
2256 pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2257
2258 /* AMD-V supports real & protected mode with or without paging. */
2259 if (pVM->hwaccm.s.svm.fEnabled)
2260 {
2261 pVCpu->hwaccm.s.fActive = true;
2262 return true;
2263 }
2264
2265 pVCpu->hwaccm.s.fActive = false;
2266
2267 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2268 Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) || (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2269
2270 bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2271 if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2272 {
2273 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2274 if (fSupportsRealMode)
2275 {
2276 if (CPUMIsGuestInRealModeEx(pCtx))
2277 {
2278 /* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2279 * The base must also be equal to (sel << 4).
2280 */
2281 if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2282 && pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2283 || pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2284 || pCtx->es != (pCtx->esHid.u64Base >> 4)
2285 || pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2286 || pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2287 || pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2288 {
2289 return false;
2290 }
2291 }
2292 else
2293 {
2294 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2295 /* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2296 * from real to protected mode. (all sorts of RPL & DPL assumptions)
2297 */
2298 if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2299 && enmGuestMode >= PGMMODE_PROTECTED)
2300 {
2301 if ( (pCtx->cs & X86_SEL_RPL)
2302 || (pCtx->ds & X86_SEL_RPL)
2303 || (pCtx->es & X86_SEL_RPL)
2304 || (pCtx->fs & X86_SEL_RPL)
2305 || (pCtx->gs & X86_SEL_RPL)
2306 || (pCtx->ss & X86_SEL_RPL))
2307 {
2308 return false;
2309 }
2310 }
2311 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2312 if ( pCtx->gdtr.cbGdt
2313 && ( pCtx->tr > pCtx->gdtr.cbGdt
2314 || pCtx->ldtr > pCtx->gdtr.cbGdt))
2315 {
2316 return false;
2317 }
2318 }
2319 }
2320 else
2321 {
2322 if ( !CPUMIsGuestInLongModeEx(pCtx)
2323 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2324 {
2325 /** @todo This should (probably) be set on every excursion to the REM,
2326 * however it's too risky right now. So, only apply it when we go
2327 * back to REM for real mode execution. (The XP hack below doesn't
2328 * work reliably without this.)
2329 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2330 pVM->aCpus[0].hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2331
2332 if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2333 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2334 return false;
2335
2336 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2337 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr == 0)
2338 return false;
2339
2340 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2341 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2342 * hidden registers (possible recompiler bug; see load_seg_vm) */
2343 if (pCtx->csHid.Attr.n.u1Present == 0)
2344 return false;
2345 if (pCtx->ssHid.Attr.n.u1Present == 0)
2346 return false;
2347
2348 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2349 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2350 /** @todo This check is actually wrong, it doesn't take the direction of the
2351 * stack segment into account. But, it does the job for now. */
2352 if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2353 return false;
2354 #if 0
2355 if ( pCtx->cs >= pCtx->gdtr.cbGdt
2356 || pCtx->ss >= pCtx->gdtr.cbGdt
2357 || pCtx->ds >= pCtx->gdtr.cbGdt
2358 || pCtx->es >= pCtx->gdtr.cbGdt
2359 || pCtx->fs >= pCtx->gdtr.cbGdt
2360 || pCtx->gs >= pCtx->gdtr.cbGdt)
2361 return false;
2362 #endif
2363 }
2364 }
2365 }
2366
2367 if (pVM->hwaccm.s.vmx.fEnabled)
2368 {
2369 uint32_t mask;
2370
2371 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2372 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2373 /* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2374 mask &= ~X86_CR0_NE;
2375
2376 if (fSupportsRealMode)
2377 {
2378 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2379 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2380 }
2381 else
2382 {
2383 /* We support protected mode without paging using identity mapping. */
2384 mask &= ~X86_CR0_PG;
2385 }
2386 if ((pCtx->cr0 & mask) != mask)
2387 return false;
2388
2389 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2390 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2391 if ((pCtx->cr0 & mask) != 0)
2392 return false;
2393
2394 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2395 mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2396 mask &= ~X86_CR4_VMXE;
2397 if ((pCtx->cr4 & mask) != mask)
2398 return false;
2399
2400 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2401 mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2402 if ((pCtx->cr4 & mask) != 0)
2403 return false;
2404
2405 pVCpu->hwaccm.s.fActive = true;
2406 return true;
2407 }
2408
2409 return false;
2410}
2411
2412/**
2413 * Checks if we need to reschedule due to VMM device heap changes
2414 *
2415 * @returns boolean
2416 * @param pVM The VM to operate on.
2417 * @param pCtx VM execution context
2418 */
2419VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2420{
2421 /** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2422 if ( pVM->hwaccm.s.vmx.fEnabled
2423 && !pVM->hwaccm.s.vmx.fUnrestrictedGuest
2424 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2425 && !PDMVMMDevHeapIsEnabled(pVM)
2426 && (pVM->hwaccm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2427 return true;
2428
2429 return false;
2430}
2431
2432
2433/**
2434 * Notification from EM about a rescheduling into hardware assisted execution
2435 * mode.
2436 *
2437 * @param pVCpu Pointer to the current virtual cpu structure.
2438 */
2439VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2440{
2441 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2442}
2443
2444/**
2445 * Notification from EM about returning from instruction emulation (REM / EM).
2446 *
2447 * @param pVCpu Pointer to the current virtual cpu structure.
2448 */
2449VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2450{
2451 pVCpu->hwaccm.s.fContextUseFlags |= HWACCM_CHANGED_ALL_GUEST;
2452}
2453
2454/**
2455 * Checks if we are currently using hardware accelerated raw mode.
2456 *
2457 * @returns boolean
2458 * @param pVCpu The VMCPU to operate on.
2459 */
2460VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2461{
2462 return pVCpu->hwaccm.s.fActive;
2463}
2464
2465/**
2466 * Checks if we are currently using nested paging.
2467 *
2468 * @returns boolean
2469 * @param pVM The VM to operate on.
2470 */
2471VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2472{
2473 return pVM->hwaccm.s.fNestedPaging;
2474}
2475
2476/**
2477 * Checks if we are currently using VPID in VT-x mode.
2478 *
2479 * @returns boolean
2480 * @param pVM The VM to operate on.
2481 */
2482VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2483{
2484 return pVM->hwaccm.s.vmx.fVPID;
2485}
2486
2487
2488/**
2489 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2490 *
2491 * @returns boolean
2492 * @param pVM The VM to operate on.
2493 */
2494VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2495{
2496 return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2497}
2498
2499/**
2500 * Checks if the VMX-preemption timer is being used.
2501 *
2502 * @returns true if it is, false if it isn't.
2503 * @param pVM The VM handle.
2504 */
2505VMMR3DECL(bool) HWACCMR3IsVmxPreemptionTimerUsed(PVM pVM)
2506{
2507 return HWACCMIsEnabled(pVM)
2508 && pVM->hwaccm.s.vmx.fEnabled
2509 && pVM->hwaccm.s.vmx.fUsePreemptTimer;
2510}
2511
2512/**
2513 * Restart an I/O instruction that was refused in ring-0
2514 *
2515 * @returns Strict VBox status code. Informational status codes other than the one documented
2516 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2517 * @retval VINF_SUCCESS Success.
2518 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2519 * status code must be passed on to EM.
2520 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2521 *
2522 * @param pVM The VM to operate on.
2523 * @param pVCpu The VMCPU to operate on.
2524 * @param pCtx VCPU register context
2525 */
2526VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2527{
2528 HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2529
2530 pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2531
2532 if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2533 || enmType == HWACCMPENDINGIO_INVALID)
2534 return VERR_NOT_FOUND;
2535
2536 VBOXSTRICTRC rcStrict;
2537 switch (enmType)
2538 {
2539 case HWACCMPENDINGIO_PORT_READ:
2540 {
2541 uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2542 uint32_t u32Val = 0;
2543
2544 rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2545 &u32Val,
2546 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2547 if (IOM_SUCCESS(rcStrict))
2548 {
2549 /* Write back to the EAX register. */
2550 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2551 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2552 }
2553 break;
2554 }
2555
2556 case HWACCMPENDINGIO_PORT_WRITE:
2557 rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2558 pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2559 pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2560 if (IOM_SUCCESS(rcStrict))
2561 pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2562 break;
2563
2564 default:
2565 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2566 }
2567
2568 return rcStrict;
2569}
2570
2571/**
2572 * Inject an NMI into a running VM (only VCPU 0!)
2573 *
2574 * @returns boolean
2575 * @param pVM The VM to operate on.
2576 */
2577VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2578{
2579 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2580 return VINF_SUCCESS;
2581}
2582
2583/**
2584 * Check fatal VT-x/AMD-V error and produce some meaningful
2585 * log release message.
2586 *
2587 * @param pVM The VM to operate on.
2588 * @param iStatusCode VBox status code
2589 */
2590VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2591{
2592 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2593 {
2594 switch(iStatusCode)
2595 {
2596 case VERR_VMX_INVALID_VMCS_FIELD:
2597 break;
2598
2599 case VERR_VMX_INVALID_VMCS_PTR:
2600 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
2601 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2602 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2603 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2604 break;
2605
2606 case VERR_VMX_UNABLE_TO_START_VM:
2607 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2608 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2609#if 0 /* @todo dump the current control fields to the release log */
2610 if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2611 {
2612
2613 }
2614#endif
2615 break;
2616
2617 case VERR_VMX_UNABLE_TO_RESUME_VM:
2618 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2619 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2620 break;
2621
2622 case VERR_VMX_INVALID_VMXON_PTR:
2623 break;
2624 }
2625 }
2626}
2627
2628/**
2629 * Execute state save operation.
2630 *
2631 * @returns VBox status code.
2632 * @param pVM VM Handle.
2633 * @param pSSM SSM operation handle.
2634 */
2635static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2636{
2637 int rc;
2638
2639 Log(("hwaccmR3Save:\n"));
2640
2641 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2642 {
2643 /*
2644 * Save the basic bits - fortunately all the other things can be resynced on load.
2645 */
2646 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2647 AssertRCReturn(rc, rc);
2648 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2649 AssertRCReturn(rc, rc);
2650 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2651 AssertRCReturn(rc, rc);
2652
2653 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2654 AssertRCReturn(rc, rc);
2655 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2656 AssertRCReturn(rc, rc);
2657 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2658 AssertRCReturn(rc, rc);
2659 }
2660#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2661 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2662 AssertRCReturn(rc, rc);
2663 rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2664 AssertRCReturn(rc, rc);
2665 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2666 AssertRCReturn(rc, rc);
2667
2668 /* Store all the guest patch records too. */
2669 rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2670 AssertRCReturn(rc, rc);
2671
2672 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2673 {
2674 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2675
2676 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2677 AssertRCReturn(rc, rc);
2678
2679 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2680 AssertRCReturn(rc, rc);
2681
2682 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2683 AssertRCReturn(rc, rc);
2684
2685 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2686 AssertRCReturn(rc, rc);
2687
2688 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2689 AssertRCReturn(rc, rc);
2690
2691 AssertCompileSize(HWACCMTPRINSTR, 4);
2692 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2693 AssertRCReturn(rc, rc);
2694
2695 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2696 AssertRCReturn(rc, rc);
2697
2698 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2699 AssertRCReturn(rc, rc);
2700
2701 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2702 AssertRCReturn(rc, rc);
2703
2704 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2705 AssertRCReturn(rc, rc);
2706 }
2707#endif
2708 return VINF_SUCCESS;
2709}
2710
2711/**
2712 * Execute state load operation.
2713 *
2714 * @returns VBox status code.
2715 * @param pVM VM Handle.
2716 * @param pSSM SSM operation handle.
2717 * @param uVersion Data layout version.
2718 * @param uPass The data pass.
2719 */
2720static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2721{
2722 int rc;
2723
2724 Log(("hwaccmR3Load:\n"));
2725 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2726
2727 /*
2728 * Validate version.
2729 */
2730 if ( uVersion != HWACCM_SSM_VERSION
2731 && uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2732 && uVersion != HWACCM_SSM_VERSION_2_0_X)
2733 {
2734 AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2735 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2736 }
2737 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2738 {
2739 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2740 AssertRCReturn(rc, rc);
2741 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2742 AssertRCReturn(rc, rc);
2743 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2744 AssertRCReturn(rc, rc);
2745
2746 if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2747 {
2748 uint32_t val;
2749
2750 rc = SSMR3GetU32(pSSM, &val);
2751 AssertRCReturn(rc, rc);
2752 pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2753
2754 rc = SSMR3GetU32(pSSM, &val);
2755 AssertRCReturn(rc, rc);
2756 pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2757
2758 rc = SSMR3GetU32(pSSM, &val);
2759 AssertRCReturn(rc, rc);
2760 pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2761 }
2762 }
2763#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2764 if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2765 {
2766 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2767 AssertRCReturn(rc, rc);
2768 rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2769 AssertRCReturn(rc, rc);
2770 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2771 AssertRCReturn(rc, rc);
2772
2773 /* Fetch all TPR patch records. */
2774 rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2775 AssertRCReturn(rc, rc);
2776
2777 for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2778 {
2779 PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2780
2781 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2782 AssertRCReturn(rc, rc);
2783
2784 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2785 AssertRCReturn(rc, rc);
2786
2787 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2788 AssertRCReturn(rc, rc);
2789
2790 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2791 AssertRCReturn(rc, rc);
2792
2793 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2794 AssertRCReturn(rc, rc);
2795
2796 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2797 AssertRCReturn(rc, rc);
2798
2799 if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2800 pVM->hwaccm.s.fTPRPatchingActive = true;
2801
2802 Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT || pVM->hwaccm.s.fTPRPatchingActive == false);
2803
2804 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2805 AssertRCReturn(rc, rc);
2806
2807 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2808 AssertRCReturn(rc, rc);
2809
2810 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2811 AssertRCReturn(rc, rc);
2812
2813 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2814 AssertRCReturn(rc, rc);
2815
2816 Log(("hwaccmR3Load: patch %d\n", i));
2817 Log(("Key = %x\n", pPatch->Core.Key));
2818 Log(("cbOp = %d\n", pPatch->cbOp));
2819 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2820 Log(("type = %d\n", pPatch->enmType));
2821 Log(("srcop = %d\n", pPatch->uSrcOperand));
2822 Log(("dstop = %d\n", pPatch->uDstOperand));
2823 Log(("cFaults = %d\n", pPatch->cFaults));
2824 Log(("target = %x\n", pPatch->pJumpTarget));
2825 rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2826 AssertRC(rc);
2827 }
2828 }
2829#endif
2830
2831 /* Recheck all VCPUs if we can go straight into hwaccm execution mode. */
2832 if (HWACCMIsEnabled(pVM))
2833 {
2834 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2835 {
2836 PVMCPU pVCpu = &pVM->aCpus[i];
2837
2838 HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2839 }
2840 }
2841 return VINF_SUCCESS;
2842}
2843
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