HWACCM.cpp@ 41173

Last change on this file since 41173 was 41173, checked in by vboxsync, 13 years ago
VMM: Fixed reading the wrong (reserved) bit in EPT capabilities, renamed capability defines to better suit the Intel Spec.
Property svn:eol-style set to `native` Property svn:keywords set to `Id`
File size: 135.4 KB

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1	/* $Id: HWACCM.cpp 41173 2012-05-04 15:45:28Z vboxsync $ */
2	/** @file
3	* HWACCM - Intel/AMD VM Hardware Support Manager
4	*/
5
6	/*
7	* Copyright (C) 2006-2007 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_HWACCM
22	#include <VBox/vmm/cpum.h>
23	#include <VBox/vmm/stam.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/pdmapi.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/ssm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/dbgf.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/patm.h>
32	#include <VBox/vmm/csam.h>
33	#include <VBox/vmm/selm.h>
34	#ifdef VBOX_WITH_REM
35	# include <VBox/vmm/rem.h>
36	#endif
37	#include <VBox/vmm/hwacc_vmx.h>
38	#include <VBox/vmm/hwacc_svm.h>
39	#include "HWACCMInternal.h"
40	#include <VBox/vmm/vm.h>
41	#include <VBox/err.h>
42	#include <VBox/param.h>
43
44	#include <iprt/assert.h>
45	#include <VBox/log.h>
46	#include <iprt/asm.h>
47	#include <iprt/asm-amd64-x86.h>
48	#include <iprt/string.h>
49	#include <iprt/env.h>
50	#include <iprt/thread.h>
51
52	/*******************************************************************************
53	* Global Variables *
54	*******************************************************************************/
55	#ifdef VBOX_WITH_STATISTICS
56	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57	# define EXIT_REASON_NIL() NULL
58	/** Exit reason descriptions for VT-x, used to describe statistics. */
59	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60	{
61	EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
62	EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
63	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68	EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69	EXIT_REASON_NIL(),
70	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71	EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72	EXIT_REASON_NIL(),
73	EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74	EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75	EXIT_REASON(VMX_EXIT_INVPG , 14, "Guest software attempted to execute INVPG."),
76	EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77	EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78	EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79	EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84	EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88	EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89	EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90	EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96	EXIT_REASON_NIL(),
97	EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98	EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
99	EXIT_REASON_NIL(),
100	EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101	EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103	EXIT_REASON_NIL(),
104	EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106	EXIT_REASON_NIL(),
107	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112	EXIT_REASON_NIL(),
113	EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117	EXIT_REASON_NIL()
118	};
119	/** Exit reason descriptions for AMD-V, used to describe statistics. */
120	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121	{
122	EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123	EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124	EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125	EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126	EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127	EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128	EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129	EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130	EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131	EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132	EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133	EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134	EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135	EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136	EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137	EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138	EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139	EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140	EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141	EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142	EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143	EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144	EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145	EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146	EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147	EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148	EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149	EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150	EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151	EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152	EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153	EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154	EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155	EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156	EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157	EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158	EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159	EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160	EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161	EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162	EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163	EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164	EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165	EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166	EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167	EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168	EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169	EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170	EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171	EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172	EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173	EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174	EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175	EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176	EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177	EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178	EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179	EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180	EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181	EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182	EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183	EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184	EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185	EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186	EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187	EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188	EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189	EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190	EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191	EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192	EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193	EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194	EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195	EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196	EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197	EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198	EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199	EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200	EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201	EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202	EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203	EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204	EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205	EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206	EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207	EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208	EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209	EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210	EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211	EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212	EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213	EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214	EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215	EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216	EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217	EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218	EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219	EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220	EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221	EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222	EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223	EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224	EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225	EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226	EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227	EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228	EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229	EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230	EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231	EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232	EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233	EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234	EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235	EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236	EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237	EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238	EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239	EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240	EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241	EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242	EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243	EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244	EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245	EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246	EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247	EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248	EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249	EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250	EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251	EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252	EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253	EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254	EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255	EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256	EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257	EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258	EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259	EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260	EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261	EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262	EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263	EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264	EXIT_REASON_NIL()
265	};
266	# undef EXIT_REASON
267	# undef EXIT_REASON_NIL
268	#endif /* VBOX_WITH_STATISTICS */
269
270	/*******************************************************************************
271	* Internal Functions *
272	*******************************************************************************/
273	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM);
274	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275	static int hwaccmR3InitCPU(PVM pVM);
276	static int hwaccmR3InitFinalizeR0(PVM pVM);
277	static int hwaccmR3TermCPU(PVM pVM);
278
279
280	/**
281	* Initializes the HWACCM.
282	*
283	* @returns VBox status code.
284	* @param pVM The VM to operate on.
285	*/
286	VMMR3DECL(int) HWACCMR3Init(PVM pVM)
287	{
288	LogFlow(("HWACCMR3Init\n"));
289
290	/*
291	* Assert alignment and sizes.
292	*/
293	AssertCompileMemberAlignment(VM, hwaccm.s, 32);
294	AssertCompile(sizeof(pVM->hwaccm.s) <= sizeof(pVM->hwaccm.padding));
295
296	/* Some structure checks. */
297	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310	AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311	AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313
314	/*
315	* Register the saved state data unit.
316	*/
317	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HWACCM_SSM_VERSION, sizeof(HWACCM),
318	NULL, NULL, NULL,
319	NULL, hwaccmR3Save, NULL,
320	NULL, hwaccmR3Load, NULL);
321	if (RT_FAILURE(rc))
322	return rc;
323
324	/* Misc initialisation. */
325	pVM->hwaccm.s.vmx.fSupported = false;
326	pVM->hwaccm.s.svm.fSupported = false;
327	pVM->hwaccm.s.vmx.fEnabled = false;
328	pVM->hwaccm.s.svm.fEnabled = false;
329
330	pVM->hwaccm.s.fNestedPaging = false;
331	pVM->hwaccm.s.fLargePages = false;
332
333	/* Disabled by default. */
334	pVM->fHWACCMEnabled = false;
335
336	/*
337	* Check CFGM options.
338	*/
339	PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
340	PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
341	/* Nested paging: disabled by default. */
342	rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hwaccm.s.fAllowNestedPaging, false);
343	AssertRC(rc);
344
345	/* Large pages: disabled by default. */
346	rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hwaccm.s.fLargePages, false);
347	AssertRC(rc);
348
349	/* VT-x VPID: disabled by default. */
350	rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hwaccm.s.vmx.fAllowVPID, false);
351	AssertRC(rc);
352
353	/* HWACCM support must be explicitely enabled in the configuration file. */
354	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hwaccm.s.fAllowed, false);
355	AssertRC(rc);
356
357	/* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
358	rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hwaccm.s.fTRPPatchingAllowed, false);
359	AssertRC(rc);
360
361	#ifdef RT_OS_DARWIN
362	if (VMMIsHwVirtExtForced(pVM) != pVM->hwaccm.s.fAllowed)
363	#else
364	if (VMMIsHwVirtExtForced(pVM) && !pVM->hwaccm.s.fAllowed)
365	#endif
366	{
367	AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
368	VMMIsHwVirtExtForced(pVM), pVM->hwaccm.s.fAllowed));
369	return VERR_HWACCM_CONFIG_MISMATCH;
370	}
371
372	if (VMMIsHwVirtExtForced(pVM))
373	pVM->fHWACCMEnabled = true;
374
375	#if HC_ARCH_BITS == 32
376	/* 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
377	* (To use the default, don't set 64bitEnabled in CFGM.) */
378	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, false);
379	AssertLogRelRCReturn(rc, rc);
380	if (pVM->hwaccm.s.fAllow64BitGuests)
381	{
382	# ifdef RT_OS_DARWIN
383	if (!VMMIsHwVirtExtForced(pVM))
384	# else
385	if (!pVM->hwaccm.s.fAllowed)
386	# endif
387	return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
388	}
389	#else
390	/* On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
391	* via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.) */
392	rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hwaccm.s.fAllow64BitGuests, true);
393	AssertLogRelRCReturn(rc, rc);
394	#endif
395
396
397	/** Determine the init method for AMD-V and VT-x; either one global init for each host CPU
398	* or local init each time we wish to execute guest code.
399	*
400	* Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
401	*/
402	rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hwaccm.s.fGlobalInit,
403	#if defined(RT_OS_DARWIN) \|\| defined(RT_OS_WINDOWS)
404	false
405	#else
406	true
407	#endif
408	);
409
410	/* Max number of resume loops. */
411	rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hwaccm.s.cMaxResumeLoops, 0 /* set by R0 later */);
412	AssertRC(rc);
413
414	return rc;
415	}
416
417	/**
418	* Initializes the per-VCPU HWACCM.
419	*
420	* @returns VBox status code.
421	* @param pVM The VM to operate on.
422	*/
423	static int hwaccmR3InitCPU(PVM pVM)
424	{
425	LogFlow(("HWACCMR3InitCPU\n"));
426
427	for (VMCPUID i = 0; i < pVM->cCpus; i++)
428	{
429	PVMCPU pVCpu = &pVM->aCpus[i];
430
431	pVCpu->hwaccm.s.fActive = false;
432	}
433
434	#ifdef VBOX_WITH_STATISTICS
435	STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
436	STAM_REG(pVM, &pVM->hwaccm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
437	STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
438	STAM_REG(pVM, &pVM->hwaccm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HWACCM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
439
440	/*
441	* Statistics.
442	*/
443	for (VMCPUID i = 0; i < pVM->cCpus; i++)
444	{
445	PVMCPU pVCpu = &pVM->aCpus[i];
446	int rc;
447
448	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
449	"/PROF/HWACCM/CPU%d/Poke", i);
450	AssertRC(rc);
451	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
452	"/PROF/HWACCM/CPU%d/PokeWait", i);
453	AssertRC(rc);
454	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
455	"/PROF/HWACCM/CPU%d/PokeWaitFailed", i);
456	AssertRC(rc);
457	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
458	"/PROF/HWACCM/CPU%d/SwitchToGC", i);
459	AssertRC(rc);
460	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
461	"/PROF/HWACCM/CPU%d/SwitchFromGC_1", i);
462	AssertRC(rc);
463	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
464	"/PROF/HWACCM/CPU%d/SwitchFromGC_2", i);
465	AssertRC(rc);
466	# if 1 /* temporary for tracking down darwin holdup. */
467	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
468	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub1", i);
469	AssertRC(rc);
470	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
471	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub2", i);
472	AssertRC(rc);
473	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
474	"/PROF/HWACCM/CPU%d/SwitchFromGC_2/Sub3", i);
475	AssertRC(rc);
476	# endif
477	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
478	"/PROF/HWACCM/CPU%d/InGC", i);
479	AssertRC(rc);
480
481	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
482	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
483	"/PROF/HWACCM/CPU%d/Switcher3264", i);
484	AssertRC(rc);
485	# endif
486
487	# define HWACCM_REG_COUNTER(a, b) \
488	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
489	AssertRC(rc);
490
491	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowNM, "/HWACCM/CPU%d/Exit/Trap/Shw/#NM");
492	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNM, "/HWACCM/CPU%d/Exit/Trap/Gst/#NM");
493	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPF, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF");
494	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitShadowPFEM, "/HWACCM/CPU%d/Exit/Trap/Shw/#PF-EM");
495	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestPF, "/HWACCM/CPU%d/Exit/Trap/Gst/#PF");
496	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestUD, "/HWACCM/CPU%d/Exit/Trap/Gst/#UD");
497	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestSS, "/HWACCM/CPU%d/Exit/Trap/Gst/#SS");
498	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestNP, "/HWACCM/CPU%d/Exit/Trap/Gst/#NP");
499	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestGP, "/HWACCM/CPU%d/Exit/Trap/Gst/#GP");
500	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestMF, "/HWACCM/CPU%d/Exit/Trap/Gst/#MF");
501	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDE, "/HWACCM/CPU%d/Exit/Trap/Gst/#DE");
502	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestDB, "/HWACCM/CPU%d/Exit/Trap/Gst/#DB");
503	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestBP, "/HWACCM/CPU%d/Exit/Trap/Gst/#BP");
504	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXF, "/HWACCM/CPU%d/Exit/Trap/Gst/#XF");
505	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitGuestXcpUnk, "/HWACCM/CPU%d/Exit/Trap/Gst/Other");
506	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvpg, "/HWACCM/CPU%d/Exit/Instr/Invlpg");
507	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInvd, "/HWACCM/CPU%d/Exit/Instr/Invd");
508	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCpuid, "/HWACCM/CPU%d/Exit/Instr/Cpuid");
509	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdtsc, "/HWACCM/CPU%d/Exit/Instr/Rdtsc");
510	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdpmc, "/HWACCM/CPU%d/Exit/Instr/Rdpmc");
511	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitRdmsr, "/HWACCM/CPU%d/Exit/Instr/Rdmsr");
512	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitWrmsr, "/HWACCM/CPU%d/Exit/Instr/Wrmsr");
513	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMwait, "/HWACCM/CPU%d/Exit/Instr/Mwait");
514	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMonitor, "/HWACCM/CPU%d/Exit/Instr/Monitor");
515	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxWrite, "/HWACCM/CPU%d/Exit/Instr/DR/Write");
516	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitDRxRead, "/HWACCM/CPU%d/Exit/Instr/DR/Read");
517	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCLTS, "/HWACCM/CPU%d/Exit/Instr/CLTS");
518	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitLMSW, "/HWACCM/CPU%d/Exit/Instr/LMSW");
519	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitCli, "/HWACCM/CPU%d/Exit/Instr/Cli");
520	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitSti, "/HWACCM/CPU%d/Exit/Instr/Sti");
521	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPushf, "/HWACCM/CPU%d/Exit/Instr/Pushf");
522	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPopf, "/HWACCM/CPU%d/Exit/Instr/Popf");
523	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIret, "/HWACCM/CPU%d/Exit/Instr/Iret");
524	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitInt, "/HWACCM/CPU%d/Exit/Instr/Int");
525	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitHlt, "/HWACCM/CPU%d/Exit/Instr/Hlt");
526	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOWrite, "/HWACCM/CPU%d/Exit/IO/Write");
527	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIORead, "/HWACCM/CPU%d/Exit/IO/Read");
528	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringWrite, "/HWACCM/CPU%d/Exit/IO/WriteString");
529	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIOStringRead, "/HWACCM/CPU%d/Exit/IO/ReadString");
530	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitIrqWindow, "/HWACCM/CPU%d/Exit/IrqWindow");
531	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMaxResume, "/HWACCM/CPU%d/Exit/MaxResume");
532	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitPreemptPending, "/HWACCM/CPU%d/Exit/PreemptPending");
533	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatExitMTF, "/HWACCM/CPU%d/Exit/MonitorTrapFlag");
534
535	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchGuestIrq, "/HWACCM/CPU%d/Switch/IrqPending");
536	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatSwitchToR3, "/HWACCM/CPU%d/Switch/ToR3");
537
538	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntInject, "/HWACCM/CPU%d/Irq/Inject");
539	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatIntReinject, "/HWACCM/CPU%d/Irq/Reinject");
540	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatPendingHostIrq, "/HWACCM/CPU%d/Irq/PendingOnHost");
541
542	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPage, "/HWACCM/CPU%d/Flush/Page");
543	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageManual, "/HWACCM/CPU%d/Flush/Page/Virt");
544	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPhysPageManual, "/HWACCM/CPU%d/Flush/Page/Phys");
545	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLB, "/HWACCM/CPU%d/Flush/TLB");
546	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBManual, "/HWACCM/CPU%d/Flush/TLB/Manual");
547	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBCRxChange, "/HWACCM/CPU%d/Flush/TLB/CRx");
548	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushPageInvlpg, "/HWACCM/CPU%d/Flush/Page/Invlpg");
549	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Switch");
550	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatNoFlushTLBWorldSwitch, "/HWACCM/CPU%d/Flush/TLB/Skipped");
551	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushASID, "/HWACCM/CPU%d/Flush/TLB/ASID");
552	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFlushTLBInvlpga, "/HWACCM/CPU%d/Flush/TLB/PhysInvl");
553	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdown, "/HWACCM/CPU%d/Flush/Shootdown/Page");
554	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTlbShootdownFlush, "/HWACCM/CPU%d/Flush/Shootdown/TLB");
555
556	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCOffset, "/HWACCM/CPU%d/TSC/Offset");
557	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCIntercept, "/HWACCM/CPU%d/TSC/Intercept");
558	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatTSCInterceptOverFlow, "/HWACCM/CPU%d/TSC/InterceptOverflow");
559
560	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxArmed, "/HWACCM/CPU%d/Debug/Armed");
561	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxContextSwitch, "/HWACCM/CPU%d/Debug/ContextSwitch");
562	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDRxIOCheck, "/HWACCM/CPU%d/Debug/IOCheck");
563
564	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadMinimal, "/HWACCM/CPU%d/Load/Minimal");
565	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatLoadFull, "/HWACCM/CPU%d/Load/Full");
566
567	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
568	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatFpu64SwitchBack, "/HWACCM/CPU%d/Switch64/Fpu");
569	HWACCM_REG_COUNTER(&pVCpu->hwaccm.s.StatDebug64SwitchBack, "/HWACCM/CPU%d/Switch64/Debug");
570	#endif
571
572	for (unsigned j=0;j<RT_ELEMENTS(pVCpu->hwaccm.s.StatExitCRxWrite);j++)
573	{
574	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
575	"/HWACCM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
576	AssertRC(rc);
577	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
578	"/HWACCM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
579	AssertRC(rc);
580	}
581
582	#undef HWACCM_REG_COUNTER
583
584	pVCpu->hwaccm.s.paStatExitReason = NULL;
585
586	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STATsizeof(pVCpu->hwaccm.s.paStatExitReason), 0, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatExitReason);
587	AssertRC(rc);
588	if (RT_SUCCESS(rc))
589	{
590	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
591	for (int j=0;j<MAX_EXITREASON_STAT;j++)
592	{
593	if (papszDesc[j])
594	{
595	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
596	papszDesc[j], "/HWACCM/CPU%d/Exit/Reason/%02x", i, j);
597	AssertRC(rc);
598	}
599	}
600	rc = STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HWACCM/CPU%d/Exit/Reason/#NPF", i);
601	AssertRC(rc);
602	}
603	pVCpu->hwaccm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatExitReason);
604	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
605	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
606	# else
607	Assert(pVCpu->hwaccm.s.paStatExitReasonR0 != NIL_RTR0PTR);
608	# endif
609
610	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HWACCM, (void **)&pVCpu->hwaccm.s.paStatInjectedIrqs);
611	AssertRCReturn(rc, rc);
612	pVCpu->hwaccm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
613	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
614	Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR \|\| !VMMIsHwVirtExtForced(pVM));
615	# else
616	Assert(pVCpu->hwaccm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
617	# endif
618	for (unsigned j = 0; j < 255; j++)
619	STAMR3RegisterF(pVM, &pVCpu->hwaccm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
620	(j < 0x20) ? "/HWACCM/CPU%d/Interrupt/Trap/%02X" : "/HWACCM/CPU%d/Interrupt/IRQ/%02X", i, j);
621
622	}
623	#endif /* VBOX_WITH_STATISTICS */
624
625	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
626	/* Magic marker for searching in crash dumps. */
627	for (VMCPUID i = 0; i < pVM->cCpus; i++)
628	{
629	PVMCPU pVCpu = &pVM->aCpus[i];
630
631	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
632	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
633	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
634	}
635	#endif
636	return VINF_SUCCESS;
637	}
638
639	/**
640	* Called when a init phase has completed.
641	*
642	* @returns VBox status code.
643	* @param pVM The VM.
644	* @param enmWhat The phase that completed.
645	*/
646	VMMR3_INT_DECL(int) HWACCMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
647	{
648	switch (enmWhat)
649	{
650	case VMINITCOMPLETED_RING3:
651	return hwaccmR3InitCPU(pVM);
652	case VMINITCOMPLETED_RING0:
653	return hwaccmR3InitFinalizeR0(pVM);
654	default:
655	return VINF_SUCCESS;
656	}
657	}
658
659	/**
660	* Turns off normal raw mode features
661	*
662	* @param pVM The VM to operate on.
663	*/
664	static void hwaccmR3DisableRawMode(PVM pVM)
665	{
666	/* Disable PATM & CSAM. */
667	PATMR3AllowPatching(pVM, false);
668	CSAMDisableScanning(pVM);
669
670	/* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
671	SELMR3DisableMonitoring(pVM);
672	TRPMR3DisableMonitoring(pVM);
673
674	/* Disable the switcher code (safety precaution). */
675	VMMR3DisableSwitcher(pVM);
676
677	/* Disable mapping of the hypervisor into the shadow page table. */
678	PGMR3MappingsDisable(pVM);
679
680	/* Disable the switcher */
681	VMMR3DisableSwitcher(pVM);
682
683	/* Reinit the paging mode to force the new shadow mode. */
684	for (VMCPUID i = 0; i < pVM->cCpus; i++)
685	{
686	PVMCPU pVCpu = &pVM->aCpus[i];
687
688	PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
689	}
690	}
691
692	/**
693	* Initialize VT-x or AMD-V.
694	*
695	* @returns VBox status code.
696	* @param pVM The VM handle.
697	*/
698	static int hwaccmR3InitFinalizeR0(PVM pVM)
699	{
700	int rc;
701
702	/* Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
703	* is already using AMD-V.
704	*/
705	if ( !pVM->hwaccm.s.vmx.fSupported
706	&& !pVM->hwaccm.s.svm.fSupported
707	&& pVM->hwaccm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
708	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
709	{
710	LogRel(("HWACCM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
711	pVM->hwaccm.s.svm.fSupported = true;
712	pVM->hwaccm.s.svm.fIgnoreInUseError = true;
713	}
714	else
715	if ( !pVM->hwaccm.s.vmx.fSupported
716	&& !pVM->hwaccm.s.svm.fSupported)
717	{
718	LogRel(("HWACCM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hwaccm.s.lLastError));
719	LogRel(("HWACCM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
720
721	if (VMMIsHwVirtExtForced(pVM))
722	{
723	switch (pVM->hwaccm.s.lLastError)
724	{
725	case VERR_VMX_NO_VMX:
726	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
727	case VERR_VMX_IN_VMX_ROOT_MODE:
728	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
729	case VERR_SVM_IN_USE:
730	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
731	case VERR_SVM_NO_SVM:
732	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
733	case VERR_SVM_DISABLED:
734	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
735	default:
736	return pVM->hwaccm.s.lLastError;
737	}
738	}
739	return VINF_SUCCESS;
740	}
741
742	if (pVM->hwaccm.s.vmx.fSupported)
743	{
744	rc = SUPR3QueryVTxSupported();
745	if (RT_FAILURE(rc))
746	{
747	#ifdef RT_OS_LINUX
748	LogRel(("HWACCM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
749	#else
750	LogRel(("HWACCM: The host kernel does not support VT-x!\n"));
751	#endif
752	if ( pVM->cCpus > 1
753	\|\| VMMIsHwVirtExtForced(pVM))
754	return rc;
755
756	/* silently fall back to raw mode */
757	return VINF_SUCCESS;
758	}
759	}
760
761	if (!pVM->hwaccm.s.fAllowed)
762	return VINF_SUCCESS; /* nothing to do */
763
764	/* Enable VT-x or AMD-V on all host CPUs. */
765	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HWACC_ENABLE, 0, NULL);
766	if (RT_FAILURE(rc))
767	{
768	LogRel(("HWACCMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HWACC_ENABLE failed with %Rrc\n", rc));
769	return rc;
770	}
771	Assert(!pVM->fHWACCMEnabled \|\| VMMIsHwVirtExtForced(pVM));
772
773	pVM->hwaccm.s.fHasIoApic = PDMHasIoApic(pVM);
774	/* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
775	if (!pVM->hwaccm.s.fHasIoApic)
776	{
777	Assert(!pVM->hwaccm.s.fTRPPatchingAllowed); /* paranoia */
778	pVM->hwaccm.s.fTRPPatchingAllowed = false;
779	}
780
781	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
782	if (pVM->hwaccm.s.vmx.fSupported)
783	{
784	Log(("pVM->hwaccm.s.vmx.fSupported = %d\n", pVM->hwaccm.s.vmx.fSupported));
785
786	if ( pVM->hwaccm.s.fInitialized == false
787	&& pVM->hwaccm.s.vmx.msr.feature_ctrl != 0)
788	{
789	uint64_t val;
790	RTGCPHYS GCPhys = 0;
791
792	LogRel(("HWACCM: Host CR4=%08X\n", pVM->hwaccm.s.vmx.hostCR4));
793	LogRel(("HWACCM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hwaccm.s.vmx.msr.feature_ctrl));
794	LogRel(("HWACCM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_basic_info));
795	LogRel(("HWACCM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
796	LogRel(("HWACCM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
797	LogRel(("HWACCM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hwaccm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
798	LogRel(("HWACCM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
799	LogRel(("HWACCM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hwaccm.s.vmx.msr.vmx_basic_info)));
800
801	LogRel(("HWACCM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.u));
802	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
803	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
804	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
805	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
806	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
807	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
808	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
809	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
810	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
811	val = pVM->hwaccm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
812	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
813	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT must be set\n"));
814	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
815	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT must be set\n"));
816	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
817	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI must be set\n"));
818	if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
819	LogRel(("HWACCM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER must be set\n"));
820
821	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.u));
822	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
823	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
824	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
825	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
826	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
827	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
828	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
829	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
830	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
831	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
832	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
833	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
834	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
835	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
836	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
837	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
838	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
839	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
840	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
841	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
842	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
843	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
844	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
845	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
846	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
847	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
848	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
849	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
850	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
851	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
852	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
853	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
854	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
855	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
856	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
857	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
858	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
859	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
860	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
861	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
862	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
863	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
864	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
865
866	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
867	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
868	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT must be set\n"));
869	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
870	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET must be set\n"));
871	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
872	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT must be set\n"));
873	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
874	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT must be set\n"));
875	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
876	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT must be set\n"));
877	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
878	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT must be set\n"));
879	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
880	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT must be set\n"));
881	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
882	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT must be set\n"));
883	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
884	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT must be set\n"));
885	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
886	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT must be set\n"));
887	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
888	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT must be set\n"));
889	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
890	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW must be set\n"));
891	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
892	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT must be set\n"));
893	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
894	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT must be set\n"));
895	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
896	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT must be set\n"));
897	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
898	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS must be set\n"));
899	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
900	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG must be set\n"));
901	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
902	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS must be set\n"));
903	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
904	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT must be set\n"));
905	if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
906	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT must be set\n"));
907	if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
908	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL must be set\n"));
909
910	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
911	{
912	LogRel(("HWACCM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.u));
913	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
914	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
915	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
916	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
917	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
918	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
919	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
920	if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
921	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT\n"));
922	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
923	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
924	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
925	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
926	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
927	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
928	if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
929	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
930	if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
931	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
932
933	val = pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
934	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
935	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC must be set\n"));
936	if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
937	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT must be set\n"));
938	if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT)
939	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP_EXIT must be set\n"));
940	if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
941	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC must be set\n"));
942	if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
943	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_EPT must be set\n"));
944	if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
945	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_VPID must be set\n"));
946	if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
947	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT must be set\n"));
948	if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
949	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE must be set\n"));
950	if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
951	LogRel(("HWACCM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT must be set\n"));
952	}
953
954	LogRel(("HWACCM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_entry.u));
955	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.allowed1;
956	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
957	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
958	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
959	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
960	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
961	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
962	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
963	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
964	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
965	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
966	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
967	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
968	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
969	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
970	val = pVM->hwaccm.s.vmx.msr.vmx_entry.n.disallowed0;
971	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
972	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG must be set\n"));
973	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
974	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE must be set\n"));
975	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
976	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM must be set\n"));
977	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
978	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON must be set\n"));
979	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
980	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR must be set\n"));
981	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
982	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR must be set\n"));
983	if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
984	LogRel(("HWACCM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR must be set\n"));
985
986	LogRel(("HWACCM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_exit.u));
987	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.allowed1;
988	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
989	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
990	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
991	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
992	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
993	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
994	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
995	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
996	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
997	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
998	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
999	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1000	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1001	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1002	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1003	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1004	val = pVM->hwaccm.s.vmx.msr.vmx_exit.n.disallowed0;
1005	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1006	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG must be set\n"));
1007	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1008	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 must be set\n"));
1009	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1010	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ must be set\n"));
1011	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1012	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR must be set\n"));
1013	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1014	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR must be set\n"));
1015	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1016	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR must be set\n"));
1017	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1018	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR must be set\n"));
1019	if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1020	LogRel(("HWACCM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER must be set\n"));
1021
1022	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps)
1023	{
1024	LogRel(("HWACCM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_eptcaps));
1025
1026	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
1027	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
1028	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
1029	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1030	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1031	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1032	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1033	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1034	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1035	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1036	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1037	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1038	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1039	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1040	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1041	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1042	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1043	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1044	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1045	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1046	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1047	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1048	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1049	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1050	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1051	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1052	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1053	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1054	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1055	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1056	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1057	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1058	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1059	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1060	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1061	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1062	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT)
1063	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT\n"));
1064	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS)
1065	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS\n"));
1066	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1067	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1068	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR)
1069	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR\n"));
1070	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT)
1071	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT\n"));
1072	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS)
1073	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS\n"));
1074	if (pVM->hwaccm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS)
1075	LogRel(("HWACCM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1076	}
1077
1078	LogRel(("HWACCM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_misc));
1079	if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc) == pVM->hwaccm.s.vmx.cPreemptTimerShift)
1080	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1081	else
1082	LogRel(("HWACCM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hwaccm.s.vmx.msr.vmx_misc), pVM->hwaccm.s.vmx.cPreemptTimerShift));
1083	LogRel(("HWACCM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1084	LogRel(("HWACCM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1085	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1086	LogRel(("HWACCM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hwaccm.s.vmx.msr.vmx_misc)));
1087
1088	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0));
1089	LogRel(("HWACCM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1));
1090	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0));
1091	LogRel(("HWACCM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1));
1092	LogRel(("HWACCM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hwaccm.s.vmx.msr.vmx_vmcs_enum));
1093
1094	LogRel(("HWACCM: TPR shadow physaddr = %RHp\n", pVM->hwaccm.s.vmx.pAPICPhys));
1095
1096	/* Paranoia */
1097	AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hwaccm.s.vmx.msr.vmx_misc) >= 512);
1098
1099	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1100	{
1101	LogRel(("HWACCM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.pMSRBitmapPhys));
1102	LogRel(("HWACCM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
1103	}
1104
1105	#ifdef HWACCM_VTX_WITH_EPT
1106	if (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1107	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1108	#endif /* HWACCM_VTX_WITH_EPT */
1109	#ifdef HWACCM_VTX_WITH_VPID
1110	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1111	&& !pVM->hwaccm.s.fNestedPaging) /* VPID and EPT are mutually exclusive. */
1112	pVM->hwaccm.s.vmx.fVPID = pVM->hwaccm.s.vmx.fAllowVPID;
1113	#endif /* HWACCM_VTX_WITH_VPID */
1114
1115	/* Unrestricted guest execution relies on EPT. */
1116	if ( pVM->hwaccm.s.fNestedPaging
1117	&& (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1118	{
1119	pVM->hwaccm.s.vmx.fUnrestrictedGuest = true;
1120	}
1121
1122	/* Only try once. */
1123	pVM->hwaccm.s.fInitialized = true;
1124
1125	if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1126	{
1127	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1128	rc = PDMR3VMMDevHeapAlloc(pVM, HWACCM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hwaccm.s.vmx.pRealModeTSS);
1129	if (RT_SUCCESS(rc))
1130	{
1131	/* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1132	ASMMemZero32(pVM->hwaccm.s.vmx.pRealModeTSS, sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS));
1133	pVM->hwaccm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hwaccm.s.vmx.pRealModeTSS);
1134	/* Bit set to 0 means redirection enabled. */
1135	memset(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hwaccm.s.vmx.pRealModeTSS->IntRedirBitmap));
1136	/* Allow all port IO, so the VT-x IO intercepts do their job. */
1137	memset(pVM->hwaccm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1138	((unsigned char )pVM->hwaccm.s.vmx.pRealModeTSS + HWACCM_VTX_TSS_SIZE - 2) = 0xff;
1139
1140	/* Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1141	* real and protected mode without paging with EPT.
1142	*/
1143	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hwaccm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1144	for (unsigned i=0;i<X86_PG_ENTRIES;i++)
1145	{
1146	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1147	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS \| X86_PDE4M_G;
1148	}
1149
1150	/* We convert it here every time as pci regions could be reconfigured. */
1151	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pRealModeTSS, &GCPhys);
1152	AssertRC(rc);
1153	LogRel(("HWACCM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1154
1155	rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1156	AssertRC(rc);
1157	LogRel(("HWACCM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1158	}
1159	else
1160	{
1161	LogRel(("HWACCM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1162	pVM->hwaccm.s.vmx.pRealModeTSS = NULL;
1163	pVM->hwaccm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1164	}
1165	}
1166
1167	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1168	AssertRC(rc);
1169	if (rc == VINF_SUCCESS)
1170	{
1171	pVM->fHWACCMEnabled = true;
1172	pVM->hwaccm.s.vmx.fEnabled = true;
1173	hwaccmR3DisableRawMode(pVM);
1174
1175	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1176	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1177	if (pVM->hwaccm.s.fAllow64BitGuests)
1178	{
1179	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1180	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1181	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1182	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1183	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1184	}
1185	else
1186	/* Turn on NXE if PAE has been enabled and the host has turned on NXE (we reuse the host EFER in the switcher) */
1187	/* Todo: this needs to be fixed properly!! */
1188	if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1189	&& (pVM->hwaccm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1190	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1191
1192	LogRel((pVM->hwaccm.s.fAllow64BitGuests
1193	? "HWACCM: 32-bit and 64-bit guests supported.\n"
1194	: "HWACCM: 32-bit guests supported.\n"));
1195	#else
1196	LogRel(("HWACCM: 32-bit guests supported.\n"));
1197	#endif
1198	LogRel(("HWACCM: VMX enabled!\n"));
1199	if (pVM->hwaccm.s.fNestedPaging)
1200	{
1201	LogRel(("HWACCM: Enabled nested paging\n"));
1202	LogRel(("HWACCM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1203	if (pVM->hwaccm.s.vmx.fUnrestrictedGuest)
1204	LogRel(("HWACCM: Unrestricted guest execution enabled!\n"));
1205
1206	#if HC_ARCH_BITS == 64
1207	if (pVM->hwaccm.s.fLargePages)
1208	{
1209	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1210	PGMSetLargePageUsage(pVM, true);
1211	LogRel(("HWACCM: Large page support enabled!\n"));
1212	}
1213	#endif
1214	}
1215	else
1216	Assert(!pVM->hwaccm.s.vmx.fUnrestrictedGuest);
1217
1218	if (pVM->hwaccm.s.vmx.fVPID)
1219	LogRel(("HWACCM: Enabled VPID\n"));
1220
1221	if ( pVM->hwaccm.s.fNestedPaging
1222	\|\| pVM->hwaccm.s.vmx.fVPID)
1223	{
1224	LogRel(("HWACCM: enmFlushPage %d\n", pVM->hwaccm.s.vmx.enmFlushPage));
1225	LogRel(("HWACCM: enmFlushContext %d\n", pVM->hwaccm.s.vmx.enmFlushContext));
1226	}
1227
1228	/* TPR patching status logging. */
1229	if (pVM->hwaccm.s.fTRPPatchingAllowed)
1230	{
1231	if ( (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1232	&& (pVM->hwaccm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1233	{
1234	pVM->hwaccm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1235	LogRel(("HWACCM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1236	}
1237	else
1238	{
1239	uint32_t u32Eax, u32Dummy;
1240
1241	/* TPR patching needs access to the MSR_K8_LSTAR msr. */
1242	ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1243	if ( u32Eax < 0x80000001
1244	\|\| !(ASMCpuId_EDX(0x80000001) & X86_CPUID_AMD_FEATURE_EDX_LONG_MODE))
1245	{
1246	pVM->hwaccm.s.fTRPPatchingAllowed = false;
1247	LogRel(("HWACCM: TPR patching disabled (long mode not supported).\n"));
1248	}
1249	}
1250	}
1251	LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1252
1253	/*
1254	* Check for preemption timer config override and log the state of it.
1255	*/
1256	if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1257	{
1258	PCFGMNODE pCfgHwAccM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HWACCM");
1259	int rc2 = CFGMR3QueryBoolDef(pCfgHwAccM, "UsePreemptTimer", &pVM->hwaccm.s.vmx.fUsePreemptTimer, true);
1260	AssertLogRelRC(rc2);
1261	}
1262	if (pVM->hwaccm.s.vmx.fUsePreemptTimer)
1263	LogRel(("HWACCM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hwaccm.s.vmx.cPreemptTimerShift));
1264	}
1265	else
1266	{
1267	LogRel(("HWACCM: VMX setup failed with rc=%Rrc!\n", rc));
1268	LogRel(("HWACCM: Last instruction error %x\n", pVM->aCpus[0].hwaccm.s.vmx.lasterror.ulInstrError));
1269	pVM->fHWACCMEnabled = false;
1270	}
1271	}
1272	}
1273	else
1274	if (pVM->hwaccm.s.svm.fSupported)
1275	{
1276	Log(("pVM->hwaccm.s.svm.fSupported = %d\n", pVM->hwaccm.s.svm.fSupported));
1277
1278	if (pVM->hwaccm.s.fInitialized == false)
1279	{
1280	/* Erratum 170 which requires a forced TLB flush for each world switch:
1281	* See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1282	*
1283	* All BH-G1/2 and DH-G1/2 models include a fix:
1284	* Athlon X2: 0x6b 1/2
1285	* 0x68 1/2
1286	* Athlon 64: 0x7f 1
1287	* 0x6f 2
1288	* Sempron: 0x7f 1/2
1289	* 0x6f 2
1290	* 0x6c 2
1291	* 0x7c 2
1292	* Turion 64: 0x68 2
1293	*
1294	*/
1295	uint32_t u32Dummy;
1296	uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1297	ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1298	u32BaseFamily= (u32Version >> 8) & 0xf;
1299	u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1300	u32Model = ((u32Version >> 4) & 0xf);
1301	u32Model = u32Model \| ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1302	u32Stepping = u32Version & 0xf;
1303	if ( u32Family == 0xf
1304	&& !((u32Model == 0x68 \|\| u32Model == 0x6b \|\| u32Model == 0x7f) && u32Stepping >= 1)
1305	&& !((u32Model == 0x6f \|\| u32Model == 0x6c \|\| u32Model == 0x7c) && u32Stepping >= 2))
1306	{
1307	LogRel(("HWACMM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1308	}
1309
1310	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureECX));
1311	LogRel(("HWACMM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hwaccm.s.cpuid.u32AMDFeatureEDX));
1312	LogRel(("HWACCM: AMD HWCR MSR = %RX64\n", pVM->hwaccm.s.svm.msrHWCR));
1313	LogRel(("HWACCM: AMD-V revision = %X\n", pVM->hwaccm.s.svm.u32Rev));
1314	LogRel(("HWACCM: AMD-V max ASID = %d\n", pVM->hwaccm.s.uMaxASID));
1315	LogRel(("HWACCM: AMD-V features = %X\n", pVM->hwaccm.s.svm.u32Features));
1316	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1317	{
1318	#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1319	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1320	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1321	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1322	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1323	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1324	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1325	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1326	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1327	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1328	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1329	FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1330	#undef FLAG_NAME
1331	};
1332	uint32_t fSvmFeatures = pVM->hwaccm.s.svm.u32Features;
1333	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1334	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1335	{
1336	LogRel(("HWACCM: %s\n", s_aSvmFeatures[i].pszName));
1337	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1338	}
1339	if (fSvmFeatures)
1340	for (unsigned iBit = 0; iBit < 32; iBit++)
1341	if (RT_BIT_32(iBit) & fSvmFeatures)
1342	LogRel(("HWACCM: Reserved bit %u\n", iBit));
1343
1344	/* Only try once. */
1345	pVM->hwaccm.s.fInitialized = true;
1346
1347	if (pVM->hwaccm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1348	pVM->hwaccm.s.fNestedPaging = pVM->hwaccm.s.fAllowNestedPaging;
1349
1350	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HWACC_SETUP_VM, 0, NULL);
1351	AssertRC(rc);
1352	if (rc == VINF_SUCCESS)
1353	{
1354	pVM->fHWACCMEnabled = true;
1355	pVM->hwaccm.s.svm.fEnabled = true;
1356
1357	if (pVM->hwaccm.s.fNestedPaging)
1358	{
1359	LogRel(("HWACCM: Enabled nested paging\n"));
1360	#if HC_ARCH_BITS == 64
1361	if (pVM->hwaccm.s.fLargePages)
1362	{
1363	/* Use large (2 MB) pages for our nested paging PDEs where possible. */
1364	PGMSetLargePageUsage(pVM, true);
1365	LogRel(("HWACCM: Large page support enabled!\n"));
1366	}
1367	#endif
1368	}
1369
1370	hwaccmR3DisableRawMode(pVM);
1371	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1372	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1373	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1374	#ifdef VBOX_ENABLE_64_BITS_GUESTS
1375	if (pVM->hwaccm.s.fAllow64BitGuests)
1376	{
1377	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1378	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1379	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1380	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1381	}
1382	else
1383	/* Turn on NXE if PAE has been enabled. */
1384	if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1385	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NXE);
1386	#endif
1387
1388	LogRel((pVM->hwaccm.s.fAllow64BitGuests
1389	? "HWACCM: 32-bit and 64-bit guest supported.\n"
1390	: "HWACCM: 32-bit guest supported.\n"));
1391
1392	LogRel(("HWACCM: TPR Patching %s.\n", (pVM->hwaccm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1393	}
1394	else
1395	{
1396	pVM->fHWACCMEnabled = false;
1397	}
1398	}
1399	}
1400	if (pVM->fHWACCMEnabled)
1401	LogRel(("HWACCM: VT-x/AMD-V init method: %s\n", (pVM->hwaccm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1402	RTLogRelSetBuffering(fOldBuffered);
1403	return VINF_SUCCESS;
1404	}
1405
1406	/**
1407	* Applies relocations to data and code managed by this
1408	* component. This function will be called at init and
1409	* whenever the VMM need to relocate it self inside the GC.
1410	*
1411	* @param pVM The VM.
1412	*/
1413	VMMR3DECL(void) HWACCMR3Relocate(PVM pVM)
1414	{
1415	Log(("HWACCMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1416
1417	/* Fetch the current paging mode during the relocate callback during state loading. */
1418	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1419	{
1420	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1421	{
1422	PVMCPU pVCpu = &pVM->aCpus[i];
1423
1424	pVCpu->hwaccm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1425	Assert(pVCpu->hwaccm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1426	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1427	}
1428	}
1429	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1430	if (pVM->fHWACCMEnabled)
1431	{
1432	int rc;
1433
1434	switch(PGMGetHostMode(pVM))
1435	{
1436	case PGMMODE_32_BIT:
1437	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1438	break;
1439
1440	case PGMMODE_PAE:
1441	case PGMMODE_PAE_NX:
1442	pVM->hwaccm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1443	break;
1444
1445	default:
1446	AssertFailed();
1447	break;
1448	}
1449	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hwaccm.s.pfnVMXGCStartVM64);
1450	AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1451
1452	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hwaccm.s.pfnSVMGCVMRun64);
1453	AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1454
1455	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestFPU64", &pVM->hwaccm.s.pfnSaveGuestFPU64);
1456	AssertReleaseMsgRC(rc, ("HWACCMSetupFPU64 -> rc=%Rrc\n", rc));
1457
1458	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMSaveGuestDebug64", &pVM->hwaccm.s.pfnSaveGuestDebug64);
1459	AssertReleaseMsgRC(rc, ("HWACCMSetupDebug64 -> rc=%Rrc\n", rc));
1460
1461	# ifdef DEBUG
1462	rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HWACCMTestSwitcher64", &pVM->hwaccm.s.pfnTest64);
1463	AssertReleaseMsgRC(rc, ("HWACCMTestSwitcher64 -> rc=%Rrc\n", rc));
1464	# endif
1465	}
1466	#endif
1467	return;
1468	}
1469
1470	/**
1471	* Checks hardware accelerated raw mode is allowed.
1472	*
1473	* @returns boolean
1474	* @param pVM The VM to operate on.
1475	*/
1476	VMMR3DECL(bool) HWACCMR3IsAllowed(PVM pVM)
1477	{
1478	return pVM->hwaccm.s.fAllowed;
1479	}
1480
1481	/**
1482	* Notification callback which is called whenever there is a chance that a CR3
1483	* value might have changed.
1484	*
1485	* This is called by PGM.
1486	*
1487	* @param pVM The VM to operate on.
1488	* @param pVCpu The VMCPU to operate on.
1489	* @param enmShadowMode New shadow paging mode.
1490	* @param enmGuestMode New guest paging mode.
1491	*/
1492	VMMR3DECL(void) HWACCMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1493	{
1494	/* Ignore page mode changes during state loading. */
1495	if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1496	return;
1497
1498	pVCpu->hwaccm.s.enmShadowMode = enmShadowMode;
1499
1500	if ( pVM->hwaccm.s.vmx.fEnabled
1501	&& pVM->fHWACCMEnabled)
1502	{
1503	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1504	&& enmGuestMode >= PGMMODE_PROTECTED)
1505	{
1506	PCPUMCTX pCtx;
1507
1508	pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1509
1510	/* After a real mode switch to protected mode we must force
1511	* CPL to 0. Our real mode emulation had to set it to 3.
1512	*/
1513	pCtx->ssHid.Attr.n.u2Dpl = 0;
1514	}
1515	}
1516
1517	if (pVCpu->hwaccm.s.vmx.enmCurrGuestMode != enmGuestMode)
1518	{
1519	/* Keep track of paging mode changes. */
1520	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = pVCpu->hwaccm.s.vmx.enmCurrGuestMode;
1521	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = enmGuestMode;
1522
1523	/* Did we miss a change, because all code was executed in the recompiler? */
1524	if (pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1525	{
1526	Log(("HWACCMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hwaccm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode)));
1527	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = pVCpu->hwaccm.s.vmx.enmPrevGuestMode;
1528	}
1529	}
1530
1531	/* Reset the contents of the read cache. */
1532	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1533	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1534	pCache->Read.aFieldVal[j] = 0;
1535	}
1536
1537	/**
1538	* Terminates the HWACCM.
1539	*
1540	* Termination means cleaning up and freeing all resources,
1541	* the VM it self is at this point powered off or suspended.
1542	*
1543	* @returns VBox status code.
1544	* @param pVM The VM to operate on.
1545	*/
1546	VMMR3DECL(int) HWACCMR3Term(PVM pVM)
1547	{
1548	if (pVM->hwaccm.s.vmx.pRealModeTSS)
1549	{
1550	PDMR3VMMDevHeapFree(pVM, pVM->hwaccm.s.vmx.pRealModeTSS);
1551	pVM->hwaccm.s.vmx.pRealModeTSS = 0;
1552	}
1553	hwaccmR3TermCPU(pVM);
1554	return 0;
1555	}
1556
1557	/**
1558	* Terminates the per-VCPU HWACCM.
1559	*
1560	* @returns VBox status code.
1561	* @param pVM The VM to operate on.
1562	*/
1563	static int hwaccmR3TermCPU(PVM pVM)
1564	{
1565	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1566	{
1567	PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1568
1569	#ifdef VBOX_WITH_STATISTICS
1570	if (pVCpu->hwaccm.s.paStatExitReason)
1571	{
1572	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatExitReason);
1573	pVCpu->hwaccm.s.paStatExitReason = NULL;
1574	pVCpu->hwaccm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1575	}
1576	if (pVCpu->hwaccm.s.paStatInjectedIrqs)
1577	{
1578	MMHyperFree(pVM, pVCpu->hwaccm.s.paStatInjectedIrqs);
1579	pVCpu->hwaccm.s.paStatInjectedIrqs = NULL;
1580	pVCpu->hwaccm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1581	}
1582	#endif
1583
1584	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1585	memset(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hwaccm.s.vmx.VMCSCache.aMagic));
1586	pVCpu->hwaccm.s.vmx.VMCSCache.uMagic = 0;
1587	pVCpu->hwaccm.s.vmx.VMCSCache.uPos = 0xffffffff;
1588	#endif
1589	}
1590	return 0;
1591	}
1592
1593	/**
1594	* Resets a virtual CPU.
1595	*
1596	* Used by HWACCMR3Reset and CPU hot plugging.
1597	*
1598	* @param pVCpu The CPU to reset.
1599	*/
1600	VMMR3DECL(void) HWACCMR3ResetCpu(PVMCPU pVCpu)
1601	{
1602	/* On first entry we'll sync everything. */
1603	pVCpu->hwaccm.s.fContextUseFlags = HWACCM_CHANGED_ALL;
1604
1605	pVCpu->hwaccm.s.vmx.cr0_mask = 0;
1606	pVCpu->hwaccm.s.vmx.cr4_mask = 0;
1607
1608	pVCpu->hwaccm.s.fActive = false;
1609	pVCpu->hwaccm.s.Event.fPending = false;
1610
1611	/* Reset state information for real-mode emulation in VT-x. */
1612	pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1613	pVCpu->hwaccm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1614	pVCpu->hwaccm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1615
1616	/* Reset the contents of the read cache. */
1617	PVMCSCACHE pCache = &pVCpu->hwaccm.s.vmx.VMCSCache;
1618	for (unsigned j=0;j<pCache->Read.cValidEntries;j++)
1619	pCache->Read.aFieldVal[j] = 0;
1620
1621	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1622	/* Magic marker for searching in crash dumps. */
1623	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1624	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1625	#endif
1626	}
1627
1628	/**
1629	* The VM is being reset.
1630	*
1631	* For the HWACCM component this means that any GDT/LDT/TSS monitors
1632	* needs to be removed.
1633	*
1634	* @param pVM VM handle.
1635	*/
1636	VMMR3DECL(void) HWACCMR3Reset(PVM pVM)
1637	{
1638	LogFlow(("HWACCMR3Reset:\n"));
1639
1640	if (pVM->fHWACCMEnabled)
1641	hwaccmR3DisableRawMode(pVM);
1642
1643	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1644	{
1645	PVMCPU pVCpu = &pVM->aCpus[i];
1646
1647	HWACCMR3ResetCpu(pVCpu);
1648	}
1649
1650	/* Clear all patch information. */
1651	pVM->hwaccm.s.pGuestPatchMem = 0;
1652	pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1653	pVM->hwaccm.s.cbGuestPatchMem = 0;
1654	pVM->hwaccm.s.cPatches = 0;
1655	pVM->hwaccm.s.PatchTree = 0;
1656	pVM->hwaccm.s.fTPRPatchingActive = false;
1657	ASMMemZero32(pVM->hwaccm.s.aPatches, sizeof(pVM->hwaccm.s.aPatches));
1658	}
1659
1660	/**
1661	* Callback to patch a TPR instruction (vmmcall or mov cr8)
1662	*
1663	* @returns VBox strict status code.
1664	* @param pVM The VM handle.
1665	* @param pVCpu The VMCPU for the EMT we're being called on.
1666	* @param pvUser Unused
1667	*
1668	*/
1669	DECLCALLBACK(VBOXSTRICTRC) hwaccmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1670	{
1671	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1672
1673	/* Only execute the handler on the VCPU the original patch request was issued. */
1674	if (pVCpu->idCpu != idCpu)
1675	return VINF_SUCCESS;
1676
1677	Log(("hwaccmR3RemovePatches\n"));
1678	for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
1679	{
1680	uint8_t szInstr[15];
1681	PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
1682	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1683	int rc;
1684
1685	#ifdef LOG_ENABLED
1686	char szOutput[256];
1687
1688	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1689	szOutput, sizeof(szOutput), NULL);
1690	if (RT_SUCCESS(rc))
1691	Log(("Patched instr: %s\n", szOutput));
1692	#endif
1693
1694	/* Check if the instruction is still the same. */
1695	rc = PGMPhysSimpleReadGCPtr(pVCpu, szInstr, pInstrGC, pPatch->cbNewOp);
1696	if (rc != VINF_SUCCESS)
1697	{
1698	Log(("Patched code removed? (rc=%Rrc0\n", rc));
1699	continue; /* swapped out or otherwise removed; skip it. */
1700	}
1701
1702	if (memcmp(szInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1703	{
1704	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1705	continue; /* skip it. */
1706	}
1707
1708	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1709	AssertRC(rc);
1710
1711	#ifdef LOG_ENABLED
1712	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1713	szOutput, sizeof(szOutput), NULL);
1714	if (RT_SUCCESS(rc))
1715	Log(("Original instr: %s\n", szOutput));
1716	#endif
1717	}
1718	pVM->hwaccm.s.cPatches = 0;
1719	pVM->hwaccm.s.PatchTree = 0;
1720	pVM->hwaccm.s.pFreeGuestPatchMem = pVM->hwaccm.s.pGuestPatchMem;
1721	pVM->hwaccm.s.fTPRPatchingActive = false;
1722	return VINF_SUCCESS;
1723	}
1724
1725	/**
1726	* Enable patching in a VT-x/AMD-V guest
1727	*
1728	* @returns VBox status code.
1729	* @param pVM The VM to operate on.
1730	* @param idCpu VCPU to execute hwaccmR3RemovePatches on
1731	* @param pPatchMem Patch memory range
1732	* @param cbPatchMem Size of the memory range
1733	*/
1734	int hwaccmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1735	{
1736	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)idCpu);
1737	AssertRC(rc);
1738
1739	pVM->hwaccm.s.pGuestPatchMem = pPatchMem;
1740	pVM->hwaccm.s.pFreeGuestPatchMem = pPatchMem;
1741	pVM->hwaccm.s.cbGuestPatchMem = cbPatchMem;
1742	return VINF_SUCCESS;
1743	}
1744
1745	/**
1746	* Enable patching in a VT-x/AMD-V guest
1747	*
1748	* @returns VBox status code.
1749	* @param pVM The VM to operate on.
1750	* @param pPatchMem Patch memory range
1751	* @param cbPatchMem Size of the memory range
1752	*/
1753	VMMR3DECL(int) HWACMMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1754	{
1755	VM_ASSERT_EMT(pVM);
1756	Log(("HWACMMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1757	if (pVM->cCpus > 1)
1758	{
1759	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1760	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1761	(PFNRT)hwaccmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1762	AssertRC(rc);
1763	return rc;
1764	}
1765	return hwaccmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1766	}
1767
1768	/**
1769	* Disable patching in a VT-x/AMD-V guest
1770	*
1771	* @returns VBox status code.
1772	* @param pVM The VM to operate on.
1773	* @param pPatchMem Patch memory range
1774	* @param cbPatchMem Size of the memory range
1775	*/
1776	VMMR3DECL(int) HWACMMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1777	{
1778	Log(("HWACMMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1779
1780	Assert(pVM->hwaccm.s.pGuestPatchMem == pPatchMem);
1781	Assert(pVM->hwaccm.s.cbGuestPatchMem == cbPatchMem);
1782
1783	/* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1784	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hwaccmR3RemovePatches, (void *)(uintptr_t)VMMGetCpuId(pVM));
1785	AssertRC(rc);
1786
1787	pVM->hwaccm.s.pGuestPatchMem = 0;
1788	pVM->hwaccm.s.pFreeGuestPatchMem = 0;
1789	pVM->hwaccm.s.cbGuestPatchMem = 0;
1790	pVM->hwaccm.s.fTPRPatchingActive = false;
1791	return VINF_SUCCESS;
1792	}
1793
1794
1795	/**
1796	* Callback to patch a TPR instruction (vmmcall or mov cr8)
1797	*
1798	* @returns VBox strict status code.
1799	* @param pVM The VM handle.
1800	* @param pVCpu The VMCPU for the EMT we're being called on.
1801	* @param pvUser User specified CPU context
1802	*
1803	*/
1804	DECLCALLBACK(VBOXSTRICTRC) hwaccmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1805	{
1806	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1807	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1808	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1809	unsigned cbOp;
1810
1811	/* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1812	if (pVCpu->idCpu != idCpu)
1813	return VINF_SUCCESS;
1814
1815	Log(("hwaccmR3ReplaceTprInstr: %RGv\n", pCtx->rip));
1816
1817	/* Two or more VCPUs were racing to patch this instruction. */
1818	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1819	if (pPatch)
1820	return VINF_SUCCESS;
1821
1822	Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1823
1824	int rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1825	AssertRC(rc);
1826	if ( rc == VINF_SUCCESS
1827	&& pDis->pCurInstr->opcode == OP_MOV
1828	&& cbOp >= 3)
1829	{
1830	uint8_t aVMMCall[3] = { 0xf, 0x1, 0xd9};
1831	uint32_t idx = pVM->hwaccm.s.cPatches;
1832
1833	pPatch = &pVM->hwaccm.s.aPatches[idx];
1834
1835	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1836	AssertRC(rc);
1837
1838	pPatch->cbOp = cbOp;
1839
1840	if (pDis->param1.flags == USE_DISPLACEMENT32)
1841	{
1842	/* write. */
1843	if (pDis->param2.flags == USE_REG_GEN32)
1844	{
1845	pPatch->enmType = HWACCMTPRINSTR_WRITE_REG;
1846	pPatch->uSrcOperand = pDis->param2.base.reg_gen;
1847	}
1848	else
1849	{
1850	Assert(pDis->param2.flags == USE_IMMEDIATE32);
1851	pPatch->enmType = HWACCMTPRINSTR_WRITE_IMM;
1852	pPatch->uSrcOperand = pDis->param2.parval;
1853	}
1854	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1855	AssertRC(rc);
1856
1857	memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1858	pPatch->cbNewOp = sizeof(aVMMCall);
1859	}
1860	else
1861	{
1862	RTGCPTR oldrip = pCtx->rip;
1863	uint32_t oldcbOp = cbOp;
1864	uint32_t uMmioReg = pDis->param1.base.reg_gen;
1865
1866	/* read */
1867	Assert(pDis->param1.flags == USE_REG_GEN32);
1868
1869	/* Found:
1870	* mov eax, dword [fffe0080] (5 bytes)
1871	* Check if next instruction is:
1872	* shr eax, 4
1873	*/
1874	pCtx->rip += cbOp;
1875	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1876	pCtx->rip = oldrip;
1877	if ( rc == VINF_SUCCESS
1878	&& pDis->pCurInstr->opcode == OP_SHR
1879	&& pDis->param1.flags == USE_REG_GEN32
1880	&& pDis->param1.base.reg_gen == uMmioReg
1881	&& pDis->param2.flags == USE_IMMEDIATE8
1882	&& pDis->param2.parval == 4
1883	&& oldcbOp + cbOp < sizeof(pVM->hwaccm.s.aPatches[idx].aOpcode))
1884	{
1885	uint8_t szInstr[15];
1886
1887	/* Replacing two instructions now. */
1888	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, oldcbOp + cbOp);
1889	AssertRC(rc);
1890
1891	pPatch->cbOp = oldcbOp + cbOp;
1892
1893	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1894	szInstr[0] = 0xF0;
1895	szInstr[1] = 0x0F;
1896	szInstr[2] = 0x20;
1897	szInstr[3] = 0xC0 \| pDis->param1.base.reg_gen;
1898	for (unsigned i = 4; i < pPatch->cbOp; i++)
1899	szInstr[i] = 0x90; /* nop */
1900
1901	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, szInstr, pPatch->cbOp);
1902	AssertRC(rc);
1903
1904	memcpy(pPatch->aNewOpcode, szInstr, pPatch->cbOp);
1905	pPatch->cbNewOp = pPatch->cbOp;
1906
1907	Log(("Acceptable read/shr candidate!\n"));
1908	pPatch->enmType = HWACCMTPRINSTR_READ_SHR4;
1909	}
1910	else
1911	{
1912	pPatch->enmType = HWACCMTPRINSTR_READ;
1913	pPatch->uDstOperand = pDis->param1.base.reg_gen;
1914
1915	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, aVMMCall, sizeof(aVMMCall));
1916	AssertRC(rc);
1917
1918	memcpy(pPatch->aNewOpcode, aVMMCall, sizeof(aVMMCall));
1919	pPatch->cbNewOp = sizeof(aVMMCall);
1920	}
1921	}
1922
1923	pPatch->Core.Key = pCtx->eip;
1924	rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1925	AssertRC(rc);
1926
1927	pVM->hwaccm.s.cPatches++;
1928	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceSuccess);
1929	return VINF_SUCCESS;
1930	}
1931
1932	/* Save invalid patch, so we will not try again. */
1933	uint32_t idx = pVM->hwaccm.s.cPatches;
1934
1935	#ifdef LOG_ENABLED
1936	char szOutput[256];
1937	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1938	szOutput, sizeof(szOutput), NULL);
1939	if (RT_SUCCESS(rc))
1940	Log(("Failed to patch instr: %s\n", szOutput));
1941	#endif
1942
1943	pPatch = &pVM->hwaccm.s.aPatches[idx];
1944	pPatch->Core.Key = pCtx->eip;
1945	pPatch->enmType = HWACCMTPRINSTR_INVALID;
1946	rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
1947	AssertRC(rc);
1948	pVM->hwaccm.s.cPatches++;
1949	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRReplaceFailure);
1950	return VINF_SUCCESS;
1951	}
1952
1953	/**
1954	* Callback to patch a TPR instruction (jump to generated code)
1955	*
1956	* @returns VBox strict status code.
1957	* @param pVM The VM handle.
1958	* @param pVCpu The VMCPU for the EMT we're being called on.
1959	* @param pvUser User specified CPU context
1960	*
1961	*/
1962	DECLCALLBACK(VBOXSTRICTRC) hwaccmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1963	{
1964	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1965	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1966	PDISCPUSTATE pDis = &pVCpu->hwaccm.s.DisState;
1967	unsigned cbOp;
1968	int rc;
1969	#ifdef LOG_ENABLED
1970	RTGCPTR pInstr;
1971	char szOutput[256];
1972	#endif
1973
1974	/* Only execute the handler on the VCPU the original patch request was issued. (the other CPU(s) might not yet have switched to protected mode) */
1975	if (pVCpu->idCpu != idCpu)
1976	return VINF_SUCCESS;
1977
1978	Assert(pVM->hwaccm.s.cPatches < RT_ELEMENTS(pVM->hwaccm.s.aPatches));
1979
1980	/* Two or more VCPUs were racing to patch this instruction. */
1981	PHWACCMTPRPATCH pPatch = (PHWACCMTPRPATCH)RTAvloU32Get(&pVM->hwaccm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1982	if (pPatch)
1983	{
1984	Log(("hwaccmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1985	return VINF_SUCCESS;
1986	}
1987
1988	Log(("hwaccmR3PatchTprInstr %RGv\n", pCtx->rip));
1989
1990	rc = EMInterpretDisasOne(pVM, pVCpu, CPUMCTX2CORE(pCtx), pDis, &cbOp);
1991	AssertRC(rc);
1992	if ( rc == VINF_SUCCESS
1993	&& pDis->pCurInstr->opcode == OP_MOV
1994	&& cbOp >= 5)
1995	{
1996	uint32_t idx = pVM->hwaccm.s.cPatches;
1997	uint8_t aPatch[64];
1998	uint32_t off = 0;
1999
2000	pPatch = &pVM->hwaccm.s.aPatches[idx];
2001
2002	#ifdef LOG_ENABLED
2003	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2004	szOutput, sizeof(szOutput), NULL);
2005	if (RT_SUCCESS(rc))
2006	Log(("Original instr: %s\n", szOutput));
2007	#endif
2008
2009	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2010	AssertRC(rc);
2011
2012	pPatch->cbOp = cbOp;
2013	pPatch->enmType = HWACCMTPRINSTR_JUMP_REPLACEMENT;
2014
2015	if (pDis->param1.flags == USE_DISPLACEMENT32)
2016	{
2017	/*
2018	* TPR write:
2019	*
2020	* push ECX [51]
2021	* push EDX [52]
2022	* push EAX [50]
2023	* xor EDX,EDX [31 D2]
2024	* mov EAX,EAX [89 C0]
2025	* or
2026	* mov EAX,0000000CCh [B8 CC 00 00 00]
2027	* mov ECX,0C0000082h [B9 82 00 00 C0]
2028	* wrmsr [0F 30]
2029	* pop EAX [58]
2030	* pop EDX [5A]
2031	* pop ECX [59]
2032	* jmp return_address [E9 return_address]
2033	*
2034	*/
2035	bool fUsesEax = (pDis->param2.flags == USE_REG_GEN32 && pDis->param2.base.reg_gen == USE_REG_EAX);
2036
2037	aPatch[off++] = 0x51; /* push ecx */
2038	aPatch[off++] = 0x52; /* push edx */
2039	if (!fUsesEax)
2040	aPatch[off++] = 0x50; /* push eax */
2041	aPatch[off++] = 0x31; /* xor edx, edx */
2042	aPatch[off++] = 0xD2;
2043	if (pDis->param2.flags == USE_REG_GEN32)
2044	{
2045	if (!fUsesEax)
2046	{
2047	aPatch[off++] = 0x89; /* mov eax, src_reg */
2048	aPatch[off++] = MAKE_MODRM(3, pDis->param2.base.reg_gen, USE_REG_EAX);
2049	}
2050	}
2051	else
2052	{
2053	Assert(pDis->param2.flags == USE_IMMEDIATE32);
2054	aPatch[off++] = 0xB8; /* mov eax, immediate */
2055	(uint32_t )&aPatch[off] = pDis->param2.parval;
2056	off += sizeof(uint32_t);
2057	}
2058	aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2059	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2060	off += sizeof(uint32_t);
2061
2062	aPatch[off++] = 0x0F; /* wrmsr */
2063	aPatch[off++] = 0x30;
2064	if (!fUsesEax)
2065	aPatch[off++] = 0x58; /* pop eax */
2066	aPatch[off++] = 0x5A; /* pop edx */
2067	aPatch[off++] = 0x59; /* pop ecx */
2068	}
2069	else
2070	{
2071	/*
2072	* TPR read:
2073	*
2074	* push ECX [51]
2075	* push EDX [52]
2076	* push EAX [50]
2077	* mov ECX,0C0000082h [B9 82 00 00 C0]
2078	* rdmsr [0F 32]
2079	* mov EAX,EAX [89 C0]
2080	* pop EAX [58]
2081	* pop EDX [5A]
2082	* pop ECX [59]
2083	* jmp return_address [E9 return_address]
2084	*
2085	*/
2086	Assert(pDis->param1.flags == USE_REG_GEN32);
2087
2088	if (pDis->param1.base.reg_gen != USE_REG_ECX)
2089	aPatch[off++] = 0x51; /* push ecx */
2090	if (pDis->param1.base.reg_gen != USE_REG_EDX)
2091	aPatch[off++] = 0x52; /* push edx */
2092	if (pDis->param1.base.reg_gen != USE_REG_EAX)
2093	aPatch[off++] = 0x50; /* push eax */
2094
2095	aPatch[off++] = 0x31; /* xor edx, edx */
2096	aPatch[off++] = 0xD2;
2097
2098	aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2099	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2100	off += sizeof(uint32_t);
2101
2102	aPatch[off++] = 0x0F; /* rdmsr */
2103	aPatch[off++] = 0x32;
2104
2105	if (pDis->param1.base.reg_gen != USE_REG_EAX)
2106	{
2107	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2108	aPatch[off++] = MAKE_MODRM(3, USE_REG_EAX, pDis->param1.base.reg_gen);
2109	}
2110
2111	if (pDis->param1.base.reg_gen != USE_REG_EAX)
2112	aPatch[off++] = 0x58; /* pop eax */
2113	if (pDis->param1.base.reg_gen != USE_REG_EDX)
2114	aPatch[off++] = 0x5A; /* pop edx */
2115	if (pDis->param1.base.reg_gen != USE_REG_ECX)
2116	aPatch[off++] = 0x59; /* pop ecx */
2117	}
2118	aPatch[off++] = 0xE9; /* jmp return_address */
2119	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem + off + 4);
2120	off += sizeof(RTRCUINTPTR);
2121
2122	if (pVM->hwaccm.s.pFreeGuestPatchMem + off <= pVM->hwaccm.s.pGuestPatchMem + pVM->hwaccm.s.cbGuestPatchMem)
2123	{
2124	/* Write new code to the patch buffer. */
2125	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hwaccm.s.pFreeGuestPatchMem, aPatch, off);
2126	AssertRC(rc);
2127
2128	#ifdef LOG_ENABLED
2129	pInstr = pVM->hwaccm.s.pFreeGuestPatchMem;
2130	while (true)
2131	{
2132	uint32_t cb;
2133
2134	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2135	szOutput, sizeof(szOutput), &cb);
2136	if (RT_SUCCESS(rc))
2137	Log(("Patch instr %s\n", szOutput));
2138
2139	pInstr += cb;
2140
2141	if (pInstr >= pVM->hwaccm.s.pFreeGuestPatchMem + off)
2142	break;
2143	}
2144	#endif
2145
2146	pPatch->aNewOpcode[0] = 0xE9;
2147	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hwaccm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2148
2149	/* Overwrite the TPR instruction with a jump. */
2150	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2151	AssertRC(rc);
2152
2153	#ifdef LOG_ENABLED
2154	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2155	szOutput, sizeof(szOutput), NULL);
2156	if (RT_SUCCESS(rc))
2157	Log(("Jump: %s\n", szOutput));
2158	#endif
2159	pVM->hwaccm.s.pFreeGuestPatchMem += off;
2160	pPatch->cbNewOp = 5;
2161
2162	pPatch->Core.Key = pCtx->eip;
2163	rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2164	AssertRC(rc);
2165
2166	pVM->hwaccm.s.cPatches++;
2167	pVM->hwaccm.s.fTPRPatchingActive = true;
2168	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchSuccess);
2169	return VINF_SUCCESS;
2170	}
2171	else
2172	Log(("Ran out of space in our patch buffer!\n"));
2173	}
2174
2175	/* Save invalid patch, so we will not try again. */
2176	uint32_t idx = pVM->hwaccm.s.cPatches;
2177
2178	#ifdef LOG_ENABLED
2179	rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs, pCtx->rip, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2180	szOutput, sizeof(szOutput), NULL);
2181	if (RT_SUCCESS(rc))
2182	Log(("Failed to patch instr: %s\n", szOutput));
2183	#endif
2184
2185	pPatch = &pVM->hwaccm.s.aPatches[idx];
2186	pPatch->Core.Key = pCtx->eip;
2187	pPatch->enmType = HWACCMTPRINSTR_INVALID;
2188	rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2189	AssertRC(rc);
2190	pVM->hwaccm.s.cPatches++;
2191	STAM_COUNTER_INC(&pVM->hwaccm.s.StatTPRPatchFailure);
2192	return VINF_SUCCESS;
2193	}
2194
2195	/**
2196	* Attempt to patch TPR mmio instructions
2197	*
2198	* @returns VBox status code.
2199	* @param pVM The VM to operate on.
2200	* @param pVCpu The VM CPU to operate on.
2201	* @param pCtx CPU context
2202	*/
2203	VMMR3DECL(int) HWACCMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2204	{
2205	NOREF(pCtx);
2206	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2207	pVM->hwaccm.s.pGuestPatchMem ? hwaccmR3PatchTprInstr : hwaccmR3ReplaceTprInstr,
2208	(void *)(uintptr_t)pVCpu->idCpu);
2209	AssertRC(rc);
2210	return rc;
2211	}
2212
2213	/**
2214	* Force execution of the current IO code in the recompiler
2215	*
2216	* @returns VBox status code.
2217	* @param pVM The VM to operate on.
2218	* @param pCtx Partial VM execution context
2219	*/
2220	VMMR3DECL(int) HWACCMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2221	{
2222	PVMCPU pVCpu = VMMGetCpu(pVM);
2223
2224	Assert(pVM->fHWACCMEnabled);
2225	Log(("HWACCMR3EmulateIoBlock\n"));
2226
2227	/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2228	if (HWACCMCanEmulateIoBlockEx(pCtx))
2229	{
2230	Log(("HWACCMR3EmulateIoBlock -> enabled\n"));
2231	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = true;
2232	pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2233	pVCpu->hwaccm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2234	return VINF_EM_RESCHEDULE_REM;
2235	}
2236	return VINF_SUCCESS;
2237	}
2238
2239	/**
2240	* Checks if we can currently use hardware accelerated raw mode.
2241	*
2242	* @returns boolean
2243	* @param pVM The VM to operate on.
2244	* @param pCtx Partial VM execution context
2245	*/
2246	VMMR3DECL(bool) HWACCMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2247	{
2248	PVMCPU pVCpu = VMMGetCpu(pVM);
2249
2250	Assert(pVM->fHWACCMEnabled);
2251
2252	/* If we're still executing the IO code, then return false. */
2253	if ( RT_UNLIKELY(pVCpu->hwaccm.s.EmulateIoBlock.fEnabled)
2254	&& pCtx->rip < pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2255	&& pCtx->rip > pVCpu->hwaccm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2256	&& pCtx->cr0 == pVCpu->hwaccm.s.EmulateIoBlock.cr0)
2257	return false;
2258
2259	pVCpu->hwaccm.s.EmulateIoBlock.fEnabled = false;
2260
2261	/* AMD-V supports real & protected mode with or without paging. */
2262	if (pVM->hwaccm.s.svm.fEnabled)
2263	{
2264	pVCpu->hwaccm.s.fActive = true;
2265	return true;
2266	}
2267
2268	pVCpu->hwaccm.s.fActive = false;
2269
2270	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2271	Assert((pVM->hwaccm.s.vmx.fUnrestrictedGuest && !pVM->hwaccm.s.vmx.pRealModeTSS) \|\| (!pVM->hwaccm.s.vmx.fUnrestrictedGuest && pVM->hwaccm.s.vmx.pRealModeTSS));
2272
2273	bool fSupportsRealMode = pVM->hwaccm.s.vmx.fUnrestrictedGuest \|\| PDMVMMDevHeapIsEnabled(pVM);
2274	if (!pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2275	{
2276	/** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. */
2277	if (fSupportsRealMode)
2278	{
2279	if (CPUMIsGuestInRealModeEx(pCtx))
2280	{
2281	/* VT-x will not allow high selector bases in v86 mode; fall back to the recompiler in that case.
2282	* The base must also be equal to (sel << 4).
2283	*/
2284	if ( ( pCtx->cs != (pCtx->csHid.u64Base >> 4)
2285	&& pCtx->csHid.u64Base != 0xffff0000 /* we can deal with the BIOS code as it's also mapped into the lower region. */)
2286	\|\| (pCtx->csHid.u32Limit != 0xffff)
2287	\|\| (pCtx->dsHid.u32Limit != 0xffff)
2288	\|\| (pCtx->esHid.u32Limit != 0xffff)
2289	\|\| (pCtx->ssHid.u32Limit != 0xffff)
2290	\|\| (pCtx->fsHid.u32Limit != 0xffff)
2291	\|\| (pCtx->gsHid.u32Limit != 0xffff)
2292	\|\| pCtx->ds != (pCtx->dsHid.u64Base >> 4)
2293	\|\| pCtx->es != (pCtx->esHid.u64Base >> 4)
2294	\|\| pCtx->fs != (pCtx->fsHid.u64Base >> 4)
2295	\|\| pCtx->gs != (pCtx->gsHid.u64Base >> 4)
2296	\|\| pCtx->ss != (pCtx->ssHid.u64Base >> 4))
2297	{
2298	return false;
2299	}
2300	}
2301	else
2302	{
2303	PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2304	/* Verify the requirements for executing code in protected mode. VT-x can't handle the CPU state right after a switch
2305	* from real to protected mode. (all sorts of RPL & DPL assumptions)
2306	*/
2307	if ( pVCpu->hwaccm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2308	&& enmGuestMode >= PGMMODE_PROTECTED)
2309	{
2310	if ( (pCtx->cs & X86_SEL_RPL)
2311	\|\| (pCtx->ds & X86_SEL_RPL)
2312	\|\| (pCtx->es & X86_SEL_RPL)
2313	\|\| (pCtx->fs & X86_SEL_RPL)
2314	\|\| (pCtx->gs & X86_SEL_RPL)
2315	\|\| (pCtx->ss & X86_SEL_RPL))
2316	{
2317	return false;
2318	}
2319	}
2320	/* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2321	if ( pCtx->gdtr.cbGdt
2322	&& ( pCtx->tr > pCtx->gdtr.cbGdt
2323	\|\| pCtx->ldtr > pCtx->gdtr.cbGdt))
2324	{
2325	return false;
2326	}
2327	}
2328	}
2329	else
2330	{
2331	if ( !CPUMIsGuestInLongModeEx(pCtx)
2332	&& !pVM->hwaccm.s.vmx.fUnrestrictedGuest)
2333	{
2334	/** @todo This should (probably) be set on every excursion to the REM,
2335	* however it's too risky right now. So, only apply it when we go
2336	* back to REM for real mode execution. (The XP hack below doesn't
2337	* work reliably without this.)
2338	* Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HWACCM. */
2339	pVM->aCpus[0].hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
2340
2341	if ( !pVM->hwaccm.s.fNestedPaging /* requires a fake PD for real and protected mode without paging - stored in the VMM device heap*/
2342	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2343	return false;
2344
2345	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2346	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr == 0)
2347	return false;
2348
2349	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2350	/* Windows XP; switch to protected mode; all selectors are marked not present in the
2351	* hidden registers (possible recompiler bug; see load_seg_vm) */
2352	if (pCtx->csHid.Attr.n.u1Present == 0)
2353	return false;
2354	if (pCtx->ssHid.Attr.n.u1Present == 0)
2355	return false;
2356
2357	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
2358	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2359	/** @todo This check is actually wrong, it doesn't take the direction of the
2360	* stack segment into account. But, it does the job for now. */
2361	if (pCtx->rsp >= pCtx->ssHid.u32Limit)
2362	return false;
2363	#if 0
2364	if ( pCtx->cs >= pCtx->gdtr.cbGdt
2365	\|\| pCtx->ss >= pCtx->gdtr.cbGdt
2366	\|\| pCtx->ds >= pCtx->gdtr.cbGdt
2367	\|\| pCtx->es >= pCtx->gdtr.cbGdt
2368	\|\| pCtx->fs >= pCtx->gdtr.cbGdt
2369	\|\| pCtx->gs >= pCtx->gdtr.cbGdt)
2370	return false;
2371	#endif
2372	}
2373	}
2374	}
2375
2376	if (pVM->hwaccm.s.vmx.fEnabled)
2377	{
2378	uint32_t mask;
2379
2380	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2381	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed0;
2382	/* Note: We ignore the NE bit here on purpose; see vmmr0\hwaccmr0.cpp for details. */
2383	mask &= ~X86_CR0_NE;
2384
2385	if (fSupportsRealMode)
2386	{
2387	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2388	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
2389	}
2390	else
2391	{
2392	/* We support protected mode without paging using identity mapping. */
2393	mask &= ~X86_CR0_PG;
2394	}
2395	if ((pCtx->cr0 & mask) != mask)
2396	return false;
2397
2398	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2399	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr0_fixed1;
2400	if ((pCtx->cr0 & mask) != 0)
2401	return false;
2402
2403	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2404	mask = (uint32_t)pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed0;
2405	mask &= ~X86_CR4_VMXE;
2406	if ((pCtx->cr4 & mask) != mask)
2407	return false;
2408
2409	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2410	mask = (uint32_t)~pVM->hwaccm.s.vmx.msr.vmx_cr4_fixed1;
2411	if ((pCtx->cr4 & mask) != 0)
2412	return false;
2413
2414	pVCpu->hwaccm.s.fActive = true;
2415	return true;
2416	}
2417
2418	return false;
2419	}
2420
2421	/**
2422	* Checks if we need to reschedule due to VMM device heap changes
2423	*
2424	* @returns boolean
2425	* @param pVM The VM to operate on.
2426	* @param pCtx VM execution context
2427	*/
2428	VMMR3DECL(bool) HWACCMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2429	{
2430	/** The VMM device heap is a requirement for emulating real mode or protected mode without paging when the unrestricted guest execution feature is missing. (VT-x only) */
2431	if ( pVM->hwaccm.s.vmx.fEnabled
2432	&& !pVM->hwaccm.s.vmx.fUnrestrictedGuest
2433	&& !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2434	&& !PDMVMMDevHeapIsEnabled(pVM)
2435	&& (pVM->hwaccm.s.fNestedPaging \|\| CPUMIsGuestInRealModeEx(pCtx)))
2436	return true;
2437
2438	return false;
2439	}
2440
2441
2442	/**
2443	* Notification from EM about a rescheduling into hardware assisted execution
2444	* mode.
2445	*
2446	* @param pVCpu Pointer to the current virtual cpu structure.
2447	*/
2448	VMMR3DECL(void) HWACCMR3NotifyScheduled(PVMCPU pVCpu)
2449	{
2450	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
2451	}
2452
2453	/**
2454	* Notification from EM about returning from instruction emulation (REM / EM).
2455	*
2456	* @param pVCpu Pointer to the current virtual cpu structure.
2457	*/
2458	VMMR3DECL(void) HWACCMR3NotifyEmulated(PVMCPU pVCpu)
2459	{
2460	pVCpu->hwaccm.s.fContextUseFlags \|= HWACCM_CHANGED_ALL_GUEST;
2461	}
2462
2463	/**
2464	* Checks if we are currently using hardware accelerated raw mode.
2465	*
2466	* @returns boolean
2467	* @param pVCpu The VMCPU to operate on.
2468	*/
2469	VMMR3DECL(bool) HWACCMR3IsActive(PVMCPU pVCpu)
2470	{
2471	return pVCpu->hwaccm.s.fActive;
2472	}
2473
2474	/**
2475	* Checks if we are currently using nested paging.
2476	*
2477	* @returns boolean
2478	* @param pVM The VM to operate on.
2479	*/
2480	VMMR3DECL(bool) HWACCMR3IsNestedPagingActive(PVM pVM)
2481	{
2482	return pVM->hwaccm.s.fNestedPaging;
2483	}
2484
2485	/**
2486	* Checks if we are currently using VPID in VT-x mode.
2487	*
2488	* @returns boolean
2489	* @param pVM The VM to operate on.
2490	*/
2491	VMMR3DECL(bool) HWACCMR3IsVPIDActive(PVM pVM)
2492	{
2493	return pVM->hwaccm.s.vmx.fVPID;
2494	}
2495
2496
2497	/**
2498	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2499	*
2500	* @returns boolean
2501	* @param pVM The VM to operate on.
2502	*/
2503	VMMR3DECL(bool) HWACCMR3IsEventPending(PVMCPU pVCpu)
2504	{
2505	return HWACCMIsEnabled(pVCpu->pVMR3) && pVCpu->hwaccm.s.Event.fPending;
2506	}
2507
2508	/**
2509	* Checks if the VMX-preemption timer is being used.
2510	*
2511	* @returns true if it is, false if it isn't.
2512	* @param pVM The VM handle.
2513	*/
2514	VMMR3DECL(bool) HWACCMR3IsVmxPreemptionTimerUsed(PVM pVM)
2515	{
2516	return HWACCMIsEnabled(pVM)
2517	&& pVM->hwaccm.s.vmx.fEnabled
2518	&& pVM->hwaccm.s.vmx.fUsePreemptTimer;
2519	}
2520
2521	/**
2522	* Restart an I/O instruction that was refused in ring-0
2523	*
2524	* @returns Strict VBox status code. Informational status codes other than the one documented
2525	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2526	* @retval VINF_SUCCESS Success.
2527	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2528	* status code must be passed on to EM.
2529	* @retval VERR_NOT_FOUND if no pending I/O instruction.
2530	*
2531	* @param pVM The VM to operate on.
2532	* @param pVCpu The VMCPU to operate on.
2533	* @param pCtx VCPU register context
2534	*/
2535	VMMR3DECL(VBOXSTRICTRC) HWACCMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2536	{
2537	HWACCMPENDINGIO enmType = pVCpu->hwaccm.s.PendingIO.enmType;
2538
2539	pVCpu->hwaccm.s.PendingIO.enmType = HWACCMPENDINGIO_INVALID;
2540
2541	if ( pVCpu->hwaccm.s.PendingIO.GCPtrRip != pCtx->rip
2542	\|\| enmType == HWACCMPENDINGIO_INVALID)
2543	return VERR_NOT_FOUND;
2544
2545	VBOXSTRICTRC rcStrict;
2546	switch (enmType)
2547	{
2548	case HWACCMPENDINGIO_PORT_READ:
2549	{
2550	uint32_t uAndVal = pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal;
2551	uint32_t u32Val = 0;
2552
2553	rcStrict = IOMIOPortRead(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2554	&u32Val,
2555	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2556	if (IOM_SUCCESS(rcStrict))
2557	{
2558	/* Write back to the EAX register. */
2559	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2560	pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2561	}
2562	break;
2563	}
2564
2565	case HWACCMPENDINGIO_PORT_WRITE:
2566	rcStrict = IOMIOPortWrite(pVM, pVCpu->hwaccm.s.PendingIO.s.Port.uPort,
2567	pCtx->eax & pVCpu->hwaccm.s.PendingIO.s.Port.uAndVal,
2568	pVCpu->hwaccm.s.PendingIO.s.Port.cbSize);
2569	if (IOM_SUCCESS(rcStrict))
2570	pCtx->rip = pVCpu->hwaccm.s.PendingIO.GCPtrRipNext;
2571	break;
2572
2573	default:
2574	AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2575	}
2576
2577	return rcStrict;
2578	}
2579
2580	/**
2581	* Inject an NMI into a running VM (only VCPU 0!)
2582	*
2583	* @returns boolean
2584	* @param pVM The VM to operate on.
2585	*/
2586	VMMR3DECL(int) HWACCMR3InjectNMI(PVM pVM)
2587	{
2588	VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2589	return VINF_SUCCESS;
2590	}
2591
2592	/**
2593	* Check fatal VT-x/AMD-V error and produce some meaningful
2594	* log release message.
2595	*
2596	* @param pVM The VM to operate on.
2597	* @param iStatusCode VBox status code
2598	*/
2599	VMMR3DECL(void) HWACCMR3CheckError(PVM pVM, int iStatusCode)
2600	{
2601	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2602	{
2603	switch(iStatusCode)
2604	{
2605	case VERR_VMX_INVALID_VMCS_FIELD:
2606	break;
2607
2608	case VERR_VMX_INVALID_VMCS_PTR:
2609	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hwaccm.s.vmx.HCPhysVMCS));
2610	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulVMCSRevision));
2611	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idEnteredCpu));
2612	LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.idCurrentCpu));
2613	break;
2614
2615	case VERR_VMX_UNABLE_TO_START_VM:
2616	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2617	LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2618	#if 0 /* @todo dump the current control fields to the release log */
2619	if (pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2620	{
2621
2622	}
2623	#endif
2624	break;
2625
2626	case VERR_VMX_UNABLE_TO_RESUME_VM:
2627	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulInstrError));
2628	LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hwaccm.s.vmx.lasterror.ulExitReason));
2629	break;
2630
2631	case VERR_VMX_INVALID_VMXON_PTR:
2632	break;
2633	}
2634	}
2635	}
2636
2637	/**
2638	* Execute state save operation.
2639	*
2640	* @returns VBox status code.
2641	* @param pVM VM Handle.
2642	* @param pSSM SSM operation handle.
2643	*/
2644	static DECLCALLBACK(int) hwaccmR3Save(PVM pVM, PSSMHANDLE pSSM)
2645	{
2646	int rc;
2647
2648	Log(("hwaccmR3Save:\n"));
2649
2650	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2651	{
2652	/*
2653	* Save the basic bits - fortunately all the other things can be resynced on load.
2654	*/
2655	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.fPending);
2656	AssertRCReturn(rc, rc);
2657	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.Event.errCode);
2658	AssertRCReturn(rc, rc);
2659	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hwaccm.s.Event.intInfo);
2660	AssertRCReturn(rc, rc);
2661
2662	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode);
2663	AssertRCReturn(rc, rc);
2664	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode);
2665	AssertRCReturn(rc, rc);
2666	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode);
2667	AssertRCReturn(rc, rc);
2668	}
2669	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2670	rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pGuestPatchMem);
2671	AssertRCReturn(rc, rc);
2672	rc = SSMR3PutGCPtr(pSSM, pVM->hwaccm.s.pFreeGuestPatchMem);
2673	AssertRCReturn(rc, rc);
2674	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cbGuestPatchMem);
2675	AssertRCReturn(rc, rc);
2676
2677	/* Store all the guest patch records too. */
2678	rc = SSMR3PutU32(pSSM, pVM->hwaccm.s.cPatches);
2679	AssertRCReturn(rc, rc);
2680
2681	for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2682	{
2683	PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2684
2685	rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2686	AssertRCReturn(rc, rc);
2687
2688	rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2689	AssertRCReturn(rc, rc);
2690
2691	rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2692	AssertRCReturn(rc, rc);
2693
2694	rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2695	AssertRCReturn(rc, rc);
2696
2697	rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2698	AssertRCReturn(rc, rc);
2699
2700	AssertCompileSize(HWACCMTPRINSTR, 4);
2701	rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2702	AssertRCReturn(rc, rc);
2703
2704	rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2705	AssertRCReturn(rc, rc);
2706
2707	rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2708	AssertRCReturn(rc, rc);
2709
2710	rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2711	AssertRCReturn(rc, rc);
2712
2713	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2714	AssertRCReturn(rc, rc);
2715	}
2716	#endif
2717	return VINF_SUCCESS;
2718	}
2719
2720	/**
2721	* Execute state load operation.
2722	*
2723	* @returns VBox status code.
2724	* @param pVM VM Handle.
2725	* @param pSSM SSM operation handle.
2726	* @param uVersion Data layout version.
2727	* @param uPass The data pass.
2728	*/
2729	static DECLCALLBACK(int) hwaccmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2730	{
2731	int rc;
2732
2733	Log(("hwaccmR3Load:\n"));
2734	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2735
2736	/*
2737	* Validate version.
2738	*/
2739	if ( uVersion != HWACCM_SSM_VERSION
2740	&& uVersion != HWACCM_SSM_VERSION_NO_PATCHING
2741	&& uVersion != HWACCM_SSM_VERSION_2_0_X)
2742	{
2743	AssertMsgFailed(("hwaccmR3Load: Invalid version uVersion=%d!\n", uVersion));
2744	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2745	}
2746	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2747	{
2748	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.fPending);
2749	AssertRCReturn(rc, rc);
2750	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hwaccm.s.Event.errCode);
2751	AssertRCReturn(rc, rc);
2752	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hwaccm.s.Event.intInfo);
2753	AssertRCReturn(rc, rc);
2754
2755	if (uVersion >= HWACCM_SSM_VERSION_NO_PATCHING)
2756	{
2757	uint32_t val;
2758
2759	rc = SSMR3GetU32(pSSM, &val);
2760	AssertRCReturn(rc, rc);
2761	pVM->aCpus[i].hwaccm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2762
2763	rc = SSMR3GetU32(pSSM, &val);
2764	AssertRCReturn(rc, rc);
2765	pVM->aCpus[i].hwaccm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2766
2767	rc = SSMR3GetU32(pSSM, &val);
2768	AssertRCReturn(rc, rc);
2769	pVM->aCpus[i].hwaccm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2770	}
2771	}
2772	#ifdef VBOX_HWACCM_WITH_GUEST_PATCHING
2773	if (uVersion > HWACCM_SSM_VERSION_NO_PATCHING)
2774	{
2775	rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pGuestPatchMem);
2776	AssertRCReturn(rc, rc);
2777	rc = SSMR3GetGCPtr(pSSM, &pVM->hwaccm.s.pFreeGuestPatchMem);
2778	AssertRCReturn(rc, rc);
2779	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cbGuestPatchMem);
2780	AssertRCReturn(rc, rc);
2781
2782	/* Fetch all TPR patch records. */
2783	rc = SSMR3GetU32(pSSM, &pVM->hwaccm.s.cPatches);
2784	AssertRCReturn(rc, rc);
2785
2786	for (unsigned i = 0; i < pVM->hwaccm.s.cPatches; i++)
2787	{
2788	PHWACCMTPRPATCH pPatch = &pVM->hwaccm.s.aPatches[i];
2789
2790	rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2791	AssertRCReturn(rc, rc);
2792
2793	rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2794	AssertRCReturn(rc, rc);
2795
2796	rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2797	AssertRCReturn(rc, rc);
2798
2799	rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2800	AssertRCReturn(rc, rc);
2801
2802	rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2803	AssertRCReturn(rc, rc);
2804
2805	rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2806	AssertRCReturn(rc, rc);
2807
2808	if (pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT)
2809	pVM->hwaccm.s.fTPRPatchingActive = true;
2810
2811	Assert(pPatch->enmType == HWACCMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hwaccm.s.fTPRPatchingActive == false);
2812
2813	rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2814	AssertRCReturn(rc, rc);
2815
2816	rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2817	AssertRCReturn(rc, rc);
2818
2819	rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2820	AssertRCReturn(rc, rc);
2821
2822	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2823	AssertRCReturn(rc, rc);
2824
2825	Log(("hwaccmR3Load: patch %d\n", i));
2826	Log(("Key = %x\n", pPatch->Core.Key));
2827	Log(("cbOp = %d\n", pPatch->cbOp));
2828	Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2829	Log(("type = %d\n", pPatch->enmType));
2830	Log(("srcop = %d\n", pPatch->uSrcOperand));
2831	Log(("dstop = %d\n", pPatch->uDstOperand));
2832	Log(("cFaults = %d\n", pPatch->cFaults));
2833	Log(("target = %x\n", pPatch->pJumpTarget));
2834	rc = RTAvloU32Insert(&pVM->hwaccm.s.PatchTree, &pPatch->Core);
2835	AssertRC(rc);
2836	}
2837	}
2838	#endif
2839
2840	/* Recheck all VCPUs if we can go straight into hwaccm execution mode. */
2841	if (HWACCMIsEnabled(pVM))
2842	{
2843	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2844	{
2845	PVMCPU pVCpu = &pVM->aCpus[i];
2846
2847	HWACCMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2848	}
2849	}
2850	return VINF_SUCCESS;
2851	}
2852

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source: vbox/trunk/src/VBox/VMM/VMMR3/HWACCM.cpp@ 41173

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