VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 68155

Last change on this file since 68155 was 66650, checked in by vboxsync, 8 years ago

Reapplied the IEMR3.cpp part of r111975: Rename instruction stats.
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  • Property svn:keywords set to Author Date Id Revision
File size: 11.0 KB
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1/* $Id: IEMR3.cpp 66650 2017-04-22 09:28:16Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/iem.h>
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/mm.h>
26#include "IEMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30#include <iprt/asm-amd64-x86.h>
31#include <iprt/assert.h>
32
33static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
34{
35 switch (enmTargetCpu)
36 {
37#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
38 CASE_RET_STR(IEMTARGETCPU_8086);
39 CASE_RET_STR(IEMTARGETCPU_V20);
40 CASE_RET_STR(IEMTARGETCPU_186);
41 CASE_RET_STR(IEMTARGETCPU_286);
42 CASE_RET_STR(IEMTARGETCPU_386);
43 CASE_RET_STR(IEMTARGETCPU_486);
44 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
45 CASE_RET_STR(IEMTARGETCPU_PPRO);
46 CASE_RET_STR(IEMTARGETCPU_CURRENT);
47#undef CASE_RET_STR
48 default: return "Unknown";
49 }
50}
51
52/**
53 * Initializes the interpreted execution manager.
54 *
55 * This must be called after CPUM as we're quering information from CPUM about
56 * the guest and host CPUs.
57 *
58 * @returns VBox status code.
59 * @param pVM The cross context VM structure.
60 */
61VMMR3DECL(int) IEMR3Init(PVM pVM)
62{
63 uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
64 uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
65
66 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
67 {
68 PVMCPU pVCpu = &pVM->aCpus[idCpu];
69 pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
70 pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
71 pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
72
73 pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
74 pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
75
76 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
77 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
78 STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
79 "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
80 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
81 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
82 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
83 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
84 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
85 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
86 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
87 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
88 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
89 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
90 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
91 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
92 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
93 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
94
95#ifdef VBOX_WITH_STATISTICS
96 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
97 "Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
98 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
99 "Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
100#endif
101 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
102 "Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
103 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
104 "Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
105 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
106 "Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
107 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
108 "Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
109
110 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
111 "Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
112 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
113 "Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
114 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
115 "Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
116
117#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
118 /* Allocate instruction statistics and register them. */
119 pVCpu->iem.s.pStatsR3 = (PIEMINSTRSTATS)MMR3HeapAllocZ(pVM, MM_TAG_IEM, sizeof(IEMINSTRSTATS));
120 AssertLogRelReturn(pVCpu->iem.s.pStatsR3, VERR_NO_MEMORY);
121 int rc = MMHyperAlloc(pVM, sizeof(IEMINSTRSTATS), sizeof(uint64_t), MM_TAG_IEM, (void **)&pVCpu->iem.s.pStatsCCR3);
122 AssertLogRelRCReturn(rc, rc);
123 pVCpu->iem.s.pStatsR0 = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
124 pVCpu->iem.s.pStatsRC = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
125# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
126 STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsCCR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
127 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
128 STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
129 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
130# include "IEMInstructionStatisticsTmpl.h"
131# undef IEM_DO_INSTR_STAT
132#endif
133
134 /*
135 * Host and guest CPU information.
136 */
137 if (idCpu == 0)
138 {
139 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
140 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
141#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
142 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
143 {
144 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
145 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
146 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
147 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
148 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
149 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
150 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
151 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
152 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
153 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
154 }
155 LogRel(("IEM: TargetCpu=%s, Microarch=%s\n", iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMR3MicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch)));
156#endif
157 }
158 else
159 {
160 pVCpu->iem.s.enmCpuVendor = pVM->aCpus[0].iem.s.enmCpuVendor;
161 pVCpu->iem.s.enmHostCpuVendor = pVM->aCpus[0].iem.s.enmHostCpuVendor;
162#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
163 pVCpu->iem.s.uTargetCpu = pVM->aCpus[0].iem.s.uTargetCpu;
164#endif
165 }
166
167 /*
168 * Mark all buffers free.
169 */
170 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
171 while (iMemMap-- > 0)
172 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
173 }
174 return VINF_SUCCESS;
175}
176
177
178VMMR3DECL(int) IEMR3Term(PVM pVM)
179{
180 NOREF(pVM);
181#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
182 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
183 {
184 PVMCPU pVCpu = &pVM->aCpus[idCpu];
185 MMR3HeapFree(pVCpu->iem.s.pStatsR3);
186 pVCpu->iem.s.pStatsR3 = NULL;
187 }
188#endif
189 return VINF_SUCCESS;
190}
191
192
193VMMR3DECL(void) IEMR3Relocate(PVM pVM)
194{
195 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
196 {
197 pVM->aCpus[idCpu].iem.s.pCtxRC = VM_RC_ADDR(pVM, pVM->aCpus[idCpu].iem.s.pCtxR3);
198 if (pVM->aCpus[idCpu].iem.s.pStatsRC)
199 pVM->aCpus[idCpu].iem.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->aCpus[idCpu].iem.s.pStatsCCR3);
200 }
201}
202
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