IEMR3.cpp@ 100696

Last change on this file since 100696 was 100695, checked in by vboxsync, 17 months ago
VMM/IEM,STAM: Some TB stats. bugref:10369
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1	/* $Id: IEMR3.cpp 100695 2023-07-25 11:03:20Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#include <VBox/vmm/iem.h>
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/vmm/mm.h>
37	#if defined(VBOX_VMM_TARGET_ARMV8)
38	# include "IEMInternal-armv8.h"
39	#else
40	# include "IEMInternal.h"
41	#endif
42	#include <VBox/vmm/vm.h>
43	#include <VBox/vmm/vmapi.h>
44	#include <VBox/err.h>
45	#ifdef VBOX_WITH_DEBUGGER
46	# include <VBox/dbg.h>
47	#endif
48
49	#include <iprt/assert.h>
50	#include <iprt/getopt.h>
51	#include <iprt/string.h>
52
53
54	/*********************************************************************************************************************************
55	* Internal Functions *
56	*********************************************************************************************************************************/
57	static FNDBGFINFOARGVINT iemR3InfoITlb;
58	static FNDBGFINFOARGVINT iemR3InfoDTlb;
59	#ifdef VBOX_WITH_DEBUGGER
60	static void iemR3RegisterDebuggerCommands(void);
61	#endif
62
63
64	#if !defined(VBOX_VMM_TARGET_ARMV8)
65	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
66	{
67	switch (enmTargetCpu)
68	{
69	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
70	CASE_RET_STR(IEMTARGETCPU_8086);
71	CASE_RET_STR(IEMTARGETCPU_V20);
72	CASE_RET_STR(IEMTARGETCPU_186);
73	CASE_RET_STR(IEMTARGETCPU_286);
74	CASE_RET_STR(IEMTARGETCPU_386);
75	CASE_RET_STR(IEMTARGETCPU_486);
76	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
77	CASE_RET_STR(IEMTARGETCPU_PPRO);
78	CASE_RET_STR(IEMTARGETCPU_CURRENT);
79	#undef CASE_RET_STR
80	default: return "Unknown";
81	}
82	}
83	#endif
84
85
86	/**
87	* Initializes the interpreted execution manager.
88	*
89	* This must be called after CPUM as we're quering information from CPUM about
90	* the guest and host CPUs.
91	*
92	* @returns VBox status code.
93	* @param pVM The cross context VM structure.
94	*/
95	VMMR3DECL(int) IEMR3Init(PVM pVM)
96	{
97	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
98	/*
99	* Read configuration.
100	*/
101	PCFGMNODE pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
102
103	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
104	* Controls whether the custom VBox specific CPUID host call interface is
105	* enabled or not. */
106	# ifdef DEBUG_bird
107	int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
108	# else
109	int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
110	# endif
111	AssertLogRelRCReturn(rc, rc);
112	#endif
113
114	/*
115	* Initialize per-CPU data and register statistics.
116	*/
117	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
118	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
119
120	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
121	{
122	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
123	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
124
125	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
126	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
127
128	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
129	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
130	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
131	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
132	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
133	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
134	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
135	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
136	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
137	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
138	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
139	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
140	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
141	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
142	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
143	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
144	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
145	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
146
147	#ifdef VBOX_WITH_STATISTICS
148	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
149	"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
150	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
151	"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
152	#endif
153	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
154	"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
155	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
156	"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
157	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
158	"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
159	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
160	"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
161
162	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
163	"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
164	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
165	"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
166	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
167	"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
168
169
170	#ifdef VBOX_WITH_IEM_RECOMPILER
171	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExec, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
172	"Executed translation block", "/IEM/CPU%u/cTbExec", idCpu);
173	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbAllocs, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
174	"Translation block allocations", "/IEM/CPU%u/cTbAllocs", idCpu);
175	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbFrees, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
176	"Translation block frees", "/IEM/CPU%u/cTbFrees", idCpu);
177	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbLookupHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
178	"Translation block lookup hits", "/IEM/CPU%u/cTbLookupHits", idCpu);
179	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbLookupMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
180	"Translation block lookup misses", "/IEM/CPU%u/cTbLookupMisses", idCpu);
181
182	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
183	"Calls per threaded translation block", "/IEM/CPU%u/ThrdCallsPerTb", idCpu);
184	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
185	"Instruction per threaded translation block", "/IEM/CPU%u/ThrdInstrPerTb", idCpu);
186	#endif
187
188	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
189	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
190	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
191	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
192	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
193	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
194
195	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
196	/* Instruction statistics: */
197	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
198	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
199	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
200	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
201	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
202	# include "IEMInstructionStatisticsTmpl.h"
203	# undef IEM_DO_INSTR_STAT
204	#endif
205
206	/*
207	* Host and guest CPU information.
208	*/
209	if (idCpu == 0)
210	{
211	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
212	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
213	#if !defined(VBOX_VMM_TARGET_ARMV8)
214	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
215	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
216	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
217	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
218	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
219	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
220	else
221	# endif
222	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
223	#else
224	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
225	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
226	#endif
227
228	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
229	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
230	{
231	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
232	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
233	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
234	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
235	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
236	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
237	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
238	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
239	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
240	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
241	}
242	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
243	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
244	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
245	#else
246	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
247	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
248	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
249	#endif
250	}
251	else
252	{
253	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
254	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
255	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
256	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
257	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
258	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
259	#endif
260	}
261
262	/*
263	* Mark all buffers free.
264	*/
265	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
266	while (iMemMap-- > 0)
267	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
268	}
269
270	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
271	/*
272	* Register the per-VM VMX APIC-access page handler type.
273	*/
274	if (pVM->cpum.ro.GuestFeatures.fVmx)
275	{
276	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
277	iemVmxApicAccessPageHandler,
278	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
279	AssertLogRelRCReturn(rc, rc);
280	}
281	#endif
282
283	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
284	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
285	#ifdef VBOX_WITH_DEBUGGER
286	iemR3RegisterDebuggerCommands();
287	#endif
288
289	return VINF_SUCCESS;
290	}
291
292
293	VMMR3DECL(int) IEMR3Term(PVM pVM)
294	{
295	NOREF(pVM);
296	return VINF_SUCCESS;
297	}
298
299
300	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
301	{
302	RT_NOREF(pVM);
303	}
304
305
306	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
307	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
308	{
309	if (*pfHeader)
310	return;
311	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
312	*pfHeader = true;
313	}
314
315
316	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
317	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
318	{
319	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
320	uSlot,
321	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
322	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
323	: "expired",
324	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
325	pTlbe->GCPhys, pTlbe->pbMappingR3,
326	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
327	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
328	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
329	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
330	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
331	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
332	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
333	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
334	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
335	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
336	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
337	}
338
339
340	/** Displays one or more TLB slots. */
341	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
342	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
343	{
344	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
345	{
346	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
347	{
348	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
349	cSlots, RT_ELEMENTS(pTlb->aEntries));
350	cSlots = RT_ELEMENTS(pTlb->aEntries);
351	}
352
353	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
354	while (cSlots-- > 0)
355	{
356	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
357	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
358	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
359	}
360	}
361	else
362	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
363	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
364	}
365
366
367	/** Displays the TLB slot for the given address. */
368	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
369	uint64_t uAddress, bool *pfHeader)
370	{
371	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
372
373	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
374	uint32_t const uSlot = (uint8_t)uTag;
375	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
376	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
377	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
378	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
379	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
380	}
381
382
383	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
384	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
385	{
386	/*
387	* This is entirely argument driven.
388	*/
389	static RTGETOPTDEF const s_aOptions[] =
390	{
391	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
392	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
393	{ "all", 'A', RTGETOPT_REQ_NOTHING },
394	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
395	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
396	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
397	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
398	};
399
400	char szDefault[] = "-A";
401	char *papszDefaults[2] = { szDefault, NULL };
402	if (cArgs == 0)
403	{
404	cArgs = 1;
405	papszArgs = papszDefaults;
406	}
407
408	RTGETOPTSTATE State;
409	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
410	AssertRCReturnVoid(rc);
411
412	bool fNeedHeader = true;
413	bool fAddressMode = true;
414	PVMCPU pVCpu = VMMGetCpu(pVM);
415	if (!pVCpu)
416	pVCpu = VMMGetCpuById(pVM, 0);
417
418	RTGETOPTUNION ValueUnion;
419	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
420	{
421	switch (rc)
422	{
423	case 'c':
424	if (ValueUnion.u32 >= pVM->cCpus)
425	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
426	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
427	{
428	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
429	fNeedHeader = true;
430	}
431	break;
432
433	case 'a':
434	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
435	ValueUnion.u64, &fNeedHeader);
436	fAddressMode = true;
437	break;
438
439	case 'A':
440	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
441	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
442	break;
443
444	case 'r':
445	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
446	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
447	fAddressMode = false;
448	break;
449
450	case 's':
451	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
452	ValueUnion.u32, 1, &fNeedHeader);
453	fAddressMode = false;
454	break;
455
456	case VINF_GETOPT_NOT_OPTION:
457	if (fAddressMode)
458	{
459	uint64_t uAddr;
460	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
461	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
462	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
463	uAddr, &fNeedHeader);
464	else
465	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
466	}
467	else
468	{
469	uint32_t uSlot;
470	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
471	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
472	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
473	uSlot, 1, &fNeedHeader);
474	else
475	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
476	}
477	break;
478
479	case 'h':
480	pHlp->pfnPrintf(pHlp,
481	"Usage: info %ctlb [options]\n"
482	"\n"
483	"Options:\n"
484	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
485	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
486	" -A, --all, all\n"
487	" Display all the TLB entries (default if no other args).\n"
488	" -a<virt>, --address=<virt>\n"
489	" Shows the TLB entry for the specified guest virtual address.\n"
490	" -r<slot:count>, --range=<slot:count>\n"
491	" Shows the TLB entries for the specified slot range.\n"
492	" -s<slot>,--slot=<slot>\n"
493	" Shows the given TLB slot.\n"
494	"\n"
495	"Non-options are interpreted according to the last -a, -r or -s option,\n"
496	"defaulting to addresses if not preceeded by any of those options.\n"
497	, fITlb ? 'i' : 'd');
498	return;
499
500	default:
501	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
502	return;
503	}
504	}
505	}
506
507
508	/**
509	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
510	*/
511	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
512	{
513	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
514	}
515
516
517	/**
518	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
519	*/
520	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
521	{
522	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
523	}
524
525
526	#ifdef VBOX_WITH_DEBUGGER
527
528	/** @callback_method_impl{FNDBGCCMD,
529	* Implements the '.alliem' command. }
530	*/
531	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
532	{
533	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
534	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
535	if (pVCpu)
536	{
537	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
538	return VINF_SUCCESS;
539	}
540	RT_NOREF(paArgs, cArgs);
541	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
542	}
543
544
545	/**
546	* Called by IEMR3Init to register debugger commands.
547	*/
548	static void iemR3RegisterDebuggerCommands(void)
549	{
550	/*
551	* Register debugger commands.
552	*/
553	static DBGCCMD const s_aCmds[] =
554	{
555	{
556	/* .pszCmd = */ "iemflushtlb",
557	/* .cArgsMin = */ 0,
558	/* .cArgsMax = */ 0,
559	/* .paArgDescs = */ NULL,
560	/* .cArgDescs = */ 0,
561	/* .fFlags = */ 0,
562	/* .pfnHandler = */ iemR3DbgFlushTlbs,
563	/* .pszSyntax = */ "",
564	/* .pszDescription = */ "Flushed the code and data TLBs"
565	},
566	};
567
568	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
569	AssertLogRelRC(rc);
570	}
571
572	#endif
573

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 100696

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