IEMR3.cpp@ 100803

Last change on this file since 100803 was 100803, checked in by vboxsync, 19 months ago
VMM/IEM: More stats. bugref:10369
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1	/* $Id: IEMR3.cpp 100803 2023-08-04 22:04:07Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#include <VBox/vmm/iem.h>
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/vmm/mm.h>
37	#if defined(VBOX_VMM_TARGET_ARMV8)
38	# include "IEMInternal-armv8.h"
39	#else
40	# include "IEMInternal.h"
41	#endif
42	#include <VBox/vmm/vm.h>
43	#include <VBox/vmm/vmapi.h>
44	#include <VBox/err.h>
45	#ifdef VBOX_WITH_DEBUGGER
46	# include <VBox/dbg.h>
47	#endif
48
49	#include <iprt/assert.h>
50	#include <iprt/getopt.h>
51	#include <iprt/string.h>
52
53
54	/*********************************************************************************************************************************
55	* Internal Functions *
56	*********************************************************************************************************************************/
57	static FNDBGFINFOARGVINT iemR3InfoITlb;
58	static FNDBGFINFOARGVINT iemR3InfoDTlb;
59	#ifdef VBOX_WITH_DEBUGGER
60	static void iemR3RegisterDebuggerCommands(void);
61	#endif
62
63
64	#if !defined(VBOX_VMM_TARGET_ARMV8)
65	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
66	{
67	switch (enmTargetCpu)
68	{
69	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
70	CASE_RET_STR(IEMTARGETCPU_8086);
71	CASE_RET_STR(IEMTARGETCPU_V20);
72	CASE_RET_STR(IEMTARGETCPU_186);
73	CASE_RET_STR(IEMTARGETCPU_286);
74	CASE_RET_STR(IEMTARGETCPU_386);
75	CASE_RET_STR(IEMTARGETCPU_486);
76	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
77	CASE_RET_STR(IEMTARGETCPU_PPRO);
78	CASE_RET_STR(IEMTARGETCPU_CURRENT);
79	#undef CASE_RET_STR
80	default: return "Unknown";
81	}
82	}
83	#endif
84
85
86	/**
87	* Initializes the interpreted execution manager.
88	*
89	* This must be called after CPUM as we're quering information from CPUM about
90	* the guest and host CPUs.
91	*
92	* @returns VBox status code.
93	* @param pVM The cross context VM structure.
94	*/
95	VMMR3DECL(int) IEMR3Init(PVM pVM)
96	{
97	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
98	/*
99	* Read configuration.
100	*/
101	PCFGMNODE pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
102
103	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
104	* Controls whether the custom VBox specific CPUID host call interface is
105	* enabled or not. */
106	# ifdef DEBUG_bird
107	int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
108	# else
109	int rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
110	# endif
111	AssertLogRelRCReturn(rc, rc);
112	#endif
113
114	/*
115	* Initialize per-CPU data and register statistics.
116	*/
117	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
118	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
119
120	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
121	{
122	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
123	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
124
125	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
126	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
127
128	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
129	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
130	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
131	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
132	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
133	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
134	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
135	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
136	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
137	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
138	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
139	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
140	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
141	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
142	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
143	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
144	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
145	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
146
147	#ifdef VBOX_WITH_STATISTICS
148	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
149	"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
150	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
151	"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
152	#endif
153	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
154	"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
155	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
156	"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
157	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
158	"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
159	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
160	"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
161
162	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
163	"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
164	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
165	"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
166	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
167	"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
168
169
170	#ifdef VBOX_WITH_IEM_RECOMPILER
171	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExec, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
172	"Executed translation block", "/IEM/CPU%u/re/cTbExec", idCpu);
173	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
174	"Times TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecBreaks", idCpu);
175	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbAllocs, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
176	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocs", idCpu);
177	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbFrees, STAMTYPE_U64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
178	"Translation block frees", "/IEM/CPU%u/re/cTbFrees", idCpu);
179	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbLookupHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
180	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
181	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbLookupMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
182	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
183
184	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
185	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
186	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
187	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
188
189	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
190	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
191	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
192	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
193	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
194	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
195	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
196	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
197	#endif
198
199	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
200	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
201	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
202	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
203	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
204	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
205
206	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
207	/* Instruction statistics: */
208	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
209	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
210	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
211	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
212	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
213	# include "IEMInstructionStatisticsTmpl.h"
214	# undef IEM_DO_INSTR_STAT
215	#endif
216
217	/*
218	* Host and guest CPU information.
219	*/
220	if (idCpu == 0)
221	{
222	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
223	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
224	#if !defined(VBOX_VMM_TARGET_ARMV8)
225	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
226	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
227	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
228	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
229	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
230	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
231	else
232	# endif
233	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
234	#else
235	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
236	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
237	#endif
238
239	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
240	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
241	{
242	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
243	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
244	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
245	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
246	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
247	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
248	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
249	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
250	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
251	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
252	}
253	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
254	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
255	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
256	#else
257	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
258	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
259	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
260	#endif
261	}
262	else
263	{
264	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
265	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
266	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
267	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
268	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
269	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
270	#endif
271	}
272
273	/*
274	* Mark all buffers free.
275	*/
276	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
277	while (iMemMap-- > 0)
278	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
279	}
280
281	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
282	/*
283	* Register the per-VM VMX APIC-access page handler type.
284	*/
285	if (pVM->cpum.ro.GuestFeatures.fVmx)
286	{
287	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
288	iemVmxApicAccessPageHandler,
289	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
290	AssertLogRelRCReturn(rc, rc);
291	}
292	#endif
293
294	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
295	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
296	#ifdef VBOX_WITH_DEBUGGER
297	iemR3RegisterDebuggerCommands();
298	#endif
299
300	return VINF_SUCCESS;
301	}
302
303
304	VMMR3DECL(int) IEMR3Term(PVM pVM)
305	{
306	NOREF(pVM);
307	return VINF_SUCCESS;
308	}
309
310
311	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
312	{
313	RT_NOREF(pVM);
314	}
315
316
317	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
318	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
319	{
320	if (*pfHeader)
321	return;
322	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
323	*pfHeader = true;
324	}
325
326
327	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
328	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
329	{
330	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
331	uSlot,
332	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
333	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
334	: "expired",
335	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
336	pTlbe->GCPhys, pTlbe->pbMappingR3,
337	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
338	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
339	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
340	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
341	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
342	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
343	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
344	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
345	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
346	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
347	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
348	}
349
350
351	/** Displays one or more TLB slots. */
352	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
353	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
354	{
355	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
356	{
357	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
358	{
359	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
360	cSlots, RT_ELEMENTS(pTlb->aEntries));
361	cSlots = RT_ELEMENTS(pTlb->aEntries);
362	}
363
364	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
365	while (cSlots-- > 0)
366	{
367	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
368	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
369	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
370	}
371	}
372	else
373	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
374	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
375	}
376
377
378	/** Displays the TLB slot for the given address. */
379	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
380	uint64_t uAddress, bool *pfHeader)
381	{
382	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
383
384	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
385	uint32_t const uSlot = (uint8_t)uTag;
386	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
387	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
388	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
389	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
390	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
391	}
392
393
394	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
395	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
396	{
397	/*
398	* This is entirely argument driven.
399	*/
400	static RTGETOPTDEF const s_aOptions[] =
401	{
402	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
403	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
404	{ "all", 'A', RTGETOPT_REQ_NOTHING },
405	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
406	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
407	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
408	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
409	};
410
411	char szDefault[] = "-A";
412	char *papszDefaults[2] = { szDefault, NULL };
413	if (cArgs == 0)
414	{
415	cArgs = 1;
416	papszArgs = papszDefaults;
417	}
418
419	RTGETOPTSTATE State;
420	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
421	AssertRCReturnVoid(rc);
422
423	bool fNeedHeader = true;
424	bool fAddressMode = true;
425	PVMCPU pVCpu = VMMGetCpu(pVM);
426	if (!pVCpu)
427	pVCpu = VMMGetCpuById(pVM, 0);
428
429	RTGETOPTUNION ValueUnion;
430	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
431	{
432	switch (rc)
433	{
434	case 'c':
435	if (ValueUnion.u32 >= pVM->cCpus)
436	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
437	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
438	{
439	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
440	fNeedHeader = true;
441	}
442	break;
443
444	case 'a':
445	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
446	ValueUnion.u64, &fNeedHeader);
447	fAddressMode = true;
448	break;
449
450	case 'A':
451	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
452	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
453	break;
454
455	case 'r':
456	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
457	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
458	fAddressMode = false;
459	break;
460
461	case 's':
462	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
463	ValueUnion.u32, 1, &fNeedHeader);
464	fAddressMode = false;
465	break;
466
467	case VINF_GETOPT_NOT_OPTION:
468	if (fAddressMode)
469	{
470	uint64_t uAddr;
471	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
472	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
473	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
474	uAddr, &fNeedHeader);
475	else
476	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
477	}
478	else
479	{
480	uint32_t uSlot;
481	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
482	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
483	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
484	uSlot, 1, &fNeedHeader);
485	else
486	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
487	}
488	break;
489
490	case 'h':
491	pHlp->pfnPrintf(pHlp,
492	"Usage: info %ctlb [options]\n"
493	"\n"
494	"Options:\n"
495	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
496	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
497	" -A, --all, all\n"
498	" Display all the TLB entries (default if no other args).\n"
499	" -a<virt>, --address=<virt>\n"
500	" Shows the TLB entry for the specified guest virtual address.\n"
501	" -r<slot:count>, --range=<slot:count>\n"
502	" Shows the TLB entries for the specified slot range.\n"
503	" -s<slot>,--slot=<slot>\n"
504	" Shows the given TLB slot.\n"
505	"\n"
506	"Non-options are interpreted according to the last -a, -r or -s option,\n"
507	"defaulting to addresses if not preceeded by any of those options.\n"
508	, fITlb ? 'i' : 'd');
509	return;
510
511	default:
512	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
513	return;
514	}
515	}
516	}
517
518
519	/**
520	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
521	*/
522	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
523	{
524	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
525	}
526
527
528	/**
529	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
530	*/
531	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
532	{
533	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
534	}
535
536
537	#ifdef VBOX_WITH_DEBUGGER
538
539	/** @callback_method_impl{FNDBGCCMD,
540	* Implements the '.alliem' command. }
541	*/
542	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
543	{
544	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
545	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
546	if (pVCpu)
547	{
548	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
549	return VINF_SUCCESS;
550	}
551	RT_NOREF(paArgs, cArgs);
552	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
553	}
554
555
556	/**
557	* Called by IEMR3Init to register debugger commands.
558	*/
559	static void iemR3RegisterDebuggerCommands(void)
560	{
561	/*
562	* Register debugger commands.
563	*/
564	static DBGCCMD const s_aCmds[] =
565	{
566	{
567	/* .pszCmd = */ "iemflushtlb",
568	/* .cArgsMin = */ 0,
569	/* .cArgsMax = */ 0,
570	/* .paArgDescs = */ NULL,
571	/* .cArgDescs = */ 0,
572	/* .fFlags = */ 0,
573	/* .pfnHandler = */ iemR3DbgFlushTlbs,
574	/* .pszSyntax = */ "",
575	/* .pszDescription = */ "Flushed the code and data TLBs"
576	},
577	};
578
579	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
580	AssertLogRelRC(rc);
581	}
582
583	#endif
584

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 100803

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