IEMR3.cpp@ 103528

Last change on this file since 103528 was 103516, checked in by vboxsync, 12 months ago
VMM/IEM,EM: Add all kind of exceptions to the exit history, adding a hack to supply the error code and cr2 when present. bugref:10376
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 59.9 KB

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1	/* $Id: IEMR3.cpp 103516 2024-02-22 03:52:49Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#include <VBox/vmm/iem.h>
34	#include <VBox/vmm/cpum.h>
35	#include <VBox/vmm/dbgf.h>
36	#include <VBox/vmm/mm.h>
37	#if defined(VBOX_VMM_TARGET_ARMV8)
38	# include "IEMInternal-armv8.h"
39	#else
40	# include "IEMInternal.h"
41	#endif
42	#include <VBox/vmm/vm.h>
43	#include <VBox/vmm/vmapi.h>
44	#include <VBox/err.h>
45	#ifdef VBOX_WITH_DEBUGGER
46	# include <VBox/dbg.h>
47	#endif
48
49	#include <iprt/assert.h>
50	#include <iprt/getopt.h>
51	#include <iprt/string.h>
52
53	#if defined(VBOX_WITH_STATISTICS) && defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
54	# include "IEMN8veRecompiler.h"
55	# include "IEMThreadedFunctions.h"
56	#endif
57
58
59	/*********************************************************************************************************************************
60	* Internal Functions *
61	*********************************************************************************************************************************/
62	static FNDBGFINFOARGVINT iemR3InfoITlb;
63	static FNDBGFINFOARGVINT iemR3InfoDTlb;
64	#ifdef VBOX_WITH_DEBUGGER
65	static void iemR3RegisterDebuggerCommands(void);
66	#endif
67
68
69	#if !defined(VBOX_VMM_TARGET_ARMV8)
70	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
71	{
72	switch (enmTargetCpu)
73	{
74	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
75	CASE_RET_STR(IEMTARGETCPU_8086);
76	CASE_RET_STR(IEMTARGETCPU_V20);
77	CASE_RET_STR(IEMTARGETCPU_186);
78	CASE_RET_STR(IEMTARGETCPU_286);
79	CASE_RET_STR(IEMTARGETCPU_386);
80	CASE_RET_STR(IEMTARGETCPU_486);
81	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
82	CASE_RET_STR(IEMTARGETCPU_PPRO);
83	CASE_RET_STR(IEMTARGETCPU_CURRENT);
84	#undef CASE_RET_STR
85	default: return "Unknown";
86	}
87	}
88	#endif
89
90
91	/**
92	* Initializes the interpreted execution manager.
93	*
94	* This must be called after CPUM as we're quering information from CPUM about
95	* the guest and host CPUs.
96	*
97	* @returns VBox status code.
98	* @param pVM The cross context VM structure.
99	*/
100	VMMR3DECL(int) IEMR3Init(PVM pVM)
101	{
102	/*
103	* Read configuration.
104	*/
105	#if (!defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)) \|\| defined(VBOX_WITH_IEM_RECOMPILER)
106	PCFGMNODE const pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
107	int rc;
108	#endif
109
110	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
111	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
112	* Controls whether the custom VBox specific CPUID host call interface is
113	* enabled or not. */
114	# ifdef DEBUG_bird
115	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
116	# else
117	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
118	# endif
119	AssertLogRelRCReturn(rc, rc);
120	#endif
121
122	#ifdef VBOX_WITH_IEM_RECOMPILER
123	/** @cfgm{/IEM/MaxTbCount, uint32_t, 524288}
124	* Max number of TBs per EMT. */
125	uint32_t cMaxTbs = 0;
126	rc = CFGMR3QueryU32Def(pIem, "MaxTbCount", &cMaxTbs, _512K);
127	AssertLogRelRCReturn(rc, rc);
128	if (cMaxTbs < _16K \|\| cMaxTbs > _8M)
129	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
130	"MaxTbCount value %u (%#x) is out of range (min %u, max %u)", cMaxTbs, cMaxTbs, _16K, _8M);
131
132	/** @cfgm{/IEM/InitialTbCount, uint32_t, 32678}
133	* Initial (minimum) number of TBs per EMT in ring-3. */
134	uint32_t cInitialTbs = 0;
135	rc = CFGMR3QueryU32Def(pIem, "InitialTbCount", &cInitialTbs, RT_MIN(cMaxTbs, _32K));
136	AssertLogRelRCReturn(rc, rc);
137	if (cInitialTbs < _16K \|\| cInitialTbs > _8M)
138	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
139	"InitialTbCount value %u (%#x) is out of range (min %u, max %u)", cInitialTbs, cInitialTbs, _16K, _8M);
140
141	/* Check that the two values makes sense together. Expect user/api to do
142	the right thing or get lost. */
143	if (cInitialTbs > cMaxTbs)
144	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
145	"InitialTbCount value %u (%#x) is higher than the MaxTbCount value %u (%#x)",
146	cInitialTbs, cInitialTbs, cMaxTbs, cMaxTbs);
147
148	/** @cfgm{/IEM/MaxExecMem, uint64_t, 512 MiB}
149	* Max executable memory for recompiled code per EMT. */
150	uint64_t cbMaxExec = 0;
151	rc = CFGMR3QueryU64Def(pIem, "MaxExecMem", &cbMaxExec, _512M);
152	AssertLogRelRCReturn(rc, rc);
153	if (cbMaxExec < _1M \|\| cbMaxExec > 16*_1G64)
154	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
155	"MaxExecMem value %'RU64 (%#RX64) is out of range (min %'RU64, max %'RU64)",
156	cbMaxExec, cbMaxExec, (uint64_t)_1M, 16*_1G64);
157
158	/** @cfgm{/IEM/ExecChunkSize, uint32_t, 0 (auto)}
159	* The executable memory allocator chunk size. */
160	uint32_t cbChunkExec = 0;
161	rc = CFGMR3QueryU32Def(pIem, "ExecChunkSize", &cbChunkExec, 0);
162	AssertLogRelRCReturn(rc, rc);
163	if (cbChunkExec != 0 && cbChunkExec != UINT32_MAX && (cbChunkExec < _1M \|\| cbChunkExec > _256M))
164	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
165	"ExecChunkSize value %'RU32 (%#RX32) is out of range (min %'RU32, max %'RU32)",
166	cbChunkExec, cbChunkExec, _1M, _256M);
167
168	/** @cfgm{/IEM/InitialExecMemSize, uint64_t, 1}
169	* The initial executable memory allocator size (per EMT). The value is
170	* rounded up to the nearest chunk size, so 1 byte means one chunk. */
171	uint64_t cbInitialExec = 0;
172	rc = CFGMR3QueryU64Def(pIem, "InitialExecMemSize", &cbInitialExec, 0);
173	AssertLogRelRCReturn(rc, rc);
174	if (cbInitialExec > cbMaxExec)
175	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
176	"InitialExecMemSize value %'RU64 (%#RX64) is out of range (max %'RU64)",
177	cbInitialExec, cbInitialExec, cbMaxExec);
178
179	#endif /* VBOX_WITH_IEM_RECOMPILER*/
180
181	/*
182	* Initialize per-CPU data and register statistics.
183	*/
184	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
185	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
186
187	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
188	{
189	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
190	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
191
192	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
193	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
194
195	/*
196	* Host and guest CPU information.
197	*/
198	if (idCpu == 0)
199	{
200	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
201	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
202	#if !defined(VBOX_VMM_TARGET_ARMV8)
203	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
204	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
205	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
206	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
207	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
208	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
209	else
210	# endif
211	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
212	#else
213	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
214	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
215	#endif
216
217	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
218	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
219	{
220	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
221	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
222	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
223	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
224	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
225	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
226	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
227	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
228	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
229	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
230	}
231	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
232	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
233	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
234	#else
235	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
236	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
237	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
238	#endif
239	}
240	else
241	{
242	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
243	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
244	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
245	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
246	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
247	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
248	#endif
249	}
250
251	/*
252	* Mark all buffers free.
253	*/
254	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
255	while (iMemMap-- > 0)
256	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
257	}
258
259
260	#ifdef VBOX_WITH_IEM_RECOMPILER
261	/*
262	* Initialize the TB allocator and cache (/ hash table).
263	*
264	* This is done by each EMT to try get more optimal thread/numa locality of
265	* the allocations.
266	*/
267	rc = VMR3ReqCallWait(pVM, VMCPUID_ALL, (PFNRT)iemTbInit, 6,
268	pVM, cInitialTbs, cMaxTbs, cbInitialExec, cbMaxExec, cbChunkExec);
269	AssertLogRelRCReturn(rc, rc);
270	#endif
271
272	/*
273	* Register statistics.
274	*/
275	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
276	{
277	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) /* quick fix for stupid structure duplication non-sense */
278	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
279
280	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
281	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
282	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
283	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
284	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
285	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
286	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
287	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
288	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
289	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
290	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
291	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
292	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
293	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
294	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
295	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
296	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
297	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
298	STAMR3RegisterF(pVM, &pVCpu->iem.s.cMisalignedAtomics, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
299	"Number of misaligned (for the host) atomic instructions", "/IEM/CPU%u/cMisalignedAtomics", idCpu);
300
301	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
302	"Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
303	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
304	"Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
305	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
306	"Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
307	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
308	"Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
309
310	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
311	"Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
312	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
313	"Data TLB safe read path", "/IEM/CPU%u/DataTlb-SafeReads", idCpu);
314	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
315	"Data TLB safe write path", "/IEM/CPU%u/DataTlb-SafeWrites", idCpu);
316	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
317	"Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
318	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
319	"Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
320
321	# ifdef VBOX_WITH_STATISTICS
322	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
323	"Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
324	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
325	"Data TLB hits", "/IEM/CPU%u/DataTlb-Hits-Other", idCpu);
326	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
327	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStack, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
328	"Data TLB native stack access hits", "/IEM/CPU%u/DataTlb-Hits-Native-Stack", idCpu);
329	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForFetch, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
330	"Data TLB native data fetch hits", "/IEM/CPU%u/DataTlb-Hits-Native-Fetch", idCpu);
331	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStore, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
332	"Data TLB native data store hits", "/IEM/CPU%u/DataTlb-Hits-Native-Store", idCpu);
333	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForMapped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
334	"Data TLB native mapped data hits", "/IEM/CPU%u/DataTlb-Hits-Native-Mapped", idCpu);
335	# endif
336	char szPat[128];
337	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Hits-*", idCpu);
338	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
339	"Data TLB hits total", "/IEM/CPU%u/DataTlb-Hits", idCpu);
340
341	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Safe*", idCpu);
342	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
343	"Data TLB actual misses", "/IEM/CPU%u/DataTlb-SafeTotal", idCpu);
344	char szVal[128];
345	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/DataTlb-SafeTotal", idCpu);
346	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/DataTlb-Hits-*", idCpu);
347	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
348	"Data TLB actual miss rate", "/IEM/CPU%u/DataTlb-SafeRate", idCpu);
349
350	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
351	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
352	"Code TLB native misses on new page", "/IEM/CPU%u/CodeTlb-Misses-New-Page", idCpu);
353	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
354	"Code TLB native misses on new page w/ offset", "/IEM/CPU%u/CodeTlb-Misses-New-Page-With-Offset", idCpu);
355	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
356	"Code TLB native hits on new page", "/IEM/CPU%u/CodeTlb-Hits-New-Page", idCpu);
357	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
358	"Code TLB native hits on new page /w offset", "/IEM/CPU%u/CodeTlb-Hits-New-Page-With-Offset", idCpu);
359	# endif
360	# endif
361
362	#ifdef VBOX_WITH_IEM_RECOMPILER
363	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecNative, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
364	"Executed native translation block", "/IEM/CPU%u/re/cTbExecNative", idCpu);
365	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecThreaded, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
366	"Executed threaded translation block", "/IEM/CPU%u/re/cTbExecThreaded", idCpu);
367	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
368	"Times TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecBreaks", idCpu);
369
370	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
371	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatAllocs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
372	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocCalls", idCpu);
373	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatFrees, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
374	"Translation block frees", "/IEM/CPU%u/re/cTbFreeCalls", idCpu);
375	# ifdef VBOX_WITH_STATISTICS
376	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
377	"Time spent freeing up TBs when full at alloc", "/IEM/CPU%u/re/TbPruningAlloc", idCpu);
378	# endif
379	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPruneNative, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
380	"Time spent freeing up native TBs when out of executable memory", "/IEM/CPU%u/re/TbPruningNative", idCpu);
381	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cAllocatedChunks, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
382	"Populated TB chunks", "/IEM/CPU%u/re/cTbChunks", idCpu);
383	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxChunks, STAMTYPE_U8, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
384	"Max number of TB chunks", "/IEM/CPU%u/re/cTbChunksMax", idCpu);
385	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cTotalTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
386	"Total number of TBs in the allocator", "/IEM/CPU%u/re/cTbTotal", idCpu);
387	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
388	"Max total number of TBs allowed", "/IEM/CPU%u/re/cTbTotalMax", idCpu);
389	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cInUseTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
390	"Number of currently allocated TBs", "/IEM/CPU%u/re/cTbAllocated", idCpu);
391	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cNativeTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
392	"Number of currently allocated native TBs", "/IEM/CPU%u/re/cTbAllocatedNative", idCpu);
393	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cThreadedTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
394	"Number of currently allocated threaded TBs", "/IEM/CPU%u/re/cTbAllocatedThreaded", idCpu);
395
396	PIEMTBCACHE const pTbCache = pVCpu->iem.s.pTbCacheR3;
397	STAMR3RegisterF(pVM, (void *)&pTbCache->cHash, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
398	"Translation block lookup table size", "/IEM/CPU%u/re/cTbHashTab", idCpu);
399
400	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHits, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
401	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
402	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
403	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
404	STAMR3RegisterF(pVM, (void *)&pTbCache->cCollisions, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
405	"Translation block hash table collisions", "/IEM/CPU%u/re/cTbCollisions", idCpu);
406	# ifdef VBOX_WITH_STATISTICS
407	STAMR3RegisterF(pVM, (void *)&pTbCache->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
408	"Time spent shortening collision lists", "/IEM/CPU%u/re/TbPruningCollisions", idCpu);
409	# endif
410
411	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
412	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
413	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
414	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
415
416	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
417	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
418	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
419	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
420	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
421	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
422	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
423	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
424
425	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsRecompiled, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
426	"Number of threaded calls per TB that have been properly recompiled to native code",
427	"/IEM/CPU%u/re/NativeCallsRecompiledPerTb", idCpu);
428	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsThreaded, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
429	"Number of threaded calls per TB that could not be recompiler to native code",
430	"/IEM/CPU%u/re/NativeCallsThreadedPerTb", idCpu);
431	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeFullyRecompiledTbs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
432	"Number of threaded calls that could not be recompiler to native code",
433	"/IEM/CPU%u/re/NativeFullyRecompiledTbs", idCpu);
434
435	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbNativeCode, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES_PER_TB,
436	"Size of native code per TB", "/IEM/CPU%u/re/NativeCodeSizePerTb", idCpu);
437	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeRecompilation, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
438	"Profiling iemNativeRecompile()", "/IEM/CPU%u/re/NativeRecompilation", idCpu);
439
440	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
441	# ifdef VBOX_WITH_STATISTICS
442	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
443	"Number of calls to iemNativeRegAllocFindFree.",
444	"/IEM/CPU%u/re/NativeRegFindFree", idCpu);
445	# endif
446	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
447	"Number of times iemNativeRegAllocFindFree needed to free a variable.",
448	"/IEM/CPU%u/re/NativeRegFindFreeVar", idCpu);
449	# ifdef VBOX_WITH_STATISTICS
450	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
451	"Number of times iemNativeRegAllocFindFree did not needed to free any variables.",
452	"/IEM/CPU%u/re/NativeRegFindFreeNoVar", idCpu);
453	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
454	"Times liveness info freeed up shadowed guest registers in iemNativeRegAllocFindFree.",
455	"/IEM/CPU%u/re/NativeRegFindFreeLivenessUnshadowed", idCpu);
456	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
457	"Times liveness info helped finding the return register in iemNativeRegAllocFindFree.",
458	"/IEM/CPU%u/re/NativeRegFindFreeLivenessHelped", idCpu);
459
460	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu);
461	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippable", idCpu);
462	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippable", idCpu);
463	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippable", idCpu);
464	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippable", idCpu);
465	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippable", idCpu);
466
467	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfRequired", idCpu);
468	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfRequired", idCpu);
469	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfRequired", idCpu);
470	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfRequired", idCpu);
471	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfRequired", idCpu);
472	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfRequired", idCpu);
473
474	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
475	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfDelayable", idCpu);
476	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfDelayable", idCpu);
477	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfDelayable", idCpu);
478	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfDelayable", idCpu);
479	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfDelayable", idCpu);
480	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfDelayable", idCpu);
481	# endif
482
483	/* Sum up all status bits ('_' is a sorting hack). */
484	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fSkippable*", idCpu);
485	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total skippable EFLAGS status bit updating",
486	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu);
487
488	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fRequired*", idCpu);
489	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total required STATUS status bit updating",
490	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusRequired", idCpu);
491
492	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
493	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fDelayable*", idCpu);
494	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total potentially delayable STATUS status bit updating",
495	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu);
496	# endif
497
498	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?f*", idCpu);
499	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total STATUS status bit events of any kind",
500	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu);
501
502	/* Ratio of the status bit skippables. */
503	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu);
504	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu);
505	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
506	"Total skippable EFLAGS status bit updating percentage",
507	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippablePct", idCpu);
508
509	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
510	/* Ratio of the status bit skippables. */
511	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu);
512	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
513	"Total potentially delayable EFLAGS status bit updating percentage",
514	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayablePct", idCpu);
515	# endif
516
517	/* Ratios of individual bits. */
518	size_t const offFlagChar = RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlagsCf*", idCpu) - 3;
519	Assert(szPat[offFlagChar] == 'C');
520	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu);
521	Assert(szVal[offFlagChar] == 'C');
522	szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippablePct", idCpu);
523	szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippablePct", idCpu);
524	szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippablePct", idCpu);
525	szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippablePct", idCpu);
526	szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippablePct", idCpu);
527	szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippablePct", idCpu);
528
529	# endif /* VBOX_WITH_STATISTICS */
530	# endif /* VBOX_WITH_IEM_NATIVE_RECOMPILER */
531
532	#endif /* VBOX_WITH_IEM_RECOMPILER */
533
534	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
535	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
536	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
537	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
538	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
539	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
540
541	# if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
542	/* Instruction statistics: */
543	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
544	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
545	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
546	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
547	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
548	# include "IEMInstructionStatisticsTmpl.h"
549	# undef IEM_DO_INSTR_STAT
550	# endif
551
552	# if defined(VBOX_WITH_STATISTICS) && defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
553	/* Threaded function statistics: */
554	for (unsigned i = 1; i < (unsigned)kIemThreadedFunc_End; i++)
555	STAMR3RegisterF(pVM, &pVCpu->iem.s.acThreadedFuncStats[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED,
556	STAMUNIT_COUNT, NULL, "/IEM/CPU%u/ThrdFuncs/%s", idCpu, g_apszIemThreadedFunctionStats[i]);
557	# endif
558
559	#endif /* !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) - quick fix for stupid structure duplication non-sense */
560	}
561
562	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
563	/*
564	* Register the per-VM VMX APIC-access page handler type.
565	*/
566	if (pVM->cpum.ro.GuestFeatures.fVmx)
567	{
568	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
569	iemVmxApicAccessPageHandler,
570	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
571	AssertLogRelRCReturn(rc, rc);
572	}
573	#endif
574
575	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
576	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
577	#ifdef VBOX_WITH_DEBUGGER
578	iemR3RegisterDebuggerCommands();
579	#endif
580
581	return VINF_SUCCESS;
582	}
583
584
585	VMMR3DECL(int) IEMR3Term(PVM pVM)
586	{
587	NOREF(pVM);
588	return VINF_SUCCESS;
589	}
590
591
592	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
593	{
594	RT_NOREF(pVM);
595	}
596
597
598	/**
599	* Gets the name of a generic IEM exit code.
600	*
601	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
602	* @param uExit The IEM exit to name.
603	*/
604	VMMR3DECL(const char *) IEMR3GetExitName(uint32_t uExit)
605	{
606	static const char * const s_apszNames[] =
607	{
608	/* external interrupts */
609	"ExtInt 00h", "ExtInt 01h", "ExtInt 02h", "ExtInt 03h", "ExtInt 04h", "ExtInt 05h", "ExtInt 06h", "ExtInt 07h",
610	"ExtInt 08h", "ExtInt 09h", "ExtInt 0ah", "ExtInt 0bh", "ExtInt 0ch", "ExtInt 0dh", "ExtInt 0eh", "ExtInt 0fh",
611	"ExtInt 10h", "ExtInt 11h", "ExtInt 12h", "ExtInt 13h", "ExtInt 14h", "ExtInt 15h", "ExtInt 16h", "ExtInt 17h",
612	"ExtInt 18h", "ExtInt 19h", "ExtInt 1ah", "ExtInt 1bh", "ExtInt 1ch", "ExtInt 1dh", "ExtInt 1eh", "ExtInt 1fh",
613	"ExtInt 20h", "ExtInt 21h", "ExtInt 22h", "ExtInt 23h", "ExtInt 24h", "ExtInt 25h", "ExtInt 26h", "ExtInt 27h",
614	"ExtInt 28h", "ExtInt 29h", "ExtInt 2ah", "ExtInt 2bh", "ExtInt 2ch", "ExtInt 2dh", "ExtInt 2eh", "ExtInt 2fh",
615	"ExtInt 30h", "ExtInt 31h", "ExtInt 32h", "ExtInt 33h", "ExtInt 34h", "ExtInt 35h", "ExtInt 36h", "ExtInt 37h",
616	"ExtInt 38h", "ExtInt 39h", "ExtInt 3ah", "ExtInt 3bh", "ExtInt 3ch", "ExtInt 3dh", "ExtInt 3eh", "ExtInt 3fh",
617	"ExtInt 40h", "ExtInt 41h", "ExtInt 42h", "ExtInt 43h", "ExtInt 44h", "ExtInt 45h", "ExtInt 46h", "ExtInt 47h",
618	"ExtInt 48h", "ExtInt 49h", "ExtInt 4ah", "ExtInt 4bh", "ExtInt 4ch", "ExtInt 4dh", "ExtInt 4eh", "ExtInt 4fh",
619	"ExtInt 50h", "ExtInt 51h", "ExtInt 52h", "ExtInt 53h", "ExtInt 54h", "ExtInt 55h", "ExtInt 56h", "ExtInt 57h",
620	"ExtInt 58h", "ExtInt 59h", "ExtInt 5ah", "ExtInt 5bh", "ExtInt 5ch", "ExtInt 5dh", "ExtInt 5eh", "ExtInt 5fh",
621	"ExtInt 60h", "ExtInt 61h", "ExtInt 62h", "ExtInt 63h", "ExtInt 64h", "ExtInt 65h", "ExtInt 66h", "ExtInt 67h",
622	"ExtInt 68h", "ExtInt 69h", "ExtInt 6ah", "ExtInt 6bh", "ExtInt 6ch", "ExtInt 6dh", "ExtInt 6eh", "ExtInt 6fh",
623	"ExtInt 70h", "ExtInt 71h", "ExtInt 72h", "ExtInt 73h", "ExtInt 74h", "ExtInt 75h", "ExtInt 76h", "ExtInt 77h",
624	"ExtInt 78h", "ExtInt 79h", "ExtInt 7ah", "ExtInt 7bh", "ExtInt 7ch", "ExtInt 7dh", "ExtInt 7eh", "ExtInt 7fh",
625	"ExtInt 80h", "ExtInt 81h", "ExtInt 82h", "ExtInt 83h", "ExtInt 84h", "ExtInt 85h", "ExtInt 86h", "ExtInt 87h",
626	"ExtInt 88h", "ExtInt 89h", "ExtInt 8ah", "ExtInt 8bh", "ExtInt 8ch", "ExtInt 8dh", "ExtInt 8eh", "ExtInt 8fh",
627	"ExtInt 90h", "ExtInt 91h", "ExtInt 92h", "ExtInt 93h", "ExtInt 94h", "ExtInt 95h", "ExtInt 96h", "ExtInt 97h",
628	"ExtInt 98h", "ExtInt 99h", "ExtInt 9ah", "ExtInt 9bh", "ExtInt 9ch", "ExtInt 9dh", "ExtInt 9eh", "ExtInt 9fh",
629	"ExtInt a0h", "ExtInt a1h", "ExtInt a2h", "ExtInt a3h", "ExtInt a4h", "ExtInt a5h", "ExtInt a6h", "ExtInt a7h",
630	"ExtInt a8h", "ExtInt a9h", "ExtInt aah", "ExtInt abh", "ExtInt ach", "ExtInt adh", "ExtInt aeh", "ExtInt afh",
631	"ExtInt b0h", "ExtInt b1h", "ExtInt b2h", "ExtInt b3h", "ExtInt b4h", "ExtInt b5h", "ExtInt b6h", "ExtInt b7h",
632	"ExtInt b8h", "ExtInt b9h", "ExtInt bah", "ExtInt bbh", "ExtInt bch", "ExtInt bdh", "ExtInt beh", "ExtInt bfh",
633	"ExtInt c0h", "ExtInt c1h", "ExtInt c2h", "ExtInt c3h", "ExtInt c4h", "ExtInt c5h", "ExtInt c6h", "ExtInt c7h",
634	"ExtInt c8h", "ExtInt c9h", "ExtInt cah", "ExtInt cbh", "ExtInt cch", "ExtInt cdh", "ExtInt ceh", "ExtInt cfh",
635	"ExtInt d0h", "ExtInt d1h", "ExtInt d2h", "ExtInt d3h", "ExtInt d4h", "ExtInt d5h", "ExtInt d6h", "ExtInt d7h",
636	"ExtInt d8h", "ExtInt d9h", "ExtInt dah", "ExtInt dbh", "ExtInt dch", "ExtInt ddh", "ExtInt deh", "ExtInt dfh",
637	"ExtInt e0h", "ExtInt e1h", "ExtInt e2h", "ExtInt e3h", "ExtInt e4h", "ExtInt e5h", "ExtInt e6h", "ExtInt e7h",
638	"ExtInt e8h", "ExtInt e9h", "ExtInt eah", "ExtInt ebh", "ExtInt ech", "ExtInt edh", "ExtInt eeh", "ExtInt efh",
639	"ExtInt f0h", "ExtInt f1h", "ExtInt f2h", "ExtInt f3h", "ExtInt f4h", "ExtInt f5h", "ExtInt f6h", "ExtInt f7h",
640	"ExtInt f8h", "ExtInt f9h", "ExtInt fah", "ExtInt fbh", "ExtInt fch", "ExtInt fdh", "ExtInt feh", "ExtInt ffh",
641	/* software interrups */
642	"SoftInt 00h", "SoftInt 01h", "SoftInt 02h", "SoftInt 03h", "SoftInt 04h", "SoftInt 05h", "SoftInt 06h", "SoftInt 07h",
643	"SoftInt 08h", "SoftInt 09h", "SoftInt 0ah", "SoftInt 0bh", "SoftInt 0ch", "SoftInt 0dh", "SoftInt 0eh", "SoftInt 0fh",
644	"SoftInt 10h", "SoftInt 11h", "SoftInt 12h", "SoftInt 13h", "SoftInt 14h", "SoftInt 15h", "SoftInt 16h", "SoftInt 17h",
645	"SoftInt 18h", "SoftInt 19h", "SoftInt 1ah", "SoftInt 1bh", "SoftInt 1ch", "SoftInt 1dh", "SoftInt 1eh", "SoftInt 1fh",
646	"SoftInt 20h", "SoftInt 21h", "SoftInt 22h", "SoftInt 23h", "SoftInt 24h", "SoftInt 25h", "SoftInt 26h", "SoftInt 27h",
647	"SoftInt 28h", "SoftInt 29h", "SoftInt 2ah", "SoftInt 2bh", "SoftInt 2ch", "SoftInt 2dh", "SoftInt 2eh", "SoftInt 2fh",
648	"SoftInt 30h", "SoftInt 31h", "SoftInt 32h", "SoftInt 33h", "SoftInt 34h", "SoftInt 35h", "SoftInt 36h", "SoftInt 37h",
649	"SoftInt 38h", "SoftInt 39h", "SoftInt 3ah", "SoftInt 3bh", "SoftInt 3ch", "SoftInt 3dh", "SoftInt 3eh", "SoftInt 3fh",
650	"SoftInt 40h", "SoftInt 41h", "SoftInt 42h", "SoftInt 43h", "SoftInt 44h", "SoftInt 45h", "SoftInt 46h", "SoftInt 47h",
651	"SoftInt 48h", "SoftInt 49h", "SoftInt 4ah", "SoftInt 4bh", "SoftInt 4ch", "SoftInt 4dh", "SoftInt 4eh", "SoftInt 4fh",
652	"SoftInt 50h", "SoftInt 51h", "SoftInt 52h", "SoftInt 53h", "SoftInt 54h", "SoftInt 55h", "SoftInt 56h", "SoftInt 57h",
653	"SoftInt 58h", "SoftInt 59h", "SoftInt 5ah", "SoftInt 5bh", "SoftInt 5ch", "SoftInt 5dh", "SoftInt 5eh", "SoftInt 5fh",
654	"SoftInt 60h", "SoftInt 61h", "SoftInt 62h", "SoftInt 63h", "SoftInt 64h", "SoftInt 65h", "SoftInt 66h", "SoftInt 67h",
655	"SoftInt 68h", "SoftInt 69h", "SoftInt 6ah", "SoftInt 6bh", "SoftInt 6ch", "SoftInt 6dh", "SoftInt 6eh", "SoftInt 6fh",
656	"SoftInt 70h", "SoftInt 71h", "SoftInt 72h", "SoftInt 73h", "SoftInt 74h", "SoftInt 75h", "SoftInt 76h", "SoftInt 77h",
657	"SoftInt 78h", "SoftInt 79h", "SoftInt 7ah", "SoftInt 7bh", "SoftInt 7ch", "SoftInt 7dh", "SoftInt 7eh", "SoftInt 7fh",
658	"SoftInt 80h", "SoftInt 81h", "SoftInt 82h", "SoftInt 83h", "SoftInt 84h", "SoftInt 85h", "SoftInt 86h", "SoftInt 87h",
659	"SoftInt 88h", "SoftInt 89h", "SoftInt 8ah", "SoftInt 8bh", "SoftInt 8ch", "SoftInt 8dh", "SoftInt 8eh", "SoftInt 8fh",
660	"SoftInt 90h", "SoftInt 91h", "SoftInt 92h", "SoftInt 93h", "SoftInt 94h", "SoftInt 95h", "SoftInt 96h", "SoftInt 97h",
661	"SoftInt 98h", "SoftInt 99h", "SoftInt 9ah", "SoftInt 9bh", "SoftInt 9ch", "SoftInt 9dh", "SoftInt 9eh", "SoftInt 9fh",
662	"SoftInt a0h", "SoftInt a1h", "SoftInt a2h", "SoftInt a3h", "SoftInt a4h", "SoftInt a5h", "SoftInt a6h", "SoftInt a7h",
663	"SoftInt a8h", "SoftInt a9h", "SoftInt aah", "SoftInt abh", "SoftInt ach", "SoftInt adh", "SoftInt aeh", "SoftInt afh",
664	"SoftInt b0h", "SoftInt b1h", "SoftInt b2h", "SoftInt b3h", "SoftInt b4h", "SoftInt b5h", "SoftInt b6h", "SoftInt b7h",
665	"SoftInt b8h", "SoftInt b9h", "SoftInt bah", "SoftInt bbh", "SoftInt bch", "SoftInt bdh", "SoftInt beh", "SoftInt bfh",
666	"SoftInt c0h", "SoftInt c1h", "SoftInt c2h", "SoftInt c3h", "SoftInt c4h", "SoftInt c5h", "SoftInt c6h", "SoftInt c7h",
667	"SoftInt c8h", "SoftInt c9h", "SoftInt cah", "SoftInt cbh", "SoftInt cch", "SoftInt cdh", "SoftInt ceh", "SoftInt cfh",
668	"SoftInt d0h", "SoftInt d1h", "SoftInt d2h", "SoftInt d3h", "SoftInt d4h", "SoftInt d5h", "SoftInt d6h", "SoftInt d7h",
669	"SoftInt d8h", "SoftInt d9h", "SoftInt dah", "SoftInt dbh", "SoftInt dch", "SoftInt ddh", "SoftInt deh", "SoftInt dfh",
670	"SoftInt e0h", "SoftInt e1h", "SoftInt e2h", "SoftInt e3h", "SoftInt e4h", "SoftInt e5h", "SoftInt e6h", "SoftInt e7h",
671	"SoftInt e8h", "SoftInt e9h", "SoftInt eah", "SoftInt ebh", "SoftInt ech", "SoftInt edh", "SoftInt eeh", "SoftInt efh",
672	"SoftInt f0h", "SoftInt f1h", "SoftInt f2h", "SoftInt f3h", "SoftInt f4h", "SoftInt f5h", "SoftInt f6h", "SoftInt f7h",
673	"SoftInt f8h", "SoftInt f9h", "SoftInt fah", "SoftInt fbh", "SoftInt fch", "SoftInt fdh", "SoftInt feh", "SoftInt ffh",
674	};
675	if (uExit < RT_ELEMENTS(s_apszNames))
676	return s_apszNames[uExit];
677	return NULL;
678	}
679
680
681	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
682	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
683	{
684	if (*pfHeader)
685	return;
686	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
687	*pfHeader = true;
688	}
689
690
691	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
692	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
693	{
694	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
695	uSlot,
696	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
697	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
698	: "expired",
699	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
700	pTlbe->GCPhys, pTlbe->pbMappingR3,
701	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
702	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
703	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
704	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
705	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
706	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
707	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
708	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
709	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
710	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
711	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
712	}
713
714
715	/** Displays one or more TLB slots. */
716	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
717	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
718	{
719	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
720	{
721	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
722	{
723	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
724	cSlots, RT_ELEMENTS(pTlb->aEntries));
725	cSlots = RT_ELEMENTS(pTlb->aEntries);
726	}
727
728	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
729	while (cSlots-- > 0)
730	{
731	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
732	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
733	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
734	}
735	}
736	else
737	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
738	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
739	}
740
741
742	/** Displays the TLB slot for the given address. */
743	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
744	uint64_t uAddress, bool *pfHeader)
745	{
746	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
747
748	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
749	uint32_t const uSlot = (uint8_t)uTag;
750	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
751	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
752	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
753	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
754	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
755	}
756
757
758	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
759	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
760	{
761	/*
762	* This is entirely argument driven.
763	*/
764	static RTGETOPTDEF const s_aOptions[] =
765	{
766	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
767	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
768	{ "all", 'A', RTGETOPT_REQ_NOTHING },
769	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
770	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
771	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
772	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
773	};
774
775	char szDefault[] = "-A";
776	char *papszDefaults[2] = { szDefault, NULL };
777	if (cArgs == 0)
778	{
779	cArgs = 1;
780	papszArgs = papszDefaults;
781	}
782
783	RTGETOPTSTATE State;
784	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
785	AssertRCReturnVoid(rc);
786
787	bool fNeedHeader = true;
788	bool fAddressMode = true;
789	PVMCPU pVCpu = VMMGetCpu(pVM);
790	if (!pVCpu)
791	pVCpu = VMMGetCpuById(pVM, 0);
792
793	RTGETOPTUNION ValueUnion;
794	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
795	{
796	switch (rc)
797	{
798	case 'c':
799	if (ValueUnion.u32 >= pVM->cCpus)
800	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
801	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
802	{
803	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
804	fNeedHeader = true;
805	}
806	break;
807
808	case 'a':
809	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
810	ValueUnion.u64, &fNeedHeader);
811	fAddressMode = true;
812	break;
813
814	case 'A':
815	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
816	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
817	break;
818
819	case 'r':
820	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
821	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
822	fAddressMode = false;
823	break;
824
825	case 's':
826	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
827	ValueUnion.u32, 1, &fNeedHeader);
828	fAddressMode = false;
829	break;
830
831	case VINF_GETOPT_NOT_OPTION:
832	if (fAddressMode)
833	{
834	uint64_t uAddr;
835	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
836	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
837	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
838	uAddr, &fNeedHeader);
839	else
840	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
841	}
842	else
843	{
844	uint32_t uSlot;
845	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
846	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
847	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
848	uSlot, 1, &fNeedHeader);
849	else
850	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
851	}
852	break;
853
854	case 'h':
855	pHlp->pfnPrintf(pHlp,
856	"Usage: info %ctlb [options]\n"
857	"\n"
858	"Options:\n"
859	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
860	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
861	" -A, --all, all\n"
862	" Display all the TLB entries (default if no other args).\n"
863	" -a<virt>, --address=<virt>\n"
864	" Shows the TLB entry for the specified guest virtual address.\n"
865	" -r<slot:count>, --range=<slot:count>\n"
866	" Shows the TLB entries for the specified slot range.\n"
867	" -s<slot>,--slot=<slot>\n"
868	" Shows the given TLB slot.\n"
869	"\n"
870	"Non-options are interpreted according to the last -a, -r or -s option,\n"
871	"defaulting to addresses if not preceeded by any of those options.\n"
872	, fITlb ? 'i' : 'd');
873	return;
874
875	default:
876	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
877	return;
878	}
879	}
880	}
881
882
883	/**
884	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
885	*/
886	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
887	{
888	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
889	}
890
891
892	/**
893	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
894	*/
895	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
896	{
897	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
898	}
899
900
901	#ifdef VBOX_WITH_DEBUGGER
902
903	/** @callback_method_impl{FNDBGCCMD,
904	* Implements the '.alliem' command. }
905	*/
906	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
907	{
908	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
909	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
910	if (pVCpu)
911	{
912	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
913	return VINF_SUCCESS;
914	}
915	RT_NOREF(paArgs, cArgs);
916	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
917	}
918
919
920	/**
921	* Called by IEMR3Init to register debugger commands.
922	*/
923	static void iemR3RegisterDebuggerCommands(void)
924	{
925	/*
926	* Register debugger commands.
927	*/
928	static DBGCCMD const s_aCmds[] =
929	{
930	{
931	/* .pszCmd = */ "iemflushtlb",
932	/* .cArgsMin = */ 0,
933	/* .cArgsMax = */ 0,
934	/* .paArgDescs = */ NULL,
935	/* .cArgDescs = */ 0,
936	/* .fFlags = */ 0,
937	/* .pfnHandler = */ iemR3DbgFlushTlbs,
938	/* .pszSyntax = */ "",
939	/* .pszDescription = */ "Flushed the code and data TLBs"
940	},
941	};
942
943	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
944	AssertLogRelRC(rc);
945	}
946
947	#endif
948

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 103528

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