IEMR3.cpp@ 105036

Last change on this file since 105036 was 105036, checked in by vboxsync, 7 months ago
VMM/IEM: Split the TLB into non-global (even) and global (odd) entries, doubling it in size. In native code the global entries are only checked for ring-0 TBs, as checking both entries is slower than just the even one. bugref:10687
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 95.9 KB

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1	/* $Id: IEMR3.cpp 105036 2024-06-26 22:33:48Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2023 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/iem.h>
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/dbgf.h>
37	#include <VBox/vmm/mm.h>
38	#if defined(VBOX_VMM_TARGET_ARMV8)
39	# include "IEMInternal-armv8.h"
40	#else
41	# include "IEMInternal.h"
42	#endif
43	#include <VBox/vmm/vm.h>
44	#include <VBox/vmm/vmapi.h>
45	#include <VBox/err.h>
46	#ifdef VBOX_WITH_DEBUGGER
47	# include <VBox/dbg.h>
48	#endif
49
50	#include <iprt/assert.h>
51	#include <iprt/getopt.h>
52	#include <iprt/string.h>
53
54	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
55	# include "IEMN8veRecompiler.h"
56	# include "IEMThreadedFunctions.h"
57	# include "IEMInline.h"
58	#endif
59
60
61	/*********************************************************************************************************************************
62	* Internal Functions *
63	*********************************************************************************************************************************/
64	static FNDBGFINFOARGVINT iemR3InfoITlb;
65	static FNDBGFINFOARGVINT iemR3InfoDTlb;
66	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
67	static FNDBGFINFOARGVINT iemR3InfoTb;
68	#endif
69	#ifdef VBOX_WITH_DEBUGGER
70	static void iemR3RegisterDebuggerCommands(void);
71	#endif
72
73
74	#if !defined(VBOX_VMM_TARGET_ARMV8)
75	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
76	{
77	switch (enmTargetCpu)
78	{
79	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
80	CASE_RET_STR(IEMTARGETCPU_8086);
81	CASE_RET_STR(IEMTARGETCPU_V20);
82	CASE_RET_STR(IEMTARGETCPU_186);
83	CASE_RET_STR(IEMTARGETCPU_286);
84	CASE_RET_STR(IEMTARGETCPU_386);
85	CASE_RET_STR(IEMTARGETCPU_486);
86	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
87	CASE_RET_STR(IEMTARGETCPU_PPRO);
88	CASE_RET_STR(IEMTARGETCPU_CURRENT);
89	#undef CASE_RET_STR
90	default: return "Unknown";
91	}
92	}
93	#endif
94
95
96	/**
97	* Initializes the interpreted execution manager.
98	*
99	* This must be called after CPUM as we're quering information from CPUM about
100	* the guest and host CPUs.
101	*
102	* @returns VBox status code.
103	* @param pVM The cross context VM structure.
104	*/
105	VMMR3DECL(int) IEMR3Init(PVM pVM)
106	{
107	/*
108	* Read configuration.
109	*/
110	#if (!defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)) \|\| defined(VBOX_WITH_IEM_RECOMPILER)
111	PCFGMNODE const pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
112	int rc;
113	#endif
114
115	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
116	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
117	* Controls whether the custom VBox specific CPUID host call interface is
118	* enabled or not. */
119	# ifdef DEBUG_bird
120	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
121	# else
122	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
123	# endif
124	AssertLogRelRCReturn(rc, rc);
125	#endif
126
127	#ifdef VBOX_WITH_IEM_RECOMPILER
128	/** @cfgm{/IEM/MaxTbCount, uint32_t, 524288}
129	* Max number of TBs per EMT. */
130	uint32_t cMaxTbs = 0;
131	rc = CFGMR3QueryU32Def(pIem, "MaxTbCount", &cMaxTbs, _512K);
132	AssertLogRelRCReturn(rc, rc);
133	if (cMaxTbs < _16K \|\| cMaxTbs > _8M)
134	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
135	"MaxTbCount value %u (%#x) is out of range (min %u, max %u)", cMaxTbs, cMaxTbs, _16K, _8M);
136
137	/** @cfgm{/IEM/InitialTbCount, uint32_t, 32678}
138	* Initial (minimum) number of TBs per EMT in ring-3. */
139	uint32_t cInitialTbs = 0;
140	rc = CFGMR3QueryU32Def(pIem, "InitialTbCount", &cInitialTbs, RT_MIN(cMaxTbs, _32K));
141	AssertLogRelRCReturn(rc, rc);
142	if (cInitialTbs < _16K \|\| cInitialTbs > _8M)
143	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
144	"InitialTbCount value %u (%#x) is out of range (min %u, max %u)", cInitialTbs, cInitialTbs, _16K, _8M);
145
146	/* Check that the two values makes sense together. Expect user/api to do
147	the right thing or get lost. */
148	if (cInitialTbs > cMaxTbs)
149	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
150	"InitialTbCount value %u (%#x) is higher than the MaxTbCount value %u (%#x)",
151	cInitialTbs, cInitialTbs, cMaxTbs, cMaxTbs);
152
153	/** @cfgm{/IEM/MaxExecMem, uint64_t, 512 MiB}
154	* Max executable memory for recompiled code per EMT. */
155	uint64_t cbMaxExec = 0;
156	rc = CFGMR3QueryU64Def(pIem, "MaxExecMem", &cbMaxExec, _512M);
157	AssertLogRelRCReturn(rc, rc);
158	if (cbMaxExec < _1M \|\| cbMaxExec > 16*_1G64)
159	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
160	"MaxExecMem value %'RU64 (%#RX64) is out of range (min %'RU64, max %'RU64)",
161	cbMaxExec, cbMaxExec, (uint64_t)_1M, 16*_1G64);
162
163	/** @cfgm{/IEM/ExecChunkSize, uint32_t, 0 (auto)}
164	* The executable memory allocator chunk size. */
165	uint32_t cbChunkExec = 0;
166	rc = CFGMR3QueryU32Def(pIem, "ExecChunkSize", &cbChunkExec, 0);
167	AssertLogRelRCReturn(rc, rc);
168	if (cbChunkExec != 0 && cbChunkExec != UINT32_MAX && (cbChunkExec < _1M \|\| cbChunkExec > _256M))
169	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
170	"ExecChunkSize value %'RU32 (%#RX32) is out of range (min %'RU32, max %'RU32)",
171	cbChunkExec, cbChunkExec, _1M, _256M);
172
173	/** @cfgm{/IEM/InitialExecMemSize, uint64_t, 1}
174	* The initial executable memory allocator size (per EMT). The value is
175	* rounded up to the nearest chunk size, so 1 byte means one chunk. */
176	uint64_t cbInitialExec = 0;
177	rc = CFGMR3QueryU64Def(pIem, "InitialExecMemSize", &cbInitialExec, 0);
178	AssertLogRelRCReturn(rc, rc);
179	if (cbInitialExec > cbMaxExec)
180	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
181	"InitialExecMemSize value %'RU64 (%#RX64) is out of range (max %'RU64)",
182	cbInitialExec, cbInitialExec, cbMaxExec);
183
184	/** @cfgm{/IEM/NativeRecompileAtUsedCount, uint32_t, 16}
185	* The translation block use count value to do native recompilation at. */
186	uint32_t uTbNativeRecompileAtUsedCount = 16;
187	rc = CFGMR3QueryU32Def(pIem, "NativeRecompileAtUsedCount", &uTbNativeRecompileAtUsedCount, 16);
188	AssertLogRelRCReturn(rc, rc);
189
190	#endif /* VBOX_WITH_IEM_RECOMPILER*/
191
192	/*
193	* Initialize per-CPU data and register statistics.
194	*/
195	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
196	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
197
198	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
199	{
200	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
201	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
202
203	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
204	#ifndef VBOX_VMM_TARGET_ARMV8
205	pVCpu->iem.s.CodeTlb.uTlbRevisionGlobal = pVCpu->iem.s.DataTlb.uTlbRevisionGlobal = uInitialTlbRevision;
206	#endif
207	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
208
209	/*
210	* Host and guest CPU information.
211	*/
212	if (idCpu == 0)
213	{
214	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
215	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
216	#if !defined(VBOX_VMM_TARGET_ARMV8)
217	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
218	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
219	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
220	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
221	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
222	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
223	else
224	# endif
225	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
226	#else
227	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
228	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
229	#endif
230
231	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
232	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
233	{
234	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
235	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
236	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
237	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
238	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
239	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
240	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
241	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
242	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
243	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
244	}
245	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
246	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
247	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
248	#else
249	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
250	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
251	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
252	#endif
253	}
254	else
255	{
256	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
257	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
258	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
259	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
260	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
261	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
262	#endif
263	}
264
265	/*
266	* Mark all buffers free.
267	*/
268	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
269	while (iMemMap-- > 0)
270	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
271
272	#ifdef VBOX_WITH_IEM_RECOMPILER
273	/*
274	* Distribute recompiler configuration.
275	*/
276	pVCpu->iem.s.uTbNativeRecompileAtUsedCount = uTbNativeRecompileAtUsedCount;
277	#endif
278	}
279
280
281	#ifdef VBOX_WITH_IEM_RECOMPILER
282	/*
283	* Initialize the TB allocator and cache (/ hash table).
284	*
285	* This is done by each EMT to try get more optimal thread/numa locality of
286	* the allocations.
287	*/
288	rc = VMR3ReqCallWait(pVM, VMCPUID_ALL, (PFNRT)iemTbInit, 6,
289	pVM, cInitialTbs, cMaxTbs, cbInitialExec, cbMaxExec, cbChunkExec);
290	AssertLogRelRCReturn(rc, rc);
291	#endif
292
293	/*
294	* Register statistics.
295	*/
296	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
297	{
298	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) /* quick fix for stupid structure duplication non-sense */
299	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
300	char szPat[128];
301	RT_NOREF_PV(szPat); /* lazy bird */
302	char szVal[128];
303	RT_NOREF_PV(szVal); /* lazy bird */
304
305	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
306	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
307	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
308	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
309	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
310	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
311	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
312	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
313	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
314	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
315	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
316	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
317	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
318	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
319	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
320	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
321	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
322	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
323	STAMR3RegisterF(pVM, &pVCpu->iem.s.cMisalignedAtomics, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
324	"Number of misaligned (for the host) atomic instructions", "/IEM/CPU%u/cMisalignedAtomics", idCpu);
325
326	/* Code TLB: */
327	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
328	"Code TLB non-global revision", "/IEM/CPU%u/Tlb/Code/RevisionNonGlobal", idCpu);
329	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevisionGlobal, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
330	"Code TLB global revision", "/IEM/CPU%u/Tlb/Code/RevisionGlobal", idCpu);
331	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
332	"Code TLB non-global flushes", "/IEM/CPU%u/Tlb/Code/RevisionNonGlobalFlushes", idCpu);
333	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsGlobalFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
334	"Code TLB global flushes", "/IEM/CPU%u/Tlb/Code/RevisionGlobalFlushes", idCpu);
335	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
336	"Code TLB revision rollovers", "/IEM/CPU%u/Tlb/Code/RevisionRollovers", idCpu);
337
338	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
339	"Code TLB physical revision", "/IEM/CPU%u/Tlb/Code/PhysicalRevision", idCpu);
340	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
341	"Code TLB revision flushes", "/IEM/CPU%u/Tlb/Code/PhysicalRevisionFlushes", idCpu);
342	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
343	"Code TLB revision rollovers", "/IEM/CPU%u/Tlb/Code/PhysicalRevisionRollovers", idCpu);
344
345	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
346	"Code TLB misses", "/IEM/CPU%u/Tlb/Code/Misses", idCpu);
347	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
348	"Code TLB global loads", "/IEM/CPU%u/Tlb/Code/Misses/GlobalLoads", idCpu);
349	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowCodeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
350	"Code TLB slow read path", "/IEM/CPU%u/Tlb/Code/SlowReads", idCpu);
351	# ifdef IEM_WITH_TLB_STATISTICS
352	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
353	"Code TLB hits (non-native)", "/IEM/CPU%u/Tlb/Code/Hits/Other", idCpu);
354	# if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
355	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
356	"Code TLB native hits on new page", "/IEM/CPU%u/Tlb/Code/Hits/New-Page", idCpu);
357	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
358	"Code TLB native hits on new page /w offset", "/IEM/CPU%u/Tlb/Code/Hits/New-Page-With-Offset", idCpu);
359	# endif
360
361	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Code/Hits/*", idCpu);
362	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Code TLB hits",
363	"/IEM/CPU%u/Tlb/Code/Hits", idCpu);
364
365	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Code/Hits\|/IEM/CPU%u/Tlb/Code/Misses", idCpu, idCpu);
366	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Code TLB lookups (sum of hits and misses)",
367	"/IEM/CPU%u/Tlb/Code/AllLookups", idCpu);
368
369	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Code/Misses", idCpu);
370	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Code/Hits", idCpu);
371	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
372	"Code TLB actual miss rate", "/IEM/CPU%u/Tlb/Code/RateMisses", idCpu);
373
374	# if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
375	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissTag, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
376	"Code TLB misses in native code: Tag mismatch [not directly included grand parent sum]",
377	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/Tag", idCpu);
378	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissFlagsAndPhysRev, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
379	"Code TLB misses in native code: Flags or physical revision mistmatch [not directly included grand parent sum]",
380	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/FlagsAndPhysRev", idCpu);
381	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissAlignment, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
382	"Code TLB misses in native code: Alignment [not directly included grand parent sum]",
383	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/Alignment", idCpu);
384	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissCrossPage, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
385	"Code TLB misses in native code: Cross page [not directly included grand parent sum]",
386	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/CrossPage", idCpu);
387	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissNonCanonical, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
388	"Code TLB misses in native code: Non-canonical [not directly included grand parent sum]",
389	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/NonCanonical", idCpu);
390
391	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
392	"Code TLB native misses on new page",
393	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown2/New-Page", idCpu);
394	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
395	"Code TLB native misses on new page w/ offset",
396	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown2/New-Page-With-Offset", idCpu);
397	# endif
398	# endif /* IEM_WITH_TLB_STATISTICS */
399
400	/* Data TLB organized as best we can... */
401	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
402	"Data TLB non-global revision", "/IEM/CPU%u/Tlb/Data/RevisionNonGlobal", idCpu);
403	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevisionGlobal, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
404	"Data TLB global revision", "/IEM/CPU%u/Tlb/Data/RevisionGlobal", idCpu);
405	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
406	"Data TLB non-global flushes", "/IEM/CPU%u/Tlb/Data/RevisionNonGlobalFlushes", idCpu);
407	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsGlobalFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
408	"Data TLB global flushes", "/IEM/CPU%u/Tlb/Data/RevisionGlobalFlushes", idCpu);
409	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
410	"Data TLB revision rollovers", "/IEM/CPU%u/Tlb/Data/RevisionRollovers", idCpu);
411
412	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
413	"Data TLB physical revision", "/IEM/CPU%u/Tlb/Data/PhysicalRevision", idCpu);
414	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
415	"Data TLB revision flushes", "/IEM/CPU%u/Tlb/Data/PhysicalRevisionFlushes", idCpu);
416	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
417	"Data TLB revision rollovers", "/IEM/CPU%u/Tlb/Data/PhysicalRevisionRollovers", idCpu);
418
419	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
420	"Data TLB core misses (iemMemMap, direct iemMemMapJmp (not safe path))",
421	"/IEM/CPU%u/Tlb/Data/Misses/Core", idCpu);
422	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
423	"Data TLB global loads",
424	"/IEM/CPU%u/Tlb/Data/Misses/Core/GlobalLoads", idCpu);
425	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
426	"Data TLB safe read path (inline/native misses going to iemMemMapJmp)",
427	"/IEM/CPU%u/Tlb/Data/Misses/Safe/Reads", idCpu);
428	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
429	"Data TLB safe write path (inline/native misses going to iemMemMapJmp)",
430	"/IEM/CPU%u/Tlb/Data/Misses/Safe/Writes", idCpu);
431	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Misses/*", idCpu);
432	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB misses",
433	"/IEM/CPU%u/Tlb/Data/Misses", idCpu);
434
435	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Misses/Safe/*", idCpu);
436	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB actual safe path calls (read + write)",
437	"/IEM/CPU%u/Tlb/Data/Misses/Safe", idCpu);
438	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
439	"Data TLB hits in iemMemMapJmp - not part of safe-path total",
440	"/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartHits", idCpu);
441	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
442	"Data TLB misses in iemMemMapJmp - not part of safe-path total",
443	"/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartMisses", idCpu);
444	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
445	"Data TLB global loads",
446	"/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartMisses/GlobalLoads", idCpu);
447
448	# ifdef IEM_WITH_TLB_STATISTICS
449	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
450	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissTag, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
451	"Data TLB misses in native code: Tag mismatch [not directly included grand parent sum]",
452	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/Tag", idCpu);
453	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissFlagsAndPhysRev, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
454	"Data TLB misses in native code: Flags or physical revision mistmatch [not directly included grand parent sum]",
455	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/FlagsAndPhysRev", idCpu);
456	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissAlignment, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
457	"Data TLB misses in native code: Alignment [not directly included grand parent sum]",
458	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/Alignment", idCpu);
459	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissCrossPage, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
460	"Data TLB misses in native code: Cross page [not directly included grand parent sum]",
461	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/CrossPage", idCpu);
462	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissNonCanonical, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
463	"Data TLB misses in native code: Non-canonical [not directly included grand parent sum]",
464	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/NonCanonical", idCpu);
465	# endif
466	# endif
467
468	# ifdef IEM_WITH_TLB_STATISTICS
469	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
470	"Data TLB core hits (iemMemMap, direct iemMemMapJmp (not safe path))",
471	"/IEM/CPU%u/Tlb/Data/Hits/Core", idCpu);
472	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInlineCodeHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
473	"Data TLB hits in IEMAllMemRWTmplInline.cpp.h",
474	"/IEM/CPU%u/Tlb/Data/Hits/Inline", idCpu);
475	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
476	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStack, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
477	"Data TLB native stack access hits",
478	"/IEM/CPU%u/Tlb/Data/Hits/Native/Stack", idCpu);
479	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForFetch, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
480	"Data TLB native data fetch hits",
481	"/IEM/CPU%u/Tlb/Data/Hits/Native/Fetch", idCpu);
482	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStore, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
483	"Data TLB native data store hits",
484	"/IEM/CPU%u/Tlb/Data/Hits/Native/Store", idCpu);
485	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForMapped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
486	"Data TLB native mapped data hits",
487	"/IEM/CPU%u/Tlb/Data/Hits/Native/Mapped", idCpu);
488	# endif
489	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits/*", idCpu);
490	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB hits",
491	"/IEM/CPU%u/Tlb/Data/Hits", idCpu);
492
493	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
494	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits/Native/*", idCpu);
495	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB hits from native code",
496	"/IEM/CPU%u/Tlb/Data/Hits/Native", idCpu);
497	# endif
498
499	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Data/Hits\|/IEM/CPU%u/Tlb/Data/Misses", idCpu, idCpu);
500	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB lookups (sum of hits and misses)",
501	"/IEM/CPU%u/Tlb/Data/AllLookups", idCpu);
502
503	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Data/Misses", idCpu);
504	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits", idCpu);
505	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
506	"Data TLB actual miss rate", "/IEM/CPU%u/Tlb/Data/RateMisses", idCpu);
507
508	# endif /* IEM_WITH_TLB_STATISTICS */
509
510
511	#ifdef VBOX_WITH_IEM_RECOMPILER
512	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecNative, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
513	"Executed native translation block", "/IEM/CPU%u/re/cTbExecNative", idCpu);
514	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecThreaded, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
515	"Executed threaded translation block", "/IEM/CPU%u/re/cTbExecThreaded", idCpu);
516	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
517	"Times threaded TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecThreadedBreaks", idCpu);
518	# ifdef VBOX_WITH_STATISTICS
519	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaksWithLookup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
520	"Times threaded TB execution was interrupted/broken off on a call with lookup entries", "/IEM/CPU%u/re/cTbExecThreadedBreaksWithLookup", idCpu);
521	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaksWithoutLookup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
522	"Times threaded TB execution was interrupted/broken off on a call without lookup entries", "/IEM/CPU%u/re/cTbExecThreadedBreaksWithoutLookup", idCpu);
523	# endif
524
525	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
526	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatAllocs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
527	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocCalls", idCpu);
528	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatFrees, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
529	"Translation block frees", "/IEM/CPU%u/re/cTbFreeCalls", idCpu);
530	# ifdef VBOX_WITH_STATISTICS
531	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
532	"Time spent freeing up TBs when full at alloc", "/IEM/CPU%u/re/TbPruningAlloc", idCpu);
533	# endif
534	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPruneNative, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
535	"Time spent freeing up native TBs when out of executable memory", "/IEM/CPU%u/re/ExecMem/TbPruningNative", idCpu);
536	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cAllocatedChunks, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
537	"Populated TB chunks", "/IEM/CPU%u/re/cTbChunks", idCpu);
538	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxChunks, STAMTYPE_U8, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
539	"Max number of TB chunks", "/IEM/CPU%u/re/cTbChunksMax", idCpu);
540	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cTotalTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
541	"Total number of TBs in the allocator", "/IEM/CPU%u/re/cTbTotal", idCpu);
542	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
543	"Max total number of TBs allowed", "/IEM/CPU%u/re/cTbTotalMax", idCpu);
544	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cInUseTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
545	"Number of currently allocated TBs", "/IEM/CPU%u/re/cTbAllocated", idCpu);
546	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cNativeTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
547	"Number of currently allocated native TBs", "/IEM/CPU%u/re/cTbAllocatedNative", idCpu);
548	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cThreadedTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
549	"Number of currently allocated threaded TBs", "/IEM/CPU%u/re/cTbAllocatedThreaded", idCpu);
550
551	PIEMTBCACHE const pTbCache = pVCpu->iem.s.pTbCacheR3;
552	STAMR3RegisterF(pVM, (void *)&pTbCache->cHash, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
553	"Translation block lookup table size", "/IEM/CPU%u/re/cTbHashTab", idCpu);
554
555	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHits, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
556	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
557	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHitsViaTbLookupTable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
558	"Translation block lookup hits via TB lookup table associated with the previous TB", "/IEM/CPU%u/re/cTbLookupHitsViaTbLookupTable", idCpu);
559	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
560	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
561	STAMR3RegisterF(pVM, (void *)&pTbCache->cCollisions, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
562	"Translation block hash table collisions", "/IEM/CPU%u/re/cTbCollisions", idCpu);
563	# ifdef VBOX_WITH_STATISTICS
564	STAMR3RegisterF(pVM, (void *)&pTbCache->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
565	"Time spent shortening collision lists", "/IEM/CPU%u/re/TbPruningCollisions", idCpu);
566	# endif
567
568	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
569	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
570	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
571	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
572	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLookupEntries, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
573	"TB lookup table entries per threaded translation block", "/IEM/CPU%u/re/ThrdLookupEntriesPerTb", idCpu);
574
575	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
576	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
577	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
578	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
579	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
580	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
581	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
582	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
583	# ifdef VBOX_WITH_STATISTICS
584	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopInTbDetected, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
585	"Detected loop within TB", "/IEM/CPU%u/re/LoopInTbDetected", idCpu);
586	#endif
587
588	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeExecMemInstrBufAllocFailed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
589	"Number of times the exec memory allocator failed to allocate a large enough buffer",
590	"/IEM/CPU%u/re/NativeExecMemInstrBufAllocFailed", idCpu);
591
592	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsRecompiled, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
593	"Number of threaded calls per TB that have been properly recompiled to native code",
594	"/IEM/CPU%u/re/NativeCallsRecompiledPerTb", idCpu);
595	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsThreaded, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
596	"Number of threaded calls per TB that could not be recompiler to native code",
597	"/IEM/CPU%u/re/NativeCallsThreadedPerTb", idCpu);
598	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeFullyRecompiledTbs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
599	"Number of threaded calls that could not be recompiler to native code",
600	"/IEM/CPU%u/re/NativeFullyRecompiledTbs", idCpu);
601
602	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbNativeCode, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES_PER_TB,
603	"Size of native code per TB", "/IEM/CPU%u/re/NativeCodeSizePerTb", idCpu);
604	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeRecompilation, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
605	"Profiling iemNativeRecompile()", "/IEM/CPU%u/re/NativeRecompilation", idCpu);
606
607	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
608	# ifdef VBOX_WITH_STATISTICS
609	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
610	"Number of calls to iemNativeRegAllocFindFree.",
611	"/IEM/CPU%u/re/NativeRegFindFree", idCpu);
612	# endif
613	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
614	"Number of times iemNativeRegAllocFindFree needed to free a variable.",
615	"/IEM/CPU%u/re/NativeRegFindFreeVar", idCpu);
616	# ifdef VBOX_WITH_STATISTICS
617	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
618	"Number of times iemNativeRegAllocFindFree did not needed to free any variables.",
619	"/IEM/CPU%u/re/NativeRegFindFreeNoVar", idCpu);
620	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
621	"Times liveness info freeed up shadowed guest registers in iemNativeRegAllocFindFree.",
622	"/IEM/CPU%u/re/NativeRegFindFreeLivenessUnshadowed", idCpu);
623	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
624	"Times liveness info helped finding the return register in iemNativeRegAllocFindFree.",
625	"/IEM/CPU%u/re/NativeRegFindFreeLivenessHelped", idCpu);
626
627	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkippedArithmetic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
628	"Skipped all status flag updating, arithmetic instructions",
629	"/IEM/CPU%u/re/NativeEFlagsSkippedArithmetic", idCpu);
630	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkippedLogical, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
631	"Skipped all status flag updating, logical instructions",
632	"/IEM/CPU%u/re/NativeEFlagsSkippedLogical", idCpu);
633
634	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu);
635	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippable", idCpu);
636	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippable", idCpu);
637	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippable", idCpu);
638	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippable", idCpu);
639	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippable", idCpu);
640
641	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfRequired", idCpu);
642	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfRequired", idCpu);
643	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfRequired", idCpu);
644	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfRequired", idCpu);
645	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfRequired", idCpu);
646	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfRequired", idCpu);
647
648	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
649	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsCfDelayable", idCpu);
650	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsPfDelayable", idCpu);
651	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsAfDelayable", idCpu);
652	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsZfDelayable", idCpu);
653	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsSfDelayable", idCpu);
654	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlagsOfDelayable", idCpu);
655	# endif
656
657	/* Sum up all status bits ('_' is a sorting hack). */
658	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fSkippable*", idCpu);
659	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total skippable EFLAGS status bit updating",
660	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu);
661
662	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fRequired*", idCpu);
663	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total required STATUS status bit updating",
664	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusRequired", idCpu);
665
666	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
667	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?fDelayable*", idCpu);
668	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total potentially delayable STATUS status bit updating",
669	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu);
670	# endif
671
672	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags?f*", idCpu);
673	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total STATUS status bit events of any kind",
674	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu);
675
676	/* Ratio of the status bit skippables. */
677	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusTotal", idCpu);
678	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippable", idCpu);
679	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
680	"Total skippable EFLAGS status bit updating percentage",
681	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusSkippablePct", idCpu);
682
683	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
684	/* Ratio of the status bit skippables. */
685	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayable", idCpu);
686	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
687	"Total potentially delayable EFLAGS status bit updating percentage",
688	"/IEM/CPU%u/re/NativeLivenessEFlags_StatusDelayablePct", idCpu);
689	# endif
690
691	/* Ratios of individual bits. */
692	size_t const offFlagChar = RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlagsCf*", idCpu) - 3;
693	Assert(szPat[offFlagChar] == 'C');
694	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippable", idCpu);
695	Assert(szVal[offFlagChar] == 'C');
696	szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsCfSkippablePct", idCpu);
697	szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsPfSkippablePct", idCpu);
698	szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsAfSkippablePct", idCpu);
699	szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsZfSkippablePct", idCpu);
700	szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsSfSkippablePct", idCpu);
701	szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlagsOfSkippablePct", idCpu);
702
703	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Total RIP updates", "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
704	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateDelayed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Delayed RIP updates", "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
705
706	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
707	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
708	"Number of calls to iemNativeSimdRegAllocFindFree.",
709	"/IEM/CPU%u/re/NativeSimdRegFindFree", idCpu);
710	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
711	"Number of times iemNativeSimdRegAllocFindFree needed to free a variable.",
712	"/IEM/CPU%u/re/NativeSimdRegFindFreeVar", idCpu);
713	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
714	"Number of times iemNativeSimdRegAllocFindFree did not needed to free any variables.",
715	"/IEM/CPU%u/re/NativeSimdRegFindFreeNoVar", idCpu);
716	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
717	"Times liveness info freeed up shadowed guest registers in iemNativeSimdRegAllocFindFree.",
718	"/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessUnshadowed", idCpu);
719	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
720	"Times liveness info helped finding the return register in iemNativeSimdRegAllocFindFree.",
721	"/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessHelped", idCpu);
722
723	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks",
724	"/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckPotential", idCpu);
725	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks",
726	"/IEM/CPU%u/re/NativeMaybeWaitDeviceNotAvailXcptCheckPotential", idCpu);
727	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks",
728	"/IEM/CPU%u/re/NativeMaybeSseXcptCheckPotential", idCpu);
729	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks",
730	"/IEM/CPU%u/re/NativeMaybeAvxXcptCheckPotential", idCpu);
731
732	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted",
733	"/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckOmitted", idCpu);
734	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted",
735	"/IEM/CPU%u/re/NativeMaybeWaitDeviceNotAvailXcptCheckOmitted", idCpu);
736	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted",
737	"/IEM/CPU%u/re/NativeMaybeSseXcptCheckOmitted", idCpu);
738	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted",
739	"/IEM/CPU%u/re/NativeMaybeAvxXcptCheckOmitted", idCpu);
740	# endif
741
742	/* Ratio of the status bit skippables. */
743	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
744	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
745	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
746	"Delayed RIP updating percentage",
747	"/IEM/CPU%u/re/NativePcUpdateDelayed_StatusDelayedPct", idCpu);
748
749	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbFinished, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
750	"Number of times the TB finishes execution completely",
751	"/IEM/CPU%u/re/NativeTbFinished", idCpu);
752	# endif /* VBOX_WITH_STATISTICS */
753	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnBreak, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
754	"Number of times the TB finished through the ReturnBreak label",
755	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak", idCpu);
756	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnBreakFF, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
757	"Number of times the TB finished through the ReturnBreak label",
758	"/IEM/CPU%u/re/NativeTbExit/ReturnBreakFF", idCpu);
759	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnWithFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
760	"Number of times the TB finished through the ReturnWithFlags label",
761	"/IEM/CPU%u/re/NativeTbExit/ReturnWithFlags", idCpu);
762	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnOtherStatus, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
763	"Number of times the TB finished with some other status value",
764	"/IEM/CPU%u/re/NativeTbExit/ReturnOtherStatus", idCpu);
765	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitLongJump, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
766	"Number of times the TB finished via long jump / throw",
767	"/IEM/CPU%u/re/NativeTbExit/LongJumps", idCpu);
768	/* These end up returning VINF_IEM_REEXEC_BREAK and are thus already counted under NativeTbExit/ReturnBreak: */
769	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitObsoleteTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
770	"Number of times the TB finished through the ObsoleteTb label",
771	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/ObsoleteTb", idCpu);
772	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
773	"Number of times the TB finished through the NeedCsLimChecking label",
774	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/NeedCsLimChecking", idCpu);
775	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
776	"Number of times the TB finished through the CheckBranchMiss label",
777	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/CheckBranchMiss", idCpu);
778	/* Raising stuff will either increment NativeTbExit/LongJumps or NativeTbExit/ReturnOtherStatus
779	depending on whether VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is defined: */
780	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
781	# define RAISE_PREFIX "/IEM/CPU%u/re/NativeTbExit/ReturnOtherStatus/"
782	# else
783	# define RAISE_PREFIX "/IEM/CPU%u/re/NativeTbExit/LongJumps/"
784	# endif
785	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseDe, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
786	"Number of times the TB finished raising a #DE exception",
787	RAISE_PREFIX "RaiseDe", idCpu);
788	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseUd, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
789	"Number of times the TB finished raising a #UD exception",
790	RAISE_PREFIX "RaiseUd", idCpu);
791	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseSseRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
792	"Number of times the TB finished raising a SSE related exception",
793	RAISE_PREFIX "RaiseSseRelated", idCpu);
794	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseAvxRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
795	"Number of times the TB finished raising a AVX related exception",
796	RAISE_PREFIX "RaiseAvxRelated", idCpu);
797	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseSseAvxFpRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
798	"Number of times the TB finished raising a SSE/AVX floating point related exception",
799	RAISE_PREFIX "RaiseSseAvxFpRelated", idCpu);
800	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseNm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
801	"Number of times the TB finished raising a #NM exception",
802	RAISE_PREFIX "RaiseNm", idCpu);
803	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseGp0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
804	"Number of times the TB finished raising a #GP(0) exception",
805	RAISE_PREFIX "RaiseGp0", idCpu);
806	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseMf, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
807	"Number of times the TB finished raising a #MF exception",
808	RAISE_PREFIX "RaiseMf", idCpu);
809	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseXf, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
810	"Number of times the TB finished raising a #XF exception",
811	RAISE_PREFIX "RaiseXf", idCpu);
812
813	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1Irq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
814	"Direct linking #1 with IRQ check succeeded",
815	"/IEM/CPU%u/re/NativeTbExit/DirectLinking1Irq", idCpu);
816	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1NoIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
817	"Direct linking #1 w/o IRQ check succeeded",
818	"/IEM/CPU%u/re/NativeTbExit/DirectLinking1NoIrq", idCpu);
819	# ifdef VBOX_WITH_STATISTICS
820	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1NoTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
821	"Direct linking #1 failed: No TB in lookup table",
822	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1NoTb", idCpu);
823	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchGCPhysPc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
824	"Direct linking #1 failed: GCPhysPc mismatch",
825	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1MismatchGCPhysPc", idCpu);
826	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
827	"Direct linking #1 failed: TB flags mismatch",
828	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1MismatchFlags", idCpu);
829	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1PendingIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
830	"Direct linking #1 failed: IRQ or FF pending",
831	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1PendingIrq", idCpu);
832	# endif
833
834	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2Irq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
835	"Direct linking #2 with IRQ check succeeded",
836	"/IEM/CPU%u/re/NativeTbExit/DirectLinking2Irq", idCpu);
837	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2NoIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
838	"Direct linking #2 w/o IRQ check succeeded",
839	"/IEM/CPU%u/re/NativeTbExit/DirectLinking2NoIrq", idCpu);
840	# ifdef VBOX_WITH_STATISTICS
841	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2NoTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
842	"Direct linking #2 failed: No TB in lookup table",
843	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2NoTb", idCpu);
844	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchGCPhysPc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
845	"Direct linking #2 failed: GCPhysPc mismatch",
846	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2MismatchGCPhysPc", idCpu);
847	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
848	"Direct linking #2 failed: TB flags mismatch",
849	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2MismatchFlags", idCpu);
850	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2PendingIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
851	"Direct linking #2 failed: IRQ or FF pending",
852	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2PendingIrq", idCpu);
853	# endif
854
855	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeTbExit/", idCpu); / only immediate children, no sub folders */
856	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
857	"Number of times native TB execution finished before the end (not counting thrown memory++ exceptions)",
858	"/IEM/CPU%u/re/NativeTbExit", idCpu);
859
860
861	# endif /* VBOX_WITH_IEM_NATIVE_RECOMPILER */
862
863
864	# ifdef VBOX_WITH_STATISTICS
865	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemMapJmp, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
866	"iemMemMapJmp calls", "/IEM/CPU%u/iemMemMapJmp", idCpu);
867	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemMapNoJmp, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
868	"iemMemMap calls", "/IEM/CPU%u/iemMemMapNoJmp", idCpu);
869	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemBounceBufferCrossPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
870	"iemMemBounceBufferMapCrossPage calls", "/IEM/CPU%u/iemMemMapBounceBufferCrossPage", idCpu);
871	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemBounceBufferMapPhys, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
872	"iemMemBounceBufferMapPhys calls", "/IEM/CPU%u/iemMemMapBounceBufferMapPhys", idCpu);
873	# endif
874
875
876	#endif /* VBOX_WITH_IEM_RECOMPILER */
877
878	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
879	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
880	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
881	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
882	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
883	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
884
885	# if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
886	/* Instruction statistics: */
887	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
888	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
889	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
890	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
891	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
892	# include "IEMInstructionStatisticsTmpl.h"
893	# undef IEM_DO_INSTR_STAT
894	# endif
895
896	# if defined(VBOX_WITH_STATISTICS) && defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
897	/* Threaded function statistics: */
898	for (unsigned i = 1; i < (unsigned)kIemThreadedFunc_End; i++)
899	STAMR3RegisterF(pVM, &pVCpu->iem.s.acThreadedFuncStats[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED,
900	STAMUNIT_COUNT, NULL, "/IEM/CPU%u/ThrdFuncs/%s", idCpu, g_apszIemThreadedFunctionStats[i]);
901	# endif
902
903	#endif /* !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) - quick fix for stupid structure duplication non-sense */
904	}
905
906	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
907	/*
908	* Register the per-VM VMX APIC-access page handler type.
909	*/
910	if (pVM->cpum.ro.GuestFeatures.fVmx)
911	{
912	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
913	iemVmxApicAccessPageHandler,
914	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
915	AssertLogRelRCReturn(rc, rc);
916	}
917	#endif
918
919	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
920	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
921	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
922	DBGFR3InfoRegisterInternalArgv(pVM, "tb", "IEM translation block", iemR3InfoTb, DBGFINFO_FLAGS_RUN_ON_EMT);
923	#endif
924	#ifdef VBOX_WITH_DEBUGGER
925	iemR3RegisterDebuggerCommands();
926	#endif
927
928	return VINF_SUCCESS;
929	}
930
931
932	VMMR3DECL(int) IEMR3Term(PVM pVM)
933	{
934	NOREF(pVM);
935	return VINF_SUCCESS;
936	}
937
938
939	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
940	{
941	RT_NOREF(pVM);
942	}
943
944
945	/**
946	* Gets the name of a generic IEM exit code.
947	*
948	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
949	* @param uExit The IEM exit to name.
950	*/
951	VMMR3DECL(const char *) IEMR3GetExitName(uint32_t uExit)
952	{
953	static const char * const s_apszNames[] =
954	{
955	/* external interrupts */
956	"ExtInt 00h", "ExtInt 01h", "ExtInt 02h", "ExtInt 03h", "ExtInt 04h", "ExtInt 05h", "ExtInt 06h", "ExtInt 07h",
957	"ExtInt 08h", "ExtInt 09h", "ExtInt 0ah", "ExtInt 0bh", "ExtInt 0ch", "ExtInt 0dh", "ExtInt 0eh", "ExtInt 0fh",
958	"ExtInt 10h", "ExtInt 11h", "ExtInt 12h", "ExtInt 13h", "ExtInt 14h", "ExtInt 15h", "ExtInt 16h", "ExtInt 17h",
959	"ExtInt 18h", "ExtInt 19h", "ExtInt 1ah", "ExtInt 1bh", "ExtInt 1ch", "ExtInt 1dh", "ExtInt 1eh", "ExtInt 1fh",
960	"ExtInt 20h", "ExtInt 21h", "ExtInt 22h", "ExtInt 23h", "ExtInt 24h", "ExtInt 25h", "ExtInt 26h", "ExtInt 27h",
961	"ExtInt 28h", "ExtInt 29h", "ExtInt 2ah", "ExtInt 2bh", "ExtInt 2ch", "ExtInt 2dh", "ExtInt 2eh", "ExtInt 2fh",
962	"ExtInt 30h", "ExtInt 31h", "ExtInt 32h", "ExtInt 33h", "ExtInt 34h", "ExtInt 35h", "ExtInt 36h", "ExtInt 37h",
963	"ExtInt 38h", "ExtInt 39h", "ExtInt 3ah", "ExtInt 3bh", "ExtInt 3ch", "ExtInt 3dh", "ExtInt 3eh", "ExtInt 3fh",
964	"ExtInt 40h", "ExtInt 41h", "ExtInt 42h", "ExtInt 43h", "ExtInt 44h", "ExtInt 45h", "ExtInt 46h", "ExtInt 47h",
965	"ExtInt 48h", "ExtInt 49h", "ExtInt 4ah", "ExtInt 4bh", "ExtInt 4ch", "ExtInt 4dh", "ExtInt 4eh", "ExtInt 4fh",
966	"ExtInt 50h", "ExtInt 51h", "ExtInt 52h", "ExtInt 53h", "ExtInt 54h", "ExtInt 55h", "ExtInt 56h", "ExtInt 57h",
967	"ExtInt 58h", "ExtInt 59h", "ExtInt 5ah", "ExtInt 5bh", "ExtInt 5ch", "ExtInt 5dh", "ExtInt 5eh", "ExtInt 5fh",
968	"ExtInt 60h", "ExtInt 61h", "ExtInt 62h", "ExtInt 63h", "ExtInt 64h", "ExtInt 65h", "ExtInt 66h", "ExtInt 67h",
969	"ExtInt 68h", "ExtInt 69h", "ExtInt 6ah", "ExtInt 6bh", "ExtInt 6ch", "ExtInt 6dh", "ExtInt 6eh", "ExtInt 6fh",
970	"ExtInt 70h", "ExtInt 71h", "ExtInt 72h", "ExtInt 73h", "ExtInt 74h", "ExtInt 75h", "ExtInt 76h", "ExtInt 77h",
971	"ExtInt 78h", "ExtInt 79h", "ExtInt 7ah", "ExtInt 7bh", "ExtInt 7ch", "ExtInt 7dh", "ExtInt 7eh", "ExtInt 7fh",
972	"ExtInt 80h", "ExtInt 81h", "ExtInt 82h", "ExtInt 83h", "ExtInt 84h", "ExtInt 85h", "ExtInt 86h", "ExtInt 87h",
973	"ExtInt 88h", "ExtInt 89h", "ExtInt 8ah", "ExtInt 8bh", "ExtInt 8ch", "ExtInt 8dh", "ExtInt 8eh", "ExtInt 8fh",
974	"ExtInt 90h", "ExtInt 91h", "ExtInt 92h", "ExtInt 93h", "ExtInt 94h", "ExtInt 95h", "ExtInt 96h", "ExtInt 97h",
975	"ExtInt 98h", "ExtInt 99h", "ExtInt 9ah", "ExtInt 9bh", "ExtInt 9ch", "ExtInt 9dh", "ExtInt 9eh", "ExtInt 9fh",
976	"ExtInt a0h", "ExtInt a1h", "ExtInt a2h", "ExtInt a3h", "ExtInt a4h", "ExtInt a5h", "ExtInt a6h", "ExtInt a7h",
977	"ExtInt a8h", "ExtInt a9h", "ExtInt aah", "ExtInt abh", "ExtInt ach", "ExtInt adh", "ExtInt aeh", "ExtInt afh",
978	"ExtInt b0h", "ExtInt b1h", "ExtInt b2h", "ExtInt b3h", "ExtInt b4h", "ExtInt b5h", "ExtInt b6h", "ExtInt b7h",
979	"ExtInt b8h", "ExtInt b9h", "ExtInt bah", "ExtInt bbh", "ExtInt bch", "ExtInt bdh", "ExtInt beh", "ExtInt bfh",
980	"ExtInt c0h", "ExtInt c1h", "ExtInt c2h", "ExtInt c3h", "ExtInt c4h", "ExtInt c5h", "ExtInt c6h", "ExtInt c7h",
981	"ExtInt c8h", "ExtInt c9h", "ExtInt cah", "ExtInt cbh", "ExtInt cch", "ExtInt cdh", "ExtInt ceh", "ExtInt cfh",
982	"ExtInt d0h", "ExtInt d1h", "ExtInt d2h", "ExtInt d3h", "ExtInt d4h", "ExtInt d5h", "ExtInt d6h", "ExtInt d7h",
983	"ExtInt d8h", "ExtInt d9h", "ExtInt dah", "ExtInt dbh", "ExtInt dch", "ExtInt ddh", "ExtInt deh", "ExtInt dfh",
984	"ExtInt e0h", "ExtInt e1h", "ExtInt e2h", "ExtInt e3h", "ExtInt e4h", "ExtInt e5h", "ExtInt e6h", "ExtInt e7h",
985	"ExtInt e8h", "ExtInt e9h", "ExtInt eah", "ExtInt ebh", "ExtInt ech", "ExtInt edh", "ExtInt eeh", "ExtInt efh",
986	"ExtInt f0h", "ExtInt f1h", "ExtInt f2h", "ExtInt f3h", "ExtInt f4h", "ExtInt f5h", "ExtInt f6h", "ExtInt f7h",
987	"ExtInt f8h", "ExtInt f9h", "ExtInt fah", "ExtInt fbh", "ExtInt fch", "ExtInt fdh", "ExtInt feh", "ExtInt ffh",
988	/* software interrups */
989	"SoftInt 00h", "SoftInt 01h", "SoftInt 02h", "SoftInt 03h", "SoftInt 04h", "SoftInt 05h", "SoftInt 06h", "SoftInt 07h",
990	"SoftInt 08h", "SoftInt 09h", "SoftInt 0ah", "SoftInt 0bh", "SoftInt 0ch", "SoftInt 0dh", "SoftInt 0eh", "SoftInt 0fh",
991	"SoftInt 10h", "SoftInt 11h", "SoftInt 12h", "SoftInt 13h", "SoftInt 14h", "SoftInt 15h", "SoftInt 16h", "SoftInt 17h",
992	"SoftInt 18h", "SoftInt 19h", "SoftInt 1ah", "SoftInt 1bh", "SoftInt 1ch", "SoftInt 1dh", "SoftInt 1eh", "SoftInt 1fh",
993	"SoftInt 20h", "SoftInt 21h", "SoftInt 22h", "SoftInt 23h", "SoftInt 24h", "SoftInt 25h", "SoftInt 26h", "SoftInt 27h",
994	"SoftInt 28h", "SoftInt 29h", "SoftInt 2ah", "SoftInt 2bh", "SoftInt 2ch", "SoftInt 2dh", "SoftInt 2eh", "SoftInt 2fh",
995	"SoftInt 30h", "SoftInt 31h", "SoftInt 32h", "SoftInt 33h", "SoftInt 34h", "SoftInt 35h", "SoftInt 36h", "SoftInt 37h",
996	"SoftInt 38h", "SoftInt 39h", "SoftInt 3ah", "SoftInt 3bh", "SoftInt 3ch", "SoftInt 3dh", "SoftInt 3eh", "SoftInt 3fh",
997	"SoftInt 40h", "SoftInt 41h", "SoftInt 42h", "SoftInt 43h", "SoftInt 44h", "SoftInt 45h", "SoftInt 46h", "SoftInt 47h",
998	"SoftInt 48h", "SoftInt 49h", "SoftInt 4ah", "SoftInt 4bh", "SoftInt 4ch", "SoftInt 4dh", "SoftInt 4eh", "SoftInt 4fh",
999	"SoftInt 50h", "SoftInt 51h", "SoftInt 52h", "SoftInt 53h", "SoftInt 54h", "SoftInt 55h", "SoftInt 56h", "SoftInt 57h",
1000	"SoftInt 58h", "SoftInt 59h", "SoftInt 5ah", "SoftInt 5bh", "SoftInt 5ch", "SoftInt 5dh", "SoftInt 5eh", "SoftInt 5fh",
1001	"SoftInt 60h", "SoftInt 61h", "SoftInt 62h", "SoftInt 63h", "SoftInt 64h", "SoftInt 65h", "SoftInt 66h", "SoftInt 67h",
1002	"SoftInt 68h", "SoftInt 69h", "SoftInt 6ah", "SoftInt 6bh", "SoftInt 6ch", "SoftInt 6dh", "SoftInt 6eh", "SoftInt 6fh",
1003	"SoftInt 70h", "SoftInt 71h", "SoftInt 72h", "SoftInt 73h", "SoftInt 74h", "SoftInt 75h", "SoftInt 76h", "SoftInt 77h",
1004	"SoftInt 78h", "SoftInt 79h", "SoftInt 7ah", "SoftInt 7bh", "SoftInt 7ch", "SoftInt 7dh", "SoftInt 7eh", "SoftInt 7fh",
1005	"SoftInt 80h", "SoftInt 81h", "SoftInt 82h", "SoftInt 83h", "SoftInt 84h", "SoftInt 85h", "SoftInt 86h", "SoftInt 87h",
1006	"SoftInt 88h", "SoftInt 89h", "SoftInt 8ah", "SoftInt 8bh", "SoftInt 8ch", "SoftInt 8dh", "SoftInt 8eh", "SoftInt 8fh",
1007	"SoftInt 90h", "SoftInt 91h", "SoftInt 92h", "SoftInt 93h", "SoftInt 94h", "SoftInt 95h", "SoftInt 96h", "SoftInt 97h",
1008	"SoftInt 98h", "SoftInt 99h", "SoftInt 9ah", "SoftInt 9bh", "SoftInt 9ch", "SoftInt 9dh", "SoftInt 9eh", "SoftInt 9fh",
1009	"SoftInt a0h", "SoftInt a1h", "SoftInt a2h", "SoftInt a3h", "SoftInt a4h", "SoftInt a5h", "SoftInt a6h", "SoftInt a7h",
1010	"SoftInt a8h", "SoftInt a9h", "SoftInt aah", "SoftInt abh", "SoftInt ach", "SoftInt adh", "SoftInt aeh", "SoftInt afh",
1011	"SoftInt b0h", "SoftInt b1h", "SoftInt b2h", "SoftInt b3h", "SoftInt b4h", "SoftInt b5h", "SoftInt b6h", "SoftInt b7h",
1012	"SoftInt b8h", "SoftInt b9h", "SoftInt bah", "SoftInt bbh", "SoftInt bch", "SoftInt bdh", "SoftInt beh", "SoftInt bfh",
1013	"SoftInt c0h", "SoftInt c1h", "SoftInt c2h", "SoftInt c3h", "SoftInt c4h", "SoftInt c5h", "SoftInt c6h", "SoftInt c7h",
1014	"SoftInt c8h", "SoftInt c9h", "SoftInt cah", "SoftInt cbh", "SoftInt cch", "SoftInt cdh", "SoftInt ceh", "SoftInt cfh",
1015	"SoftInt d0h", "SoftInt d1h", "SoftInt d2h", "SoftInt d3h", "SoftInt d4h", "SoftInt d5h", "SoftInt d6h", "SoftInt d7h",
1016	"SoftInt d8h", "SoftInt d9h", "SoftInt dah", "SoftInt dbh", "SoftInt dch", "SoftInt ddh", "SoftInt deh", "SoftInt dfh",
1017	"SoftInt e0h", "SoftInt e1h", "SoftInt e2h", "SoftInt e3h", "SoftInt e4h", "SoftInt e5h", "SoftInt e6h", "SoftInt e7h",
1018	"SoftInt e8h", "SoftInt e9h", "SoftInt eah", "SoftInt ebh", "SoftInt ech", "SoftInt edh", "SoftInt eeh", "SoftInt efh",
1019	"SoftInt f0h", "SoftInt f1h", "SoftInt f2h", "SoftInt f3h", "SoftInt f4h", "SoftInt f5h", "SoftInt f6h", "SoftInt f7h",
1020	"SoftInt f8h", "SoftInt f9h", "SoftInt fah", "SoftInt fbh", "SoftInt fch", "SoftInt fdh", "SoftInt feh", "SoftInt ffh",
1021	};
1022	if (uExit < RT_ELEMENTS(s_apszNames))
1023	return s_apszNames[uExit];
1024	return NULL;
1025	}
1026
1027
1028	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
1029	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
1030	{
1031	if (*pfHeader)
1032	return;
1033	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
1034	*pfHeader = true;
1035	}
1036
1037
1038	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
1039	static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe, uint32_t uSlot)
1040	{
1041	pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
1042	uSlot,
1043	(pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
1044	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
1045	: "expired",
1046	(pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
1047	pTlbe->GCPhys, pTlbe->pbMappingR3,
1048	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
1049	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
1050	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
1051	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
1052	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
1053	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
1054	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
1055	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
1056	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
1057	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
1058	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
1059	}
1060
1061
1062	/** Displays one or more TLB slots. */
1063	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
1064	uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
1065	{
1066	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
1067	{
1068	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
1069	{
1070	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
1071	cSlots, RT_ELEMENTS(pTlb->aEntries));
1072	cSlots = RT_ELEMENTS(pTlb->aEntries);
1073	}
1074
1075	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
1076	while (cSlots-- > 0)
1077	{
1078	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
1079	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
1080	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
1081	}
1082	}
1083	else
1084	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
1085	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
1086	}
1087
1088
1089	/** Displays the TLB slot for the given address. */
1090	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
1091	uint64_t uAddress, bool *pfHeader)
1092	{
1093	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
1094
1095	uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
1096	uint32_t const uSlot = (uint8_t)uTag;
1097	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
1098	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
1099	Tlbe.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
1100	: (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
1101	iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
1102	}
1103
1104
1105	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
1106	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
1107	{
1108	/*
1109	* This is entirely argument driven.
1110	*/
1111	static RTGETOPTDEF const s_aOptions[] =
1112	{
1113	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1114	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1115	{ "all", 'A', RTGETOPT_REQ_NOTHING },
1116	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
1117	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1118	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
1119	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
1120	};
1121
1122	char szDefault[] = "-A";
1123	char *papszDefaults[2] = { szDefault, NULL };
1124	if (cArgs == 0)
1125	{
1126	cArgs = 1;
1127	papszArgs = papszDefaults;
1128	}
1129
1130	RTGETOPTSTATE State;
1131	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
1132	AssertRCReturnVoid(rc);
1133
1134	bool fNeedHeader = true;
1135	bool fAddressMode = true;
1136	PVMCPU pVCpu = VMMGetCpu(pVM);
1137	if (!pVCpu)
1138	pVCpu = VMMGetCpuById(pVM, 0);
1139
1140	RTGETOPTUNION ValueUnion;
1141	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1142	{
1143	switch (rc)
1144	{
1145	case 'c':
1146	if (ValueUnion.u32 >= pVM->cCpus)
1147	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1148	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
1149	{
1150	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1151	fNeedHeader = true;
1152	}
1153	break;
1154
1155	case 'a':
1156	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1157	ValueUnion.u64, &fNeedHeader);
1158	fAddressMode = true;
1159	break;
1160
1161	case 'A':
1162	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1163	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
1164	break;
1165
1166	case 'r':
1167	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1168	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
1169	fAddressMode = false;
1170	break;
1171
1172	case 's':
1173	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1174	ValueUnion.u32, 1, &fNeedHeader);
1175	fAddressMode = false;
1176	break;
1177
1178	case VINF_GETOPT_NOT_OPTION:
1179	if (fAddressMode)
1180	{
1181	uint64_t uAddr;
1182	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
1183	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
1184	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1185	uAddr, &fNeedHeader);
1186	else
1187	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
1188	}
1189	else
1190	{
1191	uint32_t uSlot;
1192	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
1193	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
1194	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1195	uSlot, 1, &fNeedHeader);
1196	else
1197	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
1198	}
1199	break;
1200
1201	case 'h':
1202	pHlp->pfnPrintf(pHlp,
1203	"Usage: info %ctlb [options]\n"
1204	"\n"
1205	"Options:\n"
1206	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
1207	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
1208	" -A, --all, all\n"
1209	" Display all the TLB entries (default if no other args).\n"
1210	" -a<virt>, --address=<virt>\n"
1211	" Shows the TLB entry for the specified guest virtual address.\n"
1212	" -r<slot:count>, --range=<slot:count>\n"
1213	" Shows the TLB entries for the specified slot range.\n"
1214	" -s<slot>,--slot=<slot>\n"
1215	" Shows the given TLB slot.\n"
1216	"\n"
1217	"Non-options are interpreted according to the last -a, -r or -s option,\n"
1218	"defaulting to addresses if not preceeded by any of those options.\n"
1219	, fITlb ? 'i' : 'd');
1220	return;
1221
1222	default:
1223	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1224	return;
1225	}
1226	}
1227	}
1228
1229
1230	/**
1231	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
1232	*/
1233	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1234	{
1235	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
1236	}
1237
1238
1239	/**
1240	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
1241	*/
1242	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1243	{
1244	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
1245	}
1246
1247	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1248	/**
1249	* @callback_method_impl{FNDBGFINFOARGVINT, tb}
1250	*/
1251	static DECLCALLBACK(void) iemR3InfoTb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1252	{
1253	/*
1254	* Parse arguments.
1255	*/
1256	static RTGETOPTDEF const s_aOptions[] =
1257	{
1258	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1259	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1260	{ "--addr", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1261	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1262	{ "--phys", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1263	{ "--physical", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1264	{ "--phys-addr", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1265	{ "--phys-address", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1266	{ "--physical-address", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1267	{ "--flags", 'f', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
1268	};
1269
1270	RTGETOPTSTATE State;
1271	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
1272	AssertRCReturnVoid(rc);
1273
1274	PVMCPU const pVCpuThis = VMMGetCpu(pVM);
1275	PVMCPU pVCpu = pVCpuThis ? pVCpuThis : VMMGetCpuById(pVM, 0);
1276	RTGCPHYS GCPhysPc = NIL_RTGCPHYS;
1277	RTGCPHYS GCVirt = NIL_RTGCPTR;
1278	uint32_t fFlags = UINT32_MAX;
1279
1280	RTGETOPTUNION ValueUnion;
1281	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1282	{
1283	switch (rc)
1284	{
1285	case 'c':
1286	if (ValueUnion.u32 >= pVM->cCpus)
1287	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1288	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
1289	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1290	break;
1291
1292	case 'a':
1293	GCVirt = ValueUnion.u64;
1294	GCPhysPc = NIL_RTGCPHYS;
1295	break;
1296
1297	case 'p':
1298	GCVirt = NIL_RTGCPHYS;
1299	GCPhysPc = ValueUnion.u64;
1300	break;
1301
1302	case 'f':
1303	fFlags = ValueUnion.u32;
1304	break;
1305
1306	case 'h':
1307	pHlp->pfnPrintf(pHlp,
1308	"Usage: info %ctlb [options]\n"
1309	"\n"
1310	"Options:\n"
1311	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
1312	" Selects the CPU which TBs we're looking at. Default: Caller / 0\n"
1313	" -a<virt>, --address=<virt>\n"
1314	" Shows the TB for the specified guest virtual address.\n"
1315	" -p<phys>, --phys=<phys>, --phys-addr=<phys>\n"
1316	" Shows the TB for the specified guest physical address.\n"
1317	" -f<flags>,--flags=<flags>\n"
1318	" The TB flags value (hex) to use when looking up the TB.\n"
1319	"\n"
1320	"The default is to use CS:RIP and derive flags from the CPU mode.\n");
1321	return;
1322
1323	default:
1324	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1325	return;
1326	}
1327	}
1328
1329	/* Currently, only do work on the same EMT. */
1330	if (pVCpu != pVCpuThis)
1331	{
1332	pHlp->pfnPrintf(pHlp, "TODO: Cross EMT calling not supported yet: targeting %u, caller on %d\n",
1333	pVCpu->idCpu, pVCpuThis ? (int)pVCpuThis->idCpu : -1);
1334	return;
1335	}
1336
1337	/*
1338	* Defaults.
1339	*/
1340	if (GCPhysPc == NIL_RTGCPHYS)
1341	{
1342	if (GCVirt == NIL_RTGCPTR)
1343	GCVirt = CPUMGetGuestFlatPC(pVCpu);
1344	rc = PGMPhysGCPtr2GCPhys(pVCpu, GCVirt, &GCPhysPc);
1345	if (RT_FAILURE(rc))
1346	{
1347	pHlp->pfnPrintf(pHlp, "Failed to convert %%%RGv to an guest physical address: %Rrc\n", GCVirt, rc);
1348	return;
1349	}
1350	}
1351	if (fFlags == UINT32_MAX)
1352	{
1353	/* Note! This is duplicating code in IEMAllThrdRecompiler. */
1354	fFlags = iemCalcExecFlags(pVCpu);
1355	if (pVM->cCpus == 1)
1356	fFlags \|= IEM_F_X86_DISREGARD_LOCK;
1357	if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
1358	fFlags \|= IEMTB_F_INHIBIT_SHADOW;
1359	if (CPUMAreInterruptsInhibitedByNmiEx(&pVCpu->cpum.GstCtx))
1360	fFlags \|= IEMTB_F_INHIBIT_NMI;
1361	if ((IEM_F_MODE_CPUMODE_MASK & fFlags) != IEMMODE_64BIT)
1362	{
1363	int64_t const offFromLim = (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.eip;
1364	if (offFromLim < X86_PAGE_SIZE + 16 - (int32_t)(pVCpu->cpum.GstCtx.cs.u64Base & GUEST_PAGE_OFFSET_MASK))
1365	fFlags \|= IEMTB_F_CS_LIM_CHECKS;
1366	}
1367	}
1368
1369	/*
1370	* Do the lookup...
1371	*
1372	* Note! This is also duplicating code in IEMAllThrdRecompiler. We don't
1373	* have much choice since we don't want to increase use counters and
1374	* trigger native recompilation.
1375	*/
1376	fFlags &= IEMTB_F_KEY_MASK;
1377	IEMTBCACHE const * const pTbCache = pVCpu->iem.s.pTbCacheR3;
1378	uint32_t const idxHash = IEMTBCACHE_HASH(pTbCache, fFlags, GCPhysPc);
1379	PCIEMTB pTb = IEMTBCACHE_PTR_GET_TB(pTbCache->apHash[idxHash]);
1380	while (pTb)
1381	{
1382	if (pTb->GCPhysPc == GCPhysPc)
1383	{
1384	if ((pTb->fFlags & IEMTB_F_KEY_MASK) == fFlags)
1385	{
1386	/// @todo if (pTb->x86.fAttr == (uint16_t)pVCpu->cpum.GstCtx.cs.Attr.u)
1387	break;
1388	}
1389	}
1390	pTb = pTb->pNext;
1391	}
1392	if (!pTb)
1393	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x - no TB found on #%u\n", GCPhysPc, fFlags, pVCpu->idCpu);
1394	else
1395	{
1396	/*
1397	* Disassemble according to type.
1398	*/
1399	switch (pTb->fFlags & IEMTB_F_TYPE_MASK)
1400	{
1401	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
1402	case IEMTB_F_TYPE_NATIVE:
1403	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x on #%u: %p - native\n", GCPhysPc, fFlags, pVCpu->idCpu, pTb);
1404	iemNativeDisassembleTb(pTb, pHlp);
1405	break;
1406	# endif
1407
1408	case IEMTB_F_TYPE_THREADED:
1409	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x on #%u: %p - threaded\n", GCPhysPc, fFlags, pVCpu->idCpu, pTb);
1410	iemThreadedDisassembleTb(pTb, pHlp);
1411	break;
1412
1413	default:
1414	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x on #%u: %p - ??? %#x\n",
1415	GCPhysPc, fFlags, pVCpu->idCpu, pTb, pTb->fFlags);
1416	break;
1417	}
1418	}
1419	}
1420	#endif /* VBOX_WITH_IEM_RECOMPILER && !VBOX_VMM_TARGET_ARMV8 */
1421
1422
1423	#ifdef VBOX_WITH_DEBUGGER
1424
1425	/** @callback_method_impl{FNDBGCCMD,
1426	* Implements the '.alliem' command. }
1427	*/
1428	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
1429	{
1430	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
1431	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
1432	if (pVCpu)
1433	{
1434	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAllGlobal, 1, pVCpu);
1435	return VINF_SUCCESS;
1436	}
1437	RT_NOREF(paArgs, cArgs);
1438	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
1439	}
1440
1441
1442	/**
1443	* Called by IEMR3Init to register debugger commands.
1444	*/
1445	static void iemR3RegisterDebuggerCommands(void)
1446	{
1447	/*
1448	* Register debugger commands.
1449	*/
1450	static DBGCCMD const s_aCmds[] =
1451	{
1452	{
1453	/* .pszCmd = */ "iemflushtlb",
1454	/* .cArgsMin = */ 0,
1455	/* .cArgsMax = */ 0,
1456	/* .paArgDescs = */ NULL,
1457	/* .cArgDescs = */ 0,
1458	/* .fFlags = */ 0,
1459	/* .pfnHandler = */ iemR3DbgFlushTlbs,
1460	/* .pszSyntax = */ "",
1461	/* .pszDescription = */ "Flushed the code and data TLBs"
1462	},
1463	};
1464
1465	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
1466	AssertLogRelRC(rc);
1467	}
1468
1469	#endif /* VBOX_WITH_DEBUGGER */
1470

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 105036

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