IEMR3.cpp@ 106090

Last change on this file since 106090 was 106090, checked in by vboxsync, 5 months ago
VMM/IEM: More liveness work for delayed eflags updating. bugref:10720 bugref:10372
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1	/* $Id: IEMR3.cpp 106090 2024-09-19 09:13:54Z vboxsync $ */
2	/** @file
3	* IEM - Interpreted Execution Manager.
4	*/
5
6	/*
7	* Copyright (C) 2011-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_EM
33	#define VMCPU_INCL_CPUM_GST_CTX
34	#include <VBox/vmm/iem.h>
35	#include <VBox/vmm/cpum.h>
36	#include <VBox/vmm/dbgf.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#if defined(VBOX_VMM_TARGET_ARMV8)
40	# include "IEMInternal-armv8.h"
41	#else
42	# include "IEMInternal.h"
43	#endif
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/vmapi.h>
46	#include <VBox/err.h>
47	#ifdef VBOX_WITH_DEBUGGER
48	# include <VBox/dbg.h>
49	#endif
50
51	#include <iprt/assert.h>
52	#include <iprt/getopt.h>
53	#ifdef IEM_WITH_TLB_TRACE
54	# include <iprt/mem.h>
55	#endif
56	#include <iprt/string.h>
57
58	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
59	# include "IEMN8veRecompiler.h"
60	# include "IEMThreadedFunctions.h"
61	# include "IEMInline.h"
62	#endif
63
64
65	/*********************************************************************************************************************************
66	* Internal Functions *
67	*********************************************************************************************************************************/
68	static FNDBGFINFOARGVINT iemR3InfoITlb;
69	static FNDBGFINFOARGVINT iemR3InfoDTlb;
70	#ifdef IEM_WITH_TLB_TRACE
71	static FNDBGFINFOARGVINT iemR3InfoTlbTrace;
72	#endif
73	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
74	static FNDBGFINFOARGVINT iemR3InfoTb;
75	static FNDBGFINFOARGVINT iemR3InfoTbTop;
76	#endif
77	#ifdef VBOX_WITH_DEBUGGER
78	static void iemR3RegisterDebuggerCommands(void);
79	#endif
80
81
82	#if !defined(VBOX_VMM_TARGET_ARMV8)
83	static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
84	{
85	switch (enmTargetCpu)
86	{
87	#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
88	CASE_RET_STR(IEMTARGETCPU_8086);
89	CASE_RET_STR(IEMTARGETCPU_V20);
90	CASE_RET_STR(IEMTARGETCPU_186);
91	CASE_RET_STR(IEMTARGETCPU_286);
92	CASE_RET_STR(IEMTARGETCPU_386);
93	CASE_RET_STR(IEMTARGETCPU_486);
94	CASE_RET_STR(IEMTARGETCPU_PENTIUM);
95	CASE_RET_STR(IEMTARGETCPU_PPRO);
96	CASE_RET_STR(IEMTARGETCPU_CURRENT);
97	#undef CASE_RET_STR
98	default: return "Unknown";
99	}
100	}
101	#endif
102
103
104	/**
105	* Initializes the interpreted execution manager.
106	*
107	* This must be called after CPUM as we're quering information from CPUM about
108	* the guest and host CPUs.
109	*
110	* @returns VBox status code.
111	* @param pVM The cross context VM structure.
112	*/
113	VMMR3DECL(int) IEMR3Init(PVM pVM)
114	{
115	/*
116	* Read configuration.
117	*/
118	#if (!defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)) \|\| defined(VBOX_WITH_IEM_RECOMPILER)
119	PCFGMNODE const pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
120	int rc;
121	#endif
122
123	#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
124	/** @cfgm{/IEM/CpuIdHostCall, boolean, false}
125	* Controls whether the custom VBox specific CPUID host call interface is
126	* enabled or not. */
127	# ifdef DEBUG_bird
128	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
129	# else
130	rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
131	# endif
132	AssertLogRelRCReturn(rc, rc);
133	#endif
134
135	#ifdef VBOX_WITH_IEM_RECOMPILER
136	/** @cfgm{/IEM/MaxTbCount, uint32_t, 524288}
137	* Max number of TBs per EMT. */
138	uint32_t cMaxTbs = 0;
139	rc = CFGMR3QueryU32Def(pIem, "MaxTbCount", &cMaxTbs, _512K);
140	AssertLogRelRCReturn(rc, rc);
141	if (cMaxTbs < _16K \|\| cMaxTbs > _8M)
142	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
143	"MaxTbCount value %u (%#x) is out of range (min %u, max %u)", cMaxTbs, cMaxTbs, _16K, _8M);
144
145	/** @cfgm{/IEM/InitialTbCount, uint32_t, 32678}
146	* Initial (minimum) number of TBs per EMT in ring-3. */
147	uint32_t cInitialTbs = 0;
148	rc = CFGMR3QueryU32Def(pIem, "InitialTbCount", &cInitialTbs, RT_MIN(cMaxTbs, _32K));
149	AssertLogRelRCReturn(rc, rc);
150	if (cInitialTbs < _16K \|\| cInitialTbs > _8M)
151	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
152	"InitialTbCount value %u (%#x) is out of range (min %u, max %u)", cInitialTbs, cInitialTbs, _16K, _8M);
153
154	/* Check that the two values makes sense together. Expect user/api to do
155	the right thing or get lost. */
156	if (cInitialTbs > cMaxTbs)
157	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
158	"InitialTbCount value %u (%#x) is higher than the MaxTbCount value %u (%#x)",
159	cInitialTbs, cInitialTbs, cMaxTbs, cMaxTbs);
160
161	/** @cfgm{/IEM/MaxExecMem, uint64_t, 512 MiB}
162	* Max executable memory for recompiled code per EMT. */
163	uint64_t cbMaxExec = 0;
164	rc = CFGMR3QueryU64Def(pIem, "MaxExecMem", &cbMaxExec, _512M);
165	AssertLogRelRCReturn(rc, rc);
166	if (cbMaxExec < _1M \|\| cbMaxExec > 16*_1G64)
167	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
168	"MaxExecMem value %'RU64 (%#RX64) is out of range (min %'RU64, max %'RU64)",
169	cbMaxExec, cbMaxExec, (uint64_t)_1M, 16*_1G64);
170
171	/** @cfgm{/IEM/ExecChunkSize, uint32_t, 0 (auto)}
172	* The executable memory allocator chunk size. */
173	uint32_t cbChunkExec = 0;
174	rc = CFGMR3QueryU32Def(pIem, "ExecChunkSize", &cbChunkExec, 0);
175	AssertLogRelRCReturn(rc, rc);
176	if (cbChunkExec != 0 && cbChunkExec != UINT32_MAX && (cbChunkExec < _1M \|\| cbChunkExec > _256M))
177	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
178	"ExecChunkSize value %'RU32 (%#RX32) is out of range (min %'RU32, max %'RU32)",
179	cbChunkExec, cbChunkExec, _1M, _256M);
180
181	/** @cfgm{/IEM/InitialExecMemSize, uint64_t, 1}
182	* The initial executable memory allocator size (per EMT). The value is
183	* rounded up to the nearest chunk size, so 1 byte means one chunk. */
184	uint64_t cbInitialExec = 0;
185	rc = CFGMR3QueryU64Def(pIem, "InitialExecMemSize", &cbInitialExec, 0);
186	AssertLogRelRCReturn(rc, rc);
187	if (cbInitialExec > cbMaxExec)
188	return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
189	"InitialExecMemSize value %'RU64 (%#RX64) is out of range (max %'RU64)",
190	cbInitialExec, cbInitialExec, cbMaxExec);
191
192	/** @cfgm{/IEM/NativeRecompileAtUsedCount, uint32_t, 16}
193	* The translation block use count value to do native recompilation at.
194	* Set to zero to disable native recompilation. */
195	uint32_t uTbNativeRecompileAtUsedCount = 16;
196	rc = CFGMR3QueryU32Def(pIem, "NativeRecompileAtUsedCount", &uTbNativeRecompileAtUsedCount, 16);
197	AssertLogRelRCReturn(rc, rc);
198
199	#endif /* VBOX_WITH_IEM_RECOMPILER*/
200
201	/*
202	* Initialize per-CPU data and register statistics.
203	*/
204	#if 1
205	uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
206	uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
207	#else
208	uint64_t const uInitialTlbRevision = UINT64_C(0) + (IEMTLB_REVISION_INCR * 4U);
209	uint64_t const uInitialTlbPhysRev = UINT64_C(0) + (IEMTLB_PHYS_REV_INCR * 4U);
210	#endif
211
212	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
213	{
214	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
215	AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
216
217	pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
218	#ifndef VBOX_VMM_TARGET_ARMV8
219	pVCpu->iem.s.CodeTlb.uTlbRevisionGlobal = pVCpu->iem.s.DataTlb.uTlbRevisionGlobal = uInitialTlbRevision;
220	#endif
221	pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
222	#ifndef VBOX_VMM_TARGET_ARMV8
223	pVCpu->iem.s.CodeTlb.NonGlobalLargePageRange.uFirstTag = UINT64_MAX;
224	pVCpu->iem.s.CodeTlb.GlobalLargePageRange.uFirstTag = UINT64_MAX;
225	pVCpu->iem.s.DataTlb.NonGlobalLargePageRange.uFirstTag = UINT64_MAX;
226	pVCpu->iem.s.DataTlb.GlobalLargePageRange.uFirstTag = UINT64_MAX;
227	#endif
228
229	#ifndef VBOX_VMM_TARGET_ARMV8
230	pVCpu->iem.s.cTbsTillNextTimerPoll = 128;
231	pVCpu->iem.s.cTbsTillNextTimerPollPrev = 128;
232	#endif
233
234	/*
235	* Host and guest CPU information.
236	*/
237	if (idCpu == 0)
238	{
239	pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
240	pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
241	#if !defined(VBOX_VMM_TARGET_ARMV8)
242	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
243	\|\| pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /??/
244	? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
245	# if defined(RT_ARCH_X86) \|\| defined(RT_ARCH_AMD64)
246	if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
247	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
248	else
249	# endif
250	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
251	#else
252	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
253	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
254	#endif
255
256	#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
257	switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
258	{
259	case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
260	case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
261	case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
262	case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
263	case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
264	case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
265	case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
266	case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
267	case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
268	default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
269	}
270	LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
271	iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
272	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
273	#else
274	LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
275	CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
276	pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
277	#endif
278	}
279	else
280	{
281	pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
282	pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
283	pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
284	pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
285	#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
286	pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
287	#endif
288	}
289
290	/*
291	* Mark all buffers free.
292	*/
293	uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
294	while (iMemMap-- > 0)
295	pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
296
297	#ifdef VBOX_WITH_IEM_RECOMPILER
298	/*
299	* Recompiler state and configuration distribution.
300	*/
301	pVCpu->iem.s.uRegFpCtrl = IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED;
302	pVCpu->iem.s.uTbNativeRecompileAtUsedCount = uTbNativeRecompileAtUsedCount;
303	#endif
304
305	#ifdef IEM_WITH_TLB_TRACE
306	/*
307	* Allocate trace buffer.
308	*/
309	pVCpu->iem.s.idxTlbTraceEntry = 0;
310	pVCpu->iem.s.cTlbTraceEntriesShift = 16;
311	pVCpu->iem.s.paTlbTraceEntries = (PIEMTLBTRACEENTRY)RTMemPageAlloc( RT_BIT_Z(pVCpu->iem.s.cTlbTraceEntriesShift)
312	* sizeof(*pVCpu->iem.s.paTlbTraceEntries));
313	AssertLogRelReturn(pVCpu->iem.s.paTlbTraceEntries, VERR_NO_PAGE_MEMORY);
314	#endif
315	}
316
317
318	#ifdef VBOX_WITH_IEM_RECOMPILER
319	/*
320	* Initialize the TB allocator and cache (/ hash table).
321	*
322	* This is done by each EMT to try get more optimal thread/numa locality of
323	* the allocations.
324	*/
325	rc = VMR3ReqCallWait(pVM, VMCPUID_ALL, (PFNRT)iemTbInit, 6,
326	pVM, cInitialTbs, cMaxTbs, cbInitialExec, cbMaxExec, cbChunkExec);
327	AssertLogRelRCReturn(rc, rc);
328	#endif
329
330	/*
331	* Register statistics.
332	*/
333	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
334	{
335	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) /* quick fix for stupid structure duplication non-sense */
336	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
337	char szPat[128];
338	RT_NOREF_PV(szPat); /* lazy bird */
339	char szVal[128];
340	RT_NOREF_PV(szVal); /* lazy bird */
341
342	STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
343	"Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
344	STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
345	"Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
346	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
347	"Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
348	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
349	"VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
350	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
351	"VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
352	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
353	"Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
354	STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
355	"Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
356	STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
357	"Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
358	STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
359	"Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
360	STAMR3RegisterF(pVM, &pVCpu->iem.s.cMisalignedAtomics, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
361	"Number of misaligned (for the host) atomic instructions", "/IEM/CPU%u/cMisalignedAtomics", idCpu);
362
363	/* Code TLB: */
364	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
365	"Code TLB non-global revision", "/IEM/CPU%u/Tlb/Code/RevisionNonGlobal", idCpu);
366	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevisionGlobal, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
367	"Code TLB global revision", "/IEM/CPU%u/Tlb/Code/RevisionGlobal", idCpu);
368	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
369	"Code TLB non-global flushes", "/IEM/CPU%u/Tlb/Code/RevisionNonGlobalFlushes", idCpu);
370	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsGlobalFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
371	"Code TLB global flushes", "/IEM/CPU%u/Tlb/Code/RevisionGlobalFlushes", idCpu);
372	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
373	"Code TLB revision rollovers", "/IEM/CPU%u/Tlb/Code/RevisionRollovers", idCpu);
374
375	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
376	"Code TLB physical revision", "/IEM/CPU%u/Tlb/Code/PhysicalRevision", idCpu);
377	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
378	"Code TLB revision flushes", "/IEM/CPU%u/Tlb/Code/PhysicalRevisionFlushes", idCpu);
379	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
380	"Code TLB revision rollovers", "/IEM/CPU%u/Tlb/Code/PhysicalRevisionRollovers", idCpu);
381
382	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
383	"Code TLB global large page loads since flush", "/IEM/CPU%u/Tlb/Code/LargePageGlobalCurLoads", idCpu);
384	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.GlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
385	"Code TLB global large page range: lowest tag", "/IEM/CPU%u/Tlb/Code/LargePageGlobalFirstTag", idCpu);
386	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.GlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
387	"Code TLB global large page range: last tag", "/IEM/CPU%u/Tlb/Code/LargePageGlobalLastTag", idCpu);
388
389	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNonGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
390	"Code TLB non-global large page loads since flush", "/IEM/CPU%u/Tlb/Code/LargePageNonGlobalCurLoads", idCpu);
391	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.NonGlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
392	"Code TLB non-global large page range: lowest tag", "/IEM/CPU%u/Tlb/Code/LargePageNonGlobalFirstTag", idCpu);
393	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.NonGlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
394	"Code TLB non-global large page range: last tag", "/IEM/CPU%u/Tlb/Code/LargePageNonGlobalLastTag", idCpu);
395
396	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbInvlPg, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
397	"Code TLB page invalidation requests", "/IEM/CPU%u/Tlb/Code/InvlPg", idCpu);
398	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbInvlPgLargeGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
399	"Code TLB page invlpg scanning for global large pages", "/IEM/CPU%u/Tlb/Code/InvlPg/LargeGlobal", idCpu);
400	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbInvlPgLargeNonGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
401	"Code TLB page invlpg scanning for non-global large pages", "/IEM/CPU%u/Tlb/Code/InvlPg/LargeNonGlobal", idCpu);
402
403	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
404	"Code TLB misses", "/IEM/CPU%u/Tlb/Code/Misses", idCpu);
405	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
406	"Code TLB global loads", "/IEM/CPU%u/Tlb/Code/Misses/GlobalLoads", idCpu);
407	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowCodeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
408	"Code TLB slow read path", "/IEM/CPU%u/Tlb/Code/SlowReads", idCpu);
409	# ifdef IEM_WITH_TLB_STATISTICS
410	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
411	"Code TLB hits (non-native)", "/IEM/CPU%u/Tlb/Code/Hits/Other", idCpu);
412	# if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
413	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
414	"Code TLB native hits on new page", "/IEM/CPU%u/Tlb/Code/Hits/New-Page", idCpu);
415	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
416	"Code TLB native hits on new page /w offset", "/IEM/CPU%u/Tlb/Code/Hits/New-Page-With-Offset", idCpu);
417	# endif
418
419	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Code/Hits/*", idCpu);
420	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Code TLB hits",
421	"/IEM/CPU%u/Tlb/Code/Hits", idCpu);
422
423	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Code/Hits\|/IEM/CPU%u/Tlb/Code/Misses", idCpu, idCpu);
424	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Code TLB lookups (sum of hits and misses)",
425	"/IEM/CPU%u/Tlb/Code/AllLookups", idCpu);
426
427	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Code/Misses", idCpu);
428	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Code/Hits", idCpu);
429	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
430	"Code TLB actual miss rate", "/IEM/CPU%u/Tlb/Code/RateMisses", idCpu);
431
432	# if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
433	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissTag, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
434	"Code TLB misses in native code: Tag mismatch [not directly included grand parent sum]",
435	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/Tag", idCpu);
436	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissFlagsAndPhysRev, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
437	"Code TLB misses in native code: Flags or physical revision mistmatch [not directly included grand parent sum]",
438	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/FlagsAndPhysRev", idCpu);
439	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissAlignment, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
440	"Code TLB misses in native code: Alignment [not directly included grand parent sum]",
441	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/Alignment", idCpu);
442	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissCrossPage, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
443	"Code TLB misses in native code: Cross page [not directly included grand parent sum]",
444	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/CrossPage", idCpu);
445	STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissNonCanonical, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
446	"Code TLB misses in native code: Non-canonical [not directly included grand parent sum]",
447	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/NonCanonical", idCpu);
448
449	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
450	"Code TLB native misses on new page",
451	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown2/New-Page", idCpu);
452	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
453	"Code TLB native misses on new page w/ offset",
454	"/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown2/New-Page-With-Offset", idCpu);
455	# endif
456	# endif /* IEM_WITH_TLB_STATISTICS */
457
458	/* Data TLB organized as best we can... */
459	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
460	"Data TLB non-global revision", "/IEM/CPU%u/Tlb/Data/RevisionNonGlobal", idCpu);
461	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevisionGlobal, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
462	"Data TLB global revision", "/IEM/CPU%u/Tlb/Data/RevisionGlobal", idCpu);
463	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
464	"Data TLB non-global flushes", "/IEM/CPU%u/Tlb/Data/RevisionNonGlobalFlushes", idCpu);
465	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsGlobalFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
466	"Data TLB global flushes", "/IEM/CPU%u/Tlb/Data/RevisionGlobalFlushes", idCpu);
467	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
468	"Data TLB revision rollovers", "/IEM/CPU%u/Tlb/Data/RevisionRollovers", idCpu);
469
470	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
471	"Data TLB physical revision", "/IEM/CPU%u/Tlb/Data/PhysicalRevision", idCpu);
472	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
473	"Data TLB revision flushes", "/IEM/CPU%u/Tlb/Data/PhysicalRevisionFlushes", idCpu);
474	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
475	"Data TLB revision rollovers", "/IEM/CPU%u/Tlb/Data/PhysicalRevisionRollovers", idCpu);
476
477	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
478	"Data TLB global large page loads since flush", "/IEM/CPU%u/Tlb/Data/LargePageGlobalCurLoads", idCpu);
479	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.GlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
480	"Data TLB global large page range: lowest tag", "/IEM/CPU%u/Tlb/Data/LargePageGlobalFirstTag", idCpu);
481	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.GlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
482	"Data TLB global large page range: last tag", "/IEM/CPU%u/Tlb/Data/LargePageGlobalLastTag", idCpu);
483
484	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNonGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
485	"Data TLB non-global large page loads since flush", "/IEM/CPU%u/Tlb/Data/LargePageNonGlobalCurLoads", idCpu);
486	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.NonGlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
487	"Data TLB non-global large page range: lowest tag", "/IEM/CPU%u/Tlb/Data/LargePageNonGlobalFirstTag", idCpu);
488	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.NonGlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
489	"Data TLB non-global large page range: last tag", "/IEM/CPU%u/Tlb/Data/LargePageNonGlobalLastTag", idCpu);
490
491	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInvlPg, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
492	"Data TLB page invalidation requests", "/IEM/CPU%u/Tlb/Data/InvlPg", idCpu);
493	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInvlPgLargeGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
494	"Data TLB page invlpg scanning for global large pages", "/IEM/CPU%u/Tlb/Data/InvlPg/LargeGlobal", idCpu);
495	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInvlPgLargeNonGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
496	"Data TLB page invlpg scanning for non-global large pages", "/IEM/CPU%u/Tlb/Data/InvlPg/LargeNonGlobal", idCpu);
497
498	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
499	"Data TLB core misses (iemMemMap, direct iemMemMapJmp (not safe path))",
500	"/IEM/CPU%u/Tlb/Data/Misses/Core", idCpu);
501	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
502	"Data TLB global loads",
503	"/IEM/CPU%u/Tlb/Data/Misses/Core/GlobalLoads", idCpu);
504	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
505	"Data TLB safe read path (inline/native misses going to iemMemMapJmp)",
506	"/IEM/CPU%u/Tlb/Data/Misses/Safe/Reads", idCpu);
507	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
508	"Data TLB safe write path (inline/native misses going to iemMemMapJmp)",
509	"/IEM/CPU%u/Tlb/Data/Misses/Safe/Writes", idCpu);
510	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Misses/*", idCpu);
511	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB misses",
512	"/IEM/CPU%u/Tlb/Data/Misses", idCpu);
513
514	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Misses/Safe/*", idCpu);
515	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB actual safe path calls (read + write)",
516	"/IEM/CPU%u/Tlb/Data/Misses/Safe", idCpu);
517	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
518	"Data TLB hits in iemMemMapJmp - not part of safe-path total",
519	"/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartHits", idCpu);
520	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
521	"Data TLB misses in iemMemMapJmp - not part of safe-path total",
522	"/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartMisses", idCpu);
523	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
524	"Data TLB global loads",
525	"/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartMisses/GlobalLoads", idCpu);
526
527	# ifdef IEM_WITH_TLB_STATISTICS
528	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
529	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissTag, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
530	"Data TLB misses in native code: Tag mismatch [not directly included grand parent sum]",
531	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/Tag", idCpu);
532	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissFlagsAndPhysRev, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
533	"Data TLB misses in native code: Flags or physical revision mistmatch [not directly included grand parent sum]",
534	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/FlagsAndPhysRev", idCpu);
535	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissAlignment, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
536	"Data TLB misses in native code: Alignment [not directly included grand parent sum]",
537	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/Alignment", idCpu);
538	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissCrossPage, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
539	"Data TLB misses in native code: Cross page [not directly included grand parent sum]",
540	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/CrossPage", idCpu);
541	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissNonCanonical, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
542	"Data TLB misses in native code: Non-canonical [not directly included grand parent sum]",
543	"/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/NonCanonical", idCpu);
544	# endif
545	# endif
546
547	# ifdef IEM_WITH_TLB_STATISTICS
548	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
549	"Data TLB core hits (iemMemMap, direct iemMemMapJmp (not safe path))",
550	"/IEM/CPU%u/Tlb/Data/Hits/Core", idCpu);
551	STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInlineCodeHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
552	"Data TLB hits in IEMAllMemRWTmplInline.cpp.h",
553	"/IEM/CPU%u/Tlb/Data/Hits/Inline", idCpu);
554	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
555	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStack, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
556	"Data TLB native stack access hits",
557	"/IEM/CPU%u/Tlb/Data/Hits/Native/Stack", idCpu);
558	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForFetch, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
559	"Data TLB native data fetch hits",
560	"/IEM/CPU%u/Tlb/Data/Hits/Native/Fetch", idCpu);
561	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStore, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
562	"Data TLB native data store hits",
563	"/IEM/CPU%u/Tlb/Data/Hits/Native/Store", idCpu);
564	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForMapped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
565	"Data TLB native mapped data hits",
566	"/IEM/CPU%u/Tlb/Data/Hits/Native/Mapped", idCpu);
567	# endif
568	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits/*", idCpu);
569	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB hits",
570	"/IEM/CPU%u/Tlb/Data/Hits", idCpu);
571
572	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
573	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits/Native/*", idCpu);
574	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB hits from native code",
575	"/IEM/CPU%u/Tlb/Data/Hits/Native", idCpu);
576	# endif
577
578	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Data/Hits\|/IEM/CPU%u/Tlb/Data/Misses", idCpu, idCpu);
579	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB lookups (sum of hits and misses)",
580	"/IEM/CPU%u/Tlb/Data/AllLookups", idCpu);
581
582	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Data/Misses", idCpu);
583	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits", idCpu);
584	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
585	"Data TLB actual miss rate", "/IEM/CPU%u/Tlb/Data/RateMisses", idCpu);
586
587	# endif /* IEM_WITH_TLB_STATISTICS */
588
589
590	#ifdef VBOX_WITH_IEM_RECOMPILER
591	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecNative, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
592	"Executed native translation block", "/IEM/CPU%u/re/cTbExecNative", idCpu);
593	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecThreaded, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
594	"Executed threaded translation block", "/IEM/CPU%u/re/cTbExecThreaded", idCpu);
595	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
596	"Times threaded TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecThreadedBreaks", idCpu);
597	# ifdef VBOX_WITH_STATISTICS
598	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaksWithLookup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
599	"Times threaded TB execution was interrupted/broken off on a call with lookup entries", "/IEM/CPU%u/re/cTbExecThreadedBreaksWithLookup", idCpu);
600	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaksWithoutLookup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
601	"Times threaded TB execution was interrupted/broken off on a call without lookup entries", "/IEM/CPU%u/re/cTbExecThreadedBreaksWithoutLookup", idCpu);
602	# endif
603
604	# ifdef VBOX_WITH_STATISTICS
605	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPoll, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
606	"Timer polling profiling", "/IEM/CPU%u/re/TimerPoll", idCpu);
607	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollRun, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
608	"Timer polling profiling", "/IEM/CPU%u/re/TimerPoll/Running", idCpu);
609	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollUnchanged, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
610	"Timer polling interval unchanged", "/IEM/CPU%u/re/TimerPoll/Unchanged", idCpu);
611	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollTiny, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
612	"Timer polling interval tiny", "/IEM/CPU%u/re/TimerPoll/Tiny", idCpu);
613	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollDefaultCalc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
614	"Timer polling interval calculated using defaults", "/IEM/CPU%u/re/TimerPoll/DefaultCalc", idCpu);
615	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollMax, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
616	"Timer polling interval maxed out", "/IEM/CPU%u/re/TimerPoll/Max", idCpu);
617	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollFactorDivision, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_OCCURENCE,
618	"Timer polling factor", "/IEM/CPU%u/re/TimerPoll/FactorDivision", idCpu);
619	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollFactorMultiplication, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
620	"Timer polling factor", "/IEM/CPU%u/re/TimerPoll/FactorMultiplication", idCpu);
621	# endif
622	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbsTillNextTimerPollPrev, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
623	"Timer polling interval (in TBs)", "/IEM/CPU%u/re/TimerPollInterval", idCpu);
624
625	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
626	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatAllocs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
627	"Translation block allocations", "/IEM/CPU%u/re/cTbAllocCalls", idCpu);
628	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatFrees, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
629	"Translation block frees", "/IEM/CPU%u/re/cTbFreeCalls", idCpu);
630	# ifdef VBOX_WITH_STATISTICS
631	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
632	"Time spent freeing up TBs when full at alloc", "/IEM/CPU%u/re/TbPruningAlloc", idCpu);
633	# endif
634	STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPruneNative, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
635	"Time spent freeing up native TBs when out of executable memory", "/IEM/CPU%u/re/ExecMem/TbPruningNative", idCpu);
636	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cAllocatedChunks, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
637	"Populated TB chunks", "/IEM/CPU%u/re/cTbChunks", idCpu);
638	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxChunks, STAMTYPE_U8, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
639	"Max number of TB chunks", "/IEM/CPU%u/re/cTbChunksMax", idCpu);
640	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cTotalTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
641	"Total number of TBs in the allocator", "/IEM/CPU%u/re/cTbTotal", idCpu);
642	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
643	"Max total number of TBs allowed", "/IEM/CPU%u/re/cTbTotalMax", idCpu);
644	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cInUseTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
645	"Number of currently allocated TBs", "/IEM/CPU%u/re/cTbAllocated", idCpu);
646	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cNativeTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
647	"Number of currently allocated native TBs", "/IEM/CPU%u/re/cTbAllocatedNative", idCpu);
648	STAMR3RegisterF(pVM, (void *)&pTbAllocator->cThreadedTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
649	"Number of currently allocated threaded TBs", "/IEM/CPU%u/re/cTbAllocatedThreaded", idCpu);
650
651	PIEMTBCACHE const pTbCache = pVCpu->iem.s.pTbCacheR3;
652	STAMR3RegisterF(pVM, (void *)&pTbCache->cHash, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
653	"Translation block lookup table size", "/IEM/CPU%u/re/cTbHashTab", idCpu);
654
655	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHits, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
656	"Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
657	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHitsViaTbLookupTable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
658	"Translation block lookup hits via TB lookup table associated with the previous TB", "/IEM/CPU%u/re/cTbLookupHitsViaTbLookupTable", idCpu);
659	STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
660	"Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
661	STAMR3RegisterF(pVM, (void *)&pTbCache->cCollisions, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
662	"Translation block hash table collisions", "/IEM/CPU%u/re/cTbCollisions", idCpu);
663	# ifdef VBOX_WITH_STATISTICS
664	STAMR3RegisterF(pVM, (void *)&pTbCache->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
665	"Time spent shortening collision lists", "/IEM/CPU%u/re/TbPruningCollisions", idCpu);
666	# endif
667
668	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
669	"Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
670	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
671	"Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
672	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLookupEntries, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
673	"TB lookup table entries per threaded translation block", "/IEM/CPU%u/re/ThrdLookupEntriesPerTb", idCpu);
674
675	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
676	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
677	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckTimersBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
678	"TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckTimersBreaks", idCpu);
679	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
680	"TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
681	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
682	"Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
683	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
684	"Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
685
686	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopFullTbDetected, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
687	"Detected loop full TB", "/IEM/CPU%u/re/LoopFullTbDetected", idCpu);
688	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopFullTbDetected2, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
689	"Detected loop full TB but looping back to before the first TB instruction",
690	"/IEM/CPU%u/re/LoopFullTbDetected2", idCpu);
691	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopInTbDetected, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
692	"Detected loop within TB", "/IEM/CPU%u/re/LoopInTbDetected", idCpu);
693
694	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeExecMemInstrBufAllocFailed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
695	"Number of times the exec memory allocator failed to allocate a large enough buffer",
696	"/IEM/CPU%u/re/NativeExecMemInstrBufAllocFailed", idCpu);
697
698	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsRecompiled, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
699	"Number of threaded calls per TB that have been properly recompiled to native code",
700	"/IEM/CPU%u/re/NativeCallsRecompiledPerTb", idCpu);
701	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsThreaded, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
702	"Number of threaded calls per TB that could not be recompiler to native code",
703	"/IEM/CPU%u/re/NativeCallsThreadedPerTb", idCpu);
704	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeFullyRecompiledTbs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
705	"Number of threaded calls that could not be recompiler to native code",
706	"/IEM/CPU%u/re/NativeFullyRecompiledTbs", idCpu);
707
708	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbNativeCode, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES_PER_TB,
709	"Size of native code per TB", "/IEM/CPU%u/re/NativeCodeSizePerTb", idCpu);
710	STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeRecompilation, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
711	"Profiling iemNativeRecompile()", "/IEM/CPU%u/re/NativeRecompilation", idCpu);
712
713	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
714	# ifdef VBOX_WITH_STATISTICS
715	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
716	"Number of calls to iemNativeRegAllocFindFree.",
717	"/IEM/CPU%u/re/NativeRegFindFree", idCpu);
718	# endif
719	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
720	"Number of times iemNativeRegAllocFindFree needed to free a variable.",
721	"/IEM/CPU%u/re/NativeRegFindFreeVar", idCpu);
722	# ifdef VBOX_WITH_STATISTICS
723	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
724	"Number of times iemNativeRegAllocFindFree did not needed to free any variables.",
725	"/IEM/CPU%u/re/NativeRegFindFreeNoVar", idCpu);
726	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
727	"Times liveness info freeed up shadowed guest registers in iemNativeRegAllocFindFree.",
728	"/IEM/CPU%u/re/NativeRegFindFreeLivenessUnshadowed", idCpu);
729	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
730	"Times liveness info helped finding the return register in iemNativeRegAllocFindFree.",
731	"/IEM/CPU%u/re/NativeRegFindFreeLivenessHelped", idCpu);
732
733	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkippedArithmetic, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
734	"Skipped all status flag updating, arithmetic instructions",
735	"/IEM/CPU%u/re/NativeEFlagsSkippedArithmetic", idCpu);
736	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkippedLogical, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
737	"Skipped all status flag updating, logical instructions",
738	"/IEM/CPU%u/re/NativeEFlagsSkippedLogical", idCpu);
739
740	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/CfSkippable", idCpu);
741	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/PfSkippable", idCpu);
742	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/AfSkippable", idCpu);
743	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfSkippable", idCpu);
744	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/SfSkippable", idCpu);
745	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/OfSkippable", idCpu);
746
747	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/CfRequired", idCpu);
748	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/PfRequired", idCpu);
749	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/AfRequired", idCpu);
750	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfRequired", idCpu);
751	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/SfRequired", idCpu);
752	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/OfRequired", idCpu);
753
754	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
755	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/CfDelayable", idCpu);
756	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/PfDelayable", idCpu);
757	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/AfDelayable", idCpu);
758	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfDelayable", idCpu);
759	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/SfDelayable", idCpu);
760	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/OfDelayable", idCpu);
761	# endif
762
763	/* Sum up all status bits ('_' is a sorting hack). */
764	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?fSkippable*", idCpu);
765	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total skippable EFLAGS status bit updating",
766	"/IEM/CPU%u/re/NativeLivenessEFlags/totalSkippable", idCpu);
767
768	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?fRequired*", idCpu);
769	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total required STATUS status bit updating",
770	"/IEM/CPU%u/re/NativeLivenessEFlags/totalRequired", idCpu);
771
772	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
773	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?fDelayable*", idCpu);
774	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total potentially delayable STATUS status bit updating",
775	"/IEM/CPU%u/re/NativeLivenessEFlags/totalDelayable", idCpu);
776	# endif
777
778	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?f*", idCpu);
779	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total STATUS status bit events of any kind",
780	"/IEM/CPU%u/re/NativeLivenessEFlags/totalTotal", idCpu);
781
782	/* Corresponding ratios / percentages of the totals. */
783	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/totalTotal", idCpu);
784	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/totalSkippable", idCpu);
785	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
786	"Total skippable EFLAGS status bit updating percentage",
787	"/IEM/CPU%u/re/NativeLivenessEFlags/totalSkippablePct", idCpu);
788
789	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/totalTotal", idCpu);
790	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/totalRequired", idCpu);
791	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
792	"Total required EFLAGS status bit updating percentage",
793	"/IEM/CPU%u/re/NativeLivenessEFlags/totalRequiredPct", idCpu);
794
795	# ifdef IEMLIVENESS_EXTENDED_LAYOUT
796	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/totalDelayable", idCpu);
797	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
798	"Total potentially delayable EFLAGS status bit updating percentage",
799	"/IEM/CPU%u/re/NativeLivenessEFlags/totalDelayablePct", idCpu);
800	# endif
801
802	/* Ratios of individual bits. */
803	size_t const offFlagChar = RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/Cf*", idCpu) - 3;
804	Assert(szPat[offFlagChar] == 'C');
805	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/CfSkippable", idCpu);
806	Assert(szVal[offFlagChar] == 'C');
807	szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/CfSkippablePct", idCpu);
808	szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/PfSkippablePct", idCpu);
809	szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/AfSkippablePct", idCpu);
810	szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfSkippablePct", idCpu);
811	szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/SfSkippablePct", idCpu);
812	szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/OfSkippablePct", idCpu);
813
814	/* PC updates total and skipped, with PCT ratio. */
815	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Total RIP updates", "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
816	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateDelayed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Delayed RIP updates", "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
817	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
818	RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
819	STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
820	"Delayed RIP updating percentage",
821	"/IEM/CPU%u/re/NativePcUpdateDelayed_StatusDelayedPct", idCpu);
822
823	# endif /* VBOX_WITH_STATISTICS */
824	# ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
825	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEndIfOtherBranchDirty, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
826	"IEM_MC_ENDIF flushing dirty shadow registers for other branch (not good).",
827	"/IEM/CPU%u/re/NativeEndIfOtherBranchDirty", idCpu);
828	# endif
829	# ifdef VBOX_WITH_STATISTICS
830	# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
831	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
832	"Number of calls to iemNativeSimdRegAllocFindFree.",
833	"/IEM/CPU%u/re/NativeSimdRegFindFree", idCpu);
834	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
835	"Number of times iemNativeSimdRegAllocFindFree needed to free a variable.",
836	"/IEM/CPU%u/re/NativeSimdRegFindFreeVar", idCpu);
837	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
838	"Number of times iemNativeSimdRegAllocFindFree did not needed to free any variables.",
839	"/IEM/CPU%u/re/NativeSimdRegFindFreeNoVar", idCpu);
840	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
841	"Times liveness info freeed up shadowed guest registers in iemNativeSimdRegAllocFindFree.",
842	"/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessUnshadowed", idCpu);
843	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
844	"Times liveness info helped finding the return register in iemNativeSimdRegAllocFindFree.",
845	"/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessHelped", idCpu);
846
847	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks",
848	"/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckPotential", idCpu);
849	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks",
850	"/IEM/CPU%u/re/NativeMaybeWaitDeviceNotAvailXcptCheckPotential", idCpu);
851	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks",
852	"/IEM/CPU%u/re/NativeMaybeSseXcptCheckPotential", idCpu);
853	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks",
854	"/IEM/CPU%u/re/NativeMaybeAvxXcptCheckPotential", idCpu);
855
856	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted",
857	"/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckOmitted", idCpu);
858	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted",
859	"/IEM/CPU%u/re/NativeMaybeWaitDeviceNotAvailXcptCheckOmitted", idCpu);
860	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted",
861	"/IEM/CPU%u/re/NativeMaybeSseXcptCheckOmitted", idCpu);
862	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted",
863	"/IEM/CPU%u/re/NativeMaybeAvxXcptCheckOmitted", idCpu);
864	# endif
865
866	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbFinished, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
867	"Number of times the TB finishes execution completely",
868	"/IEM/CPU%u/re/NativeTbFinished", idCpu);
869	# endif /* VBOX_WITH_STATISTICS */
870	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnBreak, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
871	"Number of times the TB finished through the ReturnBreak label",
872	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak", idCpu);
873	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnBreakFF, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
874	"Number of times the TB finished through the ReturnBreak label",
875	"/IEM/CPU%u/re/NativeTbExit/ReturnBreakFF", idCpu);
876	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnWithFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
877	"Number of times the TB finished through the ReturnWithFlags label",
878	"/IEM/CPU%u/re/NativeTbExit/ReturnWithFlags", idCpu);
879	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnOtherStatus, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
880	"Number of times the TB finished with some other status value",
881	"/IEM/CPU%u/re/NativeTbExit/ReturnOtherStatus", idCpu);
882	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitLongJump, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
883	"Number of times the TB finished via long jump / throw",
884	"/IEM/CPU%u/re/NativeTbExit/LongJumps", idCpu);
885	/* These end up returning VINF_IEM_REEXEC_BREAK and are thus already counted under NativeTbExit/ReturnBreak: */
886	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitObsoleteTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
887	"Number of times the TB finished through the ObsoleteTb label",
888	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/ObsoleteTb", idCpu);
889	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
890	"Number of times the TB finished through the NeedCsLimChecking label",
891	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/NeedCsLimChecking", idCpu);
892	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
893	"Number of times the TB finished through the CheckBranchMiss label",
894	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/CheckBranchMiss", idCpu);
895	/* Raising stuff will either increment NativeTbExit/LongJumps or NativeTbExit/ReturnOtherStatus
896	depending on whether VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is defined: */
897	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
898	# define RAISE_PREFIX "/IEM/CPU%u/re/NativeTbExit/ReturnOtherStatus/"
899	# else
900	# define RAISE_PREFIX "/IEM/CPU%u/re/NativeTbExit/LongJumps/"
901	# endif
902	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseDe, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
903	"Number of times the TB finished raising a #DE exception",
904	RAISE_PREFIX "RaiseDe", idCpu);
905	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseUd, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
906	"Number of times the TB finished raising a #UD exception",
907	RAISE_PREFIX "RaiseUd", idCpu);
908	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseSseRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
909	"Number of times the TB finished raising a SSE related exception",
910	RAISE_PREFIX "RaiseSseRelated", idCpu);
911	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseAvxRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
912	"Number of times the TB finished raising a AVX related exception",
913	RAISE_PREFIX "RaiseAvxRelated", idCpu);
914	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseSseAvxFpRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
915	"Number of times the TB finished raising a SSE/AVX floating point related exception",
916	RAISE_PREFIX "RaiseSseAvxFpRelated", idCpu);
917	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseNm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
918	"Number of times the TB finished raising a #NM exception",
919	RAISE_PREFIX "RaiseNm", idCpu);
920	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseGp0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
921	"Number of times the TB finished raising a #GP(0) exception",
922	RAISE_PREFIX "RaiseGp0", idCpu);
923	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseMf, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
924	"Number of times the TB finished raising a #MF exception",
925	RAISE_PREFIX "RaiseMf", idCpu);
926	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseXf, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
927	"Number of times the TB finished raising a #XF exception",
928	RAISE_PREFIX "RaiseXf", idCpu);
929
930	# ifdef VBOX_WITH_STATISTICS
931	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitLoopFullTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
932	"Number of full TB loops.",
933	"/IEM/CPU%u/re/NativeTbExit/LoopFullTb", idCpu);
934	# endif
935
936	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1Irq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
937	"Direct linking #1 with IRQ check succeeded",
938	"/IEM/CPU%u/re/NativeTbExit/DirectLinking1Irq", idCpu);
939	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1NoIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
940	"Direct linking #1 w/o IRQ check succeeded",
941	"/IEM/CPU%u/re/NativeTbExit/DirectLinking1NoIrq", idCpu);
942	# ifdef VBOX_WITH_STATISTICS
943	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1NoTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
944	"Direct linking #1 failed: No TB in lookup table",
945	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1NoTb", idCpu);
946	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchGCPhysPc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
947	"Direct linking #1 failed: GCPhysPc mismatch",
948	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1MismatchGCPhysPc", idCpu);
949	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
950	"Direct linking #1 failed: TB flags mismatch",
951	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1MismatchFlags", idCpu);
952	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1PendingIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
953	"Direct linking #1 failed: IRQ or FF pending",
954	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1PendingIrq", idCpu);
955	# endif
956
957	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2Irq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
958	"Direct linking #2 with IRQ check succeeded",
959	"/IEM/CPU%u/re/NativeTbExit/DirectLinking2Irq", idCpu);
960	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2NoIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
961	"Direct linking #2 w/o IRQ check succeeded",
962	"/IEM/CPU%u/re/NativeTbExit/DirectLinking2NoIrq", idCpu);
963	# ifdef VBOX_WITH_STATISTICS
964	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2NoTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
965	"Direct linking #2 failed: No TB in lookup table",
966	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2NoTb", idCpu);
967	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchGCPhysPc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
968	"Direct linking #2 failed: GCPhysPc mismatch",
969	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2MismatchGCPhysPc", idCpu);
970	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
971	"Direct linking #2 failed: TB flags mismatch",
972	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2MismatchFlags", idCpu);
973	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2PendingIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
974	"Direct linking #2 failed: IRQ or FF pending",
975	"/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2PendingIrq", idCpu);
976	# endif
977
978	RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeTbExit/", idCpu); / only immediate children, no sub folders */
979	STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
980	"Number of times native TB execution finished before the end (not counting thrown memory++ exceptions)",
981	"/IEM/CPU%u/re/NativeTbExit", idCpu);
982
983
984	# endif /* VBOX_WITH_IEM_NATIVE_RECOMPILER */
985
986
987	# ifdef VBOX_WITH_STATISTICS
988	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemMapJmp, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
989	"iemMemMapJmp calls", "/IEM/CPU%u/iemMemMapJmp", idCpu);
990	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemMapNoJmp, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
991	"iemMemMap calls", "/IEM/CPU%u/iemMemMapNoJmp", idCpu);
992	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemBounceBufferCrossPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
993	"iemMemBounceBufferMapCrossPage calls", "/IEM/CPU%u/iemMemMapBounceBufferCrossPage", idCpu);
994	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemBounceBufferMapPhys, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
995	"iemMemBounceBufferMapPhys calls", "/IEM/CPU%u/iemMemMapBounceBufferMapPhys", idCpu);
996	# endif
997
998
999	#endif /* VBOX_WITH_IEM_RECOMPILER */
1000
1001	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
1002	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1003	"", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
1004	for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
1005	STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1006	"", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
1007
1008	# if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
1009	/* Instruction statistics: */
1010	# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
1011	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
1012	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
1013	STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
1014	STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
1015	# include "IEMInstructionStatisticsTmpl.h"
1016	# undef IEM_DO_INSTR_STAT
1017	# endif
1018
1019	# if defined(VBOX_WITH_STATISTICS) && defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1020	/* Threaded function statistics: */
1021	for (unsigned i = 1; i < (unsigned)kIemThreadedFunc_End; i++)
1022	STAMR3RegisterF(pVM, &pVCpu->iem.s.acThreadedFuncStats[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED,
1023	STAMUNIT_COUNT, NULL, "/IEM/CPU%u/ThrdFuncs/%s", idCpu, g_apszIemThreadedFunctionStats[i]);
1024	# endif
1025
1026	#endif /* !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) - quick fix for stupid structure duplication non-sense */
1027	}
1028
1029	#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1030	/*
1031	* Register the per-VM VMX APIC-access page handler type.
1032	*/
1033	if (pVM->cpum.ro.GuestFeatures.fVmx)
1034	{
1035	rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
1036	iemVmxApicAccessPageHandler,
1037	"VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
1038	AssertLogRelRCReturn(rc, rc);
1039	}
1040	#endif
1041
1042	DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
1043	DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
1044	#ifdef IEM_WITH_TLB_TRACE
1045	DBGFR3InfoRegisterInternalArgv(pVM, "tlbtrace", "IEM TLB trace log", iemR3InfoTlbTrace, DBGFINFO_FLAGS_RUN_ON_EMT);
1046	#endif
1047	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1048	DBGFR3InfoRegisterInternalArgv(pVM, "tb", "IEM translation block", iemR3InfoTb, DBGFINFO_FLAGS_RUN_ON_EMT);
1049	DBGFR3InfoRegisterInternalArgv(pVM, "tbtop", "IEM translation blocks most used or most recently used",
1050	iemR3InfoTbTop, DBGFINFO_FLAGS_RUN_ON_EMT);
1051	#endif
1052	#ifdef VBOX_WITH_DEBUGGER
1053	iemR3RegisterDebuggerCommands();
1054	#endif
1055
1056	return VINF_SUCCESS;
1057	}
1058
1059
1060	VMMR3DECL(int) IEMR3Term(PVM pVM)
1061	{
1062	NOREF(pVM);
1063	#ifdef IEM_WITH_TLB_TRACE
1064	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1065	{
1066	PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
1067	RTMemPageFree(pVCpu->iem.s.paTlbTraceEntries,
1068	RT_BIT_Z(pVCpu->iem.s.cTlbTraceEntriesShift) * sizeof(*pVCpu->iem.s.paTlbTraceEntries));
1069	}
1070	#endif
1071	return VINF_SUCCESS;
1072	}
1073
1074
1075	VMMR3DECL(void) IEMR3Relocate(PVM pVM)
1076	{
1077	RT_NOREF(pVM);
1078	}
1079
1080
1081	/**
1082	* Gets the name of a generic IEM exit code.
1083	*
1084	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
1085	* @param uExit The IEM exit to name.
1086	*/
1087	VMMR3DECL(const char *) IEMR3GetExitName(uint32_t uExit)
1088	{
1089	static const char * const s_apszNames[] =
1090	{
1091	/* external interrupts */
1092	"ExtInt 00h", "ExtInt 01h", "ExtInt 02h", "ExtInt 03h", "ExtInt 04h", "ExtInt 05h", "ExtInt 06h", "ExtInt 07h",
1093	"ExtInt 08h", "ExtInt 09h", "ExtInt 0ah", "ExtInt 0bh", "ExtInt 0ch", "ExtInt 0dh", "ExtInt 0eh", "ExtInt 0fh",
1094	"ExtInt 10h", "ExtInt 11h", "ExtInt 12h", "ExtInt 13h", "ExtInt 14h", "ExtInt 15h", "ExtInt 16h", "ExtInt 17h",
1095	"ExtInt 18h", "ExtInt 19h", "ExtInt 1ah", "ExtInt 1bh", "ExtInt 1ch", "ExtInt 1dh", "ExtInt 1eh", "ExtInt 1fh",
1096	"ExtInt 20h", "ExtInt 21h", "ExtInt 22h", "ExtInt 23h", "ExtInt 24h", "ExtInt 25h", "ExtInt 26h", "ExtInt 27h",
1097	"ExtInt 28h", "ExtInt 29h", "ExtInt 2ah", "ExtInt 2bh", "ExtInt 2ch", "ExtInt 2dh", "ExtInt 2eh", "ExtInt 2fh",
1098	"ExtInt 30h", "ExtInt 31h", "ExtInt 32h", "ExtInt 33h", "ExtInt 34h", "ExtInt 35h", "ExtInt 36h", "ExtInt 37h",
1099	"ExtInt 38h", "ExtInt 39h", "ExtInt 3ah", "ExtInt 3bh", "ExtInt 3ch", "ExtInt 3dh", "ExtInt 3eh", "ExtInt 3fh",
1100	"ExtInt 40h", "ExtInt 41h", "ExtInt 42h", "ExtInt 43h", "ExtInt 44h", "ExtInt 45h", "ExtInt 46h", "ExtInt 47h",
1101	"ExtInt 48h", "ExtInt 49h", "ExtInt 4ah", "ExtInt 4bh", "ExtInt 4ch", "ExtInt 4dh", "ExtInt 4eh", "ExtInt 4fh",
1102	"ExtInt 50h", "ExtInt 51h", "ExtInt 52h", "ExtInt 53h", "ExtInt 54h", "ExtInt 55h", "ExtInt 56h", "ExtInt 57h",
1103	"ExtInt 58h", "ExtInt 59h", "ExtInt 5ah", "ExtInt 5bh", "ExtInt 5ch", "ExtInt 5dh", "ExtInt 5eh", "ExtInt 5fh",
1104	"ExtInt 60h", "ExtInt 61h", "ExtInt 62h", "ExtInt 63h", "ExtInt 64h", "ExtInt 65h", "ExtInt 66h", "ExtInt 67h",
1105	"ExtInt 68h", "ExtInt 69h", "ExtInt 6ah", "ExtInt 6bh", "ExtInt 6ch", "ExtInt 6dh", "ExtInt 6eh", "ExtInt 6fh",
1106	"ExtInt 70h", "ExtInt 71h", "ExtInt 72h", "ExtInt 73h", "ExtInt 74h", "ExtInt 75h", "ExtInt 76h", "ExtInt 77h",
1107	"ExtInt 78h", "ExtInt 79h", "ExtInt 7ah", "ExtInt 7bh", "ExtInt 7ch", "ExtInt 7dh", "ExtInt 7eh", "ExtInt 7fh",
1108	"ExtInt 80h", "ExtInt 81h", "ExtInt 82h", "ExtInt 83h", "ExtInt 84h", "ExtInt 85h", "ExtInt 86h", "ExtInt 87h",
1109	"ExtInt 88h", "ExtInt 89h", "ExtInt 8ah", "ExtInt 8bh", "ExtInt 8ch", "ExtInt 8dh", "ExtInt 8eh", "ExtInt 8fh",
1110	"ExtInt 90h", "ExtInt 91h", "ExtInt 92h", "ExtInt 93h", "ExtInt 94h", "ExtInt 95h", "ExtInt 96h", "ExtInt 97h",
1111	"ExtInt 98h", "ExtInt 99h", "ExtInt 9ah", "ExtInt 9bh", "ExtInt 9ch", "ExtInt 9dh", "ExtInt 9eh", "ExtInt 9fh",
1112	"ExtInt a0h", "ExtInt a1h", "ExtInt a2h", "ExtInt a3h", "ExtInt a4h", "ExtInt a5h", "ExtInt a6h", "ExtInt a7h",
1113	"ExtInt a8h", "ExtInt a9h", "ExtInt aah", "ExtInt abh", "ExtInt ach", "ExtInt adh", "ExtInt aeh", "ExtInt afh",
1114	"ExtInt b0h", "ExtInt b1h", "ExtInt b2h", "ExtInt b3h", "ExtInt b4h", "ExtInt b5h", "ExtInt b6h", "ExtInt b7h",
1115	"ExtInt b8h", "ExtInt b9h", "ExtInt bah", "ExtInt bbh", "ExtInt bch", "ExtInt bdh", "ExtInt beh", "ExtInt bfh",
1116	"ExtInt c0h", "ExtInt c1h", "ExtInt c2h", "ExtInt c3h", "ExtInt c4h", "ExtInt c5h", "ExtInt c6h", "ExtInt c7h",
1117	"ExtInt c8h", "ExtInt c9h", "ExtInt cah", "ExtInt cbh", "ExtInt cch", "ExtInt cdh", "ExtInt ceh", "ExtInt cfh",
1118	"ExtInt d0h", "ExtInt d1h", "ExtInt d2h", "ExtInt d3h", "ExtInt d4h", "ExtInt d5h", "ExtInt d6h", "ExtInt d7h",
1119	"ExtInt d8h", "ExtInt d9h", "ExtInt dah", "ExtInt dbh", "ExtInt dch", "ExtInt ddh", "ExtInt deh", "ExtInt dfh",
1120	"ExtInt e0h", "ExtInt e1h", "ExtInt e2h", "ExtInt e3h", "ExtInt e4h", "ExtInt e5h", "ExtInt e6h", "ExtInt e7h",
1121	"ExtInt e8h", "ExtInt e9h", "ExtInt eah", "ExtInt ebh", "ExtInt ech", "ExtInt edh", "ExtInt eeh", "ExtInt efh",
1122	"ExtInt f0h", "ExtInt f1h", "ExtInt f2h", "ExtInt f3h", "ExtInt f4h", "ExtInt f5h", "ExtInt f6h", "ExtInt f7h",
1123	"ExtInt f8h", "ExtInt f9h", "ExtInt fah", "ExtInt fbh", "ExtInt fch", "ExtInt fdh", "ExtInt feh", "ExtInt ffh",
1124	/* software interrups */
1125	"SoftInt 00h", "SoftInt 01h", "SoftInt 02h", "SoftInt 03h", "SoftInt 04h", "SoftInt 05h", "SoftInt 06h", "SoftInt 07h",
1126	"SoftInt 08h", "SoftInt 09h", "SoftInt 0ah", "SoftInt 0bh", "SoftInt 0ch", "SoftInt 0dh", "SoftInt 0eh", "SoftInt 0fh",
1127	"SoftInt 10h", "SoftInt 11h", "SoftInt 12h", "SoftInt 13h", "SoftInt 14h", "SoftInt 15h", "SoftInt 16h", "SoftInt 17h",
1128	"SoftInt 18h", "SoftInt 19h", "SoftInt 1ah", "SoftInt 1bh", "SoftInt 1ch", "SoftInt 1dh", "SoftInt 1eh", "SoftInt 1fh",
1129	"SoftInt 20h", "SoftInt 21h", "SoftInt 22h", "SoftInt 23h", "SoftInt 24h", "SoftInt 25h", "SoftInt 26h", "SoftInt 27h",
1130	"SoftInt 28h", "SoftInt 29h", "SoftInt 2ah", "SoftInt 2bh", "SoftInt 2ch", "SoftInt 2dh", "SoftInt 2eh", "SoftInt 2fh",
1131	"SoftInt 30h", "SoftInt 31h", "SoftInt 32h", "SoftInt 33h", "SoftInt 34h", "SoftInt 35h", "SoftInt 36h", "SoftInt 37h",
1132	"SoftInt 38h", "SoftInt 39h", "SoftInt 3ah", "SoftInt 3bh", "SoftInt 3ch", "SoftInt 3dh", "SoftInt 3eh", "SoftInt 3fh",
1133	"SoftInt 40h", "SoftInt 41h", "SoftInt 42h", "SoftInt 43h", "SoftInt 44h", "SoftInt 45h", "SoftInt 46h", "SoftInt 47h",
1134	"SoftInt 48h", "SoftInt 49h", "SoftInt 4ah", "SoftInt 4bh", "SoftInt 4ch", "SoftInt 4dh", "SoftInt 4eh", "SoftInt 4fh",
1135	"SoftInt 50h", "SoftInt 51h", "SoftInt 52h", "SoftInt 53h", "SoftInt 54h", "SoftInt 55h", "SoftInt 56h", "SoftInt 57h",
1136	"SoftInt 58h", "SoftInt 59h", "SoftInt 5ah", "SoftInt 5bh", "SoftInt 5ch", "SoftInt 5dh", "SoftInt 5eh", "SoftInt 5fh",
1137	"SoftInt 60h", "SoftInt 61h", "SoftInt 62h", "SoftInt 63h", "SoftInt 64h", "SoftInt 65h", "SoftInt 66h", "SoftInt 67h",
1138	"SoftInt 68h", "SoftInt 69h", "SoftInt 6ah", "SoftInt 6bh", "SoftInt 6ch", "SoftInt 6dh", "SoftInt 6eh", "SoftInt 6fh",
1139	"SoftInt 70h", "SoftInt 71h", "SoftInt 72h", "SoftInt 73h", "SoftInt 74h", "SoftInt 75h", "SoftInt 76h", "SoftInt 77h",
1140	"SoftInt 78h", "SoftInt 79h", "SoftInt 7ah", "SoftInt 7bh", "SoftInt 7ch", "SoftInt 7dh", "SoftInt 7eh", "SoftInt 7fh",
1141	"SoftInt 80h", "SoftInt 81h", "SoftInt 82h", "SoftInt 83h", "SoftInt 84h", "SoftInt 85h", "SoftInt 86h", "SoftInt 87h",
1142	"SoftInt 88h", "SoftInt 89h", "SoftInt 8ah", "SoftInt 8bh", "SoftInt 8ch", "SoftInt 8dh", "SoftInt 8eh", "SoftInt 8fh",
1143	"SoftInt 90h", "SoftInt 91h", "SoftInt 92h", "SoftInt 93h", "SoftInt 94h", "SoftInt 95h", "SoftInt 96h", "SoftInt 97h",
1144	"SoftInt 98h", "SoftInt 99h", "SoftInt 9ah", "SoftInt 9bh", "SoftInt 9ch", "SoftInt 9dh", "SoftInt 9eh", "SoftInt 9fh",
1145	"SoftInt a0h", "SoftInt a1h", "SoftInt a2h", "SoftInt a3h", "SoftInt a4h", "SoftInt a5h", "SoftInt a6h", "SoftInt a7h",
1146	"SoftInt a8h", "SoftInt a9h", "SoftInt aah", "SoftInt abh", "SoftInt ach", "SoftInt adh", "SoftInt aeh", "SoftInt afh",
1147	"SoftInt b0h", "SoftInt b1h", "SoftInt b2h", "SoftInt b3h", "SoftInt b4h", "SoftInt b5h", "SoftInt b6h", "SoftInt b7h",
1148	"SoftInt b8h", "SoftInt b9h", "SoftInt bah", "SoftInt bbh", "SoftInt bch", "SoftInt bdh", "SoftInt beh", "SoftInt bfh",
1149	"SoftInt c0h", "SoftInt c1h", "SoftInt c2h", "SoftInt c3h", "SoftInt c4h", "SoftInt c5h", "SoftInt c6h", "SoftInt c7h",
1150	"SoftInt c8h", "SoftInt c9h", "SoftInt cah", "SoftInt cbh", "SoftInt cch", "SoftInt cdh", "SoftInt ceh", "SoftInt cfh",
1151	"SoftInt d0h", "SoftInt d1h", "SoftInt d2h", "SoftInt d3h", "SoftInt d4h", "SoftInt d5h", "SoftInt d6h", "SoftInt d7h",
1152	"SoftInt d8h", "SoftInt d9h", "SoftInt dah", "SoftInt dbh", "SoftInt dch", "SoftInt ddh", "SoftInt deh", "SoftInt dfh",
1153	"SoftInt e0h", "SoftInt e1h", "SoftInt e2h", "SoftInt e3h", "SoftInt e4h", "SoftInt e5h", "SoftInt e6h", "SoftInt e7h",
1154	"SoftInt e8h", "SoftInt e9h", "SoftInt eah", "SoftInt ebh", "SoftInt ech", "SoftInt edh", "SoftInt eeh", "SoftInt efh",
1155	"SoftInt f0h", "SoftInt f1h", "SoftInt f2h", "SoftInt f3h", "SoftInt f4h", "SoftInt f5h", "SoftInt f6h", "SoftInt f7h",
1156	"SoftInt f8h", "SoftInt f9h", "SoftInt fah", "SoftInt fbh", "SoftInt fch", "SoftInt fdh", "SoftInt feh", "SoftInt ffh",
1157	};
1158	if (uExit < RT_ELEMENTS(s_apszNames))
1159	return s_apszNames[uExit];
1160	return NULL;
1161	}
1162
1163
1164	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
1165	static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, bool pfHeader)
1166	{
1167	if (*pfHeader)
1168	return;
1169	pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
1170	*pfHeader = true;
1171	}
1172
1173
1174	#define IEMR3INFOTLB_F_ONLY_VALID RT_BIT_32(0)
1175	#define IEMR3INFOTLB_F_CHECK RT_BIT_32(1)
1176
1177	/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
1178	static void iemR3InfoTlbPrintSlot(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const pTlb, IEMTLBENTRY const pTlbe,
1179	uint32_t uSlot, uint32_t fFlags)
1180	{
1181	#ifndef VBOX_VMM_TARGET_ARMV8
1182	uint64_t const uTlbRevision = !(uSlot & 1) ? pTlb->uTlbRevision : pTlb->uTlbRevisionGlobal;
1183	#else
1184	uint64_t const uTlbRevision = pTlb->uTlbRevision;
1185	#endif
1186	if ((fFlags & IEMR3INFOTLB_F_ONLY_VALID) && (pTlbe->uTag & IEMTLB_REVISION_MASK) != uTlbRevision)
1187	return;
1188
1189	/* The address needs to be sign extended, thus the shifting fun here.*/
1190	RTGCPTR const GCPtr = (RTGCINTPTR)((pTlbe->uTag & ~IEMTLB_REVISION_MASK) << (64 - IEMTLB_TAG_ADDR_WIDTH))
1191	>> (64 - IEMTLB_TAG_ADDR_WIDTH - GUEST_PAGE_SHIFT);
1192	const char *pszValid = "";
1193	#ifndef VBOX_VMM_TARGET_ARMV8
1194	char szTmp[128];
1195	if (fFlags & IEMR3INFOTLB_F_CHECK)
1196	{
1197	uint32_t const fInvSlotG = (uint32_t)!(uSlot & 1) << X86_PTE_BIT_G;
1198	PGMPTWALKFAST WalkFast;
1199	int rc = PGMGstQueryPageFast(pVCpu, GCPtr, 0 /fFlags - don't check or modify anything /, &WalkFast);
1200	pszValid = szTmp;
1201	if (RT_FAILURE(rc))
1202	switch (rc)
1203	{
1204	case VERR_PAGE_TABLE_NOT_PRESENT:
1205	switch ((WalkFast.fFailed & PGM_WALKFAIL_LEVEL_MASK) >> PGM_WALKFAIL_LEVEL_SHIFT)
1206	{
1207	case 1: pszValid = " stale(page-not-present)"; break;
1208	case 2: pszValid = " stale(pd-entry-not-present)"; break;
1209	case 3: pszValid = " stale(pdptr-entry-not-present)"; break;
1210	case 4: pszValid = " stale(pml4-entry-not-present)"; break;
1211	case 5: pszValid = " stale(pml5-entry-not-present)"; break;
1212	default: pszValid = " stale(VERR_PAGE_TABLE_NOT_PRESENT)"; break;
1213	}
1214	break;
1215	default: RTStrPrintf(szTmp, sizeof(szTmp), " stale(rc=%d)", rc); break;
1216	}
1217	else if (WalkFast.GCPhys != pTlbe->GCPhys)
1218	RTStrPrintf(szTmp, sizeof(szTmp), " stale(GCPhys=%RGp)", WalkFast.GCPhys);
1219	else if ( (~WalkFast.fEffective & (X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D))
1220	== ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PT_NO_WRITE \| IEMTLBE_F_PT_NO_USER
1221	\| IEMTLBE_F_PT_NO_DIRTY \| IEMTLBE_F_PT_NO_ACCESSED))
1222	\| fInvSlotG ) )
1223	pszValid = " still-valid";
1224	else if ( (~WalkFast.fEffective & (X86_PTE_RW \| X86_PTE_US \| X86_PTE_G))
1225	== ((pTlbe->fFlagsAndPhysRev & (IEMTLBE_F_PT_NO_WRITE \| IEMTLBE_F_PT_NO_USER)) \| fInvSlotG) )
1226	switch ( (~WalkFast.fEffective & (X86_PTE_A \| X86_PTE_D))
1227	^ (pTlbe->fFlagsAndPhysRev & (IEMTLBE_F_PT_NO_DIRTY \| IEMTLBE_F_PT_NO_ACCESSED)) )
1228	{
1229	case X86_PTE_A:
1230	pszValid = WalkFast.fEffective & X86_PTE_A ? " still-valid(accessed-now)" : " still-valid(accessed-no-more)";
1231	break;
1232	case X86_PTE_D:
1233	pszValid = WalkFast.fEffective & X86_PTE_D ? " still-valid(dirty-now)" : " still-valid(dirty-no-more)";
1234	break;
1235	case X86_PTE_D \| X86_PTE_A:
1236	RTStrPrintf(szTmp, sizeof(szTmp), " still-valid(%s%s)",
1237	(~WalkFast.fEffective & X86_PTE_D) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY) ? ""
1238	: WalkFast.fEffective & X86_PTE_D ? "dirty-now" : "dirty-no-more",
1239	(~WalkFast.fEffective & X86_PTE_A) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED) ? ""
1240	: WalkFast.fEffective & X86_PTE_A ? " accessed-now" : " accessed-no-more");
1241	break;
1242	default: AssertFailed(); break;
1243	}
1244	else
1245	RTStrPrintf(szTmp, sizeof(szTmp), " stale(%s%s%s%s%s)",
1246	(~WalkFast.fEffective & X86_PTE_RW) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE) ? ""
1247	: WalkFast.fEffective & X86_PTE_RW ? "writeable-now" : "writable-no-more",
1248	(~WalkFast.fEffective & X86_PTE_US) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_USER) ? ""
1249	: WalkFast.fEffective & X86_PTE_US ? " user-now" : " user-no-more",
1250	(~WalkFast.fEffective & X86_PTE_G) == fInvSlotG ? ""
1251	: WalkFast.fEffective & X86_PTE_G ? " global-now" : " global-no-more",
1252	(~WalkFast.fEffective & X86_PTE_D) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY) ? ""
1253	: WalkFast.fEffective & X86_PTE_D ? " dirty-now" : " dirty-no-more",
1254	(~WalkFast.fEffective & X86_PTE_A) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED) ? ""
1255	: WalkFast.fEffective & X86_PTE_A ? " accessed-now" : " accessed-no-more");
1256	}
1257	#else
1258	RT_NOREF(pVCpu);
1259	#endif
1260
1261	pHlp->pfnPrintf(pHlp, IEMTLB_SLOT_FMT ": %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s%s%s%s/%s%s%s%s/%s %s%s\n",
1262	uSlot,
1263	(pTlbe->uTag & IEMTLB_REVISION_MASK) == uTlbRevision ? "valid "
1264	: (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
1265	: "expired",
1266	GCPtr, /* -> */
1267	pTlbe->GCPhys, /* / */ pTlbe->pbMappingR3,
1268	/* / */
1269	(uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
1270	/* */
1271	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "R-" : "RW",
1272	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "-" : "X",
1273	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
1274	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
1275	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_USER ? "U" : "S",
1276	!(uSlot & 1) ? "-" : "G",
1277	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_LARGE_PAGE ? "4K" : "2M",
1278	/* / */
1279	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
1280	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
1281	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "u" : "-",
1282	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_CODE_PAGE ? "c" : "-",
1283	/* / */
1284	pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "N" : "M",
1285	(pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
1286	: (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired",
1287	pszValid);
1288	}
1289
1290
1291	/** Displays one or more TLB slots. */
1292	static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
1293	uint32_t uSlot, uint32_t cSlots, uint32_t fFlags, bool *pfHeader)
1294	{
1295	if (uSlot < RT_ELEMENTS(pTlb->aEntries))
1296	{
1297	if (cSlots > RT_ELEMENTS(pTlb->aEntries))
1298	{
1299	pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
1300	cSlots, RT_ELEMENTS(pTlb->aEntries));
1301	cSlots = RT_ELEMENTS(pTlb->aEntries);
1302	}
1303
1304	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
1305	while (cSlots-- > 0)
1306	{
1307	IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
1308	iemR3InfoTlbPrintSlot(pVCpu, pHlp, pTlb, &Tlbe, uSlot, fFlags);
1309	uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
1310	}
1311	}
1312	else
1313	pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
1314	uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
1315	}
1316
1317
1318	/** Displays the TLB slot for the given address. */
1319	static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
1320	uint64_t uAddress, uint32_t fFlags, bool *pfHeader)
1321	{
1322	iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
1323
1324	uint64_t const uTag = IEMTLB_CALC_TAG_NO_REV(uAddress);
1325	#ifdef IEMTLB_TAG_TO_EVEN_INDEX
1326	uint32_t const uSlot = IEMTLB_TAG_TO_EVEN_INDEX(uTag);
1327	#else
1328	uint32_t const uSlot = IEMTLB_TAG_TO_INDEX(uTag);
1329	#endif
1330	IEMTLBENTRY const TlbeL = pTlb->aEntries[uSlot];
1331	#ifndef VBOX_VMM_TARGET_ARMV8
1332	IEMTLBENTRY const TlbeG = pTlb->aEntries[uSlot + 1];
1333	#endif
1334	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
1335	TlbeL.uTag == (uTag \| pTlb->uTlbRevision) ? "match"
1336	: (TlbeL.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
1337	iemR3InfoTlbPrintSlot(pVCpu, pHlp, pTlb, &TlbeL, uSlot, fFlags);
1338
1339	#ifndef VBOX_VMM_TARGET_ARMV8
1340	pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot + 1,
1341	TlbeG.uTag == (uTag \| pTlb->uTlbRevisionGlobal) ? "match"
1342	: (TlbeG.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
1343	iemR3InfoTlbPrintSlot(pVCpu, pHlp, pTlb, &TlbeG, uSlot + 1, fFlags);
1344	#endif
1345	}
1346
1347
1348	/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
1349	static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
1350	{
1351	/*
1352	* This is entirely argument driven.
1353	*/
1354	static RTGETOPTDEF const s_aOptions[] =
1355	{
1356	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1357	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1358	{ "--check", 'C', RTGETOPT_REQ_NOTHING },
1359	{ "all", 'A', RTGETOPT_REQ_NOTHING },
1360	{ "--all", 'A', RTGETOPT_REQ_NOTHING },
1361	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1362	{ "--range", 'r', RTGETOPT_REQ_UINT32_PAIR \| RTGETOPT_FLAG_HEX },
1363	{ "--slot", 's', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
1364	{ "--only-valid", 'v', RTGETOPT_REQ_NOTHING },
1365	};
1366
1367	RTGETOPTSTATE State;
1368	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
1369	AssertRCReturnVoid(rc);
1370
1371	uint32_t cActionArgs = 0;
1372	bool fNeedHeader = true;
1373	bool fAddressMode = true;
1374	uint32_t fFlags = 0;
1375	PVMCPU const pVCpuCall = VMMGetCpu(pVM);
1376	PVMCPU pVCpu = pVCpuCall;
1377	if (!pVCpu)
1378	pVCpu = VMMGetCpuById(pVM, 0);
1379
1380	RTGETOPTUNION ValueUnion;
1381	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1382	{
1383	switch (rc)
1384	{
1385	case 'c':
1386	if (ValueUnion.u32 >= pVM->cCpus)
1387	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1388	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
1389	{
1390	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1391	fNeedHeader = true;
1392	if (!pVCpuCall \|\| pVCpuCall->idCpu != ValueUnion.u32)
1393	{
1394	pHlp->pfnPrintf(pHlp, "info: Can't check guest PTs when switching to a different VCpu! Targetting %u, on %u.\n",
1395	ValueUnion.u32, pVCpuCall->idCpu);
1396	fFlags &= ~IEMR3INFOTLB_F_CHECK;
1397	}
1398	}
1399	break;
1400
1401	case 'C':
1402	if (!pVCpuCall)
1403	pHlp->pfnPrintf(pHlp, "error: Can't check guest PT when not running on an EMT!\n");
1404	else if (pVCpu != pVCpuCall)
1405	pHlp->pfnPrintf(pHlp, "error: Can't check guest PTs when on a different EMT! Targetting %u, on %u.\n",
1406	pVCpu->idCpu, pVCpuCall->idCpu);
1407	else
1408	fFlags \|= IEMR3INFOTLB_F_CHECK;
1409	break;
1410
1411	case 'a':
1412	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1413	ValueUnion.u64, fFlags, &fNeedHeader);
1414	fAddressMode = true;
1415	cActionArgs++;
1416	break;
1417
1418	case 'A':
1419	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1420	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), fFlags, &fNeedHeader);
1421	cActionArgs++;
1422	break;
1423
1424	case 'r':
1425	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1426	ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, fFlags, &fNeedHeader);
1427	fAddressMode = false;
1428	cActionArgs++;
1429	break;
1430
1431	case 's':
1432	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1433	ValueUnion.u32, 1, fFlags, &fNeedHeader);
1434	fAddressMode = false;
1435	cActionArgs++;
1436	break;
1437
1438	case 'v':
1439	fFlags \|= IEMR3INFOTLB_F_ONLY_VALID;
1440	break;
1441
1442	case VINF_GETOPT_NOT_OPTION:
1443	if (fAddressMode)
1444	{
1445	uint64_t uAddr;
1446	rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
1447	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
1448	iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1449	uAddr, fFlags, &fNeedHeader);
1450	else
1451	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
1452	}
1453	else
1454	{
1455	uint32_t uSlot;
1456	rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
1457	if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
1458	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1459	uSlot, 1, fFlags, &fNeedHeader);
1460	else
1461	pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
1462	}
1463	cActionArgs++;
1464	break;
1465
1466	case 'h':
1467	pHlp->pfnPrintf(pHlp,
1468	"Usage: info %ctlb [options]\n"
1469	"\n"
1470	"Options:\n"
1471	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
1472	" Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
1473	" -C,--check\n"
1474	" Check valid entries against guest PTs.\n"
1475	" -A, --all, all\n"
1476	" Display all the TLB entries (default if no other args).\n"
1477	" -a<virt>, --address=<virt>\n"
1478	" Shows the TLB entry for the specified guest virtual address.\n"
1479	" -r<slot:count>, --range=<slot:count>\n"
1480	" Shows the TLB entries for the specified slot range.\n"
1481	" -s<slot>,--slot=<slot>\n"
1482	" Shows the given TLB slot.\n"
1483	" -v,--only-valid\n"
1484	" Only show valid TLB entries (TAG, not phys)\n"
1485	"\n"
1486	"Non-options are interpreted according to the last -a, -r or -s option,\n"
1487	"defaulting to addresses if not preceeded by any of those options.\n"
1488	, fITlb ? 'i' : 'd');
1489	return;
1490
1491	default:
1492	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1493	return;
1494	}
1495	}
1496
1497	/*
1498	* If no action taken, we display all (-A) by default.
1499	*/
1500	if (!cActionArgs)
1501	iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1502	0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), fFlags, &fNeedHeader);
1503	}
1504
1505
1506	/**
1507	* @callback_method_impl{FNDBGFINFOARGVINT, itlb}
1508	*/
1509	static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1510	{
1511	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /fITlb/);
1512	}
1513
1514
1515	/**
1516	* @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
1517	*/
1518	static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1519	{
1520	return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /fITlb/);
1521	}
1522
1523
1524	#ifdef IEM_WITH_TLB_TRACE
1525	/**
1526	* @callback_method_impl{FNDBGFINFOARGVINT, tlbtrace}
1527	*/
1528	static DECLCALLBACK(void) iemR3InfoTlbTrace(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1529	{
1530	/*
1531	* Parse arguments.
1532	*/
1533	static RTGETOPTDEF const s_aOptions[] =
1534	{
1535	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1536	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1537	{ "--last", 'l', RTGETOPT_REQ_UINT32 },
1538	{ "--limit", 'l', RTGETOPT_REQ_UINT32 },
1539	{ "--stop-at-global-flush", 'g', RTGETOPT_REQ_NOTHING },
1540	{ "--resolve-rip", 'r', RTGETOPT_REQ_NOTHING },
1541	};
1542
1543	RTGETOPTSTATE State;
1544	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
1545	AssertRCReturnVoid(rc);
1546
1547	uint32_t cLimit = UINT32_MAX;
1548	bool fStopAtGlobalFlush = false;
1549	bool fResolveRip = false;
1550	PVMCPU const pVCpuCall = VMMGetCpu(pVM);
1551	PVMCPU pVCpu = pVCpuCall;
1552	if (!pVCpu)
1553	pVCpu = VMMGetCpuById(pVM, 0);
1554
1555	RTGETOPTUNION ValueUnion;
1556	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1557	{
1558	switch (rc)
1559	{
1560	case 'c':
1561	if (ValueUnion.u32 >= pVM->cCpus)
1562	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1563	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
1564	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1565	break;
1566
1567	case 'l':
1568	cLimit = ValueUnion.u32;
1569	break;
1570
1571	case 'g':
1572	fStopAtGlobalFlush = true;
1573	break;
1574
1575	case 'r':
1576	fResolveRip = true;
1577	break;
1578
1579	case 'h':
1580	pHlp->pfnPrintf(pHlp,
1581	"Usage: info tlbtrace [options] [n]\n"
1582	"\n"
1583	"Options:\n"
1584	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
1585	" Selects the CPU which TLB trace we're looking at. Default: Caller / 0\n"
1586	" [n], -l<n>, --last=<n>\n"
1587	" Limit display to the last N entries. Default: all\n"
1588	" -g, --stop-at-global-flush\n"
1589	" Stop after the first global flush entry.\n"
1590	" -r, --resolve-rip\n"
1591	" Resolve symbols for the flattened RIP addresses.\n"
1592	);
1593	return;
1594
1595	case VINF_GETOPT_NOT_OPTION:
1596	rc = RTStrToUInt32Full(ValueUnion.psz, 0, &cLimit);
1597	if (RT_SUCCESS(rc))
1598	break;
1599	pHlp->pfnPrintf(pHlp, "error: failed to convert '%s' to a number: %Rrc\n", ValueUnion.psz, rc);
1600	return;
1601
1602	default:
1603	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1604	return;
1605	}
1606	}
1607
1608	/*
1609	* Get the details.
1610	*/
1611	AssertReturnVoid(pVCpu);
1612	Assert(pVCpu->iem.s.cTlbTraceEntriesShift <= 28);
1613	uint32_t idx = pVCpu->iem.s.idxTlbTraceEntry;
1614	uint32_t const cShift = RT_MIN(pVCpu->iem.s.cTlbTraceEntriesShift, 28);
1615	uint32_t const fMask = RT_BIT_32(cShift) - 1;
1616	uint32_t cLeft = RT_MIN(RT_MIN(idx, RT_BIT_32(cShift)), cLimit);
1617	PCIEMTLBTRACEENTRY paEntries = pVCpu->iem.s.paTlbTraceEntries;
1618	if (cLeft && paEntries)
1619	{
1620	/*
1621	* Display the entries.
1622	*/
1623	pHlp->pfnPrintf(pHlp, "TLB Trace for CPU %u:\n", pVCpu->idCpu);
1624	while (cLeft-- > 0)
1625	{
1626	PCIEMTLBTRACEENTRY const pCur = &paEntries[--idx & fMask];
1627	const char *pszSymbol = "";
1628	union
1629	{
1630	RTDBGSYMBOL Symbol;
1631	char ach[sizeof(RTDBGSYMBOL) + 32];
1632	} uBuf;
1633	if (fResolveRip)
1634	{
1635	RTGCINTPTR offDisp = 0;
1636	DBGFADDRESS Addr;
1637	rc = DBGFR3AsSymbolByAddr(pVM->pUVM, DBGF_AS_GLOBAL, DBGFR3AddrFromFlat(pVM->pUVM, &Addr, pCur->rip),
1638	RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL
1639	\| RTDBGSYMADDR_FLAGS_SKIP_ABS
1640	\| RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
1641	&offDisp, &uBuf.Symbol, NULL);
1642	if (RT_SUCCESS(rc))
1643	{
1644	/* Add displacement. */
1645	if (offDisp)
1646	{
1647	size_t const cchName = strlen(uBuf.Symbol.szName);
1648	char * const pszEndName = &uBuf.Symbol.szName[cchName];
1649	size_t const cbLeft = sizeof(uBuf) - sizeof(uBuf.Symbol) + sizeof(uBuf.Symbol.szName) - cchName;
1650	if (offDisp > 0)
1651	RTStrPrintf(pszEndName, cbLeft, "+%#1RGv", offDisp);
1652	else
1653	RTStrPrintf(pszEndName, cbLeft, "-%#1RGv", -offDisp);
1654	}
1655
1656	/* Put a space before it. */
1657	AssertCompile(RTASSERT_OFFSET_OF(RTDBGSYMBOL, szName) > 0);
1658	char *pszName = uBuf.Symbol.szName;
1659	*--pszName = ' ';
1660	pszSymbol = pszName;
1661	}
1662	}
1663	static const char *s_apszTlbType[2] = { "code", "data" };
1664	static const char *s_apszScanType[4] = { "skipped", "global", "non-global", "both" };
1665	switch (pCur->enmType)
1666	{
1667	case kIemTlbTraceType_InvlPg:
1668	pHlp->pfnPrintf(pHlp, "%u: %016RX64 invlpg %RGv slot=" IEMTLB_SLOT_FMT "%s\n", idx, pCur->rip,
1669	pCur->u64Param, (uint32_t)IEMTLB_ADDR_TO_EVEN_INDEX(pCur->u64Param), pszSymbol);
1670	break;
1671	case kIemTlbTraceType_EvictSlot:
1672	pHlp->pfnPrintf(pHlp, "%u: %016RX64 evict %s slot=" IEMTLB_SLOT_FMT " %RGv (%#RX64) gcphys=%RGp%s\n",
1673	idx, pCur->rip, s_apszTlbType[pCur->bParam & 1], pCur->u32Param,
1674	(RTGCINTPTR)((pCur->u64Param & ~IEMTLB_REVISION_MASK) << (64 - IEMTLB_TAG_ADDR_WIDTH))
1675	>> (64 - IEMTLB_TAG_ADDR_WIDTH - GUEST_PAGE_SHIFT), pCur->u64Param,
1676	pCur->u64Param2, pszSymbol);
1677	break;
1678	case kIemTlbTraceType_LargeEvictSlot:
1679	pHlp->pfnPrintf(pHlp, "%u: %016RX64 large evict %s slot=" IEMTLB_SLOT_FMT " %RGv (%#RX64) gcphys=%RGp%s\n",
1680	idx, pCur->rip, s_apszTlbType[pCur->bParam & 1], pCur->u32Param,
1681	(RTGCINTPTR)((pCur->u64Param & ~IEMTLB_REVISION_MASK) << (64 - IEMTLB_TAG_ADDR_WIDTH))
1682	>> (64 - IEMTLB_TAG_ADDR_WIDTH - GUEST_PAGE_SHIFT), pCur->u64Param,
1683	pCur->u64Param2, pszSymbol);
1684	break;
1685	case kIemTlbTraceType_LargeScan:
1686	pHlp->pfnPrintf(pHlp, "%u: %016RX64 large scan %s %s%s\n", idx, pCur->rip, s_apszTlbType[pCur->bParam & 1],
1687	s_apszScanType[pCur->u32Param & 3], pszSymbol);
1688	break;
1689
1690	case kIemTlbTraceType_Flush:
1691	pHlp->pfnPrintf(pHlp, "%u: %016RX64 flush %s rev=%#RX64%s\n", idx, pCur->rip,
1692	s_apszTlbType[pCur->bParam & 1], pCur->u64Param, pszSymbol);
1693	break;
1694	case kIemTlbTraceType_FlushGlobal:
1695	pHlp->pfnPrintf(pHlp, "%u: %016RX64 flush %s rev=%#RX64 grev=%#RX64%s\n", idx, pCur->rip,
1696	s_apszTlbType[pCur->bParam & 1], pCur->u64Param, pCur->u64Param2, pszSymbol);
1697	if (fStopAtGlobalFlush)
1698	return;
1699	break;
1700	case kIemTlbTraceType_Load:
1701	case kIemTlbTraceType_LoadGlobal:
1702	pHlp->pfnPrintf(pHlp, "%u: %016RX64 %cload %s %RGv slot=" IEMTLB_SLOT_FMT " gcphys=%RGp fTlb=%#RX32%s\n",
1703	idx, pCur->rip,
1704	pCur->enmType == kIemTlbTraceType_LoadGlobal ? 'g' : 'l', s_apszTlbType[pCur->bParam & 1],
1705	pCur->u64Param,
1706	(uint32_t)IEMTLB_ADDR_TO_EVEN_INDEX(pCur->u64Param)
1707	\| (pCur->enmType == kIemTlbTraceType_LoadGlobal),
1708	(RTGCPTR)pCur->u64Param2, pCur->u32Param, pszSymbol);
1709	break;
1710
1711	case kIemTlbTraceType_Load_Cr0:
1712	pHlp->pfnPrintf(pHlp, "%u: %016RX64 load cr0 %08RX64 (was %08RX64)%s\n",
1713	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1714	break;
1715	case kIemTlbTraceType_Load_Cr3:
1716	pHlp->pfnPrintf(pHlp, "%u: %016RX64 load cr3 %016RX64 (was %016RX64)%s\n",
1717	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1718	break;
1719	case kIemTlbTraceType_Load_Cr4:
1720	pHlp->pfnPrintf(pHlp, "%u: %016RX64 load cr4 %08RX64 (was %08RX64)%s\n",
1721	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1722	break;
1723	case kIemTlbTraceType_Load_Efer:
1724	pHlp->pfnPrintf(pHlp, "%u: %016RX64 load efer %016RX64 (was %016RX64)%s\n",
1725	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1726	break;
1727
1728	case kIemTlbTraceType_Irq:
1729	pHlp->pfnPrintf(pHlp, "%u: %016RX64 irq %#04x flags=%#x eflboth=%#RX64%s\n",
1730	idx, pCur->rip, pCur->bParam, pCur->u32Param,
1731	pCur->u64Param & ((RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - 1) \| CPUMX86EFLAGS_INT_MASK_64),
1732	pszSymbol);
1733	break;
1734	case kIemTlbTraceType_Xcpt:
1735	if (pCur->u32Param & IEM_XCPT_FLAGS_CR2)
1736	pHlp->pfnPrintf(pHlp, "%u: %016RX64 xcpt %#04x flags=%#x errcd=%#x cr2=%RX64%s\n",
1737	idx, pCur->rip, pCur->bParam, pCur->u32Param, pCur->u64Param, pCur->u64Param2, pszSymbol);
1738	else if (pCur->u32Param & IEM_XCPT_FLAGS_ERR)
1739	pHlp->pfnPrintf(pHlp, "%u: %016RX64 xcpt %#04x flags=%#x errcd=%#x%s\n",
1740	idx, pCur->rip, pCur->bParam, pCur->u32Param, pCur->u64Param, pszSymbol);
1741	else
1742	pHlp->pfnPrintf(pHlp, "%u: %016RX64 xcpt %#04x flags=%#x%s\n",
1743	idx, pCur->rip, pCur->bParam, pCur->u32Param, pszSymbol);
1744	break;
1745	case kIemTlbTraceType_IRet:
1746	pHlp->pfnPrintf(pHlp, "%u: %016RX64 iret cs:rip=%04x:%016RX64 efl=%08RX32%s\n",
1747	idx, pCur->rip, pCur->u32Param, pCur->u64Param, (uint32_t)pCur->u64Param2, pszSymbol);
1748	break;
1749
1750	case kIemTlbTraceType_Tb_Compile:
1751	pHlp->pfnPrintf(pHlp, "%u: %016RX64 tb comp GCPhysPc=%012RX64%s\n",
1752	idx, pCur->rip, pCur->u64Param, pszSymbol);
1753	break;
1754	case kIemTlbTraceType_Tb_Exec_Threaded:
1755	pHlp->pfnPrintf(pHlp, "%u: %016RX64 tb thrd GCPhysPc=%012RX64 tb=%p used=%u%s\n",
1756	idx, pCur->rip, pCur->u64Param, (uintptr_t)pCur->u64Param2, pCur->u32Param, pszSymbol);
1757	break;
1758	case kIemTlbTraceType_Tb_Exec_Native:
1759	pHlp->pfnPrintf(pHlp, "%u: %016RX64 tb n8ve GCPhysPc=%012RX64 tb=%p used=%u%s\n",
1760	idx, pCur->rip, pCur->u64Param, (uintptr_t)pCur->u64Param2, pCur->u32Param, pszSymbol);
1761	break;
1762
1763	case kIemTlbTraceType_User0:
1764	pHlp->pfnPrintf(pHlp, "%u: %016RX64 user0 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1765	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1766	break;
1767	case kIemTlbTraceType_User1:
1768	pHlp->pfnPrintf(pHlp, "%u: %016RX64 user1 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1769	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1770	break;
1771	case kIemTlbTraceType_User2:
1772	pHlp->pfnPrintf(pHlp, "%u: %016RX64 user2 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1773	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1774	break;
1775	case kIemTlbTraceType_User3:
1776	pHlp->pfnPrintf(pHlp, "%u: %016RX64 user3 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1777	idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1778	break;
1779
1780	case kIemTlbTraceType_Invalid:
1781	pHlp->pfnPrintf(pHlp, "%u: Invalid!\n");
1782	break;
1783	}
1784	}
1785	}
1786	else
1787	pHlp->pfnPrintf(pHlp, "No trace entries to display\n");
1788	}
1789	#endif /* IEM_WITH_TLB_TRACE */
1790
1791	#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1792
1793	/**
1794	* Get get compile time flat PC for the TB.
1795	*/
1796	DECL_FORCE_INLINE(RTGCPTR) iemR3GetTbFlatPc(PCIEMTB pTb)
1797	{
1798	#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
1799	if (pTb->fFlags & IEMTB_F_TYPE_NATIVE)
1800	{
1801	PCIEMTBDBG const pDbgInfo = pTb->pDbgInfo;
1802	return pDbgInfo ? pDbgInfo->FlatPc : RTGCPTR_MAX;
1803	}
1804	#endif
1805	return pTb->FlatPc;
1806	}
1807
1808
1809	/**
1810	* @callback_method_impl{FNDBGFINFOARGVINT, tb}
1811	*/
1812	static DECLCALLBACK(void) iemR3InfoTb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1813	{
1814	/*
1815	* Parse arguments.
1816	*/
1817	static RTGETOPTDEF const s_aOptions[] =
1818	{
1819	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1820	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1821	{ "--addr", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1822	{ "--address", 'a', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1823	{ "--phys", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1824	{ "--physical", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1825	{ "--phys-addr", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1826	{ "--phys-address", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1827	{ "--physical-address", 'p', RTGETOPT_REQ_UINT64 \| RTGETOPT_FLAG_HEX },
1828	{ "--flags", 'f', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
1829	{ "--tb", 't', RTGETOPT_REQ_UINT32 \| RTGETOPT_FLAG_HEX },
1830	{ "--tb-id", 't', RTGETOPT_REQ_UINT32 },
1831	};
1832
1833	RTGETOPTSTATE State;
1834	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
1835	AssertRCReturnVoid(rc);
1836
1837	PVMCPU const pVCpuThis = VMMGetCpu(pVM);
1838	PVMCPU pVCpu = pVCpuThis ? pVCpuThis : VMMGetCpuById(pVM, 0);
1839	RTGCPHYS GCPhysPc = NIL_RTGCPHYS;
1840	RTGCPHYS GCVirt = NIL_RTGCPTR;
1841	uint32_t fFlags = UINT32_MAX;
1842	uint32_t idTb = UINT32_MAX;
1843
1844	RTGETOPTUNION ValueUnion;
1845	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1846	{
1847	switch (rc)
1848	{
1849	case 'c':
1850	if (ValueUnion.u32 >= pVM->cCpus)
1851	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1852	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
1853	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1854	break;
1855
1856	case 'a':
1857	GCVirt = ValueUnion.u64;
1858	GCPhysPc = NIL_RTGCPHYS;
1859	idTb = UINT32_MAX;
1860	break;
1861
1862	case 'p':
1863	GCVirt = NIL_RTGCPHYS;
1864	GCPhysPc = ValueUnion.u64;
1865	idTb = UINT32_MAX;
1866	break;
1867
1868	case 'f':
1869	fFlags = ValueUnion.u32;
1870	break;
1871
1872	case 't':
1873	GCVirt = NIL_RTGCPHYS;
1874	GCPhysPc = NIL_RTGCPHYS;
1875	idTb = ValueUnion.u32;
1876	break;
1877
1878	case VINF_GETOPT_NOT_OPTION:
1879	{
1880	if ( (ValueUnion.psz[0] == 'T' \|\| ValueUnion.psz[0] == 't')
1881	&& (ValueUnion.psz[1] == 'B' \|\| ValueUnion.psz[1] == 'b')
1882	&& ValueUnion.psz[2] == '#')
1883	{
1884	rc = RTStrToUInt32Full(&ValueUnion.psz[3], 0, &idTb);
1885	if (RT_SUCCESS(rc))
1886	{
1887	GCVirt = NIL_RTGCPHYS;
1888	GCPhysPc = NIL_RTGCPHYS;
1889	break;
1890	}
1891	pHlp->pfnPrintf(pHlp, "error: failed to convert '%s' to TD ID: %Rrc\n", ValueUnion.psz, rc);
1892	}
1893	else
1894	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1895	return;
1896	}
1897
1898	case 'h':
1899	pHlp->pfnPrintf(pHlp,
1900	"Usage: info tb [options]\n"
1901	"\n"
1902	"Options:\n"
1903	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
1904	" Selects the CPU which TBs we're looking at. Default: Caller / 0\n"
1905	" -a<virt>, --address=<virt>\n"
1906	" Shows the TB for the specified guest virtual address.\n"
1907	" -p<phys>, --phys=<phys>, --phys-addr=<phys>\n"
1908	" Shows the TB for the specified guest physical address.\n"
1909	" -t<id>, --tb=<id>, --tb-id=<id>, TD#<id>\n"
1910	" Show the TB specified by the identifier/number (from tbtop).\n"
1911	" -f<flags>,--flags=<flags>\n"
1912	" The TB flags value (hex) to use when looking up the TB.\n"
1913	"\n"
1914	"The default is to use CS:RIP and derive flags from the CPU mode.\n");
1915	return;
1916
1917	default:
1918	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1919	return;
1920	}
1921	}
1922
1923	/* Currently, only do work on the same EMT. */
1924	if (pVCpu != pVCpuThis)
1925	{
1926	pHlp->pfnPrintf(pHlp, "TODO: Cross EMT calling not supported yet: targeting %u, caller on %d\n",
1927	pVCpu->idCpu, pVCpuThis ? (int)pVCpuThis->idCpu : -1);
1928	return;
1929	}
1930
1931	/*
1932	* Defaults.
1933	*/
1934	if (GCPhysPc == NIL_RTGCPHYS && idTb == UINT32_MAX)
1935	{
1936	if (GCVirt == NIL_RTGCPTR)
1937	GCVirt = CPUMGetGuestFlatPC(pVCpu);
1938	rc = PGMPhysGCPtr2GCPhys(pVCpu, GCVirt, &GCPhysPc);
1939	if (RT_FAILURE(rc))
1940	{
1941	pHlp->pfnPrintf(pHlp, "Failed to convert %%%RGv to an guest physical address: %Rrc\n", GCVirt, rc);
1942	return;
1943	}
1944	}
1945	if (fFlags == UINT32_MAX && idTb == UINT32_MAX)
1946	{
1947	/* Note! This is duplicating code in IEMAllThrdRecompiler. */
1948	fFlags = iemCalcExecFlags(pVCpu);
1949	if (pVM->cCpus == 1)
1950	fFlags \|= IEM_F_X86_DISREGARD_LOCK;
1951	if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
1952	fFlags \|= IEMTB_F_INHIBIT_SHADOW;
1953	if (CPUMAreInterruptsInhibitedByNmiEx(&pVCpu->cpum.GstCtx))
1954	fFlags \|= IEMTB_F_INHIBIT_NMI;
1955	if ((IEM_F_MODE_CPUMODE_MASK & fFlags) != IEMMODE_64BIT)
1956	{
1957	int64_t const offFromLim = (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.eip;
1958	if (offFromLim < X86_PAGE_SIZE + 16 - (int32_t)(pVCpu->cpum.GstCtx.cs.u64Base & GUEST_PAGE_OFFSET_MASK))
1959	fFlags \|= IEMTB_F_CS_LIM_CHECKS;
1960	}
1961	}
1962
1963	PCIEMTB pTb;
1964	if (idTb == UINT32_MAX)
1965	{
1966	/*
1967	* Do the lookup...
1968	*
1969	* Note! This is also duplicating code in IEMAllThrdRecompiler. We don't
1970	* have much choice since we don't want to increase use counters and
1971	* trigger native recompilation.
1972	*/
1973	fFlags &= IEMTB_F_KEY_MASK;
1974	IEMTBCACHE const * const pTbCache = pVCpu->iem.s.pTbCacheR3;
1975	uint32_t const idxHash = IEMTBCACHE_HASH(pTbCache, fFlags, GCPhysPc);
1976	pTb = IEMTBCACHE_PTR_GET_TB(pTbCache->apHash[idxHash]);
1977	while (pTb)
1978	{
1979	if (pTb->GCPhysPc == GCPhysPc)
1980	{
1981	if ((pTb->fFlags & IEMTB_F_KEY_MASK) == fFlags)
1982	{
1983	/// @todo if (pTb->x86.fAttr == (uint16_t)pVCpu->cpum.GstCtx.cs.Attr.u)
1984	break;
1985	}
1986	}
1987	pTb = pTb->pNext;
1988	}
1989	if (!pTb)
1990	pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x - no TB found on #%u\n", GCPhysPc, fFlags, pVCpu->idCpu);
1991	}
1992	else
1993	{
1994	/*
1995	* Use the TB ID for indexing.
1996	*/
1997	pTb = NULL;
1998	PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
1999	if (pTbAllocator)
2000	{
2001	size_t const idxTbChunk = idTb / pTbAllocator->cTbsPerChunk;
2002	size_t const idxTbInChunk = idTb % pTbAllocator->cTbsPerChunk;
2003	if (idxTbChunk < pTbAllocator->cAllocatedChunks)
2004	pTb = &pTbAllocator->aChunks[idxTbChunk].paTbs[idxTbInChunk];
2005	else
2006	pHlp->pfnPrintf(pHlp, "Invalid TB ID: %u (%#x)\n", idTb, idTb);
2007	}
2008	}
2009
2010	if (pTb)
2011	{
2012	/*
2013	* Disassemble according to type.
2014	*/
2015	size_t const idxTbChunk = pTb->idxAllocChunk;
2016	size_t const idxTbNo = (pTb - &pVCpu->iem.s.pTbAllocatorR3->aChunks[idxTbChunk].paTbs[0])
2017	+ idxTbChunk * pVCpu->iem.s.pTbAllocatorR3->cTbsPerChunk;
2018	switch (pTb->fFlags & IEMTB_F_TYPE_MASK)
2019	{
2020	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
2021	case IEMTB_F_TYPE_NATIVE:
2022	pHlp->pfnPrintf(pHlp, "PC=%RGp (%%%RGv) fFlags=%#x on #%u: TB#%#zx/%p - native\n",
2023	GCPhysPc, iemR3GetTbFlatPc(pTb), fFlags, pVCpu->idCpu, idxTbNo, pTb);
2024	iemNativeDisassembleTb(pVCpu, pTb, pHlp);
2025	break;
2026	# endif
2027
2028	case IEMTB_F_TYPE_THREADED:
2029	pHlp->pfnPrintf(pHlp, "PC=%RGp (%%%RGv) fFlags=%#x on #%u: TB#%#zx/%p - threaded\n",
2030	GCPhysPc, pTb->FlatPc, fFlags, pVCpu->idCpu, idxTbNo, pTb);
2031	iemThreadedDisassembleTb(pTb, pHlp);
2032	break;
2033
2034	default:
2035	pHlp->pfnPrintf(pHlp, "PC=%RGp (%%%RGv) fFlags=%#x on #%u: TB#%#zx/%p - ??? %#x\n",
2036	GCPhysPc, pTb->FlatPc, fFlags, pVCpu->idCpu, idxTbNo, pTb, pTb->fFlags);
2037	break;
2038	}
2039	}
2040	}
2041
2042
2043	/**
2044	* @callback_method_impl{FNDBGFINFOARGVINT, tbtop}
2045	*/
2046	static DECLCALLBACK(void) iemR3InfoTbTop(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
2047	{
2048	/*
2049	* Parse arguments.
2050	*/
2051	static RTGETOPTDEF const s_aOptions[] =
2052	{
2053	{ "--cpu", 'c', RTGETOPT_REQ_UINT32 },
2054	{ "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
2055	{ "--dis", 'd', RTGETOPT_REQ_NOTHING },
2056	{ "--disas", 'd', RTGETOPT_REQ_NOTHING },
2057	{ "--disasm", 'd', RTGETOPT_REQ_NOTHING },
2058	{ "--disassemble", 'd', RTGETOPT_REQ_NOTHING },
2059	{ "--no-dis", 'D', RTGETOPT_REQ_NOTHING },
2060	{ "--no-disas", 'D', RTGETOPT_REQ_NOTHING },
2061	{ "--no-disasm", 'D', RTGETOPT_REQ_NOTHING },
2062	{ "--no-disassemble", 'D', RTGETOPT_REQ_NOTHING },
2063	{ "--most-freq", 'f', RTGETOPT_REQ_NOTHING },
2064	{ "--most-frequent", 'f', RTGETOPT_REQ_NOTHING },
2065	{ "--most-frequently", 'f', RTGETOPT_REQ_NOTHING },
2066	{ "--most-frequently-used", 'f', RTGETOPT_REQ_NOTHING },
2067	{ "--most-recent", 'r', RTGETOPT_REQ_NOTHING },
2068	{ "--most-recently", 'r', RTGETOPT_REQ_NOTHING },
2069	{ "--most-recently-used", 'r', RTGETOPT_REQ_NOTHING },
2070	{ "--count", 'n', RTGETOPT_REQ_UINT32 },
2071	};
2072
2073	RTGETOPTSTATE State;
2074	int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /iFirst/, 0 /fFlags/);
2075	AssertRCReturnVoid(rc);
2076
2077	PVMCPU const pVCpuThis = VMMGetCpu(pVM);
2078	PVMCPU pVCpu = pVCpuThis ? pVCpuThis : VMMGetCpuById(pVM, 0);
2079	enum { kTbTop_MostFrequentlyUsed, kTbTop_MostRececentlyUsed }
2080	enmTop = kTbTop_MostFrequentlyUsed;
2081	bool fDisassemble = false;
2082	uint32_t const cTopDefault = 64;
2083	uint32_t const cTopMin = 1;
2084	uint32_t const cTopMax = 1024;
2085	uint32_t cTop = cTopDefault;
2086
2087	RTGETOPTUNION ValueUnion;
2088	while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
2089	{
2090	switch (rc)
2091	{
2092	case 'c':
2093	if (ValueUnion.u32 >= pVM->cCpus)
2094	pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
2095	else if (!pVCpu \|\| pVCpu->idCpu != ValueUnion.u32)
2096	pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
2097	break;
2098
2099	case 'd':
2100	fDisassemble = true;
2101	break;
2102
2103	case 'D':
2104	fDisassemble = true;
2105	break;
2106
2107	case 'f':
2108	enmTop = kTbTop_MostFrequentlyUsed;
2109	break;
2110
2111	case 'r':
2112	enmTop = kTbTop_MostRececentlyUsed;
2113	break;
2114
2115	case VINF_GETOPT_NOT_OPTION:
2116	rc = RTStrToUInt32Full(ValueUnion.psz, 0, &cTop);
2117	if (RT_FAILURE(rc))
2118	{
2119	pHlp->pfnPrintf(pHlp, "error: failed to convert '%s' to a number: %Rrc\n", ValueUnion.psz, rc);
2120	return;
2121	}
2122	ValueUnion.u32 = cTop;
2123	RT_FALL_THROUGH();
2124	case 'n':
2125	if (!ValueUnion.u32)
2126	cTop = cTopDefault;
2127	else
2128	{
2129	cTop = RT_MAX(RT_MIN(ValueUnion.u32, cTopMax), cTopMin);
2130	if (cTop != ValueUnion.u32)
2131	pHlp->pfnPrintf(pHlp, "warning: adjusted %u to %u (valid range: [%u..%u], 0 for default (%d))",
2132	ValueUnion.u32, cTop, cTopMin, cTopMax, cTopDefault);
2133	}
2134	break;
2135
2136	case 'h':
2137	pHlp->pfnPrintf(pHlp,
2138	"Usage: info tbtop [options]\n"
2139	"\n"
2140	"Options:\n"
2141	" -c<n>, --cpu=<n>, --vcpu=<n>\n"
2142	" Selects the CPU which TBs we're looking at. Default: Caller / 0\n"
2143	" -d, --dis[as[m]], --disassemble\n"
2144	" Show full TB disassembly.\n"
2145	" -D, --no-dis[as[m]], --no-disassemble\n"
2146	" Do not show TB diassembly. The default.\n"
2147	" -f, --most-freq[ent[ly[-used]]]\n"
2148	" Shows the most frequently used TBs (IEMTB::cUsed). The default.\n"
2149	" -r, --most-recent[ly[-used]]\n"
2150	" Shows the most recently used TBs (IEMTB::msLastUsed).\n"
2151	" -n<num>, --count=<num>\n"
2152	" The number of TBs to display. Default: %u\n"
2153	" This is also what non-option arguments will be taken as.\n"
2154	, cTopDefault);
2155	return;
2156
2157	default:
2158	pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
2159	return;
2160	}
2161	}
2162
2163	/* Currently, only do work on the same EMT. */
2164	if (pVCpu != pVCpuThis)
2165	{
2166	pHlp->pfnPrintf(pHlp, "TODO: Cross EMT calling not supported yet: targeting %u, caller on %d\n",
2167	pVCpu->idCpu, pVCpuThis ? (int)pVCpuThis->idCpu : -1);
2168	return;
2169	}
2170
2171	/*
2172	* Collect the data by scanning the TB allocation map.
2173	*/
2174	struct IEMTBTOPENTRY
2175	{
2176	/** Pointer to the translation block. */
2177	PCIEMTB pTb;
2178	/** The sorting key. */
2179	uint64_t uSortKey;
2180	} aTop[cTopMax] = { { NULL, 0 }, };
2181	uint32_t cValid = 0;
2182	PIEMTBALLOCATOR pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
2183	if (pTbAllocator)
2184	{
2185	uint32_t const cTbsPerChunk = pTbAllocator->cTbsPerChunk;
2186	for (uint32_t iChunk = 0; iChunk < pTbAllocator->cAllocatedChunks; iChunk++)
2187	{
2188	for (uint32_t iTb = 0; iTb < cTbsPerChunk; iTb++)
2189	{
2190	PCIEMTB const pTb = &pTbAllocator->aChunks[iChunk].paTbs[iTb];
2191	AssertContinue(pTb);
2192	if (pTb->fFlags & IEMTB_F_TYPE_MASK)
2193	{
2194	/* Extract and compose the sort key. */
2195	uint64_t const uSortKey = enmTop == kTbTop_MostFrequentlyUsed
2196	? RT_MAKE_U64(pTb->msLastUsed, pTb->cUsed)
2197	: RT_MAKE_U64(pTb->cUsed, pTb->msLastUsed);
2198
2199	/*
2200	* Discard the key if it's smaller than the smallest in the table when it is full.
2201	*/
2202	if ( cValid >= cTop
2203	&& uSortKey <= aTop[cTop - 1].uSortKey)
2204	{ /* discard it */ }
2205	else
2206	{
2207	/*
2208	* Do binary search to find the insert location
2209	*/
2210	uint32_t idx;
2211	if (cValid > 0)
2212	{
2213	uint32_t idxEnd = cValid;
2214	uint32_t idxStart = 0;
2215	idx = cValid / 2;
2216	for (;;)
2217	{
2218	if (uSortKey > aTop[idx].uSortKey)
2219	{
2220	if (idx > idxStart)
2221	idxEnd = idx;
2222	else
2223	break;
2224	}
2225	else if (uSortKey < aTop[idx].uSortKey)
2226	{
2227	idx += 1;
2228	if (idx < idxEnd)
2229	idxStart = idx;
2230	else
2231	break;
2232	}
2233	else
2234	{
2235	do
2236	idx++;
2237	while (idx < cValid && uSortKey == aTop[idx].uSortKey);
2238	break;
2239	}
2240	idx = idxStart + (idxEnd - idxStart) / 2;
2241	}
2242	AssertContinue(idx < RT_ELEMENTS(aTop));
2243
2244	/*
2245	* Shift entries as needed.
2246	*/
2247	if (cValid >= cTop)
2248	{
2249	if (idx != cTop - 1U)
2250	memmove(&aTop[idx + 1], &aTop[idx], (cTop - idx - 1) * sizeof(aTop[0]));
2251	}
2252	else
2253	{
2254	if (idx != cValid)
2255	memmove(&aTop[idx + 1], &aTop[idx], (cValid - idx) * sizeof(aTop[0]));
2256	cValid++;
2257	}
2258	}
2259	else
2260	{
2261	/* Special case: The first insertion. */
2262	cValid = 1;
2263	idx = 0;
2264	}
2265
2266	/*
2267	* Fill in the new entry.
2268	*/
2269	aTop[idx].uSortKey = uSortKey;
2270	aTop[idx].pTb = pTb;
2271	}
2272	}
2273	}
2274	}
2275	}
2276
2277	/*
2278	* Display the result.
2279	*/
2280	if (cTop > cValid)
2281	cTop = cValid;
2282	pHlp->pfnPrintf(pHlp, "Displaying the top %u TBs for CPU #%u ordered by %s:\n",
2283	cTop, pVCpu->idCpu, enmTop == kTbTop_MostFrequentlyUsed ? "cUsed" : "msLastUsed");
2284	if (fDisassemble)
2285	pHlp->pfnPrintf(pHlp, "================================================================================\n");
2286
2287	for (uint32_t idx = 0; idx < cTop; idx++)
2288	{
2289	if (fDisassemble && idx)
2290	pHlp->pfnPrintf(pHlp, "\n------------------------------- %u -------------------------------\n", idx);
2291
2292	PCIEMTB const pTb = aTop[idx].pTb;
2293	size_t const idxTbChunk = pTb->idxAllocChunk;
2294	Assert(idxTbChunk < pTbAllocator->cAllocatedChunks);
2295	size_t const idxTbNo = (pTb - &pTbAllocator->aChunks[idxTbChunk].paTbs[0])
2296	+ idxTbChunk * pTbAllocator->cTbsPerChunk;
2297	switch (pTb->fFlags & IEMTB_F_TYPE_MASK)
2298	{
2299	# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
2300	case IEMTB_F_TYPE_NATIVE:
2301	pHlp->pfnPrintf(pHlp, "TB#%#zx: PC=%RGp (%%%RGv) cUsed=%u msLastUsed=%u fFlags=%#010x - native\n",
2302	idxTbNo, pTb->GCPhysPc, iemR3GetTbFlatPc(pTb), pTb->cUsed, pTb->msLastUsed, pTb->fFlags);
2303	if (fDisassemble)
2304	iemNativeDisassembleTb(pVCpu, pTb, pHlp);
2305	break;
2306	# endif
2307
2308	case IEMTB_F_TYPE_THREADED:
2309	pHlp->pfnPrintf(pHlp, "TB#%#zx: PC=%RGp (%%%RGv) cUsed=%u msLastUsed=%u fFlags=%#010x - threaded\n",
2310	idxTbNo, pTb->GCPhysPc, pTb->FlatPc, pTb->cUsed, pTb->msLastUsed, pTb->fFlags);
2311	if (fDisassemble)
2312	iemThreadedDisassembleTb(pTb, pHlp);
2313	break;
2314
2315	default:
2316	pHlp->pfnPrintf(pHlp, "TB#%#zx: PC=%RGp (%%%RGv) cUsed=%u msLastUsed=%u fFlags=%#010x - ???\n",
2317	idxTbNo, pTb->GCPhysPc, pTb->FlatPc, pTb->cUsed, pTb->msLastUsed, pTb->fFlags);
2318	break;
2319	}
2320	}
2321	}
2322
2323	#endif /* VBOX_WITH_IEM_RECOMPILER && !VBOX_VMM_TARGET_ARMV8 */
2324
2325
2326	#ifdef VBOX_WITH_DEBUGGER
2327
2328	/** @callback_method_impl{FNDBGCCMD,
2329	* Implements the '.alliem' command. }
2330	*/
2331	static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2332	{
2333	VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
2334	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
2335	if (pVCpu)
2336	{
2337	VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAllGlobal, 1, pVCpu);
2338	return VINF_SUCCESS;
2339	}
2340	RT_NOREF(paArgs, cArgs);
2341	return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
2342	}
2343
2344
2345	/**
2346	* Called by IEMR3Init to register debugger commands.
2347	*/
2348	static void iemR3RegisterDebuggerCommands(void)
2349	{
2350	/*
2351	* Register debugger commands.
2352	*/
2353	static DBGCCMD const s_aCmds[] =
2354	{
2355	{
2356	/* .pszCmd = */ "iemflushtlb",
2357	/* .cArgsMin = */ 0,
2358	/* .cArgsMax = */ 0,
2359	/* .paArgDescs = */ NULL,
2360	/* .cArgDescs = */ 0,
2361	/* .fFlags = */ 0,
2362	/* .pfnHandler = */ iemR3DbgFlushTlbs,
2363	/* .pszSyntax = */ "",
2364	/* .pszDescription = */ "Flushed the code and data TLBs"
2365	},
2366	};
2367
2368	int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
2369	AssertLogRelRC(rc);
2370	}
2371
2372	#endif /* VBOX_WITH_DEBUGGER */
2373

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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 106090

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