VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 106297

Last change on this file since 106297 was 106297, checked in by vboxsync, 7 weeks ago

VMM/IEM: Attempts at optimizing iemExecMemAllocatorAllocInChunkInt and iemExecMemAllocatorReadyForUse. bugref:10720

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1/* $Id: IEMR3.cpp 106297 2024-10-12 01:07:27Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_EM
33#define VMCPU_INCL_CPUM_GST_CTX
34#include <VBox/vmm/iem.h>
35#include <VBox/vmm/cpum.h>
36#include <VBox/vmm/dbgf.h>
37#include <VBox/vmm/mm.h>
38#include <VBox/vmm/ssm.h>
39#if defined(VBOX_VMM_TARGET_ARMV8)
40# include "IEMInternal-armv8.h"
41#else
42# include "IEMInternal.h"
43#endif
44#include <VBox/vmm/vm.h>
45#include <VBox/vmm/vmapi.h>
46#include <VBox/err.h>
47#ifdef VBOX_WITH_DEBUGGER
48# include <VBox/dbg.h>
49#endif
50
51#include <iprt/assert.h>
52#include <iprt/getopt.h>
53#ifdef IEM_WITH_TLB_TRACE
54# include <iprt/mem.h>
55#endif
56#include <iprt/string.h>
57
58#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
59# include "IEMN8veRecompiler.h"
60# include "IEMThreadedFunctions.h"
61# include "IEMInline.h"
62#endif
63
64
65/*********************************************************************************************************************************
66* Internal Functions *
67*********************************************************************************************************************************/
68static FNDBGFINFOARGVINT iemR3InfoITlb;
69static FNDBGFINFOARGVINT iemR3InfoDTlb;
70#ifdef IEM_WITH_TLB_TRACE
71static FNDBGFINFOARGVINT iemR3InfoTlbTrace;
72#endif
73#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
74static FNDBGFINFOARGVINT iemR3InfoTb;
75static FNDBGFINFOARGVINT iemR3InfoTbTop;
76#endif
77#ifdef VBOX_WITH_DEBUGGER
78static void iemR3RegisterDebuggerCommands(void);
79#endif
80
81
82#if !defined(VBOX_VMM_TARGET_ARMV8)
83static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
84{
85 switch (enmTargetCpu)
86 {
87#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
88 CASE_RET_STR(IEMTARGETCPU_8086);
89 CASE_RET_STR(IEMTARGETCPU_V20);
90 CASE_RET_STR(IEMTARGETCPU_186);
91 CASE_RET_STR(IEMTARGETCPU_286);
92 CASE_RET_STR(IEMTARGETCPU_386);
93 CASE_RET_STR(IEMTARGETCPU_486);
94 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
95 CASE_RET_STR(IEMTARGETCPU_PPRO);
96 CASE_RET_STR(IEMTARGETCPU_CURRENT);
97#undef CASE_RET_STR
98 default: return "Unknown";
99 }
100}
101#endif
102
103
104/**
105 * Initializes the interpreted execution manager.
106 *
107 * This must be called after CPUM as we're quering information from CPUM about
108 * the guest and host CPUs.
109 *
110 * @returns VBox status code.
111 * @param pVM The cross context VM structure.
112 */
113VMMR3DECL(int) IEMR3Init(PVM pVM)
114{
115 /*
116 * Read configuration.
117 */
118#if (!defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)) || defined(VBOX_WITH_IEM_RECOMPILER)
119 PCFGMNODE const pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
120 int rc;
121#endif
122
123#if !defined(VBOX_VMM_TARGET_ARMV8) && !defined(VBOX_WITHOUT_CPUID_HOST_CALL)
124 /** @cfgm{/IEM/CpuIdHostCall, boolean, false}
125 * Controls whether the custom VBox specific CPUID host call interface is
126 * enabled or not. */
127# ifdef DEBUG_bird
128 rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
129# else
130 rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
131# endif
132 AssertLogRelRCReturn(rc, rc);
133#endif
134
135#ifdef VBOX_WITH_IEM_RECOMPILER
136 /** @cfgm{/IEM/MaxTbCount, uint32_t, 524288}
137 * Max number of TBs per EMT. */
138 uint32_t cMaxTbs = 0;
139 rc = CFGMR3QueryU32Def(pIem, "MaxTbCount", &cMaxTbs, _512K);
140 AssertLogRelRCReturn(rc, rc);
141 if (cMaxTbs < _16K || cMaxTbs > _8M)
142 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
143 "MaxTbCount value %u (%#x) is out of range (min %u, max %u)", cMaxTbs, cMaxTbs, _16K, _8M);
144
145 /** @cfgm{/IEM/InitialTbCount, uint32_t, 32678}
146 * Initial (minimum) number of TBs per EMT in ring-3. */
147 uint32_t cInitialTbs = 0;
148 rc = CFGMR3QueryU32Def(pIem, "InitialTbCount", &cInitialTbs, RT_MIN(cMaxTbs, _32K));
149 AssertLogRelRCReturn(rc, rc);
150 if (cInitialTbs < _16K || cInitialTbs > _8M)
151 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
152 "InitialTbCount value %u (%#x) is out of range (min %u, max %u)", cInitialTbs, cInitialTbs, _16K, _8M);
153
154 /* Check that the two values makes sense together. Expect user/api to do
155 the right thing or get lost. */
156 if (cInitialTbs > cMaxTbs)
157 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
158 "InitialTbCount value %u (%#x) is higher than the MaxTbCount value %u (%#x)",
159 cInitialTbs, cInitialTbs, cMaxTbs, cMaxTbs);
160
161 /** @cfgm{/IEM/MaxExecMem, uint64_t, 512 MiB}
162 * Max executable memory for recompiled code per EMT. */
163 uint64_t cbMaxExec = 0;
164 rc = CFGMR3QueryU64Def(pIem, "MaxExecMem", &cbMaxExec, _512M);
165 AssertLogRelRCReturn(rc, rc);
166 if (cbMaxExec < _1M || cbMaxExec > 16*_1G64)
167 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
168 "MaxExecMem value %'RU64 (%#RX64) is out of range (min %'RU64, max %'RU64)",
169 cbMaxExec, cbMaxExec, (uint64_t)_1M, 16*_1G64);
170
171 /** @cfgm{/IEM/ExecChunkSize, uint32_t, 0 (auto)}
172 * The executable memory allocator chunk size. */
173 uint32_t cbChunkExec = 0;
174 rc = CFGMR3QueryU32Def(pIem, "ExecChunkSize", &cbChunkExec, 0);
175 AssertLogRelRCReturn(rc, rc);
176 if (cbChunkExec != 0 && cbChunkExec != UINT32_MAX && (cbChunkExec < _1M || cbChunkExec > _256M))
177 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
178 "ExecChunkSize value %'RU32 (%#RX32) is out of range (min %'RU32, max %'RU32)",
179 cbChunkExec, cbChunkExec, _1M, _256M);
180
181 /** @cfgm{/IEM/InitialExecMemSize, uint64_t, 1}
182 * The initial executable memory allocator size (per EMT). The value is
183 * rounded up to the nearest chunk size, so 1 byte means one chunk. */
184 uint64_t cbInitialExec = 0;
185 rc = CFGMR3QueryU64Def(pIem, "InitialExecMemSize", &cbInitialExec, 0);
186 AssertLogRelRCReturn(rc, rc);
187 if (cbInitialExec > cbMaxExec)
188 return VMSetError(pVM, VERR_OUT_OF_RANGE, RT_SRC_POS,
189 "InitialExecMemSize value %'RU64 (%#RX64) is out of range (max %'RU64)",
190 cbInitialExec, cbInitialExec, cbMaxExec);
191
192 /** @cfgm{/IEM/NativeRecompileAtUsedCount, uint32_t, 16}
193 * The translation block use count value to do native recompilation at.
194 * Set to zero to disable native recompilation. */
195 uint32_t uTbNativeRecompileAtUsedCount = 16;
196 rc = CFGMR3QueryU32Def(pIem, "NativeRecompileAtUsedCount", &uTbNativeRecompileAtUsedCount, 16);
197 AssertLogRelRCReturn(rc, rc);
198
199 /** @cfgm{/IEM/HostICacheInvalidationViaHostAPI, bool, false}
200 * Whether to use any available host OS API for flushing the instruction cache
201 * after completing an translation block. */
202 bool fFlag = false;
203 rc = CFGMR3QueryBoolDef(pIem, "HostICacheInvalidationViaHostAPI", &fFlag, false);
204 AssertLogRelRCReturn(rc, rc);
205 uint8_t fHostICacheInvalidation = fFlag ? IEMNATIVE_ICACHE_F_USE_HOST_API : 0;
206
207 /** @cfgm{/IEM/HostICacheInvalidationEndWithIsb, bool, false}
208 * Whether to include an ISB in the instruction cache invalidation sequence
209 * after completing an translation block. */
210 fFlag = false;
211 rc = CFGMR3QueryBoolDef(pIem, "HostICacheInvalidationEndWithIsb", &fFlag, false);
212 AssertLogRelRCReturn(rc, rc);
213 if (fFlag)
214 fHostICacheInvalidation |= IEMNATIVE_ICACHE_F_END_WITH_ISH;
215
216#endif /* VBOX_WITH_IEM_RECOMPILER*/
217
218 /*
219 * Initialize per-CPU data and register statistics.
220 */
221#if 1
222 uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
223 uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
224#else
225 uint64_t const uInitialTlbRevision = UINT64_C(0) + (IEMTLB_REVISION_INCR * 4U);
226 uint64_t const uInitialTlbPhysRev = UINT64_C(0) + (IEMTLB_PHYS_REV_INCR * 4U);
227#endif
228
229 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
230 {
231 PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
232 AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
233
234 pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
235#ifndef VBOX_VMM_TARGET_ARMV8
236 pVCpu->iem.s.CodeTlb.uTlbRevisionGlobal = pVCpu->iem.s.DataTlb.uTlbRevisionGlobal = uInitialTlbRevision;
237#endif
238 pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
239#ifndef VBOX_VMM_TARGET_ARMV8
240 pVCpu->iem.s.CodeTlb.NonGlobalLargePageRange.uFirstTag = UINT64_MAX;
241 pVCpu->iem.s.CodeTlb.GlobalLargePageRange.uFirstTag = UINT64_MAX;
242 pVCpu->iem.s.DataTlb.NonGlobalLargePageRange.uFirstTag = UINT64_MAX;
243 pVCpu->iem.s.DataTlb.GlobalLargePageRange.uFirstTag = UINT64_MAX;
244#endif
245
246#ifndef VBOX_VMM_TARGET_ARMV8
247 pVCpu->iem.s.cTbsTillNextTimerPoll = 128;
248 pVCpu->iem.s.cTbsTillNextTimerPollPrev = 128;
249#endif
250
251 /*
252 * Host and guest CPU information.
253 */
254 if (idCpu == 0)
255 {
256 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
257 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
258#if !defined(VBOX_VMM_TARGET_ARMV8)
259 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
260 || pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /*??*/
261 ? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
262# if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
263 if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
264 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
265 else
266# endif
267 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
268#else
269 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
270 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
271#endif
272
273#if !defined(VBOX_VMM_TARGET_ARMV8) && (IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC)
274 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
275 {
276 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
277 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
278 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
279 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
280 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
281 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
282 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
283 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
284 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
285 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
286 }
287 LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
288 iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
289 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
290#else
291 LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
292 CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
293 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
294#endif
295 }
296 else
297 {
298 pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
299 pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
300 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
301 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
302#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
303 pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
304#endif
305 }
306
307 /*
308 * Mark all buffers free.
309 */
310 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
311 while (iMemMap-- > 0)
312 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
313
314#ifdef VBOX_WITH_IEM_RECOMPILER
315 /*
316 * Recompiler state and configuration distribution.
317 */
318 pVCpu->iem.s.uRegFpCtrl = IEMNATIVE_SIMD_FP_CTRL_REG_NOT_MODIFIED;
319 pVCpu->iem.s.uTbNativeRecompileAtUsedCount = uTbNativeRecompileAtUsedCount;
320 pVCpu->iem.s.fHostICacheInvalidation = fHostICacheInvalidation;
321#endif
322
323#ifdef IEM_WITH_TLB_TRACE
324 /*
325 * Allocate trace buffer.
326 */
327 pVCpu->iem.s.idxTlbTraceEntry = 0;
328 pVCpu->iem.s.cTlbTraceEntriesShift = 16;
329 pVCpu->iem.s.paTlbTraceEntries = (PIEMTLBTRACEENTRY)RTMemPageAlloc( RT_BIT_Z(pVCpu->iem.s.cTlbTraceEntriesShift)
330 * sizeof(*pVCpu->iem.s.paTlbTraceEntries));
331 AssertLogRelReturn(pVCpu->iem.s.paTlbTraceEntries, VERR_NO_PAGE_MEMORY);
332#endif
333 }
334
335
336#ifdef VBOX_WITH_IEM_RECOMPILER
337 /*
338 * Initialize the TB allocator and cache (/ hash table).
339 *
340 * This is done by each EMT to try get more optimal thread/numa locality of
341 * the allocations.
342 */
343 rc = VMR3ReqCallWait(pVM, VMCPUID_ALL, (PFNRT)iemTbInit, 6,
344 pVM, cInitialTbs, cMaxTbs, cbInitialExec, cbMaxExec, cbChunkExec);
345 AssertLogRelRCReturn(rc, rc);
346#endif
347
348 /*
349 * Register statistics.
350 */
351 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
352 {
353#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) /* quick fix for stupid structure duplication non-sense */
354 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
355 char szPat[128];
356 RT_NOREF_PV(szPat); /* lazy bird */
357 char szVal[128];
358 RT_NOREF_PV(szVal); /* lazy bird */
359
360 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
361 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
362 STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
363 "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
364 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
365 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
366 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
367 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
368 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
369 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
370 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
371 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
372 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
373 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
374 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
375 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
376 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
377 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
378 STAMR3RegisterF(pVM, &pVCpu->iem.s.cMisalignedAtomics, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
379 "Number of misaligned (for the host) atomic instructions", "/IEM/CPU%u/cMisalignedAtomics", idCpu);
380
381 /* Code TLB: */
382 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
383 "Code TLB non-global revision", "/IEM/CPU%u/Tlb/Code/RevisionNonGlobal", idCpu);
384 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevisionGlobal, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
385 "Code TLB global revision", "/IEM/CPU%u/Tlb/Code/RevisionGlobal", idCpu);
386 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
387 "Code TLB non-global flushes", "/IEM/CPU%u/Tlb/Code/RevisionNonGlobalFlushes", idCpu);
388 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlsGlobalFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
389 "Code TLB global flushes", "/IEM/CPU%u/Tlb/Code/RevisionGlobalFlushes", idCpu);
390 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
391 "Code TLB revision rollovers", "/IEM/CPU%u/Tlb/Code/RevisionRollovers", idCpu);
392
393 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
394 "Code TLB physical revision", "/IEM/CPU%u/Tlb/Code/PhysicalRevision", idCpu);
395 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
396 "Code TLB revision flushes", "/IEM/CPU%u/Tlb/Code/PhysicalRevisionFlushes", idCpu);
397 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
398 "Code TLB revision rollovers", "/IEM/CPU%u/Tlb/Code/PhysicalRevisionRollovers", idCpu);
399
400 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
401 "Code TLB global large page loads since flush", "/IEM/CPU%u/Tlb/Code/LargePageGlobalCurLoads", idCpu);
402 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.GlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
403 "Code TLB global large page range: lowest tag", "/IEM/CPU%u/Tlb/Code/LargePageGlobalFirstTag", idCpu);
404 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.GlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
405 "Code TLB global large page range: last tag", "/IEM/CPU%u/Tlb/Code/LargePageGlobalLastTag", idCpu);
406
407 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNonGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
408 "Code TLB non-global large page loads since flush", "/IEM/CPU%u/Tlb/Code/LargePageNonGlobalCurLoads", idCpu);
409 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.NonGlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
410 "Code TLB non-global large page range: lowest tag", "/IEM/CPU%u/Tlb/Code/LargePageNonGlobalFirstTag", idCpu);
411 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.NonGlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
412 "Code TLB non-global large page range: last tag", "/IEM/CPU%u/Tlb/Code/LargePageNonGlobalLastTag", idCpu);
413
414 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbInvlPg, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
415 "Code TLB page invalidation requests", "/IEM/CPU%u/Tlb/Code/InvlPg", idCpu);
416 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbInvlPgLargeGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
417 "Code TLB page invlpg scanning for global large pages", "/IEM/CPU%u/Tlb/Code/InvlPg/LargeGlobal", idCpu);
418 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbInvlPgLargeNonGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
419 "Code TLB page invlpg scanning for non-global large pages", "/IEM/CPU%u/Tlb/Code/InvlPg/LargeNonGlobal", idCpu);
420
421 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
422 "Code TLB misses", "/IEM/CPU%u/Tlb/Code/Misses", idCpu);
423 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
424 "Code TLB global loads", "/IEM/CPU%u/Tlb/Code/Misses/GlobalLoads", idCpu);
425 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowCodeReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
426 "Code TLB slow read path", "/IEM/CPU%u/Tlb/Code/SlowReads", idCpu);
427# ifdef IEM_WITH_TLB_STATISTICS
428 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbCoreHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
429 "Code TLB hits (non-native)", "/IEM/CPU%u/Tlb/Code/Hits/Other", idCpu);
430# if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
431 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
432 "Code TLB native hits on new page", "/IEM/CPU%u/Tlb/Code/Hits/New-Page", idCpu);
433 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbHitsForNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
434 "Code TLB native hits on new page /w offset", "/IEM/CPU%u/Tlb/Code/Hits/New-Page-With-Offset", idCpu);
435# endif
436
437 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Code/Hits/*", idCpu);
438 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Code TLB hits",
439 "/IEM/CPU%u/Tlb/Code/Hits", idCpu);
440
441 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Code/Hits|/IEM/CPU%u/Tlb/Code/Misses", idCpu, idCpu);
442 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Code TLB lookups (sum of hits and misses)",
443 "/IEM/CPU%u/Tlb/Code/AllLookups", idCpu);
444
445 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Code/Misses", idCpu);
446 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Code/Hits", idCpu);
447 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
448 "Code TLB actual miss rate", "/IEM/CPU%u/Tlb/Code/RateMisses", idCpu);
449
450# if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER)
451 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissTag, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
452 "Code TLB misses in native code: Tag mismatch [not directly included grand parent sum]",
453 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/Tag", idCpu);
454 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissFlagsAndPhysRev, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
455 "Code TLB misses in native code: Flags or physical revision mistmatch [not directly included grand parent sum]",
456 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/FlagsAndPhysRev", idCpu);
457 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissAlignment, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
458 "Code TLB misses in native code: Alignment [not directly included grand parent sum]",
459 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/Alignment", idCpu);
460 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissCrossPage, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
461 "Code TLB misses in native code: Cross page [not directly included grand parent sum]",
462 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/CrossPage", idCpu);
463 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbNativeMissNonCanonical, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
464 "Code TLB misses in native code: Non-canonical [not directly included grand parent sum]",
465 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown/NonCanonical", idCpu);
466
467 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
468 "Code TLB native misses on new page",
469 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown2/New-Page", idCpu);
470 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCodeTlbMissesNewPageWithOffset, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
471 "Code TLB native misses on new page w/ offset",
472 "/IEM/CPU%u/Tlb/Code/Misses/NativeBreakdown2/New-Page-With-Offset", idCpu);
473# endif
474# endif /* IEM_WITH_TLB_STATISTICS */
475
476 /* Data TLB organized as best we can... */
477 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
478 "Data TLB non-global revision", "/IEM/CPU%u/Tlb/Data/RevisionNonGlobal", idCpu);
479 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevisionGlobal, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
480 "Data TLB global revision", "/IEM/CPU%u/Tlb/Data/RevisionGlobal", idCpu);
481 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
482 "Data TLB non-global flushes", "/IEM/CPU%u/Tlb/Data/RevisionNonGlobalFlushes", idCpu);
483 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlsGlobalFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
484 "Data TLB global flushes", "/IEM/CPU%u/Tlb/Data/RevisionGlobalFlushes", idCpu);
485 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbRevisionRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
486 "Data TLB revision rollovers", "/IEM/CPU%u/Tlb/Data/RevisionRollovers", idCpu);
487
488 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
489 "Data TLB physical revision", "/IEM/CPU%u/Tlb/Data/PhysicalRevision", idCpu);
490 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevFlushes, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
491 "Data TLB revision flushes", "/IEM/CPU%u/Tlb/Data/PhysicalRevisionFlushes", idCpu);
492 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbPhysRevRollovers, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
493 "Data TLB revision rollovers", "/IEM/CPU%u/Tlb/Data/PhysicalRevisionRollovers", idCpu);
494
495 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
496 "Data TLB global large page loads since flush", "/IEM/CPU%u/Tlb/Data/LargePageGlobalCurLoads", idCpu);
497 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.GlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
498 "Data TLB global large page range: lowest tag", "/IEM/CPU%u/Tlb/Data/LargePageGlobalFirstTag", idCpu);
499 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.GlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
500 "Data TLB global large page range: last tag", "/IEM/CPU%u/Tlb/Data/LargePageGlobalLastTag", idCpu);
501
502 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNonGlobalLargePageCurLoads, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
503 "Data TLB non-global large page loads since flush", "/IEM/CPU%u/Tlb/Data/LargePageNonGlobalCurLoads", idCpu);
504 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.NonGlobalLargePageRange.uFirstTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
505 "Data TLB non-global large page range: lowest tag", "/IEM/CPU%u/Tlb/Data/LargePageNonGlobalFirstTag", idCpu);
506 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.NonGlobalLargePageRange.uLastTag, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
507 "Data TLB non-global large page range: last tag", "/IEM/CPU%u/Tlb/Data/LargePageNonGlobalLastTag", idCpu);
508
509 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInvlPg, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
510 "Data TLB page invalidation requests", "/IEM/CPU%u/Tlb/Data/InvlPg", idCpu);
511 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInvlPgLargeGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
512 "Data TLB page invlpg scanning for global large pages", "/IEM/CPU%u/Tlb/Data/InvlPg/LargeGlobal", idCpu);
513 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInvlPgLargeNonGlobal, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
514 "Data TLB page invlpg scanning for non-global large pages", "/IEM/CPU%u/Tlb/Data/InvlPg/LargeNonGlobal", idCpu);
515
516 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
517 "Data TLB core misses (iemMemMap, direct iemMemMapJmp (not safe path))",
518 "/IEM/CPU%u/Tlb/Data/Misses/Core", idCpu);
519 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
520 "Data TLB global loads",
521 "/IEM/CPU%u/Tlb/Data/Misses/Core/GlobalLoads", idCpu);
522 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeReadPath, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
523 "Data TLB safe read path (inline/native misses going to iemMemMapJmp)",
524 "/IEM/CPU%u/Tlb/Data/Misses/Safe/Reads", idCpu);
525 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeWritePath, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
526 "Data TLB safe write path (inline/native misses going to iemMemMapJmp)",
527 "/IEM/CPU%u/Tlb/Data/Misses/Safe/Writes", idCpu);
528 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Misses/*", idCpu);
529 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB misses",
530 "/IEM/CPU%u/Tlb/Data/Misses", idCpu);
531
532 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Misses/Safe/*", idCpu);
533 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB actual safe path calls (read + write)",
534 "/IEM/CPU%u/Tlb/Data/Misses/Safe", idCpu);
535 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
536 "Data TLB hits in iemMemMapJmp - not part of safe-path total",
537 "/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartHits", idCpu);
538 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeMisses, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
539 "Data TLB misses in iemMemMapJmp - not part of safe-path total",
540 "/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartMisses", idCpu);
541 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbSafeGlobalLoads, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
542 "Data TLB global loads",
543 "/IEM/CPU%u/Tlb/Data/Misses/Safe/SubPartMisses/GlobalLoads", idCpu);
544
545# ifdef IEM_WITH_TLB_STATISTICS
546# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
547 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissTag, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
548 "Data TLB misses in native code: Tag mismatch [not directly included grand parent sum]",
549 "/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/Tag", idCpu);
550 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissFlagsAndPhysRev, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
551 "Data TLB misses in native code: Flags or physical revision mistmatch [not directly included grand parent sum]",
552 "/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/FlagsAndPhysRev", idCpu);
553 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissAlignment, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
554 "Data TLB misses in native code: Alignment [not directly included grand parent sum]",
555 "/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/Alignment", idCpu);
556 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissCrossPage, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
557 "Data TLB misses in native code: Cross page [not directly included grand parent sum]",
558 "/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/CrossPage", idCpu);
559 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbNativeMissNonCanonical, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
560 "Data TLB misses in native code: Non-canonical [not directly included grand parent sum]",
561 "/IEM/CPU%u/Tlb/Data/Misses/NativeBreakdown/NonCanonical", idCpu);
562# endif
563# endif
564
565# ifdef IEM_WITH_TLB_STATISTICS
566 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbCoreHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
567 "Data TLB core hits (iemMemMap, direct iemMemMapJmp (not safe path))",
568 "/IEM/CPU%u/Tlb/Data/Hits/Core", idCpu);
569 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbInlineCodeHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
570 "Data TLB hits in IEMAllMemRWTmplInline.cpp.h",
571 "/IEM/CPU%u/Tlb/Data/Hits/Inline", idCpu);
572# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
573 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStack, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
574 "Data TLB native stack access hits",
575 "/IEM/CPU%u/Tlb/Data/Hits/Native/Stack", idCpu);
576 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForFetch, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
577 "Data TLB native data fetch hits",
578 "/IEM/CPU%u/Tlb/Data/Hits/Native/Fetch", idCpu);
579 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForStore, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
580 "Data TLB native data store hits",
581 "/IEM/CPU%u/Tlb/Data/Hits/Native/Store", idCpu);
582 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeTlbHitsForMapped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
583 "Data TLB native mapped data hits",
584 "/IEM/CPU%u/Tlb/Data/Hits/Native/Mapped", idCpu);
585# endif
586 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits/*", idCpu);
587 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB hits",
588 "/IEM/CPU%u/Tlb/Data/Hits", idCpu);
589
590# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
591 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits/Native/*", idCpu);
592 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB hits from native code",
593 "/IEM/CPU%u/Tlb/Data/Hits/Native", idCpu);
594# endif
595
596 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Data/Hits|/IEM/CPU%u/Tlb/Data/Misses", idCpu, idCpu);
597 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Data TLB lookups (sum of hits and misses)",
598 "/IEM/CPU%u/Tlb/Data/AllLookups", idCpu);
599
600 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/Tlb/Data/Misses", idCpu);
601 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/Tlb/Data/Hits", idCpu);
602 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PPM, szVal, true, szPat,
603 "Data TLB actual miss rate", "/IEM/CPU%u/Tlb/Data/RateMisses", idCpu);
604
605# endif /* IEM_WITH_TLB_STATISTICS */
606
607
608#ifdef VBOX_WITH_IEM_RECOMPILER
609 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecNative, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
610 "Executed native translation block", "/IEM/CPU%u/re/cTbExecNative", idCpu);
611 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbExecThreaded, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
612 "Executed threaded translation block", "/IEM/CPU%u/re/cTbExecThreaded", idCpu);
613 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
614 "Times threaded TB execution was interrupted/broken off", "/IEM/CPU%u/re/cTbExecThreadedBreaks", idCpu);
615# ifdef VBOX_WITH_STATISTICS
616 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaksWithLookup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
617 "Times threaded TB execution was interrupted/broken off on a call with lookup entries", "/IEM/CPU%u/re/cTbExecThreadedBreaksWithLookup", idCpu);
618 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedExecBreaksWithoutLookup, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
619 "Times threaded TB execution was interrupted/broken off on a call without lookup entries", "/IEM/CPU%u/re/cTbExecThreadedBreaksWithoutLookup", idCpu);
620# endif
621
622# ifdef VBOX_WITH_STATISTICS
623 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPoll, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
624 "Timer polling profiling", "/IEM/CPU%u/re/TimerPoll", idCpu);
625 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollRun, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
626 "Timer polling profiling", "/IEM/CPU%u/re/TimerPoll/Running", idCpu);
627 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollUnchanged, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
628 "Timer polling interval unchanged", "/IEM/CPU%u/re/TimerPoll/Unchanged", idCpu);
629 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollTiny, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
630 "Timer polling interval tiny", "/IEM/CPU%u/re/TimerPoll/Tiny", idCpu);
631 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollDefaultCalc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
632 "Timer polling interval calculated using defaults", "/IEM/CPU%u/re/TimerPoll/DefaultCalc", idCpu);
633 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollMax, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
634 "Timer polling interval maxed out", "/IEM/CPU%u/re/TimerPoll/Max", idCpu);
635 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollFactorDivision, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NS_PER_OCCURENCE,
636 "Timer polling factor", "/IEM/CPU%u/re/TimerPoll/FactorDivision", idCpu);
637 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTimerPollFactorMultiplication, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
638 "Timer polling factor", "/IEM/CPU%u/re/TimerPoll/FactorMultiplication", idCpu);
639# endif
640 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.cTbsTillNextTimerPollPrev, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
641 "Timer polling interval (in TBs)", "/IEM/CPU%u/re/TimerPollInterval", idCpu);
642
643 PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
644 STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatAllocs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
645 "Translation block allocations", "/IEM/CPU%u/re/cTbAllocCalls", idCpu);
646 STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatFrees, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS,
647 "Translation block frees", "/IEM/CPU%u/re/cTbFreeCalls", idCpu);
648# ifdef VBOX_WITH_STATISTICS
649 STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
650 "Time spent freeing up TBs when full at alloc", "/IEM/CPU%u/re/TbPruningAlloc", idCpu);
651# endif
652 STAMR3RegisterF(pVM, (void *)&pTbAllocator->StatPruneNative, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
653 "Time spent freeing up native TBs when out of executable memory", "/IEM/CPU%u/re/ExecMem/TbPruningNative", idCpu);
654 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cAllocatedChunks, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
655 "Populated TB chunks", "/IEM/CPU%u/re/cTbChunks", idCpu);
656 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxChunks, STAMTYPE_U8, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
657 "Max number of TB chunks", "/IEM/CPU%u/re/cTbChunksMax", idCpu);
658 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cTotalTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
659 "Total number of TBs in the allocator", "/IEM/CPU%u/re/cTbTotal", idCpu);
660 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cMaxTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
661 "Max total number of TBs allowed", "/IEM/CPU%u/re/cTbTotalMax", idCpu);
662 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cInUseTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
663 "Number of currently allocated TBs", "/IEM/CPU%u/re/cTbAllocated", idCpu);
664 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cNativeTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
665 "Number of currently allocated native TBs", "/IEM/CPU%u/re/cTbAllocatedNative", idCpu);
666 STAMR3RegisterF(pVM, (void *)&pTbAllocator->cThreadedTbs, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
667 "Number of currently allocated threaded TBs", "/IEM/CPU%u/re/cTbAllocatedThreaded", idCpu);
668
669 PIEMTBCACHE const pTbCache = pVCpu->iem.s.pTbCacheR3;
670 STAMR3RegisterF(pVM, (void *)&pTbCache->cHash, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
671 "Translation block lookup table size", "/IEM/CPU%u/re/cTbHashTab", idCpu);
672
673 STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHits, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
674 "Translation block lookup hits", "/IEM/CPU%u/re/cTbLookupHits", idCpu);
675 STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupHitsViaTbLookupTable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
676 "Translation block lookup hits via TB lookup table associated with the previous TB", "/IEM/CPU%u/re/cTbLookupHitsViaTbLookupTable", idCpu);
677 STAMR3RegisterF(pVM, (void *)&pTbCache->cLookupMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
678 "Translation block lookup misses", "/IEM/CPU%u/re/cTbLookupMisses", idCpu);
679 STAMR3RegisterF(pVM, (void *)&pTbCache->cCollisions, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES,
680 "Translation block hash table collisions", "/IEM/CPU%u/re/cTbCollisions", idCpu);
681# ifdef VBOX_WITH_STATISTICS
682 STAMR3RegisterF(pVM, (void *)&pTbCache->StatPrune, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
683 "Time spent shortening collision lists", "/IEM/CPU%u/re/TbPruningCollisions", idCpu);
684# endif
685
686 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbThreadedCalls, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
687 "Calls per threaded translation block", "/IEM/CPU%u/re/ThrdCallsPerTb", idCpu);
688 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbInstr, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
689 "Instruction per threaded translation block", "/IEM/CPU%u/re/ThrdInstrPerTb", idCpu);
690 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLookupEntries, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_INSTR_PER_TB,
691 "TB lookup table entries per threaded translation block", "/IEM/CPU%u/re/ThrdLookupEntriesPerTb", idCpu);
692
693 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckIrqBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
694 "TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckIrqBreaks", idCpu);
695 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckTimersBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
696 "TB breaks by CheckIrq", "/IEM/CPU%u/re/CheckTimersBreaks", idCpu);
697 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckModeBreaks, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
698 "TB breaks by CheckMode", "/IEM/CPU%u/re/CheckModeBreaks", idCpu);
699 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
700 "Branch target misses", "/IEM/CPU%u/re/CheckTbJmpMisses", idCpu);
701 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
702 "Needing CS.LIM checking TB after branch or on page crossing", "/IEM/CPU%u/re/CheckTbNeedCsLimChecking", idCpu);
703
704 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopFullTbDetected, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
705 "Detected loop full TB", "/IEM/CPU%u/re/LoopFullTbDetected", idCpu);
706 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopFullTbDetected2, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
707 "Detected loop full TB but looping back to before the first TB instruction",
708 "/IEM/CPU%u/re/LoopFullTbDetected2", idCpu);
709 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbLoopInTbDetected, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
710 "Detected loop within TB", "/IEM/CPU%u/re/LoopInTbDetected", idCpu);
711
712 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeExecMemInstrBufAllocFailed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
713 "Number of times the exec memory allocator failed to allocate a large enough buffer",
714 "/IEM/CPU%u/re/NativeExecMemInstrBufAllocFailed", idCpu);
715
716 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsRecompiled, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
717 "Number of threaded calls per TB that have been properly recompiled to native code",
718 "/IEM/CPU%u/re/NativeCallsRecompiledPerTb", idCpu);
719 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeCallsThreaded, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_CALLS_PER_TB,
720 "Number of threaded calls per TB that could not be recompiler to native code",
721 "/IEM/CPU%u/re/NativeCallsThreadedPerTb", idCpu);
722 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeFullyRecompiledTbs, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
723 "Number of threaded calls that could not be recompiler to native code",
724 "/IEM/CPU%u/re/NativeFullyRecompiledTbs", idCpu);
725
726 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatTbNativeCode, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES_PER_TB,
727 "Size of native code per TB", "/IEM/CPU%u/re/NativeCodeSizePerTb", idCpu);
728 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.StatNativeRecompilation, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL,
729 "Profiling iemNativeRecompile()", "/IEM/CPU%u/re/NativeRecompilation", idCpu);
730
731# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
732# ifdef VBOX_WITH_STATISTICS
733 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
734 "Number of calls to iemNativeRegAllocFindFree.",
735 "/IEM/CPU%u/re/NativeRegFindFree", idCpu);
736# endif
737 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
738 "Number of times iemNativeRegAllocFindFree needed to free a variable.",
739 "/IEM/CPU%u/re/NativeRegFindFreeVar", idCpu);
740# ifdef VBOX_WITH_STATISTICS
741 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
742 "Number of times iemNativeRegAllocFindFree did not needed to free any variables.",
743 "/IEM/CPU%u/re/NativeRegFindFreeNoVar", idCpu);
744 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
745 "Times liveness info freeed up shadowed guest registers in iemNativeRegAllocFindFree.",
746 "/IEM/CPU%u/re/NativeRegFindFreeLivenessUnshadowed", idCpu);
747 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
748 "Times liveness info helped finding the return register in iemNativeRegAllocFindFree.",
749 "/IEM/CPU%u/re/NativeRegFindFreeLivenessHelped", idCpu);
750
751# define REG_NATIVE_EFL_GROUP(a_Lower, a_Camel) do { \
752 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflPostponed ## a_Camel, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, \
753 "Postponed all status flag updating, " #a_Lower " instructions", \
754 "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "Postponed", idCpu); \
755 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflSkipped ## a_Camel, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, \
756 "Skipped all status flag updating, " #a_Lower " instructions", \
757 "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "Skipped", idCpu); \
758 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflTotal ## a_Camel, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, \
759 "Total number of " #a_Lower " intructions with status flag updating", \
760 "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "Total", idCpu); \
761 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "Total", idCpu); \
762 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "Postponed", idCpu); \
763 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat, \
764 "Postponed all status flag updating, " #a_Lower " instructions, percentage", \
765 "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "PostponedPct", idCpu); \
766 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "Skipped", idCpu); \
767 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat, \
768 "Skipped all status flag updating, " #a_Lower " instructions, percentage", \
769 "/IEM/CPU%u/re/NativeEFlags/" #a_Camel "SkippedPct", idCpu); \
770 } while (0)
771 REG_NATIVE_EFL_GROUP(arithmetic, Arithmetic);
772 REG_NATIVE_EFL_GROUP(logical, Logical);
773 REG_NATIVE_EFL_GROUP(shift, Shift);
774# undef REG_NATIVE_EFL_GROUP
775
776 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEflPostponedEmits, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
777 "Postponed EFLAGS calculation emits", "/IEM/CPU%u/re/NativeEFlags/ZZEmits", idCpu);
778
779 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/CfSkippable", idCpu);
780 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/PfSkippable", idCpu);
781 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/AfSkippable", idCpu);
782 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfSkippable", idCpu);
783 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/SfSkippable", idCpu);
784 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfSkippable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Skippable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/OfSkippable", idCpu);
785
786 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/CfRequired", idCpu);
787 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/PfRequired", idCpu);
788 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/AfRequired", idCpu);
789 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfRequired", idCpu);
790 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/SfRequired", idCpu);
791 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfRequired, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Required EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/OfRequired", idCpu);
792
793# ifdef IEMLIVENESS_EXTENDED_LAYOUT
794 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflCfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.CF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/CfDelayable", idCpu);
795 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflPfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.PF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/PfDelayable", idCpu);
796 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflAfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.AF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/AfDelayable", idCpu);
797 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflZfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.ZF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfDelayable", idCpu);
798 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflSfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.SF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/SfDelayable", idCpu);
799 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeLivenessEflOfDelayable, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Maybe delayable EFLAGS.OF updating", "/IEM/CPU%u/re/NativeLivenessEFlags/OfDelayable", idCpu);
800# endif
801
802 /* Sum up all status bits ('_' is a sorting hack). */
803 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?fSkippable*", idCpu);
804 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total skippable EFLAGS status bit updating",
805 "/IEM/CPU%u/re/NativeLivenessEFlags/totalSkippable", idCpu);
806
807 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?fRequired*", idCpu);
808 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total required STATUS status bit updating",
809 "/IEM/CPU%u/re/NativeLivenessEFlags/totalRequired", idCpu);
810
811# ifdef IEMLIVENESS_EXTENDED_LAYOUT
812 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?fDelayable*", idCpu);
813 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total potentially delayable STATUS status bit updating",
814 "/IEM/CPU%u/re/NativeLivenessEFlags/totalDelayable", idCpu);
815# endif
816
817 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/?f*", idCpu);
818 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat, "Total STATUS status bit events of any kind",
819 "/IEM/CPU%u/re/NativeLivenessEFlags/totalTotal", idCpu);
820
821 /* Corresponding ratios / percentages of the totals. */
822 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/totalTotal", idCpu);
823 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/totalSkippable", idCpu);
824 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
825 "Total skippable EFLAGS status bit updating percentage",
826 "/IEM/CPU%u/re/NativeLivenessEFlags/totalSkippablePct", idCpu);
827
828 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/totalTotal", idCpu);
829 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/totalRequired", idCpu);
830 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
831 "Total required EFLAGS status bit updating percentage",
832 "/IEM/CPU%u/re/NativeLivenessEFlags/totalRequiredPct", idCpu);
833
834# ifdef IEMLIVENESS_EXTENDED_LAYOUT
835 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/totalDelayable", idCpu);
836 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
837 "Total potentially delayable EFLAGS status bit updating percentage",
838 "/IEM/CPU%u/re/NativeLivenessEFlags/totalDelayablePct", idCpu);
839# endif
840
841 /* Ratios of individual bits. */
842 size_t const offFlagChar = RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeLivenessEFlags/Cf*", idCpu) - 3;
843 Assert(szPat[offFlagChar] == 'C');
844 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativeLivenessEFlags/CfSkippable", idCpu);
845 Assert(szVal[offFlagChar] == 'C');
846 szPat[offFlagChar] = szVal[offFlagChar] = 'C'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.CF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/CfSkippablePct", idCpu);
847 szPat[offFlagChar] = szVal[offFlagChar] = 'P'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.PF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/PfSkippablePct", idCpu);
848 szPat[offFlagChar] = szVal[offFlagChar] = 'A'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.AF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/AfSkippablePct", idCpu);
849 szPat[offFlagChar] = szVal[offFlagChar] = 'Z'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.ZF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/ZfSkippablePct", idCpu);
850 szPat[offFlagChar] = szVal[offFlagChar] = 'S'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.SF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/SfSkippablePct", idCpu);
851 szPat[offFlagChar] = szVal[offFlagChar] = 'O'; STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, true, szPat, "Skippable EFLAGS.OF updating percentage", "/IEM/CPU%u/re/NativeLivenessEFlags/OfSkippablePct", idCpu);
852
853 /* PC updates total and skipped, with PCT ratio. */
854 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Total RIP updates", "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
855 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativePcUpdateDelayed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Delayed RIP updates", "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
856 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativePcUpdateTotal", idCpu);
857 RTStrPrintf(szVal, sizeof(szVal), "/IEM/CPU%u/re/NativePcUpdateDelayed", idCpu);
858 STAMR3RegisterPctOfSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, STAMUNIT_PCT, szVal, false, szPat,
859 "Delayed RIP updating percentage",
860 "/IEM/CPU%u/re/NativePcUpdateDelayed_StatusDelayedPct", idCpu);
861
862# endif /* VBOX_WITH_STATISTICS */
863# ifdef IEMNATIVE_WITH_DELAYED_REGISTER_WRITEBACK
864 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeEndIfOtherBranchDirty, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
865 "IEM_MC_ENDIF flushing dirty shadow registers for other branch (not good).",
866 "/IEM/CPU%u/re/NativeEndIfOtherBranchDirty", idCpu);
867# endif
868# ifdef VBOX_WITH_STATISTICS
869# ifdef IEMNATIVE_WITH_SIMD_REG_ALLOCATOR
870 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFree, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
871 "Number of calls to iemNativeSimdRegAllocFindFree.",
872 "/IEM/CPU%u/re/NativeSimdRegFindFree", idCpu);
873 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
874 "Number of times iemNativeSimdRegAllocFindFree needed to free a variable.",
875 "/IEM/CPU%u/re/NativeSimdRegFindFreeVar", idCpu);
876 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeNoVar, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
877 "Number of times iemNativeSimdRegAllocFindFree did not needed to free any variables.",
878 "/IEM/CPU%u/re/NativeSimdRegFindFreeNoVar", idCpu);
879 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessUnshadowed, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
880 "Times liveness info freeed up shadowed guest registers in iemNativeSimdRegAllocFindFree.",
881 "/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessUnshadowed", idCpu);
882 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeSimdRegFindFreeLivenessHelped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
883 "Times liveness info helped finding the return register in iemNativeSimdRegAllocFindFree.",
884 "/IEM/CPU%u/re/NativeSimdRegFindFreeLivenessHelped", idCpu);
885
886 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks",
887 "/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckPotential", idCpu);
888 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks",
889 "/IEM/CPU%u/re/NativeMaybeWaitDeviceNotAvailXcptCheckPotential", idCpu);
890 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks",
891 "/IEM/CPU%u/re/NativeMaybeSseXcptCheckPotential", idCpu);
892 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckPotential, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "Potential IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks",
893 "/IEM/CPU%u/re/NativeMaybeAvxXcptCheckPotential", idCpu);
894
895 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() checks omitted",
896 "/IEM/CPU%u/re/NativeMaybeDeviceNotAvailXcptCheckOmitted", idCpu);
897 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeWaitDeviceNotAvailXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() checks omitted",
898 "/IEM/CPU%u/re/NativeMaybeWaitDeviceNotAvailXcptCheckOmitted", idCpu);
899 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeSseXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() checks omitted",
900 "/IEM/CPU%u/re/NativeMaybeSseXcptCheckOmitted", idCpu);
901 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeMaybeAvxXcptCheckOmitted, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT, "IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT() checks omitted",
902 "/IEM/CPU%u/re/NativeMaybeAvxXcptCheckOmitted", idCpu);
903# endif
904
905 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbFinished, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
906 "Number of times the TB finishes execution completely",
907 "/IEM/CPU%u/re/NativeTbFinished", idCpu);
908# endif /* VBOX_WITH_STATISTICS */
909 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnBreak, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
910 "Number of times the TB finished through the ReturnBreak label",
911 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak", idCpu);
912 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnBreakFF, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
913 "Number of times the TB finished through the ReturnBreak label",
914 "/IEM/CPU%u/re/NativeTbExit/ReturnBreakFF", idCpu);
915 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnWithFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
916 "Number of times the TB finished through the ReturnWithFlags label",
917 "/IEM/CPU%u/re/NativeTbExit/ReturnWithFlags", idCpu);
918 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitReturnOtherStatus, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
919 "Number of times the TB finished with some other status value",
920 "/IEM/CPU%u/re/NativeTbExit/ReturnOtherStatus", idCpu);
921 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitLongJump, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
922 "Number of times the TB finished via long jump / throw",
923 "/IEM/CPU%u/re/NativeTbExit/LongJumps", idCpu);
924 /* These end up returning VINF_IEM_REEXEC_BREAK and are thus already counted under NativeTbExit/ReturnBreak: */
925 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitObsoleteTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
926 "Number of times the TB finished through the ObsoleteTb label",
927 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/ObsoleteTb", idCpu);
928 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatCheckNeedCsLimChecking, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
929 "Number of times the TB finished through the NeedCsLimChecking label",
930 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/NeedCsLimChecking", idCpu);
931 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatCheckBranchMisses, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
932 "Number of times the TB finished through the CheckBranchMiss label",
933 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/CheckBranchMiss", idCpu);
934 /* Raising stuff will either increment NativeTbExit/LongJumps or NativeTbExit/ReturnOtherStatus
935 depending on whether VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP is defined: */
936# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER_LONGJMP
937# define RAISE_PREFIX "/IEM/CPU%u/re/NativeTbExit/ReturnOtherStatus/"
938# else
939# define RAISE_PREFIX "/IEM/CPU%u/re/NativeTbExit/LongJumps/"
940# endif
941 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseDe, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
942 "Number of times the TB finished raising a #DE exception",
943 RAISE_PREFIX "RaiseDe", idCpu);
944 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseUd, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
945 "Number of times the TB finished raising a #UD exception",
946 RAISE_PREFIX "RaiseUd", idCpu);
947 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseSseRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
948 "Number of times the TB finished raising a SSE related exception",
949 RAISE_PREFIX "RaiseSseRelated", idCpu);
950 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseAvxRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
951 "Number of times the TB finished raising a AVX related exception",
952 RAISE_PREFIX "RaiseAvxRelated", idCpu);
953 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseSseAvxFpRelated, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
954 "Number of times the TB finished raising a SSE/AVX floating point related exception",
955 RAISE_PREFIX "RaiseSseAvxFpRelated", idCpu);
956 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseNm, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
957 "Number of times the TB finished raising a #NM exception",
958 RAISE_PREFIX "RaiseNm", idCpu);
959 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseGp0, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
960 "Number of times the TB finished raising a #GP(0) exception",
961 RAISE_PREFIX "RaiseGp0", idCpu);
962 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseMf, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
963 "Number of times the TB finished raising a #MF exception",
964 RAISE_PREFIX "RaiseMf", idCpu);
965 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitRaiseXf, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
966 "Number of times the TB finished raising a #XF exception",
967 RAISE_PREFIX "RaiseXf", idCpu);
968
969# ifdef VBOX_WITH_STATISTICS
970 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitLoopFullTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
971 "Number of full TB loops.",
972 "/IEM/CPU%u/re/NativeTbExit/LoopFullTb", idCpu);
973# endif
974
975 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1Irq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
976 "Direct linking #1 with IRQ check succeeded",
977 "/IEM/CPU%u/re/NativeTbExit/DirectLinking1Irq", idCpu);
978 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1NoIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
979 "Direct linking #1 w/o IRQ check succeeded",
980 "/IEM/CPU%u/re/NativeTbExit/DirectLinking1NoIrq", idCpu);
981# ifdef VBOX_WITH_STATISTICS
982 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1NoTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
983 "Direct linking #1 failed: No TB in lookup table",
984 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1NoTb", idCpu);
985 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchGCPhysPc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
986 "Direct linking #1 failed: GCPhysPc mismatch",
987 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1MismatchGCPhysPc", idCpu);
988 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1MismatchFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
989 "Direct linking #1 failed: TB flags mismatch",
990 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1MismatchFlags", idCpu);
991 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking1PendingIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
992 "Direct linking #1 failed: IRQ or FF pending",
993 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking1PendingIrq", idCpu);
994# endif
995
996 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2Irq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
997 "Direct linking #2 with IRQ check succeeded",
998 "/IEM/CPU%u/re/NativeTbExit/DirectLinking2Irq", idCpu);
999 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2NoIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1000 "Direct linking #2 w/o IRQ check succeeded",
1001 "/IEM/CPU%u/re/NativeTbExit/DirectLinking2NoIrq", idCpu);
1002# ifdef VBOX_WITH_STATISTICS
1003 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2NoTb, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1004 "Direct linking #2 failed: No TB in lookup table",
1005 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2NoTb", idCpu);
1006 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchGCPhysPc, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1007 "Direct linking #2 failed: GCPhysPc mismatch",
1008 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2MismatchGCPhysPc", idCpu);
1009 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2MismatchFlags, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1010 "Direct linking #2 failed: TB flags mismatch",
1011 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2MismatchFlags", idCpu);
1012 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatNativeTbExitDirectLinking2PendingIrq, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1013 "Direct linking #2 failed: IRQ or FF pending",
1014 "/IEM/CPU%u/re/NativeTbExit/ReturnBreak/DirectLinking2PendingIrq", idCpu);
1015# endif
1016
1017 RTStrPrintf(szPat, sizeof(szPat), "/IEM/CPU%u/re/NativeTbExit/*", idCpu); /* only immediate children, no sub folders */
1018 STAMR3RegisterSum(pVM->pUVM, STAMVISIBILITY_ALWAYS, szPat,
1019 "Number of times native TB execution finished before the end (not counting thrown memory++ exceptions)",
1020 "/IEM/CPU%u/re/NativeTbExit", idCpu);
1021
1022
1023# endif /* VBOX_WITH_IEM_NATIVE_RECOMPILER */
1024
1025
1026# ifdef VBOX_WITH_STATISTICS
1027 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemMapJmp, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1028 "iemMemMapJmp calls", "/IEM/CPU%u/iemMemMapJmp", idCpu);
1029 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemMapNoJmp, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1030 "iemMemMap calls", "/IEM/CPU%u/iemMemMapNoJmp", idCpu);
1031 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemBounceBufferCrossPage, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1032 "iemMemBounceBufferMapCrossPage calls", "/IEM/CPU%u/iemMemMapBounceBufferCrossPage", idCpu);
1033 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatMemBounceBufferMapPhys, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
1034 "iemMemBounceBufferMapPhys calls", "/IEM/CPU%u/iemMemMapBounceBufferMapPhys", idCpu);
1035# endif
1036
1037
1038#endif /* VBOX_WITH_IEM_RECOMPILER */
1039
1040 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
1041 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1042 "", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
1043 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
1044 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1045 "", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
1046
1047# if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
1048 /* Instruction statistics: */
1049# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
1050 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
1051 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
1052 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
1053 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
1054# include "IEMInstructionStatisticsTmpl.h"
1055# undef IEM_DO_INSTR_STAT
1056# endif
1057
1058# if defined(VBOX_WITH_STATISTICS) && defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1059 /* Threaded function statistics: */
1060 for (unsigned i = 1; i < (unsigned)kIemThreadedFunc_End; i++)
1061 STAMR3RegisterF(pVM, &pVCpu->iem.s.acThreadedFuncStats[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED,
1062 STAMUNIT_COUNT, NULL, "/IEM/CPU%u/ThrdFuncs/%s", idCpu, g_apszIemThreadedFunctionStats[i]);
1063# endif
1064
1065#endif /* !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX) - quick fix for stupid structure duplication non-sense */
1066 }
1067
1068#if !defined(VBOX_VMM_TARGET_ARMV8) && defined(VBOX_WITH_NESTED_HWVIRT_VMX)
1069 /*
1070 * Register the per-VM VMX APIC-access page handler type.
1071 */
1072 if (pVM->cpum.ro.GuestFeatures.fVmx)
1073 {
1074 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
1075 iemVmxApicAccessPageHandler,
1076 "VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
1077 AssertLogRelRCReturn(rc, rc);
1078 }
1079#endif
1080
1081 DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
1082 DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
1083#ifdef IEM_WITH_TLB_TRACE
1084 DBGFR3InfoRegisterInternalArgv(pVM, "tlbtrace", "IEM TLB trace log", iemR3InfoTlbTrace, DBGFINFO_FLAGS_RUN_ON_EMT);
1085#endif
1086#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1087 DBGFR3InfoRegisterInternalArgv(pVM, "tb", "IEM translation block", iemR3InfoTb, DBGFINFO_FLAGS_RUN_ON_EMT);
1088 DBGFR3InfoRegisterInternalArgv(pVM, "tbtop", "IEM translation blocks most used or most recently used",
1089 iemR3InfoTbTop, DBGFINFO_FLAGS_RUN_ON_EMT);
1090#endif
1091#ifdef VBOX_WITH_DEBUGGER
1092 iemR3RegisterDebuggerCommands();
1093#endif
1094
1095 return VINF_SUCCESS;
1096}
1097
1098
1099VMMR3DECL(int) IEMR3Term(PVM pVM)
1100{
1101 NOREF(pVM);
1102#ifdef IEM_WITH_TLB_TRACE
1103 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1104 {
1105 PVMCPU const pVCpu = pVM->apCpusR3[idCpu];
1106 RTMemPageFree(pVCpu->iem.s.paTlbTraceEntries,
1107 RT_BIT_Z(pVCpu->iem.s.cTlbTraceEntriesShift) * sizeof(*pVCpu->iem.s.paTlbTraceEntries));
1108 }
1109#endif
1110#if defined(VBOX_WITH_IEM_NATIVE_RECOMPILER) && defined(VBOX_WITH_SAVE_THREADED_TBS_FOR_PROFILING)
1111 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1112 iemThreadedSaveTbForProfilingCleanup(pVM->apCpusR3[idCpu]);
1113#endif
1114 return VINF_SUCCESS;
1115}
1116
1117
1118VMMR3DECL(void) IEMR3Relocate(PVM pVM)
1119{
1120 RT_NOREF(pVM);
1121}
1122
1123
1124/**
1125 * Gets the name of a generic IEM exit code.
1126 *
1127 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
1128 * @param uExit The IEM exit to name.
1129 */
1130VMMR3DECL(const char *) IEMR3GetExitName(uint32_t uExit)
1131{
1132 static const char * const s_apszNames[] =
1133 {
1134 /* external interrupts */
1135 "ExtInt 00h", "ExtInt 01h", "ExtInt 02h", "ExtInt 03h", "ExtInt 04h", "ExtInt 05h", "ExtInt 06h", "ExtInt 07h",
1136 "ExtInt 08h", "ExtInt 09h", "ExtInt 0ah", "ExtInt 0bh", "ExtInt 0ch", "ExtInt 0dh", "ExtInt 0eh", "ExtInt 0fh",
1137 "ExtInt 10h", "ExtInt 11h", "ExtInt 12h", "ExtInt 13h", "ExtInt 14h", "ExtInt 15h", "ExtInt 16h", "ExtInt 17h",
1138 "ExtInt 18h", "ExtInt 19h", "ExtInt 1ah", "ExtInt 1bh", "ExtInt 1ch", "ExtInt 1dh", "ExtInt 1eh", "ExtInt 1fh",
1139 "ExtInt 20h", "ExtInt 21h", "ExtInt 22h", "ExtInt 23h", "ExtInt 24h", "ExtInt 25h", "ExtInt 26h", "ExtInt 27h",
1140 "ExtInt 28h", "ExtInt 29h", "ExtInt 2ah", "ExtInt 2bh", "ExtInt 2ch", "ExtInt 2dh", "ExtInt 2eh", "ExtInt 2fh",
1141 "ExtInt 30h", "ExtInt 31h", "ExtInt 32h", "ExtInt 33h", "ExtInt 34h", "ExtInt 35h", "ExtInt 36h", "ExtInt 37h",
1142 "ExtInt 38h", "ExtInt 39h", "ExtInt 3ah", "ExtInt 3bh", "ExtInt 3ch", "ExtInt 3dh", "ExtInt 3eh", "ExtInt 3fh",
1143 "ExtInt 40h", "ExtInt 41h", "ExtInt 42h", "ExtInt 43h", "ExtInt 44h", "ExtInt 45h", "ExtInt 46h", "ExtInt 47h",
1144 "ExtInt 48h", "ExtInt 49h", "ExtInt 4ah", "ExtInt 4bh", "ExtInt 4ch", "ExtInt 4dh", "ExtInt 4eh", "ExtInt 4fh",
1145 "ExtInt 50h", "ExtInt 51h", "ExtInt 52h", "ExtInt 53h", "ExtInt 54h", "ExtInt 55h", "ExtInt 56h", "ExtInt 57h",
1146 "ExtInt 58h", "ExtInt 59h", "ExtInt 5ah", "ExtInt 5bh", "ExtInt 5ch", "ExtInt 5dh", "ExtInt 5eh", "ExtInt 5fh",
1147 "ExtInt 60h", "ExtInt 61h", "ExtInt 62h", "ExtInt 63h", "ExtInt 64h", "ExtInt 65h", "ExtInt 66h", "ExtInt 67h",
1148 "ExtInt 68h", "ExtInt 69h", "ExtInt 6ah", "ExtInt 6bh", "ExtInt 6ch", "ExtInt 6dh", "ExtInt 6eh", "ExtInt 6fh",
1149 "ExtInt 70h", "ExtInt 71h", "ExtInt 72h", "ExtInt 73h", "ExtInt 74h", "ExtInt 75h", "ExtInt 76h", "ExtInt 77h",
1150 "ExtInt 78h", "ExtInt 79h", "ExtInt 7ah", "ExtInt 7bh", "ExtInt 7ch", "ExtInt 7dh", "ExtInt 7eh", "ExtInt 7fh",
1151 "ExtInt 80h", "ExtInt 81h", "ExtInt 82h", "ExtInt 83h", "ExtInt 84h", "ExtInt 85h", "ExtInt 86h", "ExtInt 87h",
1152 "ExtInt 88h", "ExtInt 89h", "ExtInt 8ah", "ExtInt 8bh", "ExtInt 8ch", "ExtInt 8dh", "ExtInt 8eh", "ExtInt 8fh",
1153 "ExtInt 90h", "ExtInt 91h", "ExtInt 92h", "ExtInt 93h", "ExtInt 94h", "ExtInt 95h", "ExtInt 96h", "ExtInt 97h",
1154 "ExtInt 98h", "ExtInt 99h", "ExtInt 9ah", "ExtInt 9bh", "ExtInt 9ch", "ExtInt 9dh", "ExtInt 9eh", "ExtInt 9fh",
1155 "ExtInt a0h", "ExtInt a1h", "ExtInt a2h", "ExtInt a3h", "ExtInt a4h", "ExtInt a5h", "ExtInt a6h", "ExtInt a7h",
1156 "ExtInt a8h", "ExtInt a9h", "ExtInt aah", "ExtInt abh", "ExtInt ach", "ExtInt adh", "ExtInt aeh", "ExtInt afh",
1157 "ExtInt b0h", "ExtInt b1h", "ExtInt b2h", "ExtInt b3h", "ExtInt b4h", "ExtInt b5h", "ExtInt b6h", "ExtInt b7h",
1158 "ExtInt b8h", "ExtInt b9h", "ExtInt bah", "ExtInt bbh", "ExtInt bch", "ExtInt bdh", "ExtInt beh", "ExtInt bfh",
1159 "ExtInt c0h", "ExtInt c1h", "ExtInt c2h", "ExtInt c3h", "ExtInt c4h", "ExtInt c5h", "ExtInt c6h", "ExtInt c7h",
1160 "ExtInt c8h", "ExtInt c9h", "ExtInt cah", "ExtInt cbh", "ExtInt cch", "ExtInt cdh", "ExtInt ceh", "ExtInt cfh",
1161 "ExtInt d0h", "ExtInt d1h", "ExtInt d2h", "ExtInt d3h", "ExtInt d4h", "ExtInt d5h", "ExtInt d6h", "ExtInt d7h",
1162 "ExtInt d8h", "ExtInt d9h", "ExtInt dah", "ExtInt dbh", "ExtInt dch", "ExtInt ddh", "ExtInt deh", "ExtInt dfh",
1163 "ExtInt e0h", "ExtInt e1h", "ExtInt e2h", "ExtInt e3h", "ExtInt e4h", "ExtInt e5h", "ExtInt e6h", "ExtInt e7h",
1164 "ExtInt e8h", "ExtInt e9h", "ExtInt eah", "ExtInt ebh", "ExtInt ech", "ExtInt edh", "ExtInt eeh", "ExtInt efh",
1165 "ExtInt f0h", "ExtInt f1h", "ExtInt f2h", "ExtInt f3h", "ExtInt f4h", "ExtInt f5h", "ExtInt f6h", "ExtInt f7h",
1166 "ExtInt f8h", "ExtInt f9h", "ExtInt fah", "ExtInt fbh", "ExtInt fch", "ExtInt fdh", "ExtInt feh", "ExtInt ffh",
1167 /* software interrups */
1168 "SoftInt 00h", "SoftInt 01h", "SoftInt 02h", "SoftInt 03h", "SoftInt 04h", "SoftInt 05h", "SoftInt 06h", "SoftInt 07h",
1169 "SoftInt 08h", "SoftInt 09h", "SoftInt 0ah", "SoftInt 0bh", "SoftInt 0ch", "SoftInt 0dh", "SoftInt 0eh", "SoftInt 0fh",
1170 "SoftInt 10h", "SoftInt 11h", "SoftInt 12h", "SoftInt 13h", "SoftInt 14h", "SoftInt 15h", "SoftInt 16h", "SoftInt 17h",
1171 "SoftInt 18h", "SoftInt 19h", "SoftInt 1ah", "SoftInt 1bh", "SoftInt 1ch", "SoftInt 1dh", "SoftInt 1eh", "SoftInt 1fh",
1172 "SoftInt 20h", "SoftInt 21h", "SoftInt 22h", "SoftInt 23h", "SoftInt 24h", "SoftInt 25h", "SoftInt 26h", "SoftInt 27h",
1173 "SoftInt 28h", "SoftInt 29h", "SoftInt 2ah", "SoftInt 2bh", "SoftInt 2ch", "SoftInt 2dh", "SoftInt 2eh", "SoftInt 2fh",
1174 "SoftInt 30h", "SoftInt 31h", "SoftInt 32h", "SoftInt 33h", "SoftInt 34h", "SoftInt 35h", "SoftInt 36h", "SoftInt 37h",
1175 "SoftInt 38h", "SoftInt 39h", "SoftInt 3ah", "SoftInt 3bh", "SoftInt 3ch", "SoftInt 3dh", "SoftInt 3eh", "SoftInt 3fh",
1176 "SoftInt 40h", "SoftInt 41h", "SoftInt 42h", "SoftInt 43h", "SoftInt 44h", "SoftInt 45h", "SoftInt 46h", "SoftInt 47h",
1177 "SoftInt 48h", "SoftInt 49h", "SoftInt 4ah", "SoftInt 4bh", "SoftInt 4ch", "SoftInt 4dh", "SoftInt 4eh", "SoftInt 4fh",
1178 "SoftInt 50h", "SoftInt 51h", "SoftInt 52h", "SoftInt 53h", "SoftInt 54h", "SoftInt 55h", "SoftInt 56h", "SoftInt 57h",
1179 "SoftInt 58h", "SoftInt 59h", "SoftInt 5ah", "SoftInt 5bh", "SoftInt 5ch", "SoftInt 5dh", "SoftInt 5eh", "SoftInt 5fh",
1180 "SoftInt 60h", "SoftInt 61h", "SoftInt 62h", "SoftInt 63h", "SoftInt 64h", "SoftInt 65h", "SoftInt 66h", "SoftInt 67h",
1181 "SoftInt 68h", "SoftInt 69h", "SoftInt 6ah", "SoftInt 6bh", "SoftInt 6ch", "SoftInt 6dh", "SoftInt 6eh", "SoftInt 6fh",
1182 "SoftInt 70h", "SoftInt 71h", "SoftInt 72h", "SoftInt 73h", "SoftInt 74h", "SoftInt 75h", "SoftInt 76h", "SoftInt 77h",
1183 "SoftInt 78h", "SoftInt 79h", "SoftInt 7ah", "SoftInt 7bh", "SoftInt 7ch", "SoftInt 7dh", "SoftInt 7eh", "SoftInt 7fh",
1184 "SoftInt 80h", "SoftInt 81h", "SoftInt 82h", "SoftInt 83h", "SoftInt 84h", "SoftInt 85h", "SoftInt 86h", "SoftInt 87h",
1185 "SoftInt 88h", "SoftInt 89h", "SoftInt 8ah", "SoftInt 8bh", "SoftInt 8ch", "SoftInt 8dh", "SoftInt 8eh", "SoftInt 8fh",
1186 "SoftInt 90h", "SoftInt 91h", "SoftInt 92h", "SoftInt 93h", "SoftInt 94h", "SoftInt 95h", "SoftInt 96h", "SoftInt 97h",
1187 "SoftInt 98h", "SoftInt 99h", "SoftInt 9ah", "SoftInt 9bh", "SoftInt 9ch", "SoftInt 9dh", "SoftInt 9eh", "SoftInt 9fh",
1188 "SoftInt a0h", "SoftInt a1h", "SoftInt a2h", "SoftInt a3h", "SoftInt a4h", "SoftInt a5h", "SoftInt a6h", "SoftInt a7h",
1189 "SoftInt a8h", "SoftInt a9h", "SoftInt aah", "SoftInt abh", "SoftInt ach", "SoftInt adh", "SoftInt aeh", "SoftInt afh",
1190 "SoftInt b0h", "SoftInt b1h", "SoftInt b2h", "SoftInt b3h", "SoftInt b4h", "SoftInt b5h", "SoftInt b6h", "SoftInt b7h",
1191 "SoftInt b8h", "SoftInt b9h", "SoftInt bah", "SoftInt bbh", "SoftInt bch", "SoftInt bdh", "SoftInt beh", "SoftInt bfh",
1192 "SoftInt c0h", "SoftInt c1h", "SoftInt c2h", "SoftInt c3h", "SoftInt c4h", "SoftInt c5h", "SoftInt c6h", "SoftInt c7h",
1193 "SoftInt c8h", "SoftInt c9h", "SoftInt cah", "SoftInt cbh", "SoftInt cch", "SoftInt cdh", "SoftInt ceh", "SoftInt cfh",
1194 "SoftInt d0h", "SoftInt d1h", "SoftInt d2h", "SoftInt d3h", "SoftInt d4h", "SoftInt d5h", "SoftInt d6h", "SoftInt d7h",
1195 "SoftInt d8h", "SoftInt d9h", "SoftInt dah", "SoftInt dbh", "SoftInt dch", "SoftInt ddh", "SoftInt deh", "SoftInt dfh",
1196 "SoftInt e0h", "SoftInt e1h", "SoftInt e2h", "SoftInt e3h", "SoftInt e4h", "SoftInt e5h", "SoftInt e6h", "SoftInt e7h",
1197 "SoftInt e8h", "SoftInt e9h", "SoftInt eah", "SoftInt ebh", "SoftInt ech", "SoftInt edh", "SoftInt eeh", "SoftInt efh",
1198 "SoftInt f0h", "SoftInt f1h", "SoftInt f2h", "SoftInt f3h", "SoftInt f4h", "SoftInt f5h", "SoftInt f6h", "SoftInt f7h",
1199 "SoftInt f8h", "SoftInt f9h", "SoftInt fah", "SoftInt fbh", "SoftInt fch", "SoftInt fdh", "SoftInt feh", "SoftInt ffh",
1200 };
1201 if (uExit < RT_ELEMENTS(s_apszNames))
1202 return s_apszNames[uExit];
1203 return NULL;
1204}
1205
1206
1207/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
1208static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, bool *pfHeader)
1209{
1210 if (*pfHeader)
1211 return;
1212 pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
1213 *pfHeader = true;
1214}
1215
1216
1217#define IEMR3INFOTLB_F_ONLY_VALID RT_BIT_32(0)
1218#define IEMR3INFOTLB_F_CHECK RT_BIT_32(1)
1219
1220/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
1221static void iemR3InfoTlbPrintSlot(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, IEMTLBENTRY const *pTlbe,
1222 uint32_t uSlot, uint32_t fFlags)
1223{
1224#ifndef VBOX_VMM_TARGET_ARMV8
1225 uint64_t const uTlbRevision = !(uSlot & 1) ? pTlb->uTlbRevision : pTlb->uTlbRevisionGlobal;
1226#else
1227 uint64_t const uTlbRevision = pTlb->uTlbRevision;
1228#endif
1229 if ((fFlags & IEMR3INFOTLB_F_ONLY_VALID) && (pTlbe->uTag & IEMTLB_REVISION_MASK) != uTlbRevision)
1230 return;
1231
1232 /* The address needs to be sign extended, thus the shifting fun here.*/
1233 RTGCPTR const GCPtr = (RTGCINTPTR)((pTlbe->uTag & ~IEMTLB_REVISION_MASK) << (64 - IEMTLB_TAG_ADDR_WIDTH))
1234 >> (64 - IEMTLB_TAG_ADDR_WIDTH - GUEST_PAGE_SHIFT);
1235 const char *pszValid = "";
1236#ifndef VBOX_VMM_TARGET_ARMV8
1237 char szTmp[128];
1238 if (fFlags & IEMR3INFOTLB_F_CHECK)
1239 {
1240 uint32_t const fInvSlotG = (uint32_t)!(uSlot & 1) << X86_PTE_BIT_G;
1241 PGMPTWALKFAST WalkFast;
1242 int rc = PGMGstQueryPageFast(pVCpu, GCPtr, 0 /*fFlags - don't check or modify anything */, &WalkFast);
1243 pszValid = szTmp;
1244 if (RT_FAILURE(rc))
1245 switch (rc)
1246 {
1247 case VERR_PAGE_TABLE_NOT_PRESENT:
1248 switch ((WalkFast.fFailed & PGM_WALKFAIL_LEVEL_MASK) >> PGM_WALKFAIL_LEVEL_SHIFT)
1249 {
1250 case 1: pszValid = " stale(page-not-present)"; break;
1251 case 2: pszValid = " stale(pd-entry-not-present)"; break;
1252 case 3: pszValid = " stale(pdptr-entry-not-present)"; break;
1253 case 4: pszValid = " stale(pml4-entry-not-present)"; break;
1254 case 5: pszValid = " stale(pml5-entry-not-present)"; break;
1255 default: pszValid = " stale(VERR_PAGE_TABLE_NOT_PRESENT)"; break;
1256 }
1257 break;
1258 default: RTStrPrintf(szTmp, sizeof(szTmp), " stale(rc=%d)", rc); break;
1259 }
1260 else if (WalkFast.GCPhys != pTlbe->GCPhys)
1261 RTStrPrintf(szTmp, sizeof(szTmp), " stale(GCPhys=%RGp)", WalkFast.GCPhys);
1262 else if ( (~WalkFast.fEffective & (X86_PTE_RW | X86_PTE_US | X86_PTE_G | X86_PTE_A | X86_PTE_D))
1263 == ( (pTlbe->fFlagsAndPhysRev & ( IEMTLBE_F_PT_NO_WRITE | IEMTLBE_F_PT_NO_USER
1264 | IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_ACCESSED))
1265 | fInvSlotG ) )
1266 pszValid = " still-valid";
1267 else if ( (~WalkFast.fEffective & (X86_PTE_RW | X86_PTE_US | X86_PTE_G))
1268 == ((pTlbe->fFlagsAndPhysRev & (IEMTLBE_F_PT_NO_WRITE | IEMTLBE_F_PT_NO_USER)) | fInvSlotG) )
1269 switch ( (~WalkFast.fEffective & (X86_PTE_A | X86_PTE_D))
1270 ^ (pTlbe->fFlagsAndPhysRev & (IEMTLBE_F_PT_NO_DIRTY | IEMTLBE_F_PT_NO_ACCESSED)) )
1271 {
1272 case X86_PTE_A:
1273 pszValid = WalkFast.fEffective & X86_PTE_A ? " still-valid(accessed-now)" : " still-valid(accessed-no-more)";
1274 break;
1275 case X86_PTE_D:
1276 pszValid = WalkFast.fEffective & X86_PTE_D ? " still-valid(dirty-now)" : " still-valid(dirty-no-more)";
1277 break;
1278 case X86_PTE_D | X86_PTE_A:
1279 RTStrPrintf(szTmp, sizeof(szTmp), " still-valid(%s%s)",
1280 (~WalkFast.fEffective & X86_PTE_D) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY) ? ""
1281 : WalkFast.fEffective & X86_PTE_D ? "dirty-now" : "dirty-no-more",
1282 (~WalkFast.fEffective & X86_PTE_A) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED) ? ""
1283 : WalkFast.fEffective & X86_PTE_A ? " accessed-now" : " accessed-no-more");
1284 break;
1285 default: AssertFailed(); break;
1286 }
1287 else
1288 RTStrPrintf(szTmp, sizeof(szTmp), " stale(%s%s%s%s%s)",
1289 (~WalkFast.fEffective & X86_PTE_RW) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE) ? ""
1290 : WalkFast.fEffective & X86_PTE_RW ? "writeable-now" : "writable-no-more",
1291 (~WalkFast.fEffective & X86_PTE_US) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_USER) ? ""
1292 : WalkFast.fEffective & X86_PTE_US ? " user-now" : " user-no-more",
1293 (~WalkFast.fEffective & X86_PTE_G) == fInvSlotG ? ""
1294 : WalkFast.fEffective & X86_PTE_G ? " global-now" : " global-no-more",
1295 (~WalkFast.fEffective & X86_PTE_D) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY) ? ""
1296 : WalkFast.fEffective & X86_PTE_D ? " dirty-now" : " dirty-no-more",
1297 (~WalkFast.fEffective & X86_PTE_A) == (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED) ? ""
1298 : WalkFast.fEffective & X86_PTE_A ? " accessed-now" : " accessed-no-more");
1299 }
1300#else
1301 RT_NOREF(pVCpu);
1302#endif
1303
1304 pHlp->pfnPrintf(pHlp, IEMTLB_SLOT_FMT ": %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s%s%s%s/%s%s%s%s/%s %s%s\n",
1305 uSlot,
1306 (pTlbe->uTag & IEMTLB_REVISION_MASK) == uTlbRevision ? "valid "
1307 : (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
1308 : "expired",
1309 GCPtr, /* -> */
1310 pTlbe->GCPhys, /* / */ pTlbe->pbMappingR3,
1311 /* / */
1312 (uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
1313 /* */
1314 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "R-" : "RW",
1315 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "-" : "X",
1316 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
1317 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
1318 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_USER ? "U" : "S",
1319 !(uSlot & 1) ? "-" : "G",
1320 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_LARGE_PAGE ? "4K" : "2M",
1321 /* / */
1322 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
1323 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
1324 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "u" : "-",
1325 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_CODE_PAGE ? "c" : "-",
1326 /* / */
1327 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "N" : "M",
1328 (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
1329 : (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired",
1330 pszValid);
1331}
1332
1333
1334/** Displays one or more TLB slots. */
1335static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
1336 uint32_t uSlot, uint32_t cSlots, uint32_t fFlags, bool *pfHeader)
1337{
1338 if (uSlot < RT_ELEMENTS(pTlb->aEntries))
1339 {
1340 if (cSlots > RT_ELEMENTS(pTlb->aEntries))
1341 {
1342 pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
1343 cSlots, RT_ELEMENTS(pTlb->aEntries));
1344 cSlots = RT_ELEMENTS(pTlb->aEntries);
1345 }
1346
1347 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
1348 while (cSlots-- > 0)
1349 {
1350 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
1351 iemR3InfoTlbPrintSlot(pVCpu, pHlp, pTlb, &Tlbe, uSlot, fFlags);
1352 uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
1353 }
1354 }
1355 else
1356 pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
1357 uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
1358}
1359
1360
1361/** Displays the TLB slot for the given address. */
1362static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
1363 uint64_t uAddress, uint32_t fFlags, bool *pfHeader)
1364{
1365 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
1366
1367 uint64_t const uTag = IEMTLB_CALC_TAG_NO_REV(uAddress);
1368#ifdef IEMTLB_TAG_TO_EVEN_INDEX
1369 uint32_t const uSlot = IEMTLB_TAG_TO_EVEN_INDEX(uTag);
1370#else
1371 uint32_t const uSlot = IEMTLB_TAG_TO_INDEX(uTag);
1372#endif
1373 IEMTLBENTRY const TlbeL = pTlb->aEntries[uSlot];
1374#ifndef VBOX_VMM_TARGET_ARMV8
1375 IEMTLBENTRY const TlbeG = pTlb->aEntries[uSlot + 1];
1376#endif
1377 pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
1378 TlbeL.uTag == (uTag | pTlb->uTlbRevision) ? "match"
1379 : (TlbeL.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
1380 iemR3InfoTlbPrintSlot(pVCpu, pHlp, pTlb, &TlbeL, uSlot, fFlags);
1381
1382#ifndef VBOX_VMM_TARGET_ARMV8
1383 pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot + 1,
1384 TlbeG.uTag == (uTag | pTlb->uTlbRevisionGlobal) ? "match"
1385 : (TlbeG.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
1386 iemR3InfoTlbPrintSlot(pVCpu, pHlp, pTlb, &TlbeG, uSlot + 1, fFlags);
1387#endif
1388}
1389
1390
1391/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
1392static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
1393{
1394 /*
1395 * This is entirely argument driven.
1396 */
1397 static RTGETOPTDEF const s_aOptions[] =
1398 {
1399 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1400 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1401 { "--check", 'C', RTGETOPT_REQ_NOTHING },
1402 { "all", 'A', RTGETOPT_REQ_NOTHING },
1403 { "--all", 'A', RTGETOPT_REQ_NOTHING },
1404 { "--address", 'a', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1405 { "--range", 'r', RTGETOPT_REQ_UINT32_PAIR | RTGETOPT_FLAG_HEX },
1406 { "--slot", 's', RTGETOPT_REQ_UINT32 | RTGETOPT_FLAG_HEX },
1407 { "--only-valid", 'v', RTGETOPT_REQ_NOTHING },
1408 };
1409
1410 RTGETOPTSTATE State;
1411 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
1412 AssertRCReturnVoid(rc);
1413
1414 uint32_t cActionArgs = 0;
1415 bool fNeedHeader = true;
1416 bool fAddressMode = true;
1417 uint32_t fFlags = 0;
1418 PVMCPU const pVCpuCall = VMMGetCpu(pVM);
1419 PVMCPU pVCpu = pVCpuCall;
1420 if (!pVCpu)
1421 pVCpu = VMMGetCpuById(pVM, 0);
1422
1423 RTGETOPTUNION ValueUnion;
1424 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1425 {
1426 switch (rc)
1427 {
1428 case 'c':
1429 if (ValueUnion.u32 >= pVM->cCpus)
1430 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1431 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
1432 {
1433 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1434 fNeedHeader = true;
1435 if (!pVCpuCall || pVCpuCall->idCpu != ValueUnion.u32)
1436 {
1437 pHlp->pfnPrintf(pHlp, "info: Can't check guest PTs when switching to a different VCpu! Targetting %u, on %u.\n",
1438 ValueUnion.u32, pVCpuCall->idCpu);
1439 fFlags &= ~IEMR3INFOTLB_F_CHECK;
1440 }
1441 }
1442 break;
1443
1444 case 'C':
1445 if (!pVCpuCall)
1446 pHlp->pfnPrintf(pHlp, "error: Can't check guest PT when not running on an EMT!\n");
1447 else if (pVCpu != pVCpuCall)
1448 pHlp->pfnPrintf(pHlp, "error: Can't check guest PTs when on a different EMT! Targetting %u, on %u.\n",
1449 pVCpu->idCpu, pVCpuCall->idCpu);
1450 else
1451 fFlags |= IEMR3INFOTLB_F_CHECK;
1452 break;
1453
1454 case 'a':
1455 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1456 ValueUnion.u64, fFlags, &fNeedHeader);
1457 fAddressMode = true;
1458 cActionArgs++;
1459 break;
1460
1461 case 'A':
1462 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1463 0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), fFlags, &fNeedHeader);
1464 cActionArgs++;
1465 break;
1466
1467 case 'r':
1468 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1469 ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, fFlags, &fNeedHeader);
1470 fAddressMode = false;
1471 cActionArgs++;
1472 break;
1473
1474 case 's':
1475 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1476 ValueUnion.u32, 1, fFlags, &fNeedHeader);
1477 fAddressMode = false;
1478 cActionArgs++;
1479 break;
1480
1481 case 'v':
1482 fFlags |= IEMR3INFOTLB_F_ONLY_VALID;
1483 break;
1484
1485 case VINF_GETOPT_NOT_OPTION:
1486 if (fAddressMode)
1487 {
1488 uint64_t uAddr;
1489 rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
1490 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
1491 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1492 uAddr, fFlags, &fNeedHeader);
1493 else
1494 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
1495 }
1496 else
1497 {
1498 uint32_t uSlot;
1499 rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
1500 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
1501 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1502 uSlot, 1, fFlags, &fNeedHeader);
1503 else
1504 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
1505 }
1506 cActionArgs++;
1507 break;
1508
1509 case 'h':
1510 pHlp->pfnPrintf(pHlp,
1511 "Usage: info %ctlb [options]\n"
1512 "\n"
1513 "Options:\n"
1514 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
1515 " Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
1516 " -C,--check\n"
1517 " Check valid entries against guest PTs.\n"
1518 " -A, --all, all\n"
1519 " Display all the TLB entries (default if no other args).\n"
1520 " -a<virt>, --address=<virt>\n"
1521 " Shows the TLB entry for the specified guest virtual address.\n"
1522 " -r<slot:count>, --range=<slot:count>\n"
1523 " Shows the TLB entries for the specified slot range.\n"
1524 " -s<slot>,--slot=<slot>\n"
1525 " Shows the given TLB slot.\n"
1526 " -v,--only-valid\n"
1527 " Only show valid TLB entries (TAG, not phys)\n"
1528 "\n"
1529 "Non-options are interpreted according to the last -a, -r or -s option,\n"
1530 "defaulting to addresses if not preceeded by any of those options.\n"
1531 , fITlb ? 'i' : 'd');
1532 return;
1533
1534 default:
1535 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1536 return;
1537 }
1538 }
1539
1540 /*
1541 * If no action taken, we display all (-A) by default.
1542 */
1543 if (!cActionArgs)
1544 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
1545 0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), fFlags, &fNeedHeader);
1546}
1547
1548
1549/**
1550 * @callback_method_impl{FNDBGFINFOARGVINT, itlb}
1551 */
1552static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1553{
1554 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /*fITlb*/);
1555}
1556
1557
1558/**
1559 * @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
1560 */
1561static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1562{
1563 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /*fITlb*/);
1564}
1565
1566
1567#ifdef IEM_WITH_TLB_TRACE
1568/**
1569 * @callback_method_impl{FNDBGFINFOARGVINT, tlbtrace}
1570 */
1571static DECLCALLBACK(void) iemR3InfoTlbTrace(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1572{
1573 /*
1574 * Parse arguments.
1575 */
1576 static RTGETOPTDEF const s_aOptions[] =
1577 {
1578 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1579 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1580 { "--last", 'l', RTGETOPT_REQ_UINT32 },
1581 { "--limit", 'l', RTGETOPT_REQ_UINT32 },
1582 { "--stop-at-global-flush", 'g', RTGETOPT_REQ_NOTHING },
1583 { "--resolve-rip", 'r', RTGETOPT_REQ_NOTHING },
1584 };
1585
1586 RTGETOPTSTATE State;
1587 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
1588 AssertRCReturnVoid(rc);
1589
1590 uint32_t cLimit = UINT32_MAX;
1591 bool fStopAtGlobalFlush = false;
1592 bool fResolveRip = false;
1593 PVMCPU const pVCpuCall = VMMGetCpu(pVM);
1594 PVMCPU pVCpu = pVCpuCall;
1595 if (!pVCpu)
1596 pVCpu = VMMGetCpuById(pVM, 0);
1597
1598 RTGETOPTUNION ValueUnion;
1599 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1600 {
1601 switch (rc)
1602 {
1603 case 'c':
1604 if (ValueUnion.u32 >= pVM->cCpus)
1605 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1606 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
1607 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1608 break;
1609
1610 case 'l':
1611 cLimit = ValueUnion.u32;
1612 break;
1613
1614 case 'g':
1615 fStopAtGlobalFlush = true;
1616 break;
1617
1618 case 'r':
1619 fResolveRip = true;
1620 break;
1621
1622 case 'h':
1623 pHlp->pfnPrintf(pHlp,
1624 "Usage: info tlbtrace [options] [n]\n"
1625 "\n"
1626 "Options:\n"
1627 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
1628 " Selects the CPU which TLB trace we're looking at. Default: Caller / 0\n"
1629 " [n], -l<n>, --last=<n>\n"
1630 " Limit display to the last N entries. Default: all\n"
1631 " -g, --stop-at-global-flush\n"
1632 " Stop after the first global flush entry.\n"
1633 " -r, --resolve-rip\n"
1634 " Resolve symbols for the flattened RIP addresses.\n"
1635 );
1636 return;
1637
1638 case VINF_GETOPT_NOT_OPTION:
1639 rc = RTStrToUInt32Full(ValueUnion.psz, 0, &cLimit);
1640 if (RT_SUCCESS(rc))
1641 break;
1642 pHlp->pfnPrintf(pHlp, "error: failed to convert '%s' to a number: %Rrc\n", ValueUnion.psz, rc);
1643 return;
1644
1645 default:
1646 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1647 return;
1648 }
1649 }
1650
1651 /*
1652 * Get the details.
1653 */
1654 AssertReturnVoid(pVCpu);
1655 Assert(pVCpu->iem.s.cTlbTraceEntriesShift <= 28);
1656 uint32_t idx = pVCpu->iem.s.idxTlbTraceEntry;
1657 uint32_t const cShift = RT_MIN(pVCpu->iem.s.cTlbTraceEntriesShift, 28);
1658 uint32_t const fMask = RT_BIT_32(cShift) - 1;
1659 uint32_t cLeft = RT_MIN(RT_MIN(idx, RT_BIT_32(cShift)), cLimit);
1660 PCIEMTLBTRACEENTRY paEntries = pVCpu->iem.s.paTlbTraceEntries;
1661 if (cLeft && paEntries)
1662 {
1663 /*
1664 * Display the entries.
1665 */
1666 pHlp->pfnPrintf(pHlp, "TLB Trace for CPU %u:\n", pVCpu->idCpu);
1667 while (cLeft-- > 0)
1668 {
1669 PCIEMTLBTRACEENTRY const pCur = &paEntries[--idx & fMask];
1670 const char *pszSymbol = "";
1671 union
1672 {
1673 RTDBGSYMBOL Symbol;
1674 char ach[sizeof(RTDBGSYMBOL) + 32];
1675 } uBuf;
1676 if (fResolveRip)
1677 {
1678 RTGCINTPTR offDisp = 0;
1679 DBGFADDRESS Addr;
1680 rc = DBGFR3AsSymbolByAddr(pVM->pUVM, DBGF_AS_GLOBAL, DBGFR3AddrFromFlat(pVM->pUVM, &Addr, pCur->rip),
1681 RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL
1682 | RTDBGSYMADDR_FLAGS_SKIP_ABS
1683 | RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
1684 &offDisp, &uBuf.Symbol, NULL);
1685 if (RT_SUCCESS(rc))
1686 {
1687 /* Add displacement. */
1688 if (offDisp)
1689 {
1690 size_t const cchName = strlen(uBuf.Symbol.szName);
1691 char * const pszEndName = &uBuf.Symbol.szName[cchName];
1692 size_t const cbLeft = sizeof(uBuf) - sizeof(uBuf.Symbol) + sizeof(uBuf.Symbol.szName) - cchName;
1693 if (offDisp > 0)
1694 RTStrPrintf(pszEndName, cbLeft, "+%#1RGv", offDisp);
1695 else
1696 RTStrPrintf(pszEndName, cbLeft, "-%#1RGv", -offDisp);
1697 }
1698
1699 /* Put a space before it. */
1700 AssertCompile(RTASSERT_OFFSET_OF(RTDBGSYMBOL, szName) > 0);
1701 char *pszName = uBuf.Symbol.szName;
1702 *--pszName = ' ';
1703 pszSymbol = pszName;
1704 }
1705 }
1706 static const char *s_apszTlbType[2] = { "code", "data" };
1707 static const char *s_apszScanType[4] = { "skipped", "global", "non-global", "both" };
1708 switch (pCur->enmType)
1709 {
1710 case kIemTlbTraceType_InvlPg:
1711 pHlp->pfnPrintf(pHlp, "%u: %016RX64 invlpg %RGv slot=" IEMTLB_SLOT_FMT "%s\n", idx, pCur->rip,
1712 pCur->u64Param, (uint32_t)IEMTLB_ADDR_TO_EVEN_INDEX(pCur->u64Param), pszSymbol);
1713 break;
1714 case kIemTlbTraceType_EvictSlot:
1715 pHlp->pfnPrintf(pHlp, "%u: %016RX64 evict %s slot=" IEMTLB_SLOT_FMT " %RGv (%#RX64) gcphys=%RGp%s\n",
1716 idx, pCur->rip, s_apszTlbType[pCur->bParam & 1], pCur->u32Param,
1717 (RTGCINTPTR)((pCur->u64Param & ~IEMTLB_REVISION_MASK) << (64 - IEMTLB_TAG_ADDR_WIDTH))
1718 >> (64 - IEMTLB_TAG_ADDR_WIDTH - GUEST_PAGE_SHIFT), pCur->u64Param,
1719 pCur->u64Param2, pszSymbol);
1720 break;
1721 case kIemTlbTraceType_LargeEvictSlot:
1722 pHlp->pfnPrintf(pHlp, "%u: %016RX64 large evict %s slot=" IEMTLB_SLOT_FMT " %RGv (%#RX64) gcphys=%RGp%s\n",
1723 idx, pCur->rip, s_apszTlbType[pCur->bParam & 1], pCur->u32Param,
1724 (RTGCINTPTR)((pCur->u64Param & ~IEMTLB_REVISION_MASK) << (64 - IEMTLB_TAG_ADDR_WIDTH))
1725 >> (64 - IEMTLB_TAG_ADDR_WIDTH - GUEST_PAGE_SHIFT), pCur->u64Param,
1726 pCur->u64Param2, pszSymbol);
1727 break;
1728 case kIemTlbTraceType_LargeScan:
1729 pHlp->pfnPrintf(pHlp, "%u: %016RX64 large scan %s %s%s\n", idx, pCur->rip, s_apszTlbType[pCur->bParam & 1],
1730 s_apszScanType[pCur->u32Param & 3], pszSymbol);
1731 break;
1732
1733 case kIemTlbTraceType_Flush:
1734 pHlp->pfnPrintf(pHlp, "%u: %016RX64 flush %s rev=%#RX64%s\n", idx, pCur->rip,
1735 s_apszTlbType[pCur->bParam & 1], pCur->u64Param, pszSymbol);
1736 break;
1737 case kIemTlbTraceType_FlushGlobal:
1738 pHlp->pfnPrintf(pHlp, "%u: %016RX64 flush %s rev=%#RX64 grev=%#RX64%s\n", idx, pCur->rip,
1739 s_apszTlbType[pCur->bParam & 1], pCur->u64Param, pCur->u64Param2, pszSymbol);
1740 if (fStopAtGlobalFlush)
1741 return;
1742 break;
1743 case kIemTlbTraceType_Load:
1744 case kIemTlbTraceType_LoadGlobal:
1745 pHlp->pfnPrintf(pHlp, "%u: %016RX64 %cload %s %RGv slot=" IEMTLB_SLOT_FMT " gcphys=%RGp fTlb=%#RX32%s\n",
1746 idx, pCur->rip,
1747 pCur->enmType == kIemTlbTraceType_LoadGlobal ? 'g' : 'l', s_apszTlbType[pCur->bParam & 1],
1748 pCur->u64Param,
1749 (uint32_t)IEMTLB_ADDR_TO_EVEN_INDEX(pCur->u64Param)
1750 | (pCur->enmType == kIemTlbTraceType_LoadGlobal),
1751 (RTGCPTR)pCur->u64Param2, pCur->u32Param, pszSymbol);
1752 break;
1753
1754 case kIemTlbTraceType_Load_Cr0:
1755 pHlp->pfnPrintf(pHlp, "%u: %016RX64 load cr0 %08RX64 (was %08RX64)%s\n",
1756 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1757 break;
1758 case kIemTlbTraceType_Load_Cr3:
1759 pHlp->pfnPrintf(pHlp, "%u: %016RX64 load cr3 %016RX64 (was %016RX64)%s\n",
1760 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1761 break;
1762 case kIemTlbTraceType_Load_Cr4:
1763 pHlp->pfnPrintf(pHlp, "%u: %016RX64 load cr4 %08RX64 (was %08RX64)%s\n",
1764 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1765 break;
1766 case kIemTlbTraceType_Load_Efer:
1767 pHlp->pfnPrintf(pHlp, "%u: %016RX64 load efer %016RX64 (was %016RX64)%s\n",
1768 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pszSymbol);
1769 break;
1770
1771 case kIemTlbTraceType_Irq:
1772 pHlp->pfnPrintf(pHlp, "%u: %016RX64 irq %#04x flags=%#x eflboth=%#RX64%s\n",
1773 idx, pCur->rip, pCur->bParam, pCur->u32Param,
1774 pCur->u64Param & ((RT_BIT_64(CPUMX86EFLAGS_HW_BITS) - 1) | CPUMX86EFLAGS_INT_MASK_64),
1775 pszSymbol);
1776 break;
1777 case kIemTlbTraceType_Xcpt:
1778 if (pCur->u32Param & IEM_XCPT_FLAGS_CR2)
1779 pHlp->pfnPrintf(pHlp, "%u: %016RX64 xcpt %#04x flags=%#x errcd=%#x cr2=%RX64%s\n",
1780 idx, pCur->rip, pCur->bParam, pCur->u32Param, pCur->u64Param, pCur->u64Param2, pszSymbol);
1781 else if (pCur->u32Param & IEM_XCPT_FLAGS_ERR)
1782 pHlp->pfnPrintf(pHlp, "%u: %016RX64 xcpt %#04x flags=%#x errcd=%#x%s\n",
1783 idx, pCur->rip, pCur->bParam, pCur->u32Param, pCur->u64Param, pszSymbol);
1784 else
1785 pHlp->pfnPrintf(pHlp, "%u: %016RX64 xcpt %#04x flags=%#x%s\n",
1786 idx, pCur->rip, pCur->bParam, pCur->u32Param, pszSymbol);
1787 break;
1788 case kIemTlbTraceType_IRet:
1789 pHlp->pfnPrintf(pHlp, "%u: %016RX64 iret cs:rip=%04x:%016RX64 efl=%08RX32%s\n",
1790 idx, pCur->rip, pCur->u32Param, pCur->u64Param, (uint32_t)pCur->u64Param2, pszSymbol);
1791 break;
1792
1793 case kIemTlbTraceType_Tb_Compile:
1794 pHlp->pfnPrintf(pHlp, "%u: %016RX64 tb comp GCPhysPc=%012RX64%s\n",
1795 idx, pCur->rip, pCur->u64Param, pszSymbol);
1796 break;
1797 case kIemTlbTraceType_Tb_Exec_Threaded:
1798 pHlp->pfnPrintf(pHlp, "%u: %016RX64 tb thrd GCPhysPc=%012RX64 tb=%p used=%u%s\n",
1799 idx, pCur->rip, pCur->u64Param, (uintptr_t)pCur->u64Param2, pCur->u32Param, pszSymbol);
1800 break;
1801 case kIemTlbTraceType_Tb_Exec_Native:
1802 pHlp->pfnPrintf(pHlp, "%u: %016RX64 tb n8ve GCPhysPc=%012RX64 tb=%p used=%u%s\n",
1803 idx, pCur->rip, pCur->u64Param, (uintptr_t)pCur->u64Param2, pCur->u32Param, pszSymbol);
1804 break;
1805
1806 case kIemTlbTraceType_User0:
1807 pHlp->pfnPrintf(pHlp, "%u: %016RX64 user0 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1808 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1809 break;
1810 case kIemTlbTraceType_User1:
1811 pHlp->pfnPrintf(pHlp, "%u: %016RX64 user1 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1812 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1813 break;
1814 case kIemTlbTraceType_User2:
1815 pHlp->pfnPrintf(pHlp, "%u: %016RX64 user2 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1816 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1817 break;
1818 case kIemTlbTraceType_User3:
1819 pHlp->pfnPrintf(pHlp, "%u: %016RX64 user3 %016RX64 %016RX64 %08RX32 %02RX8%s\n",
1820 idx, pCur->rip, pCur->u64Param, pCur->u64Param2, pCur->u32Param, pCur->bParam, pszSymbol);
1821 break;
1822
1823 case kIemTlbTraceType_Invalid:
1824 pHlp->pfnPrintf(pHlp, "%u: Invalid!\n");
1825 break;
1826 }
1827 }
1828 }
1829 else
1830 pHlp->pfnPrintf(pHlp, "No trace entries to display\n");
1831}
1832#endif /* IEM_WITH_TLB_TRACE */
1833
1834#if defined(VBOX_WITH_IEM_RECOMPILER) && !defined(VBOX_VMM_TARGET_ARMV8)
1835
1836/**
1837 * Get get compile time flat PC for the TB.
1838 */
1839DECL_FORCE_INLINE(RTGCPTR) iemR3GetTbFlatPc(PCIEMTB pTb)
1840{
1841#ifdef IEMNATIVE_WITH_TB_DEBUG_INFO
1842 if (pTb->fFlags & IEMTB_F_TYPE_NATIVE)
1843 {
1844 PCIEMTBDBG const pDbgInfo = pTb->pDbgInfo;
1845 return pDbgInfo ? pDbgInfo->FlatPc : RTGCPTR_MAX;
1846 }
1847#endif
1848 return pTb->FlatPc;
1849}
1850
1851
1852/**
1853 * @callback_method_impl{FNDBGFINFOARGVINT, tb}
1854 */
1855static DECLCALLBACK(void) iemR3InfoTb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
1856{
1857 /*
1858 * Parse arguments.
1859 */
1860 static RTGETOPTDEF const s_aOptions[] =
1861 {
1862 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
1863 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
1864 { "--addr", 'a', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1865 { "--address", 'a', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1866 { "--phys", 'p', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1867 { "--physical", 'p', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1868 { "--phys-addr", 'p', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1869 { "--phys-address", 'p', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1870 { "--physical-address", 'p', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
1871 { "--flags", 'f', RTGETOPT_REQ_UINT32 | RTGETOPT_FLAG_HEX },
1872 { "--tb", 't', RTGETOPT_REQ_UINT32 | RTGETOPT_FLAG_HEX },
1873 { "--tb-id", 't', RTGETOPT_REQ_UINT32 },
1874 };
1875
1876 RTGETOPTSTATE State;
1877 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
1878 AssertRCReturnVoid(rc);
1879
1880 PVMCPU const pVCpuThis = VMMGetCpu(pVM);
1881 PVMCPU pVCpu = pVCpuThis ? pVCpuThis : VMMGetCpuById(pVM, 0);
1882 RTGCPHYS GCPhysPc = NIL_RTGCPHYS;
1883 RTGCPHYS GCVirt = NIL_RTGCPTR;
1884 uint32_t fFlags = UINT32_MAX;
1885 uint32_t idTb = UINT32_MAX;
1886
1887 RTGETOPTUNION ValueUnion;
1888 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
1889 {
1890 switch (rc)
1891 {
1892 case 'c':
1893 if (ValueUnion.u32 >= pVM->cCpus)
1894 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
1895 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
1896 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
1897 break;
1898
1899 case 'a':
1900 GCVirt = ValueUnion.u64;
1901 GCPhysPc = NIL_RTGCPHYS;
1902 idTb = UINT32_MAX;
1903 break;
1904
1905 case 'p':
1906 GCVirt = NIL_RTGCPHYS;
1907 GCPhysPc = ValueUnion.u64;
1908 idTb = UINT32_MAX;
1909 break;
1910
1911 case 'f':
1912 fFlags = ValueUnion.u32;
1913 break;
1914
1915 case 't':
1916 GCVirt = NIL_RTGCPHYS;
1917 GCPhysPc = NIL_RTGCPHYS;
1918 idTb = ValueUnion.u32;
1919 break;
1920
1921 case VINF_GETOPT_NOT_OPTION:
1922 {
1923 if ( (ValueUnion.psz[0] == 'T' || ValueUnion.psz[0] == 't')
1924 && (ValueUnion.psz[1] == 'B' || ValueUnion.psz[1] == 'b')
1925 && ValueUnion.psz[2] == '#')
1926 {
1927 rc = RTStrToUInt32Full(&ValueUnion.psz[3], 0, &idTb);
1928 if (RT_SUCCESS(rc))
1929 {
1930 GCVirt = NIL_RTGCPHYS;
1931 GCPhysPc = NIL_RTGCPHYS;
1932 break;
1933 }
1934 pHlp->pfnPrintf(pHlp, "error: failed to convert '%s' to TD ID: %Rrc\n", ValueUnion.psz, rc);
1935 }
1936 else
1937 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1938 return;
1939 }
1940
1941 case 'h':
1942 pHlp->pfnPrintf(pHlp,
1943 "Usage: info tb [options]\n"
1944 "\n"
1945 "Options:\n"
1946 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
1947 " Selects the CPU which TBs we're looking at. Default: Caller / 0\n"
1948 " -a<virt>, --address=<virt>\n"
1949 " Shows the TB for the specified guest virtual address.\n"
1950 " -p<phys>, --phys=<phys>, --phys-addr=<phys>\n"
1951 " Shows the TB for the specified guest physical address.\n"
1952 " -t<id>, --tb=<id>, --tb-id=<id>, TD#<id>\n"
1953 " Show the TB specified by the identifier/number (from tbtop).\n"
1954 " -f<flags>,--flags=<flags>\n"
1955 " The TB flags value (hex) to use when looking up the TB.\n"
1956 "\n"
1957 "The default is to use CS:RIP and derive flags from the CPU mode.\n");
1958 return;
1959
1960 default:
1961 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
1962 return;
1963 }
1964 }
1965
1966 /* Currently, only do work on the same EMT. */
1967 if (pVCpu != pVCpuThis)
1968 {
1969 pHlp->pfnPrintf(pHlp, "TODO: Cross EMT calling not supported yet: targeting %u, caller on %d\n",
1970 pVCpu->idCpu, pVCpuThis ? (int)pVCpuThis->idCpu : -1);
1971 return;
1972 }
1973
1974 /*
1975 * Defaults.
1976 */
1977 if (GCPhysPc == NIL_RTGCPHYS && idTb == UINT32_MAX)
1978 {
1979 if (GCVirt == NIL_RTGCPTR)
1980 GCVirt = CPUMGetGuestFlatPC(pVCpu);
1981 rc = PGMPhysGCPtr2GCPhys(pVCpu, GCVirt, &GCPhysPc);
1982 if (RT_FAILURE(rc))
1983 {
1984 pHlp->pfnPrintf(pHlp, "Failed to convert %%%RGv to an guest physical address: %Rrc\n", GCVirt, rc);
1985 return;
1986 }
1987 }
1988 if (fFlags == UINT32_MAX && idTb == UINT32_MAX)
1989 {
1990 /* Note! This is duplicating code in IEMAllThrdRecompiler. */
1991 fFlags = iemCalcExecFlags(pVCpu);
1992 if (pVM->cCpus == 1)
1993 fFlags |= IEM_F_X86_DISREGARD_LOCK;
1994 if (CPUMIsInInterruptShadow(&pVCpu->cpum.GstCtx))
1995 fFlags |= IEMTB_F_INHIBIT_SHADOW;
1996 if (CPUMAreInterruptsInhibitedByNmiEx(&pVCpu->cpum.GstCtx))
1997 fFlags |= IEMTB_F_INHIBIT_NMI;
1998 if ((IEM_F_MODE_CPUMODE_MASK & fFlags) != IEMMODE_64BIT)
1999 {
2000 int64_t const offFromLim = (int64_t)pVCpu->cpum.GstCtx.cs.u32Limit - (int64_t)pVCpu->cpum.GstCtx.eip;
2001 if (offFromLim < X86_PAGE_SIZE + 16 - (int32_t)(pVCpu->cpum.GstCtx.cs.u64Base & GUEST_PAGE_OFFSET_MASK))
2002 fFlags |= IEMTB_F_CS_LIM_CHECKS;
2003 }
2004 }
2005
2006 PCIEMTB pTb;
2007 if (idTb == UINT32_MAX)
2008 {
2009 /*
2010 * Do the lookup...
2011 *
2012 * Note! This is also duplicating code in IEMAllThrdRecompiler. We don't
2013 * have much choice since we don't want to increase use counters and
2014 * trigger native recompilation.
2015 */
2016 fFlags &= IEMTB_F_KEY_MASK;
2017 IEMTBCACHE const * const pTbCache = pVCpu->iem.s.pTbCacheR3;
2018 uint32_t const idxHash = IEMTBCACHE_HASH(pTbCache, fFlags, GCPhysPc);
2019 pTb = IEMTBCACHE_PTR_GET_TB(pTbCache->apHash[idxHash]);
2020 while (pTb)
2021 {
2022 if (pTb->GCPhysPc == GCPhysPc)
2023 {
2024 if ((pTb->fFlags & IEMTB_F_KEY_MASK) == fFlags)
2025 {
2026 /// @todo if (pTb->x86.fAttr == (uint16_t)pVCpu->cpum.GstCtx.cs.Attr.u)
2027 break;
2028 }
2029 }
2030 pTb = pTb->pNext;
2031 }
2032 if (!pTb)
2033 pHlp->pfnPrintf(pHlp, "PC=%RGp fFlags=%#x - no TB found on #%u\n", GCPhysPc, fFlags, pVCpu->idCpu);
2034 }
2035 else
2036 {
2037 /*
2038 * Use the TB ID for indexing.
2039 */
2040 pTb = NULL;
2041 PIEMTBALLOCATOR const pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
2042 if (pTbAllocator)
2043 {
2044 size_t const idxTbChunk = idTb / pTbAllocator->cTbsPerChunk;
2045 size_t const idxTbInChunk = idTb % pTbAllocator->cTbsPerChunk;
2046 if (idxTbChunk < pTbAllocator->cAllocatedChunks)
2047 pTb = &pTbAllocator->aChunks[idxTbChunk].paTbs[idxTbInChunk];
2048 else
2049 pHlp->pfnPrintf(pHlp, "Invalid TB ID: %u (%#x)\n", idTb, idTb);
2050 }
2051 }
2052
2053 if (pTb)
2054 {
2055 /*
2056 * Disassemble according to type.
2057 */
2058 size_t const idxTbChunk = pTb->idxAllocChunk;
2059 size_t const idxTbNo = (pTb - &pVCpu->iem.s.pTbAllocatorR3->aChunks[idxTbChunk].paTbs[0])
2060 + idxTbChunk * pVCpu->iem.s.pTbAllocatorR3->cTbsPerChunk;
2061 switch (pTb->fFlags & IEMTB_F_TYPE_MASK)
2062 {
2063# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
2064 case IEMTB_F_TYPE_NATIVE:
2065 pHlp->pfnPrintf(pHlp, "PC=%RGp (%%%RGv) fFlags=%#x on #%u: TB#%#zx/%p - native\n",
2066 GCPhysPc, iemR3GetTbFlatPc(pTb), fFlags, pVCpu->idCpu, idxTbNo, pTb);
2067 iemNativeDisassembleTb(pVCpu, pTb, pHlp);
2068 break;
2069# endif
2070
2071 case IEMTB_F_TYPE_THREADED:
2072 pHlp->pfnPrintf(pHlp, "PC=%RGp (%%%RGv) fFlags=%#x on #%u: TB#%#zx/%p - threaded\n",
2073 GCPhysPc, pTb->FlatPc, fFlags, pVCpu->idCpu, idxTbNo, pTb);
2074 iemThreadedDisassembleTb(pTb, pHlp);
2075 break;
2076
2077 default:
2078 pHlp->pfnPrintf(pHlp, "PC=%RGp (%%%RGv) fFlags=%#x on #%u: TB#%#zx/%p - ??? %#x\n",
2079 GCPhysPc, pTb->FlatPc, fFlags, pVCpu->idCpu, idxTbNo, pTb, pTb->fFlags);
2080 break;
2081 }
2082 }
2083}
2084
2085
2086/**
2087 * @callback_method_impl{FNDBGFINFOARGVINT, tbtop}
2088 */
2089static DECLCALLBACK(void) iemR3InfoTbTop(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
2090{
2091 /*
2092 * Parse arguments.
2093 */
2094 static RTGETOPTDEF const s_aOptions[] =
2095 {
2096 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
2097 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
2098 { "--dis", 'd', RTGETOPT_REQ_NOTHING },
2099 { "--disas", 'd', RTGETOPT_REQ_NOTHING },
2100 { "--disasm", 'd', RTGETOPT_REQ_NOTHING },
2101 { "--disassemble", 'd', RTGETOPT_REQ_NOTHING },
2102 { "--no-dis", 'D', RTGETOPT_REQ_NOTHING },
2103 { "--no-disas", 'D', RTGETOPT_REQ_NOTHING },
2104 { "--no-disasm", 'D', RTGETOPT_REQ_NOTHING },
2105 { "--no-disassemble", 'D', RTGETOPT_REQ_NOTHING },
2106 { "--most-freq", 'f', RTGETOPT_REQ_NOTHING },
2107 { "--most-frequent", 'f', RTGETOPT_REQ_NOTHING },
2108 { "--most-frequently", 'f', RTGETOPT_REQ_NOTHING },
2109 { "--most-frequently-used", 'f', RTGETOPT_REQ_NOTHING },
2110 { "--most-recent", 'r', RTGETOPT_REQ_NOTHING },
2111 { "--most-recently", 'r', RTGETOPT_REQ_NOTHING },
2112 { "--most-recently-used", 'r', RTGETOPT_REQ_NOTHING },
2113 { "--count", 'n', RTGETOPT_REQ_UINT32 },
2114 };
2115
2116 RTGETOPTSTATE State;
2117 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
2118 AssertRCReturnVoid(rc);
2119
2120 PVMCPU const pVCpuThis = VMMGetCpu(pVM);
2121 PVMCPU pVCpu = pVCpuThis ? pVCpuThis : VMMGetCpuById(pVM, 0);
2122 enum { kTbTop_MostFrequentlyUsed, kTbTop_MostRececentlyUsed }
2123 enmTop = kTbTop_MostFrequentlyUsed;
2124 bool fDisassemble = false;
2125 uint32_t const cTopDefault = 64;
2126 uint32_t const cTopMin = 1;
2127 uint32_t const cTopMax = 1024;
2128 uint32_t cTop = cTopDefault;
2129
2130 RTGETOPTUNION ValueUnion;
2131 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
2132 {
2133 switch (rc)
2134 {
2135 case 'c':
2136 if (ValueUnion.u32 >= pVM->cCpus)
2137 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
2138 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
2139 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
2140 break;
2141
2142 case 'd':
2143 fDisassemble = true;
2144 break;
2145
2146 case 'D':
2147 fDisassemble = true;
2148 break;
2149
2150 case 'f':
2151 enmTop = kTbTop_MostFrequentlyUsed;
2152 break;
2153
2154 case 'r':
2155 enmTop = kTbTop_MostRececentlyUsed;
2156 break;
2157
2158 case VINF_GETOPT_NOT_OPTION:
2159 rc = RTStrToUInt32Full(ValueUnion.psz, 0, &cTop);
2160 if (RT_FAILURE(rc))
2161 {
2162 pHlp->pfnPrintf(pHlp, "error: failed to convert '%s' to a number: %Rrc\n", ValueUnion.psz, rc);
2163 return;
2164 }
2165 ValueUnion.u32 = cTop;
2166 RT_FALL_THROUGH();
2167 case 'n':
2168 if (!ValueUnion.u32)
2169 cTop = cTopDefault;
2170 else
2171 {
2172 cTop = RT_MAX(RT_MIN(ValueUnion.u32, cTopMax), cTopMin);
2173 if (cTop != ValueUnion.u32)
2174 pHlp->pfnPrintf(pHlp, "warning: adjusted %u to %u (valid range: [%u..%u], 0 for default (%d))",
2175 ValueUnion.u32, cTop, cTopMin, cTopMax, cTopDefault);
2176 }
2177 break;
2178
2179 case 'h':
2180 pHlp->pfnPrintf(pHlp,
2181 "Usage: info tbtop [options]\n"
2182 "\n"
2183 "Options:\n"
2184 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
2185 " Selects the CPU which TBs we're looking at. Default: Caller / 0\n"
2186 " -d, --dis[as[m]], --disassemble\n"
2187 " Show full TB disassembly.\n"
2188 " -D, --no-dis[as[m]], --no-disassemble\n"
2189 " Do not show TB diassembly. The default.\n"
2190 " -f, --most-freq[ent[ly[-used]]]\n"
2191 " Shows the most frequently used TBs (IEMTB::cUsed). The default.\n"
2192 " -r, --most-recent[ly[-used]]\n"
2193 " Shows the most recently used TBs (IEMTB::msLastUsed).\n"
2194 " -n<num>, --count=<num>\n"
2195 " The number of TBs to display. Default: %u\n"
2196 " This is also what non-option arguments will be taken as.\n"
2197 , cTopDefault);
2198 return;
2199
2200 default:
2201 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
2202 return;
2203 }
2204 }
2205
2206 /* Currently, only do work on the same EMT. */
2207 if (pVCpu != pVCpuThis)
2208 {
2209 pHlp->pfnPrintf(pHlp, "TODO: Cross EMT calling not supported yet: targeting %u, caller on %d\n",
2210 pVCpu->idCpu, pVCpuThis ? (int)pVCpuThis->idCpu : -1);
2211 return;
2212 }
2213
2214 /*
2215 * Collect the data by scanning the TB allocation map.
2216 */
2217 struct IEMTBTOPENTRY
2218 {
2219 /** Pointer to the translation block. */
2220 PCIEMTB pTb;
2221 /** The sorting key. */
2222 uint64_t uSortKey;
2223 } aTop[cTopMax] = { { NULL, 0 }, };
2224 uint32_t cValid = 0;
2225 PIEMTBALLOCATOR pTbAllocator = pVCpu->iem.s.pTbAllocatorR3;
2226 if (pTbAllocator)
2227 {
2228 uint32_t const cTbsPerChunk = pTbAllocator->cTbsPerChunk;
2229 for (uint32_t iChunk = 0; iChunk < pTbAllocator->cAllocatedChunks; iChunk++)
2230 {
2231 for (uint32_t iTb = 0; iTb < cTbsPerChunk; iTb++)
2232 {
2233 PCIEMTB const pTb = &pTbAllocator->aChunks[iChunk].paTbs[iTb];
2234 AssertContinue(pTb);
2235 if (pTb->fFlags & IEMTB_F_TYPE_MASK)
2236 {
2237 /* Extract and compose the sort key. */
2238 uint64_t const uSortKey = enmTop == kTbTop_MostFrequentlyUsed
2239 ? RT_MAKE_U64(pTb->msLastUsed, pTb->cUsed)
2240 : RT_MAKE_U64(pTb->cUsed, pTb->msLastUsed);
2241
2242 /*
2243 * Discard the key if it's smaller than the smallest in the table when it is full.
2244 */
2245 if ( cValid >= cTop
2246 && uSortKey <= aTop[cTop - 1].uSortKey)
2247 { /* discard it */ }
2248 else
2249 {
2250 /*
2251 * Do binary search to find the insert location
2252 */
2253 uint32_t idx;
2254 if (cValid > 0)
2255 {
2256 uint32_t idxEnd = cValid;
2257 uint32_t idxStart = 0;
2258 idx = cValid / 2;
2259 for (;;)
2260 {
2261 if (uSortKey > aTop[idx].uSortKey)
2262 {
2263 if (idx > idxStart)
2264 idxEnd = idx;
2265 else
2266 break;
2267 }
2268 else if (uSortKey < aTop[idx].uSortKey)
2269 {
2270 idx += 1;
2271 if (idx < idxEnd)
2272 idxStart = idx;
2273 else
2274 break;
2275 }
2276 else
2277 {
2278 do
2279 idx++;
2280 while (idx < cValid && uSortKey == aTop[idx].uSortKey);
2281 break;
2282 }
2283 idx = idxStart + (idxEnd - idxStart) / 2;
2284 }
2285 AssertContinue(idx < RT_ELEMENTS(aTop));
2286
2287 /*
2288 * Shift entries as needed.
2289 */
2290 if (cValid >= cTop)
2291 {
2292 if (idx != cTop - 1U)
2293 memmove(&aTop[idx + 1], &aTop[idx], (cTop - idx - 1) * sizeof(aTop[0]));
2294 }
2295 else
2296 {
2297 if (idx != cValid)
2298 memmove(&aTop[idx + 1], &aTop[idx], (cValid - idx) * sizeof(aTop[0]));
2299 cValid++;
2300 }
2301 }
2302 else
2303 {
2304 /* Special case: The first insertion. */
2305 cValid = 1;
2306 idx = 0;
2307 }
2308
2309 /*
2310 * Fill in the new entry.
2311 */
2312 aTop[idx].uSortKey = uSortKey;
2313 aTop[idx].pTb = pTb;
2314 }
2315 }
2316 }
2317 }
2318 }
2319
2320 /*
2321 * Display the result.
2322 */
2323 if (cTop > cValid)
2324 cTop = cValid;
2325 pHlp->pfnPrintf(pHlp, "Displaying the top %u TBs for CPU #%u ordered by %s:\n",
2326 cTop, pVCpu->idCpu, enmTop == kTbTop_MostFrequentlyUsed ? "cUsed" : "msLastUsed");
2327 if (fDisassemble)
2328 pHlp->pfnPrintf(pHlp, "================================================================================\n");
2329
2330 for (uint32_t idx = 0; idx < cTop; idx++)
2331 {
2332 if (fDisassemble && idx)
2333 pHlp->pfnPrintf(pHlp, "\n------------------------------- %u -------------------------------\n", idx);
2334
2335 PCIEMTB const pTb = aTop[idx].pTb;
2336 size_t const idxTbChunk = pTb->idxAllocChunk;
2337 Assert(idxTbChunk < pTbAllocator->cAllocatedChunks);
2338 size_t const idxTbNo = (pTb - &pTbAllocator->aChunks[idxTbChunk].paTbs[0])
2339 + idxTbChunk * pTbAllocator->cTbsPerChunk;
2340 switch (pTb->fFlags & IEMTB_F_TYPE_MASK)
2341 {
2342# ifdef VBOX_WITH_IEM_NATIVE_RECOMPILER
2343 case IEMTB_F_TYPE_NATIVE:
2344 pHlp->pfnPrintf(pHlp, "TB#%#zx: PC=%RGp (%%%RGv) cUsed=%u msLastUsed=%u fFlags=%#010x - native\n",
2345 idxTbNo, pTb->GCPhysPc, iemR3GetTbFlatPc(pTb), pTb->cUsed, pTb->msLastUsed, pTb->fFlags);
2346 if (fDisassemble)
2347 iemNativeDisassembleTb(pVCpu, pTb, pHlp);
2348 break;
2349# endif
2350
2351 case IEMTB_F_TYPE_THREADED:
2352 pHlp->pfnPrintf(pHlp, "TB#%#zx: PC=%RGp (%%%RGv) cUsed=%u msLastUsed=%u fFlags=%#010x - threaded\n",
2353 idxTbNo, pTb->GCPhysPc, pTb->FlatPc, pTb->cUsed, pTb->msLastUsed, pTb->fFlags);
2354 if (fDisassemble)
2355 iemThreadedDisassembleTb(pTb, pHlp);
2356 break;
2357
2358 default:
2359 pHlp->pfnPrintf(pHlp, "TB#%#zx: PC=%RGp (%%%RGv) cUsed=%u msLastUsed=%u fFlags=%#010x - ???\n",
2360 idxTbNo, pTb->GCPhysPc, pTb->FlatPc, pTb->cUsed, pTb->msLastUsed, pTb->fFlags);
2361 break;
2362 }
2363 }
2364}
2365
2366#endif /* VBOX_WITH_IEM_RECOMPILER && !VBOX_VMM_TARGET_ARMV8 */
2367
2368
2369#ifdef VBOX_WITH_DEBUGGER
2370
2371/** @callback_method_impl{FNDBGCCMD,
2372 * Implements the '.alliem' command. }
2373 */
2374static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
2375{
2376 VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
2377 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
2378 if (pVCpu)
2379 {
2380 VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAllGlobal, 1, pVCpu);
2381 return VINF_SUCCESS;
2382 }
2383 RT_NOREF(paArgs, cArgs);
2384 return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
2385}
2386
2387
2388/**
2389 * Called by IEMR3Init to register debugger commands.
2390 */
2391static void iemR3RegisterDebuggerCommands(void)
2392{
2393 /*
2394 * Register debugger commands.
2395 */
2396 static DBGCCMD const s_aCmds[] =
2397 {
2398 {
2399 /* .pszCmd = */ "iemflushtlb",
2400 /* .cArgsMin = */ 0,
2401 /* .cArgsMax = */ 0,
2402 /* .paArgDescs = */ NULL,
2403 /* .cArgDescs = */ 0,
2404 /* .fFlags = */ 0,
2405 /* .pfnHandler = */ iemR3DbgFlushTlbs,
2406 /* .pszSyntax = */ "",
2407 /* .pszDescription = */ "Flushed the code and data TLBs"
2408 },
2409 };
2410
2411 int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
2412 AssertLogRelRC(rc);
2413}
2414
2415#endif /* VBOX_WITH_DEBUGGER */
2416
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