| 1 | /* $Id: IEMR3.cpp 58122 2015-10-08 17:11:58Z vboxsync $ */
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| 2 | /** @file
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| 3 | * IEM - Interpreted Execution Manager.
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| 4 | */
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| 5 |
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| 6 | /*
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| 7 | * Copyright (C) 2011-2015 Oracle Corporation
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| 8 | *
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| 9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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| 10 | * available from http://www.virtualbox.org. This file is free software;
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| 11 | * you can redistribute it and/or modify it under the terms of the GNU
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| 12 | * General Public License (GPL) as published by the Free Software
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| 13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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| 14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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| 15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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| 16 | */
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| 17 |
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| 18 |
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| 19 | /*********************************************************************************************************************************
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| 20 | * Header Files *
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| 21 | *********************************************************************************************************************************/
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| 22 | #define LOG_GROUP LOG_GROUP_EM
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| 23 | #include <VBox/vmm/iem.h>
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| 24 | #include <VBox/vmm/cpum.h>
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| 25 | #include "IEMInternal.h"
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| 26 | #include <VBox/vmm/vm.h>
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| 27 | #include <VBox/err.h>
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| 28 |
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| 29 | #include <iprt/asm-amd64-x86.h>
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| 30 | #include <iprt/assert.h>
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| 31 |
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| 32 |
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| 33 |
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| 34 | /**
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| 35 | * Initializes the interpreted execution manager.
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| 36 | *
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| 37 | * This must be called after CPUM as we're quering information from CPUM about
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| 38 | * the guest and host CPUs.
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| 39 | *
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| 40 | * @returns VBox status code.
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| 41 | * @param pVM The cross context VM structure.
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| 42 | */
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| 43 | VMMR3DECL(int) IEMR3Init(PVM pVM)
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| 44 | {
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| 45 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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| 46 | {
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| 47 | PVMCPU pVCpu = &pVM->aCpus[idCpu];
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| 48 | pVCpu->iem.s.offVM = -RT_OFFSETOF(VM, aCpus[idCpu].iem.s);
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| 49 | pVCpu->iem.s.offVMCpu = -RT_OFFSETOF(VMCPU, iem.s);
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| 50 | pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
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| 51 | pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
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| 52 | pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
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| 53 |
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| 54 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 55 | "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
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| 56 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 57 | "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
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| 58 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 59 | "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
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| 60 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 61 | "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
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| 62 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 63 | "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
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| 64 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
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| 65 | "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
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| 66 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
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| 67 | "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
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| 68 | STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
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| 69 | "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
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| 70 |
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| 71 | /*
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| 72 | * Host and guest CPU information.
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| 73 | */
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| 74 | if (idCpu == 0)
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| 75 | {
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| 76 | pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
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| 77 | pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
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| 78 | }
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| 79 | else
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| 80 | {
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| 81 | pVCpu->iem.s.enmCpuVendor = pVM->aCpus[0].iem.s.enmCpuVendor;
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| 82 | pVCpu->iem.s.enmHostCpuVendor = pVM->aCpus[0].iem.s.enmHostCpuVendor;
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| 83 | }
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| 84 |
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| 85 | /*
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| 86 | * Mark all buffers free.
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| 87 | */
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| 88 | uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
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| 89 | while (iMemMap-- > 0)
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| 90 | pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
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| 91 | }
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| 92 | return VINF_SUCCESS;
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| 93 | }
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| 94 |
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| 95 |
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| 96 | VMMR3DECL(int) IEMR3Term(PVM pVM)
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| 97 | {
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| 98 | NOREF(pVM);
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| 99 | return VINF_SUCCESS;
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| 100 | }
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| 101 |
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| 102 |
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| 103 | VMMR3DECL(void) IEMR3Relocate(PVM pVM)
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| 104 | {
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| 105 | for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
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| 106 | pVM->aCpus[idCpu].iem.s.pCtxRC = VM_RC_ADDR(pVM, pVM->aCpus[idCpu].iem.s.pCtxR3);
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| 107 | }
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| 108 |
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