VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 61794

Last change on this file since 61794 was 61307, checked in by vboxsync, 9 years ago

IEM: log actual names of target CPU and microarchitecture
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 6.8 KB
Line 
1/* $Id: IEMR3.cpp 61307 2016-05-30 16:19:27Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/iem.h>
24#include <VBox/vmm/cpum.h>
25#include "IEMInternal.h"
26#include <VBox/vmm/vm.h>
27#include <VBox/err.h>
28
29#include <iprt/asm-amd64-x86.h>
30#include <iprt/assert.h>
31
32static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
33{
34 switch (enmTargetCpu)
35 {
36#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
37 CASE_RET_STR(IEMTARGETCPU_8086);
38 CASE_RET_STR(IEMTARGETCPU_V20);
39 CASE_RET_STR(IEMTARGETCPU_186);
40 CASE_RET_STR(IEMTARGETCPU_286);
41 CASE_RET_STR(IEMTARGETCPU_386);
42 CASE_RET_STR(IEMTARGETCPU_486);
43 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
44 CASE_RET_STR(IEMTARGETCPU_PPRO);
45 CASE_RET_STR(IEMTARGETCPU_CURRENT);
46#undef CASE_RET_STR
47 default: return "Unknown";
48 }
49}
50
51/**
52 * Initializes the interpreted execution manager.
53 *
54 * This must be called after CPUM as we're quering information from CPUM about
55 * the guest and host CPUs.
56 *
57 * @returns VBox status code.
58 * @param pVM The cross context VM structure.
59 */
60VMMR3DECL(int) IEMR3Init(PVM pVM)
61{
62 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
63 {
64 PVMCPU pVCpu = &pVM->aCpus[idCpu];
65 pVCpu->iem.s.offVM = -RT_OFFSETOF(VM, aCpus[idCpu].iem.s);
66 pVCpu->iem.s.offVMCpu = -RT_OFFSETOF(VMCPU, iem.s);
67 pVCpu->iem.s.pCtxR3 = CPUMQueryGuestCtxPtr(pVCpu);
68 pVCpu->iem.s.pCtxR0 = VM_R0_ADDR(pVM, pVCpu->iem.s.pCtxR3);
69 pVCpu->iem.s.pCtxRC = VM_RC_ADDR(pVM, pVCpu->iem.s.pCtxR3);
70
71 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
72 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
73 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
74 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
75 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
76 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
77 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
78 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
79 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
80 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
81 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
82 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
83 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
84 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
85 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
86 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
87
88 /*
89 * Host and guest CPU information.
90 */
91 if (idCpu == 0)
92 {
93 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
94 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
95#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
96 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
97 {
98 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
99 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
100 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
101 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
102 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
103 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
104 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
105 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
106 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
107 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
108 }
109 LogRel(("IEM: TargetCpu=%s, Microarch=%s\n", iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMR3MicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch)));
110#endif
111 }
112 else
113 {
114 pVCpu->iem.s.enmCpuVendor = pVM->aCpus[0].iem.s.enmCpuVendor;
115 pVCpu->iem.s.enmHostCpuVendor = pVM->aCpus[0].iem.s.enmHostCpuVendor;
116#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
117 pVCpu->iem.s.uTargetCpu = pVM->aCpus[0].iem.s.uTargetCpu;
118#endif
119 }
120
121 /*
122 * Mark all buffers free.
123 */
124 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
125 while (iMemMap-- > 0)
126 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
127 }
128 return VINF_SUCCESS;
129}
130
131
132VMMR3DECL(int) IEMR3Term(PVM pVM)
133{
134 NOREF(pVM);
135 return VINF_SUCCESS;
136}
137
138
139VMMR3DECL(void) IEMR3Relocate(PVM pVM)
140{
141 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
142 pVM->aCpus[idCpu].iem.s.pCtxRC = VM_RC_ADDR(pVM, pVM->aCpus[idCpu].iem.s.pCtxR3);
143}
144
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette