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source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 78592

Last change on this file since 78592 was 76553, checked in by vboxsync, 6 years ago

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1/* $Id: IEMR3.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_EM
23#include <VBox/vmm/iem.h>
24#include <VBox/vmm/cpum.h>
25#include <VBox/vmm/mm.h>
26#include "IEMInternal.h"
27#include <VBox/vmm/vm.h>
28#include <VBox/err.h>
29
30#include <iprt/asm-amd64-x86.h>
31#include <iprt/assert.h>
32
33static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
34{
35 switch (enmTargetCpu)
36 {
37#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
38 CASE_RET_STR(IEMTARGETCPU_8086);
39 CASE_RET_STR(IEMTARGETCPU_V20);
40 CASE_RET_STR(IEMTARGETCPU_186);
41 CASE_RET_STR(IEMTARGETCPU_286);
42 CASE_RET_STR(IEMTARGETCPU_386);
43 CASE_RET_STR(IEMTARGETCPU_486);
44 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
45 CASE_RET_STR(IEMTARGETCPU_PPRO);
46 CASE_RET_STR(IEMTARGETCPU_CURRENT);
47#undef CASE_RET_STR
48 default: return "Unknown";
49 }
50}
51
52/**
53 * Initializes the interpreted execution manager.
54 *
55 * This must be called after CPUM as we're quering information from CPUM about
56 * the guest and host CPUs.
57 *
58 * @returns VBox status code.
59 * @param pVM The cross context VM structure.
60 */
61VMMR3DECL(int) IEMR3Init(PVM pVM)
62{
63 uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
64 uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
65
66 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
67 {
68 PVMCPU pVCpu = &pVM->aCpus[idCpu];
69
70 pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
71 pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
72
73 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
74 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
75 STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
76 "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
77 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
78 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
79 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
80 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
81 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
82 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
83 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
84 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
85 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
86 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
87 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
88 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
89 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
90 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
91
92#ifdef VBOX_WITH_STATISTICS
93 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
94 "Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
95 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
96 "Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
97#endif
98 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
99 "Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
100 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
101 "Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
102 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
103 "Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
104 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
105 "Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
106
107 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
108 "Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
109 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
110 "Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
111 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
112 "Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
113
114#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
115 /* Allocate instruction statistics and register them. */
116 pVCpu->iem.s.pStatsR3 = (PIEMINSTRSTATS)MMR3HeapAllocZ(pVM, MM_TAG_IEM, sizeof(IEMINSTRSTATS));
117 AssertLogRelReturn(pVCpu->iem.s.pStatsR3, VERR_NO_MEMORY);
118 int rc = MMHyperAlloc(pVM, sizeof(IEMINSTRSTATS), sizeof(uint64_t), MM_TAG_IEM, (void **)&pVCpu->iem.s.pStatsCCR3);
119 AssertLogRelRCReturn(rc, rc);
120 pVCpu->iem.s.pStatsR0 = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
121 pVCpu->iem.s.pStatsRC = MMHyperR3ToR0(pVM, pVCpu->iem.s.pStatsCCR3);
122# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
123 STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsCCR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
124 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
125 STAMR3RegisterF(pVM, &pVCpu->iem.s.pStatsR3->a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
126 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
127# include "IEMInstructionStatisticsTmpl.h"
128# undef IEM_DO_INSTR_STAT
129#endif
130
131 /*
132 * Host and guest CPU information.
133 */
134 if (idCpu == 0)
135 {
136 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
137 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
138#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
139 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
140 {
141 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
142 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
143 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
144 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
145 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
146 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
147 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
148 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
149 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
150 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
151 }
152 LogRel(("IEM: TargetCpu=%s, Microarch=%s\n", iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMR3MicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch)));
153#endif
154 }
155 else
156 {
157 pVCpu->iem.s.enmCpuVendor = pVM->aCpus[0].iem.s.enmCpuVendor;
158 pVCpu->iem.s.enmHostCpuVendor = pVM->aCpus[0].iem.s.enmHostCpuVendor;
159#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
160 pVCpu->iem.s.uTargetCpu = pVM->aCpus[0].iem.s.uTargetCpu;
161#endif
162 }
163
164 /*
165 * Mark all buffers free.
166 */
167 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
168 while (iMemMap-- > 0)
169 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
170 }
171
172#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
173 /*
174 * Register the per-VM VMX APIC-access page handler type.
175 */
176 if (pVM->cpum.ro.GuestFeatures.fVmx)
177 {
178 PVMCPU pVCpu0 = &pVM->aCpus[0];
179 int rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, iemVmxApicAccessPageHandler,
180 NULL /* pszModR0 */,
181 "iemVmxApicAccessPageHandler", NULL /* pszPfHandlerR0 */,
182 NULL /* pszModRC */,
183 NULL /* pszHandlerRC */, NULL /* pszPfHandlerRC */,
184 "VMX APIC-access page", &pVCpu0->iem.s.hVmxApicAccessPage);
185 AssertLogRelRCReturn(rc, rc);
186 }
187#endif
188
189 return VINF_SUCCESS;
190}
191
192
193VMMR3DECL(int) IEMR3Term(PVM pVM)
194{
195 NOREF(pVM);
196#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
197 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
198 {
199 PVMCPU pVCpu = &pVM->aCpus[idCpu];
200 MMR3HeapFree(pVCpu->iem.s.pStatsR3);
201 pVCpu->iem.s.pStatsR3 = NULL;
202 }
203#endif
204 return VINF_SUCCESS;
205}
206
207
208VMMR3DECL(void) IEMR3Relocate(PVM pVM)
209{
210 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
211 if (pVM->aCpus[idCpu].iem.s.pStatsRC)
212 pVM->aCpus[idCpu].iem.s.pStatsRC = MMHyperR3ToRC(pVM, pVM->aCpus[idCpu].iem.s.pStatsCCR3);
213}
214
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