VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IEMR3.cpp@ 97295

Last change on this file since 97295 was 96979, checked in by vboxsync, 2 years ago

VMM/PGM,IEM,HM: Added a PGMPHYSHANDLER_F_NOT_IN_HM flag to better deal with a nested APIC access page. bugref:10092
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1/* $Id: IEMR3.cpp 96979 2022-10-04 12:46:05Z vboxsync $ */
2/** @file
3 * IEM - Interpreted Execution Manager.
4 */
5
6/*
7 * Copyright (C) 2011-2022 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_EM
33#include <VBox/vmm/iem.h>
34#include <VBox/vmm/cpum.h>
35#include <VBox/vmm/dbgf.h>
36#include <VBox/vmm/mm.h>
37#include "IEMInternal.h"
38#include <VBox/vmm/vm.h>
39#include <VBox/vmm/vmapi.h>
40#include <VBox/err.h>
41#ifdef VBOX_WITH_DEBUGGER
42# include <VBox/dbg.h>
43#endif
44
45#include <iprt/assert.h>
46#include <iprt/getopt.h>
47#include <iprt/string.h>
48
49
50/*********************************************************************************************************************************
51* Internal Functions *
52*********************************************************************************************************************************/
53static FNDBGFINFOARGVINT iemR3InfoITlb;
54static FNDBGFINFOARGVINT iemR3InfoDTlb;
55#ifdef VBOX_WITH_DEBUGGER
56static void iemR3RegisterDebuggerCommands(void);
57#endif
58
59
60static const char *iemGetTargetCpuName(uint32_t enmTargetCpu)
61{
62 switch (enmTargetCpu)
63 {
64#define CASE_RET_STR(enmValue) case enmValue: return #enmValue + (sizeof("IEMTARGETCPU_") - 1)
65 CASE_RET_STR(IEMTARGETCPU_8086);
66 CASE_RET_STR(IEMTARGETCPU_V20);
67 CASE_RET_STR(IEMTARGETCPU_186);
68 CASE_RET_STR(IEMTARGETCPU_286);
69 CASE_RET_STR(IEMTARGETCPU_386);
70 CASE_RET_STR(IEMTARGETCPU_486);
71 CASE_RET_STR(IEMTARGETCPU_PENTIUM);
72 CASE_RET_STR(IEMTARGETCPU_PPRO);
73 CASE_RET_STR(IEMTARGETCPU_CURRENT);
74#undef CASE_RET_STR
75 default: return "Unknown";
76 }
77}
78
79
80/**
81 * Initializes the interpreted execution manager.
82 *
83 * This must be called after CPUM as we're quering information from CPUM about
84 * the guest and host CPUs.
85 *
86 * @returns VBox status code.
87 * @param pVM The cross context VM structure.
88 */
89VMMR3DECL(int) IEMR3Init(PVM pVM)
90{
91 int rc;
92
93 /*
94 * Read configuration.
95 */
96 PCFGMNODE pIem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "IEM");
97
98#ifndef VBOX_WITHOUT_CPUID_HOST_CALL
99 /** @cfgm{/IEM/CpuIdHostCall, boolean, false}
100 * Controls whether the custom VBox specific CPUID host call interface is
101 * enabled or not. */
102# ifdef DEBUG_bird
103 rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, true);
104# else
105 rc = CFGMR3QueryBoolDef(pIem, "CpuIdHostCall", &pVM->iem.s.fCpuIdHostCall, false);
106# endif
107 AssertLogRelRCReturn(rc, rc);
108#endif
109
110 /*
111 * Initialize per-CPU data and register statistics.
112 */
113 uint64_t const uInitialTlbRevision = UINT64_C(0) - (IEMTLB_REVISION_INCR * 200U);
114 uint64_t const uInitialTlbPhysRev = UINT64_C(0) - (IEMTLB_PHYS_REV_INCR * 100U);
115
116 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
117 {
118 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
119 AssertCompile(sizeof(pVCpu->iem.s) <= sizeof(pVCpu->iem.padding)); /* (tstVMStruct can't do it's job w/o instruction stats) */
120
121 pVCpu->iem.s.CodeTlb.uTlbRevision = pVCpu->iem.s.DataTlb.uTlbRevision = uInitialTlbRevision;
122 pVCpu->iem.s.CodeTlb.uTlbPhysRev = pVCpu->iem.s.DataTlb.uTlbPhysRev = uInitialTlbPhysRev;
123
124 STAMR3RegisterF(pVM, &pVCpu->iem.s.cInstructions, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
125 "Instructions interpreted", "/IEM/CPU%u/cInstructions", idCpu);
126 STAMR3RegisterF(pVM, &pVCpu->iem.s.cLongJumps, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
127 "Number of longjmp calls", "/IEM/CPU%u/cLongJumps", idCpu);
128 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPotentialExits, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
129 "Potential exits", "/IEM/CPU%u/cPotentialExits", idCpu);
130 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetAspectNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
131 "VERR_IEM_ASPECT_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetAspectNotImplemented", idCpu);
132 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInstrNotImplemented, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
133 "VERR_IEM_INSTR_NOT_IMPLEMENTED", "/IEM/CPU%u/cRetInstrNotImplemented", idCpu);
134 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetInfStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
135 "Informational statuses returned", "/IEM/CPU%u/cRetInfStatuses", idCpu);
136 STAMR3RegisterF(pVM, &pVCpu->iem.s.cRetErrStatuses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
137 "Error statuses returned", "/IEM/CPU%u/cRetErrStatuses", idCpu);
138 STAMR3RegisterF(pVM, &pVCpu->iem.s.cbWritten, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
139 "Approx bytes written", "/IEM/CPU%u/cbWritten", idCpu);
140 STAMR3RegisterF(pVM, &pVCpu->iem.s.cPendingCommit, STAMTYPE_U32, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES,
141 "Times RC/R0 had to postpone instruction committing to ring-3", "/IEM/CPU%u/cPendingCommit", idCpu);
142
143#ifdef VBOX_WITH_STATISTICS
144 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
145 "Code TLB hits", "/IEM/CPU%u/CodeTlb-Hits", idCpu);
146 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbHits, STAMTYPE_U64_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
147 "Data TLB hits", "/IEM/CPU%u/DataTlb-Hits", idCpu);
148#endif
149 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
150 "Code TLB misses", "/IEM/CPU%u/CodeTlb-Misses", idCpu);
151 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
152 "Code TLB revision", "/IEM/CPU%u/CodeTlb-Revision", idCpu);
153 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.CodeTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
154 "Code TLB physical revision", "/IEM/CPU%u/CodeTlb-PhysRev", idCpu);
155 STAMR3RegisterF(pVM, &pVCpu->iem.s.CodeTlb.cTlbSlowReadPath, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
156 "Code TLB slow read path", "/IEM/CPU%u/CodeTlb-SlowReads", idCpu);
157
158 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.cTlbMisses, STAMTYPE_U32_RESET, STAMVISIBILITY_ALWAYS, STAMUNIT_COUNT,
159 "Data TLB misses", "/IEM/CPU%u/DataTlb-Misses", idCpu);
160 STAMR3RegisterF(pVM, &pVCpu->iem.s.DataTlb.uTlbRevision, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
161 "Data TLB revision", "/IEM/CPU%u/DataTlb-Revision", idCpu);
162 STAMR3RegisterF(pVM, (void *)&pVCpu->iem.s.DataTlb.uTlbPhysRev, STAMTYPE_X64, STAMVISIBILITY_ALWAYS, STAMUNIT_NONE,
163 "Data TLB physical revision", "/IEM/CPU%u/DataTlb-PhysRev", idCpu);
164
165 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatXcpts); i++)
166 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatXcpts[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
167 "", "/IEM/CPU%u/Exceptions/%02x", idCpu, i);
168 for (uint32_t i = 0; i < RT_ELEMENTS(pVCpu->iem.s.aStatInts); i++)
169 STAMR3RegisterF(pVM, &pVCpu->iem.s.aStatInts[i], STAMTYPE_U32_RESET, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
170 "", "/IEM/CPU%u/Interrupts/%02x", idCpu, i);
171
172#if defined(VBOX_WITH_STATISTICS) && !defined(DOXYGEN_RUNNING)
173 /* Instruction statistics: */
174# define IEM_DO_INSTR_STAT(a_Name, a_szDesc) \
175 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsRZ.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
176 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-RZ/" #a_Name, idCpu); \
177 STAMR3RegisterF(pVM, &pVCpu->iem.s.StatsR3.a_Name, STAMTYPE_U32_RESET, STAMVISIBILITY_USED, \
178 STAMUNIT_COUNT, a_szDesc, "/IEM/CPU%u/instr-R3/" #a_Name, idCpu);
179# include "IEMInstructionStatisticsTmpl.h"
180# undef IEM_DO_INSTR_STAT
181#endif
182
183 /*
184 * Host and guest CPU information.
185 */
186 if (idCpu == 0)
187 {
188 pVCpu->iem.s.enmCpuVendor = CPUMGetGuestCpuVendor(pVM);
189 pVCpu->iem.s.enmHostCpuVendor = CPUMGetHostCpuVendor(pVM);
190 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_INTEL
191 || pVCpu->iem.s.enmCpuVendor == CPUMCPUVENDOR_VIA /*??*/
192 ? IEMTARGETCPU_EFL_BEHAVIOR_INTEL : IEMTARGETCPU_EFL_BEHAVIOR_AMD;
193#if defined(RT_ARCH_X86) || defined(RT_ARCH_AMD64)
194 if (pVCpu->iem.s.enmCpuVendor == pVCpu->iem.s.enmHostCpuVendor)
195 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = IEMTARGETCPU_EFL_BEHAVIOR_NATIVE;
196 else
197#endif
198 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVCpu->iem.s.aidxTargetCpuEflFlavour[0];
199
200#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
201 switch (pVM->cpum.ro.GuestFeatures.enmMicroarch)
202 {
203 case kCpumMicroarch_Intel_8086: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_8086; break;
204 case kCpumMicroarch_Intel_80186: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_186; break;
205 case kCpumMicroarch_Intel_80286: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_286; break;
206 case kCpumMicroarch_Intel_80386: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_386; break;
207 case kCpumMicroarch_Intel_80486: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_486; break;
208 case kCpumMicroarch_Intel_P5: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PENTIUM; break;
209 case kCpumMicroarch_Intel_P6: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_PPRO; break;
210 case kCpumMicroarch_NEC_V20: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
211 case kCpumMicroarch_NEC_V30: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_V20; break;
212 default: pVCpu->iem.s.uTargetCpu = IEMTARGETCPU_CURRENT; break;
213 }
214 LogRel(("IEM: TargetCpu=%s, Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
215 iemGetTargetCpuName(pVCpu->iem.s.uTargetCpu), CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
216 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
217#else
218 LogRel(("IEM: Microarch=%s aidxTargetCpuEflFlavour={%d,%d}\n",
219 CPUMMicroarchName(pVM->cpum.ro.GuestFeatures.enmMicroarch),
220 pVCpu->iem.s.aidxTargetCpuEflFlavour[0], pVCpu->iem.s.aidxTargetCpuEflFlavour[1]));
221#endif
222 }
223 else
224 {
225 pVCpu->iem.s.enmCpuVendor = pVM->apCpusR3[0]->iem.s.enmCpuVendor;
226 pVCpu->iem.s.enmHostCpuVendor = pVM->apCpusR3[0]->iem.s.enmHostCpuVendor;
227 pVCpu->iem.s.aidxTargetCpuEflFlavour[0] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[0];
228 pVCpu->iem.s.aidxTargetCpuEflFlavour[1] = pVM->apCpusR3[0]->iem.s.aidxTargetCpuEflFlavour[1];
229#if IEM_CFG_TARGET_CPU == IEMTARGETCPU_DYNAMIC
230 pVCpu->iem.s.uTargetCpu = pVM->apCpusR3[0]->iem.s.uTargetCpu;
231#endif
232 }
233
234 /*
235 * Mark all buffers free.
236 */
237 uint32_t iMemMap = RT_ELEMENTS(pVCpu->iem.s.aMemMappings);
238 while (iMemMap-- > 0)
239 pVCpu->iem.s.aMemMappings[iMemMap].fAccess = IEM_ACCESS_INVALID;
240 }
241
242#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
243 /*
244 * Register the per-VM VMX APIC-access page handler type.
245 */
246 if (pVM->cpum.ro.GuestFeatures.fVmx)
247 {
248 rc = PGMR3HandlerPhysicalTypeRegister(pVM, PGMPHYSHANDLERKIND_ALL, PGMPHYSHANDLER_F_NOT_IN_HM,
249 iemVmxApicAccessPageHandler,
250 "VMX APIC-access page", &pVM->iem.s.hVmxApicAccessPage);
251 AssertLogRelRCReturn(rc, rc);
252 }
253#endif
254
255 DBGFR3InfoRegisterInternalArgv(pVM, "itlb", "IEM instruction TLB", iemR3InfoITlb, DBGFINFO_FLAGS_RUN_ON_EMT);
256 DBGFR3InfoRegisterInternalArgv(pVM, "dtlb", "IEM instruction TLB", iemR3InfoDTlb, DBGFINFO_FLAGS_RUN_ON_EMT);
257#ifdef VBOX_WITH_DEBUGGER
258 iemR3RegisterDebuggerCommands();
259#endif
260
261 return VINF_SUCCESS;
262}
263
264
265VMMR3DECL(int) IEMR3Term(PVM pVM)
266{
267 NOREF(pVM);
268 return VINF_SUCCESS;
269}
270
271
272VMMR3DECL(void) IEMR3Relocate(PVM pVM)
273{
274 RT_NOREF(pVM);
275}
276
277
278/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
279static void iemR3InfoTlbPrintHeader(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, bool *pfHeader)
280{
281 if (*pfHeader)
282 return;
283 pHlp->pfnPrintf(pHlp, "%cTLB for CPU %u:\n", &pVCpu->iem.s.CodeTlb == pTlb ? 'I' : 'D', pVCpu->idCpu);
284 *pfHeader = true;
285}
286
287
288/** Worker for iemR3InfoTlbPrintSlots and iemR3InfoTlbPrintAddress. */
289static void iemR3InfoTlbPrintSlot(PCDBGFINFOHLP pHlp, IEMTLB const *pTlb, IEMTLBENTRY const *pTlbe, uint32_t uSlot)
290{
291 pHlp->pfnPrintf(pHlp, "%02x: %s %#018RX64 -> %RGp / %p / %#05x %s%s%s%s/%s%s%s/%s %s\n",
292 uSlot,
293 (pTlbe->uTag & IEMTLB_REVISION_MASK) == pTlb->uTlbRevision ? "valid "
294 : (pTlbe->uTag & IEMTLB_REVISION_MASK) == 0 ? "empty "
295 : "expired",
296 (pTlbe->uTag & ~IEMTLB_REVISION_MASK) << X86_PAGE_SHIFT,
297 pTlbe->GCPhys, pTlbe->pbMappingR3,
298 (uint32_t)(pTlbe->fFlagsAndPhysRev & ~IEMTLBE_F_PHYS_REV),
299 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_EXEC ? "NX" : " X",
300 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_WRITE ? "RO" : "RW",
301 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_ACCESSED ? "-" : "A",
302 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PT_NO_DIRTY ? "-" : "D",
303 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_WRITE ? "-" : "w",
304 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_NO_READ ? "-" : "r",
305 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PG_UNASSIGNED ? "U" : "-",
306 pTlbe->fFlagsAndPhysRev & IEMTLBE_F_NO_MAPPINGR3 ? "S" : "M",
307 (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == pTlb->uTlbPhysRev ? "phys-valid"
308 : (pTlbe->fFlagsAndPhysRev & IEMTLBE_F_PHYS_REV) == 0 ? "phys-empty" : "phys-expired");
309}
310
311
312/** Displays one or more TLB slots. */
313static void iemR3InfoTlbPrintSlots(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
314 uint32_t uSlot, uint32_t cSlots, bool *pfHeader)
315{
316 if (uSlot < RT_ELEMENTS(pTlb->aEntries))
317 {
318 if (cSlots > RT_ELEMENTS(pTlb->aEntries))
319 {
320 pHlp->pfnPrintf(pHlp, "error: Too many slots given: %u, adjusting it down to the max (%u)\n",
321 cSlots, RT_ELEMENTS(pTlb->aEntries));
322 cSlots = RT_ELEMENTS(pTlb->aEntries);
323 }
324
325 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
326 while (cSlots-- > 0)
327 {
328 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
329 iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
330 uSlot = (uSlot + 1) % RT_ELEMENTS(pTlb->aEntries);
331 }
332 }
333 else
334 pHlp->pfnPrintf(pHlp, "error: TLB slot is out of range: %u (%#x), max %u (%#x)\n",
335 uSlot, uSlot, RT_ELEMENTS(pTlb->aEntries) - 1, RT_ELEMENTS(pTlb->aEntries) - 1);
336}
337
338
339/** Displays the TLB slot for the given address. */
340static void iemR3InfoTlbPrintAddress(PVMCPU pVCpu, PCDBGFINFOHLP pHlp, IEMTLB const *pTlb,
341 uint64_t uAddress, bool *pfHeader)
342{
343 iemR3InfoTlbPrintHeader(pVCpu, pHlp, pTlb, pfHeader);
344
345 uint64_t const uTag = (uAddress << 16) >> (X86_PAGE_SHIFT + 16);
346 uint32_t const uSlot = (uint8_t)uTag;
347 IEMTLBENTRY const Tlbe = pTlb->aEntries[uSlot];
348 pHlp->pfnPrintf(pHlp, "Address %#RX64 -> slot %#x - %s\n", uAddress, uSlot,
349 Tlbe.uTag == (uTag | pTlb->uTlbRevision) ? "match"
350 : (Tlbe.uTag & ~IEMTLB_REVISION_MASK) == uTag ? "expired" : "mismatch");
351 iemR3InfoTlbPrintSlot(pHlp, pTlb, &Tlbe, uSlot);
352}
353
354
355/** Common worker for iemR3InfoDTlb and iemR3InfoITlb. */
356static void iemR3InfoTlbCommon(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs, bool fITlb)
357{
358 /*
359 * This is entirely argument driven.
360 */
361 static RTGETOPTDEF const s_aOptions[] =
362 {
363 { "--cpu", 'c', RTGETOPT_REQ_UINT32 },
364 { "--vcpu", 'c', RTGETOPT_REQ_UINT32 },
365 { "all", 'A', RTGETOPT_REQ_NOTHING },
366 { "--all", 'A', RTGETOPT_REQ_NOTHING },
367 { "--address", 'a', RTGETOPT_REQ_UINT64 | RTGETOPT_FLAG_HEX },
368 { "--range", 'r', RTGETOPT_REQ_UINT32_PAIR | RTGETOPT_FLAG_HEX },
369 { "--slot", 's', RTGETOPT_REQ_UINT32 | RTGETOPT_FLAG_HEX },
370 };
371
372 char szDefault[] = "-A";
373 char *papszDefaults[2] = { szDefault, NULL };
374 if (cArgs == 0)
375 {
376 cArgs = 1;
377 papszArgs = papszDefaults;
378 }
379
380 RTGETOPTSTATE State;
381 int rc = RTGetOptInit(&State, cArgs, papszArgs, s_aOptions, RT_ELEMENTS(s_aOptions), 0 /*iFirst*/, 0 /*fFlags*/);
382 AssertRCReturnVoid(rc);
383
384 bool fNeedHeader = true;
385 bool fAddressMode = true;
386 PVMCPU pVCpu = VMMGetCpu(pVM);
387 if (!pVCpu)
388 pVCpu = VMMGetCpuById(pVM, 0);
389
390 RTGETOPTUNION ValueUnion;
391 while ((rc = RTGetOpt(&State, &ValueUnion)) != 0)
392 {
393 switch (rc)
394 {
395 case 'c':
396 if (ValueUnion.u32 >= pVM->cCpus)
397 pHlp->pfnPrintf(pHlp, "error: Invalid CPU ID: %u\n", ValueUnion.u32);
398 else if (!pVCpu || pVCpu->idCpu != ValueUnion.u32)
399 {
400 pVCpu = VMMGetCpuById(pVM, ValueUnion.u32);
401 fNeedHeader = true;
402 }
403 break;
404
405 case 'a':
406 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
407 ValueUnion.u64, &fNeedHeader);
408 fAddressMode = true;
409 break;
410
411 case 'A':
412 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
413 0, RT_ELEMENTS(pVCpu->iem.s.CodeTlb.aEntries), &fNeedHeader);
414 break;
415
416 case 'r':
417 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
418 ValueUnion.PairU32.uFirst, ValueUnion.PairU32.uSecond, &fNeedHeader);
419 fAddressMode = false;
420 break;
421
422 case 's':
423 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
424 ValueUnion.u32, 1, &fNeedHeader);
425 fAddressMode = false;
426 break;
427
428 case VINF_GETOPT_NOT_OPTION:
429 if (fAddressMode)
430 {
431 uint64_t uAddr;
432 rc = RTStrToUInt64Full(ValueUnion.psz, 16, &uAddr);
433 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
434 iemR3InfoTlbPrintAddress(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
435 uAddr, &fNeedHeader);
436 else
437 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed guest address '%s': %Rrc\n", ValueUnion.psz, rc);
438 }
439 else
440 {
441 uint32_t uSlot;
442 rc = RTStrToUInt32Full(ValueUnion.psz, 16, &uSlot);
443 if (RT_SUCCESS(rc) && rc != VWRN_NUMBER_TOO_BIG)
444 iemR3InfoTlbPrintSlots(pVCpu, pHlp, fITlb ? &pVCpu->iem.s.CodeTlb : &pVCpu->iem.s.DataTlb,
445 uSlot, 1, &fNeedHeader);
446 else
447 pHlp->pfnPrintf(pHlp, "error: Invalid or malformed TLB slot number '%s': %Rrc\n", ValueUnion.psz, rc);
448 }
449 break;
450
451 case 'h':
452 pHlp->pfnPrintf(pHlp,
453 "Usage: info %ctlb [options]\n"
454 "\n"
455 "Options:\n"
456 " -c<n>, --cpu=<n>, --vcpu=<n>\n"
457 " Selects the CPU which TLBs we're looking at. Default: Caller / 0\n"
458 " -A, --all, all\n"
459 " Display all the TLB entries (default if no other args).\n"
460 " -a<virt>, --address=<virt>\n"
461 " Shows the TLB entry for the specified guest virtual address.\n"
462 " -r<slot:count>, --range=<slot:count>\n"
463 " Shows the TLB entries for the specified slot range.\n"
464 " -s<slot>,--slot=<slot>\n"
465 " Shows the given TLB slot.\n"
466 "\n"
467 "Non-options are interpreted according to the last -a, -r or -s option,\n"
468 "defaulting to addresses if not preceeded by any of those options.\n"
469 , fITlb ? 'i' : 'd');
470 return;
471
472 default:
473 pHlp->pfnGetOptError(pHlp, rc, &ValueUnion, &State);
474 return;
475 }
476 }
477}
478
479
480/**
481 * @callback_method_impl{FNDBGFINFOARGVINT, itlb}
482 */
483static DECLCALLBACK(void) iemR3InfoITlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
484{
485 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, true /*fITlb*/);
486}
487
488
489/**
490 * @callback_method_impl{FNDBGFINFOARGVINT, dtlb}
491 */
492static DECLCALLBACK(void) iemR3InfoDTlb(PVM pVM, PCDBGFINFOHLP pHlp, int cArgs, char **papszArgs)
493{
494 return iemR3InfoTlbCommon(pVM, pHlp, cArgs, papszArgs, false /*fITlb*/);
495}
496
497
498#ifdef VBOX_WITH_DEBUGGER
499
500/** @callback_method_impl{FNDBGCCMD,
501 * Implements the '.alliem' command. }
502 */
503static DECLCALLBACK(int) iemR3DbgFlushTlbs(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
504{
505 VMCPUID idCpu = DBGCCmdHlpGetCurrentCpu(pCmdHlp);
506 PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, idCpu);
507 if (pVCpu)
508 {
509 VMR3ReqPriorityCallVoidWaitU(pUVM, idCpu, (PFNRT)IEMTlbInvalidateAll, 1, pVCpu);
510 return VINF_SUCCESS;
511 }
512 RT_NOREF(paArgs, cArgs);
513 return DBGCCmdHlpFail(pCmdHlp, pCmd, "failed to get the PVMCPU for the current CPU");
514}
515
516
517/**
518 * Called by IEMR3Init to register debugger commands.
519 */
520static void iemR3RegisterDebuggerCommands(void)
521{
522 /*
523 * Register debugger commands.
524 */
525 static DBGCCMD const s_aCmds[] =
526 {
527 {
528 /* .pszCmd = */ "iemflushtlb",
529 /* .cArgsMin = */ 0,
530 /* .cArgsMax = */ 0,
531 /* .paArgDescs = */ NULL,
532 /* .cArgDescs = */ 0,
533 /* .fFlags = */ 0,
534 /* .pfnHandler = */ iemR3DbgFlushTlbs,
535 /* .pszSyntax = */ "",
536 /* .pszDescription = */ "Flushed the code and data TLBs"
537 },
538 };
539
540 int rc = DBGCRegisterCommands(&s_aCmds[0], RT_ELEMENTS(s_aCmds));
541 AssertLogRelRC(rc);
542}
543
544#endif
545
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