VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/IOMR3IoPort.cpp@ 81209

Last change on this file since 81209 was 81162, checked in by vboxsync, 5 years ago

IOM: New MMIO management code - work in progress. bugref:9218

  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 24.2 KB
Line 
1/* $Id: IOMR3IoPort.cpp 81162 2019-10-08 16:45:46Z vboxsync $ */
2/** @file
3 * IOM - Input / Output Monitor, I/O port related APIs.
4 */
5
6/*
7 * Copyright (C) 2006-2019 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_IOM
23#include <VBox/vmm/iom.h>
24#include <VBox/sup.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/stam.h>
27#include <VBox/vmm/dbgf.h>
28#include <VBox/vmm/pdmapi.h>
29#include <VBox/vmm/pdmdev.h>
30#include "IOMInternal.h"
31#include <VBox/vmm/vm.h>
32
33#include <VBox/param.h>
34#include <iprt/assert.h>
35#include <iprt/string.h>
36#include <VBox/log.h>
37#include <VBox/err.h>
38
39#include "IOMInline.h"
40
41
42#ifdef VBOX_WITH_STATISTICS
43
44/**
45 * Register statistics for an I/O port entry.
46 */
47void iomR3IoPortRegStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry)
48{
49 PIOMIOPORTSTATSENTRY pStats = &pVM->iom.s.paIoPortStats[pRegEntry->idxStats];
50 PCIOMIOPORTDESC pExtDesc = pRegEntry->paExtDescs;
51 unsigned uPort = pRegEntry->uPort;
52 unsigned const uFirstPort = uPort;
53 unsigned const uEndPort = uPort + pRegEntry->cPorts;
54
55 /* Register a dummy statistics for the prefix. */
56 char szName[80];
57 size_t cchPrefix;
58 if (uFirstPort < uEndPort - 1)
59 cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/NewPorts/%04x-%04x", uFirstPort, uEndPort - 1);
60 else
61 cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/NewPorts/%04x", uPort);
62 const char *pszDesc = pRegEntry->pszDesc;
63 char *pszFreeDesc = NULL;
64 if (pRegEntry->pDevIns && pRegEntry->pDevIns->iInstance > 0 && pszDesc)
65 pszDesc = pszFreeDesc = RTStrAPrintf2("%u / %s", pRegEntry->pDevIns->iInstance, pszDesc);
66 int rc = STAMR3Register(pVM, &pRegEntry->idxSelf, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, szName,
67 STAMUNIT_NONE, pRegEntry->pszDesc);
68 AssertRC(rc);
69 RTStrFree(pszFreeDesc);
70
71 /* Register stats for each port under it */
72 do
73 {
74 size_t cchBaseNm;
75 if (uFirstPort < uEndPort - 1)
76 cchBaseNm = cchPrefix + RTStrPrintf(&szName[cchPrefix], sizeof(szName) - cchPrefix, "/%04x-", uPort);
77 else
78 {
79 szName[cchPrefix] = '/';
80 cchBaseNm = cchPrefix + 1;
81 }
82
83# define SET_NM_SUFFIX(a_sz) memcpy(&szName[cchBaseNm], a_sz, sizeof(a_sz));
84 const char * const pszInDesc = pExtDesc ? pExtDesc->pszIn : NULL;
85 const char * const pszOutDesc = pExtDesc ? pExtDesc->pszOut : NULL;
86
87 /* register the statistics counters. */
88 SET_NM_SUFFIX("In-R3");
89 rc = STAMR3Register(pVM, &pStats->InR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
90 SET_NM_SUFFIX("Out-R3");
91 rc = STAMR3Register(pVM, &pStats->OutR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
92 SET_NM_SUFFIX("In-RZ");
93 rc = STAMR3Register(pVM, &pStats->InRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
94 SET_NM_SUFFIX("Out-RZ");
95 rc = STAMR3Register(pVM, &pStats->OutRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
96 SET_NM_SUFFIX("In-RZtoR3");
97 rc = STAMR3Register(pVM, &pStats->InRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
98 SET_NM_SUFFIX("Out-RZtoR3");
99 rc = STAMR3Register(pVM, &pStats->OutRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
100
101 /* Profiling */
102 SET_NM_SUFFIX("In-R3-Prof");
103 rc = STAMR3Register(pVM, &pStats->ProfInR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
104 SET_NM_SUFFIX("Out-R3-Prof");
105 rc = STAMR3Register(pVM, &pStats->ProfOutR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
106 SET_NM_SUFFIX("In-RZ-Prof");
107 rc = STAMR3Register(pVM, &pStats->ProfInRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
108 SET_NM_SUFFIX("Out-RZ-Prof");
109 rc = STAMR3Register(pVM, &pStats->ProfOutRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
110
111 pStats++;
112 uPort++;
113 if (pExtDesc)
114 pExtDesc = pszInDesc || pszOutDesc ? pExtDesc + 1 : NULL;
115 } while (uPort < uEndPort);
116}
117
118
119/**
120 * Deregister statistics for an I/O port entry.
121 */
122static void iomR3IoPortDeregStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry, unsigned uPort)
123{
124 char szPrefix[80];
125 size_t cchPrefix;
126 if (pRegEntry->cPorts > 1)
127 cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/NewPorts/%04x-%04x/", uPort, uPort + pRegEntry->cPorts - 1);
128 else
129 cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/NewPorts/%04x/", uPort);
130 STAMR3DeregisterByPrefix(pVM->pUVM, szPrefix);
131}
132
133#endif /* VBOX_WITH_STATISTICS */
134
135
136/**
137 * @callback_method_impl{FNIOMIOPORTNEWIN,
138 * Dummy Port I/O Handler for IN operations.}
139 */
140static DECLCALLBACK(VBOXSTRICTRC)
141iomR3IOPortDummyNewIn(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t *pu32, unsigned cb)
142{
143 NOREF(pDevIns); NOREF(pvUser); NOREF(Port);
144 switch (cb)
145 {
146 case 1: *pu32 = 0xff; break;
147 case 2: *pu32 = 0xffff; break;
148 case 4: *pu32 = UINT32_C(0xffffffff); break;
149 default:
150 AssertReleaseMsgFailed(("cb=%d\n", cb));
151 return VERR_IOM_IOPORT_IPE_2;
152 }
153 return VINF_SUCCESS;
154}
155
156
157/**
158 * @callback_method_impl{FNIOMIOPORTNEWINSTRING,
159 * Dummy Port I/O Handler for string IN operations.}
160 */
161static DECLCALLBACK(VBOXSTRICTRC)
162iomR3IOPortDummyNewInStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t *pbDst, uint32_t *pcTransfer, unsigned cb)
163{
164 NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbDst); NOREF(pcTransfer); NOREF(cb);
165 return VINF_SUCCESS;
166}
167
168
169/**
170 * @callback_method_impl{FNIOMIOPORTNEWOUT,
171 * Dummy Port I/O Handler for OUT operations.}
172 */
173static DECLCALLBACK(VBOXSTRICTRC)
174iomR3IOPortDummyNewOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
175{
176 NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(u32); NOREF(cb);
177 return VINF_SUCCESS;
178}
179
180
181/**
182 * @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
183 * Dummy Port I/O Handler for string OUT operations.}
184 */
185static DECLCALLBACK(VBOXSTRICTRC)
186iomR3IOPortDummyNewOutStr(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint8_t const *pbSrc, uint32_t *pcTransfer, unsigned cb)
187{
188 NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbSrc); NOREF(pcTransfer); NOREF(cb);
189 return VINF_SUCCESS;
190}
191
192
193
194/**
195 * Worker for PDMDEVHLPR3::pfnIoPortCreateEx.
196 */
197VMMR3_INT_DECL(int) IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
198 uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
199 PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
200 const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
201{
202 /*
203 * Validate input.
204 */
205 AssertPtrReturn(phIoPorts, VERR_INVALID_POINTER);
206 *phIoPorts = UINT32_MAX;
207 VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
208 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
209
210 AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
211
212 AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%#x\n", cPorts), VERR_OUT_OF_RANGE);
213 AssertReturn(!(fFlags & ~IOM_IOPORT_F_VALID_MASK), VERR_INVALID_FLAGS);
214
215 AssertReturn(pfnOut || pfnIn || pfnOutStr || pfnInStr, VERR_INVALID_PARAMETER);
216 AssertPtrNullReturn(pfnOut, VERR_INVALID_POINTER);
217 AssertPtrNullReturn(pfnIn, VERR_INVALID_POINTER);
218 AssertPtrNullReturn(pfnOutStr, VERR_INVALID_POINTER);
219 AssertPtrNullReturn(pfnInStr, VERR_INVALID_POINTER);
220 AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
221 AssertReturn(*pszDesc != '\0', VERR_INVALID_POINTER);
222 AssertReturn(strlen(pszDesc) < 128, VERR_INVALID_POINTER);
223 if (paExtDescs)
224 {
225 AssertPtrReturn(paExtDescs, VERR_INVALID_POINTER);
226 for (size_t i = 0;; i++)
227 {
228 const char *pszIn = paExtDescs[i].pszIn;
229 const char *pszOut = paExtDescs[i].pszIn;
230 if (!pszIn && !pszOut)
231 break;
232 AssertReturn(i < _8K, VERR_OUT_OF_RANGE);
233 AssertReturn(!pszIn || strlen(pszIn) < 128, VERR_INVALID_POINTER);
234 AssertReturn(!pszOut || strlen(pszOut) < 128, VERR_INVALID_POINTER);
235 }
236 }
237
238 /*
239 * Ensure that we've got table space for it.
240 */
241#ifndef VBOX_WITH_STATISTICS
242 uint16_t const idxStats = UINT16_MAX;
243#else
244 uint32_t const idxStats = pVM->iom.s.cIoPortStats;
245 uint32_t const cNewIoPortStats = idxStats + cPorts;
246 AssertReturn(cNewIoPortStats <= _64K, VERR_IOM_TOO_MANY_IOPORT_REGISTRATIONS);
247 if (cNewIoPortStats > pVM->iom.s.cIoPortStatsAllocation)
248 {
249 int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORT_STATS, cNewIoPortStats, NULL);
250 AssertLogRelRCReturn(rc, rc);
251 AssertReturn(idxStats == pVM->iom.s.cIoPortStats, VERR_IOM_IOPORT_IPE_1);
252 AssertReturn(cNewIoPortStats <= pVM->iom.s.cIoPortStatsAllocation, VERR_IOM_IOPORT_IPE_2);
253 }
254#endif
255
256 uint32_t idx = pVM->iom.s.cIoPortRegs;
257 if (idx >= pVM->iom.s.cIoPortAlloc)
258 {
259 int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORTS, pVM->iom.s.cIoPortAlloc + 1, NULL);
260 AssertLogRelRCReturn(rc, rc);
261 AssertReturn(idx == pVM->iom.s.cIoPortRegs, VERR_IOM_IOPORT_IPE_1);
262 AssertReturn(idx < pVM->iom.s.cIoPortAlloc, VERR_IOM_IOPORT_IPE_2);
263 }
264
265 /*
266 * Enter it.
267 */
268 pVM->iom.s.paIoPortRegs[idx].pvUser = pvUser;
269 pVM->iom.s.paIoPortRegs[idx].pDevIns = pDevIns;
270 pVM->iom.s.paIoPortRegs[idx].pfnOutCallback = pfnOut ? pfnOut : iomR3IOPortDummyNewOut;
271 pVM->iom.s.paIoPortRegs[idx].pfnInCallback = pfnIn ? pfnIn : iomR3IOPortDummyNewIn;
272 pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback = pfnOutStr ? pfnOutStr : iomR3IOPortDummyNewOutStr;
273 pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback = pfnInStr ? pfnInStr : iomR3IOPortDummyNewInStr;
274 pVM->iom.s.paIoPortRegs[idx].pszDesc = pszDesc;
275 pVM->iom.s.paIoPortRegs[idx].paExtDescs = paExtDescs;
276 pVM->iom.s.paIoPortRegs[idx].pPciDev = pPciDev;
277 pVM->iom.s.paIoPortRegs[idx].iPciRegion = iPciRegion;
278 pVM->iom.s.paIoPortRegs[idx].cPorts = cPorts;
279 pVM->iom.s.paIoPortRegs[idx].uPort = UINT16_MAX;
280 pVM->iom.s.paIoPortRegs[idx].idxStats = (uint16_t)idxStats;
281 pVM->iom.s.paIoPortRegs[idx].fMapped = false;
282 pVM->iom.s.paIoPortRegs[idx].fFlags = (uint8_t)fFlags;
283 pVM->iom.s.paIoPortRegs[idx].idxSelf = idx;
284
285 pVM->iom.s.cIoPortRegs = idx + 1;
286 *phIoPorts = idx;
287 return VINF_SUCCESS;
288}
289
290
291/**
292 * Worker for PDMDEVHLPR3::pfnIoPortMap.
293 */
294VMMR3_INT_DECL(int) IOMR3IoPortMap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT uPort)
295{
296 /*
297 * Validate input and state.
298 */
299 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
300 AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
301 PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
302 AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
303
304 RTIOPORT const cPorts = pRegEntry->cPorts;
305 AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%s\n", cPorts), VERR_IOM_IOPORT_IPE_1);
306 AssertReturn((uint32_t)uPort + cPorts <= _64K, VERR_OUT_OF_RANGE);
307 RTIOPORT const uLastPort = uPort + cPorts - 1;
308
309 /*
310 * Do the mapping.
311 */
312 int rc = VINF_SUCCESS;
313 IOM_LOCK_EXCL(pVM);
314
315 if (!pRegEntry->fMapped)
316 {
317 uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
318 Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
319
320 PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
321 PIOMIOPORTLOOKUPENTRY pEntry;
322 if (cEntries > 0)
323 {
324 uint32_t iFirst = 0;
325 uint32_t iEnd = cEntries;
326 uint32_t i = cEntries / 2;
327 for (;;)
328 {
329 pEntry = &paEntries[i];
330 if (pEntry->uLastPort < uPort)
331 {
332 i += 1;
333 if (i < iEnd)
334 iFirst = i;
335 else
336 {
337 /* Insert after the entry we just considered: */
338 pEntry += 1;
339 if (i < cEntries)
340 memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
341 break;
342 }
343 }
344 else if (pEntry->uFirstPort > uLastPort)
345 {
346 if (i > iFirst)
347 iEnd = i;
348 else
349 {
350 /* Insert at the entry we just considered: */
351 if (i < cEntries)
352 memmove(pEntry + 1, pEntry, sizeof(*pEntry) * (cEntries - i));
353 break;
354 }
355 }
356 else
357 {
358 /* Oops! We've got a conflict. */
359 AssertLogRelMsgFailed(("%x..%x (%s) conflicts with existing mapping %x..%x (%s)\n",
360 uPort, uLastPort, pRegEntry->pszDesc,
361 pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
362 IOM_UNLOCK_EXCL(pVM);
363 return VERR_IOM_IOPORT_RANGE_CONFLICT;
364 }
365
366 i = iFirst + (iEnd - iFirst) / 2;
367 }
368 }
369 else
370 pEntry = paEntries;
371
372 /*
373 * Fill in the entry and bump the table size.
374 */
375 pEntry->idx = hIoPorts;
376 pEntry->uFirstPort = uPort;
377 pEntry->uLastPort = uLastPort;
378 pVM->iom.s.cIoPortLookupEntries = cEntries + 1;
379
380 pRegEntry->uPort = uPort;
381 pRegEntry->fMapped = true;
382
383#ifdef VBOX_WITH_STATISTICS
384 /* Don't register stats here when we're creating the VM as the
385 statistics table may still be reallocated. */
386 if (pVM->enmVMState >= VMSTATE_CREATED)
387 iomR3IoPortRegStats(pVM, pRegEntry);
388#endif
389
390#ifdef VBOX_STRICT
391 /*
392 * Assert table sanity.
393 */
394 AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
395 AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
396
397 RTIOPORT uPortPrev = paEntries[0].uLastPort;
398 for (size_t i = 1; i <= cEntries; i++)
399 {
400 AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
401 AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
402 AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
403 uPortPrev = paEntries[i].uLastPort;
404 }
405#endif
406 }
407 else
408 {
409 AssertFailed();
410 rc = VERR_IOM_IOPORTS_ALREADY_MAPPED;
411 }
412
413 IOM_UNLOCK_EXCL(pVM);
414 return rc;
415}
416
417
418/**
419 * Worker for PDMDEVHLPR3::pfnIoPortUnmap.
420 */
421VMMR3_INT_DECL(int) IOMR3IoPortUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
422{
423 /*
424 * Validate input and state.
425 */
426 AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
427 AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
428 PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
429 AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
430
431 /*
432 * Do the mapping.
433 */
434 int rc;
435 IOM_LOCK_EXCL(pVM);
436
437 if (pRegEntry->fMapped)
438 {
439 RTIOPORT const uPort = pRegEntry->uPort;
440 RTIOPORT const uLastPort = uPort + pRegEntry->cPorts - 1;
441 uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
442 Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
443 Assert(cEntries > 0);
444
445 PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
446 uint32_t iFirst = 0;
447 uint32_t iEnd = cEntries;
448 uint32_t i = cEntries / 2;
449 for (;;)
450 {
451 PIOMIOPORTLOOKUPENTRY pEntry = &paEntries[i];
452 if (pEntry->uLastPort < uPort)
453 {
454 i += 1;
455 if (i < iEnd)
456 iFirst = i;
457 else
458 {
459 rc = VERR_IOM_IOPORT_IPE_1;
460 AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
461 }
462 }
463 else if (pEntry->uFirstPort > uLastPort)
464 {
465 if (i > iFirst)
466 iEnd = i;
467 else
468 {
469 rc = VERR_IOM_IOPORT_IPE_1;
470 AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
471 }
472 }
473 else if (pEntry->idx == hIoPorts)
474 {
475 Assert(pEntry->uFirstPort == uPort);
476 Assert(pEntry->uLastPort == uLastPort);
477#ifdef VBOX_WITH_STATISTICS
478 iomR3IoPortDeregStats(pVM, pRegEntry, uPort);
479#endif
480 if (i + 1 < cEntries)
481 memmove(pEntry, pEntry + 1, sizeof(*pEntry) * (cEntries - i - 1));
482 pVM->iom.s.cIoPortLookupEntries = cEntries - 1;
483 pRegEntry->uPort = UINT16_MAX;
484 pRegEntry->fMapped = false;
485 rc = VINF_SUCCESS;
486 break;
487 }
488 else
489 {
490 AssertLogRelMsgFailed(("Lookig for %x..%x (%s), found %x..%x (%s) instead!\n",
491 uPort, uLastPort, pRegEntry->pszDesc,
492 pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
493 rc = VERR_IOM_IOPORT_IPE_1;
494 break;
495 }
496
497 i = iFirst + (iEnd - iFirst) / 2;
498 }
499
500#ifdef VBOX_STRICT
501 /*
502 * Assert table sanity.
503 */
504 AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
505 AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
506
507 RTIOPORT uPortPrev = paEntries[0].uLastPort;
508 for (i = 1; i < cEntries - 1; i++)
509 {
510 AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
511 AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
512 AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
513 uPortPrev = paEntries[i].uLastPort;
514 }
515#endif
516 }
517 else
518 {
519 AssertFailed();
520 rc = VERR_IOM_IOPORTS_NOT_MAPPED;
521 }
522
523 IOM_UNLOCK_EXCL(pVM);
524 return rc;
525}
526
527
528/**
529 * Display a single I/O port ring-3 range.
530 *
531 * @returns 0
532 * @param pNode Pointer to I/O port HC range.
533 * @param pvUser Pointer to info output callback structure.
534 */
535static DECLCALLBACK(int) iomR3IOPortInfoOneR3(PAVLROIOPORTNODECORE pNode, void *pvUser)
536{
537 PIOMIOPORTRANGER3 pRange = (PIOMIOPORTRANGER3)pNode;
538 PCDBGFINFOHLP pHlp = (PCDBGFINFOHLP)pvUser;
539 pHlp->pfnPrintf(pHlp,
540 "%04x-%04x %p %p %p %p %s\n",
541 pRange->Core.Key,
542 pRange->Core.KeyLast,
543 pRange->pDevIns,
544 pRange->pfnInCallback,
545 pRange->pfnOutCallback,
546 pRange->pvUser,
547 pRange->pszDesc);
548 return 0;
549}
550
551
552/**
553 * Display all registered I/O port ranges.
554 *
555 * @param pVM The cross context VM structure.
556 * @param pHlp The info helpers.
557 * @param pszArgs Arguments, ignored.
558 */
559DECLCALLBACK(void) iomR3IoPortInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
560{
561 /* No locking needed here as registerations are only happening during VMSTATE_CREATING. */
562 pHlp->pfnPrintf(pHlp,
563 "I/O port registrations: %u (%u allocated)\n"
564 " ## Ctx Ports Mapping PCI Description\n",
565 pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc);
566 PIOMIOPORTENTRYR3 paRegs = pVM->iom.s.paIoPortRegs;
567 for (uint32_t i = 0; i < pVM->iom.s.cIoPortRegs; i++)
568 {
569 const char * const pszRing = paRegs[i].fRing0 ? paRegs[i].fRawMode ? "+0+C" : "+0 "
570 : paRegs[i].fRawMode ? "+C " : " ";
571 if (paRegs[i].fMapped && paRegs[i].pPciDev)
572 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
573 paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1,
574 paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
575 else if (paRegs[i].fMapped && !paRegs[i].pPciDev)
576 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
577 paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1, paRegs[i].pszDesc);
578 else if (paRegs[i].pPciDev)
579 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
580 paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
581 else
582 pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped %s\n",
583 paRegs[i].idxSelf, pszRing, paRegs[i].cPorts, paRegs[i].pszDesc);
584 }
585
586 /* Legacy registration: */
587 NOREF(pszArgs);
588 pHlp->pfnPrintf(pHlp,
589 "I/O Port R3 ranges (pVM=%p)\n"
590 "Range %.*s %.*s %.*s %.*s Description\n",
591 pVM,
592 sizeof(RTHCPTR) * 2, "pDevIns ",
593 sizeof(RTHCPTR) * 2, "In ",
594 sizeof(RTHCPTR) * 2, "Out ",
595 sizeof(RTHCPTR) * 2, "pvUser ");
596 IOM_LOCK_SHARED(pVM);
597 RTAvlroIOPortDoWithAll(&pVM->iom.s.pTreesR3->IOPortTreeR3, true, iomR3IOPortInfoOneR3, (void *)pHlp);
598 IOM_UNLOCK_SHARED(pVM);
599
600 pHlp->pfnPrintf(pHlp,
601 "I/O Port R0 ranges (pVM=%p)\n"
602 "Range %.*s %.*s %.*s %.*s Description\n",
603 pVM,
604 sizeof(RTHCPTR) * 2, "pDevIns ",
605 sizeof(RTHCPTR) * 2, "In ",
606 sizeof(RTHCPTR) * 2, "Out ",
607 sizeof(RTHCPTR) * 2, "pvUser ");
608 IOM_LOCK_SHARED(pVM);
609 RTAvlroIOPortDoWithAll(&pVM->iom.s.pTreesR3->IOPortTreeR0, true, iomR3IOPortInfoOneR3, (void *)pHlp);
610 IOM_UNLOCK_SHARED(pVM);
611}
612
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette