IOMR3IoPort.cpp@ 81613

Last change on this file since 81613 was 81564, checked in by vboxsync, 5 years ago
VMM/PDMDevHlp: Adding helpers for getting the mapping addresses of I/O port and MMIO regions, mainly for info handlers and logging (thus only ring-3). bugref:9218
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 26.1 KB

Line
1	/* $Id: IOMR3IoPort.cpp 81564 2019-10-29 10:38:26Z vboxsync $ */
2	/** @file
3	* IOM - Input / Output Monitor, I/O port related APIs.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_IOM_IOPORT
23	#include <VBox/vmm/iom.h>
24	#include <VBox/sup.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/stam.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include "IOMInternal.h"
31	#include <VBox/vmm/vm.h>
32
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38
39	#include "IOMInline.h"
40
41
42	#ifdef VBOX_WITH_STATISTICS
43
44	/**
45	* Register statistics for an I/O port entry.
46	*/
47	void iomR3IoPortRegStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry)
48	{
49	PIOMIOPORTSTATSENTRY pStats = &pVM->iom.s.paIoPortStats[pRegEntry->idxStats];
50	PCIOMIOPORTDESC pExtDesc = pRegEntry->paExtDescs;
51	unsigned uPort = pRegEntry->uPort;
52	unsigned const uFirstPort = uPort;
53	unsigned const uEndPort = uPort + pRegEntry->cPorts;
54
55	/* Register a dummy statistics for the prefix. */
56	char szName[80];
57	size_t cchPrefix;
58	if (uFirstPort < uEndPort - 1)
59	cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/NewPorts/%04x-%04x", uFirstPort, uEndPort - 1);
60	else
61	cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/NewPorts/%04x", uPort);
62	const char *pszDesc = pRegEntry->pszDesc;
63	char *pszFreeDesc = NULL;
64	if (pRegEntry->pDevIns && pRegEntry->pDevIns->iInstance > 0 && pszDesc)
65	pszDesc = pszFreeDesc = RTStrAPrintf2("%u / %s", pRegEntry->pDevIns->iInstance, pszDesc);
66	int rc = STAMR3Register(pVM, &pRegEntry->idxSelf, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, szName,
67	STAMUNIT_NONE, pRegEntry->pszDesc);
68	AssertRC(rc);
69	RTStrFree(pszFreeDesc);
70
71	/* Register stats for each port under it */
72	do
73	{
74	size_t cchBaseNm;
75	if (uFirstPort < uEndPort - 1)
76	cchBaseNm = cchPrefix + RTStrPrintf(&szName[cchPrefix], sizeof(szName) - cchPrefix, "/%04x-", uPort);
77	else
78	{
79	szName[cchPrefix] = '/';
80	cchBaseNm = cchPrefix + 1;
81	}
82
83	# define SET_NM_SUFFIX(a_sz) memcpy(&szName[cchBaseNm], a_sz, sizeof(a_sz));
84	const char * const pszInDesc = pExtDesc ? pExtDesc->pszIn : NULL;
85	const char * const pszOutDesc = pExtDesc ? pExtDesc->pszOut : NULL;
86
87	/* register the statistics counters. */
88	SET_NM_SUFFIX("In-R3");
89	rc = STAMR3Register(pVM, &pStats->InR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
90	SET_NM_SUFFIX("Out-R3");
91	rc = STAMR3Register(pVM, &pStats->OutR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
92	SET_NM_SUFFIX("In-RZ");
93	rc = STAMR3Register(pVM, &pStats->InRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszInDesc); AssertRC(rc);
94	SET_NM_SUFFIX("Out-RZ");
95	rc = STAMR3Register(pVM, &pStats->OutRZ, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, pszOutDesc); AssertRC(rc);
96	SET_NM_SUFFIX("In-RZtoR3");
97	rc = STAMR3Register(pVM, &pStats->InRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
98	SET_NM_SUFFIX("Out-RZtoR3");
99	rc = STAMR3Register(pVM, &pStats->OutRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
100
101	/* Profiling */
102	SET_NM_SUFFIX("In-R3-Prof");
103	rc = STAMR3Register(pVM, &pStats->ProfInR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
104	SET_NM_SUFFIX("Out-R3-Prof");
105	rc = STAMR3Register(pVM, &pStats->ProfOutR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
106	SET_NM_SUFFIX("In-RZ-Prof");
107	rc = STAMR3Register(pVM, &pStats->ProfInRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszInDesc); AssertRC(rc);
108	SET_NM_SUFFIX("Out-RZ-Prof");
109	rc = STAMR3Register(pVM, &pStats->ProfOutRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, pszOutDesc); AssertRC(rc);
110
111	pStats++;
112	uPort++;
113	if (pExtDesc)
114	pExtDesc = pszInDesc \|\| pszOutDesc ? pExtDesc + 1 : NULL;
115	} while (uPort < uEndPort);
116	}
117
118
119	/**
120	* Deregister statistics for an I/O port entry.
121	*/
122	static void iomR3IoPortDeregStats(PVM pVM, PIOMIOPORTENTRYR3 pRegEntry, unsigned uPort)
123	{
124	char szPrefix[80];
125	size_t cchPrefix;
126	if (pRegEntry->cPorts > 1)
127	cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/NewPorts/%04x-%04x", uPort, uPort + pRegEntry->cPorts - 1);
128	else
129	cchPrefix = RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/NewPorts/%04x", uPort);
130	STAMR3DeregisterByPrefix(pVM->pUVM, szPrefix);
131	}
132
133	#endif /* VBOX_WITH_STATISTICS */
134
135
136	/**
137	* @callback_method_impl{FNIOMIOPORTNEWIN,
138	* Dummy Port I/O Handler for IN operations.}
139	*/
140	static DECLCALLBACK(VBOXSTRICTRC)
141	iomR3IOPortDummyNewIn(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint32_t pu32, unsigned cb)
142	{
143	NOREF(pDevIns); NOREF(pvUser); NOREF(Port);
144	switch (cb)
145	{
146	case 1: *pu32 = 0xff; break;
147	case 2: *pu32 = 0xffff; break;
148	case 4: *pu32 = UINT32_C(0xffffffff); break;
149	default:
150	AssertReleaseMsgFailed(("cb=%d\n", cb));
151	return VERR_IOM_IOPORT_IPE_2;
152	}
153	return VINF_SUCCESS;
154	}
155
156
157	/**
158	* @callback_method_impl{FNIOMIOPORTNEWINSTRING,
159	* Dummy Port I/O Handler for string IN operations.}
160	*/
161	static DECLCALLBACK(VBOXSTRICTRC)
162	iomR3IOPortDummyNewInStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint8_t pbDst, uint32_t *pcTransfer, unsigned cb)
163	{
164	NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbDst); NOREF(pcTransfer); NOREF(cb);
165	return VINF_SUCCESS;
166	}
167
168
169	/**
170	* @callback_method_impl{FNIOMIOPORTNEWOUT,
171	* Dummy Port I/O Handler for OUT operations.}
172	*/
173	static DECLCALLBACK(VBOXSTRICTRC)
174	iomR3IOPortDummyNewOut(PPDMDEVINS pDevIns, void *pvUser, RTIOPORT Port, uint32_t u32, unsigned cb)
175	{
176	NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(u32); NOREF(cb);
177	return VINF_SUCCESS;
178	}
179
180
181	/**
182	* @callback_method_impl{FNIOMIOPORTNEWOUTSTRING,
183	* Dummy Port I/O Handler for string OUT operations.}
184	*/
185	static DECLCALLBACK(VBOXSTRICTRC)
186	iomR3IOPortDummyNewOutStr(PPDMDEVINS pDevIns, void pvUser, RTIOPORT Port, uint8_t const pbSrc, uint32_t *pcTransfer, unsigned cb)
187	{
188	NOREF(pDevIns); NOREF(pvUser); NOREF(Port); NOREF(pbSrc); NOREF(pcTransfer); NOREF(cb);
189	return VINF_SUCCESS;
190	}
191
192
193
194	/**
195	* Worker for PDMDEVHLPR3::pfnIoPortCreateEx.
196	*/
197	VMMR3_INT_DECL(int) IOMR3IoPortCreate(PVM pVM, PPDMDEVINS pDevIns, RTIOPORT cPorts, uint32_t fFlags, PPDMPCIDEV pPciDev,
198	uint32_t iPciRegion, PFNIOMIOPORTNEWOUT pfnOut, PFNIOMIOPORTNEWIN pfnIn,
199	PFNIOMIOPORTNEWOUTSTRING pfnOutStr, PFNIOMIOPORTNEWINSTRING pfnInStr, RTR3PTR pvUser,
200	const char *pszDesc, PCIOMIOPORTDESC paExtDescs, PIOMIOPORTHANDLE phIoPorts)
201	{
202	/*
203	* Validate input.
204	*/
205	AssertPtrReturn(phIoPorts, VERR_INVALID_POINTER);
206	*phIoPorts = UINT32_MAX;
207	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
208	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
209
210	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
211
212	AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%#x\n", cPorts), VERR_OUT_OF_RANGE);
213	AssertReturn(!(fFlags & ~IOM_IOPORT_F_VALID_MASK), VERR_INVALID_FLAGS);
214
215	AssertReturn(pfnOut \|\| pfnIn \|\| pfnOutStr \|\| pfnInStr, VERR_INVALID_PARAMETER);
216	AssertPtrNullReturn(pfnOut, VERR_INVALID_POINTER);
217	AssertPtrNullReturn(pfnIn, VERR_INVALID_POINTER);
218	AssertPtrNullReturn(pfnOutStr, VERR_INVALID_POINTER);
219	AssertPtrNullReturn(pfnInStr, VERR_INVALID_POINTER);
220	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
221	AssertReturn(*pszDesc != '\0', VERR_INVALID_POINTER);
222	AssertReturn(strlen(pszDesc) < 128, VERR_INVALID_POINTER);
223	if (paExtDescs)
224	{
225	AssertPtrReturn(paExtDescs, VERR_INVALID_POINTER);
226	for (size_t i = 0;; i++)
227	{
228	const char *pszIn = paExtDescs[i].pszIn;
229	const char *pszOut = paExtDescs[i].pszIn;
230	if (!pszIn && !pszOut)
231	break;
232	AssertReturn(i < _8K, VERR_OUT_OF_RANGE);
233	AssertReturn(!pszIn \|\| strlen(pszIn) < 128, VERR_INVALID_POINTER);
234	AssertReturn(!pszOut \|\| strlen(pszOut) < 128, VERR_INVALID_POINTER);
235	}
236	}
237
238	/*
239	* Ensure that we've got table space for it.
240	*/
241	#ifndef VBOX_WITH_STATISTICS
242	uint16_t const idxStats = UINT16_MAX;
243	#else
244	uint32_t const idxStats = pVM->iom.s.cIoPortStats;
245	uint32_t const cNewIoPortStats = idxStats + cPorts;
246	AssertReturn(cNewIoPortStats <= _64K, VERR_IOM_TOO_MANY_IOPORT_REGISTRATIONS);
247	if (cNewIoPortStats > pVM->iom.s.cIoPortStatsAllocation)
248	{
249	int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORT_STATS, cNewIoPortStats, NULL);
250	AssertLogRelRCReturn(rc, rc);
251	AssertReturn(idxStats == pVM->iom.s.cIoPortStats, VERR_IOM_IOPORT_IPE_1);
252	AssertReturn(cNewIoPortStats <= pVM->iom.s.cIoPortStatsAllocation, VERR_IOM_IOPORT_IPE_2);
253	}
254	#endif
255
256	uint32_t idx = pVM->iom.s.cIoPortRegs;
257	if (idx >= pVM->iom.s.cIoPortAlloc)
258	{
259	int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_IO_PORTS, pVM->iom.s.cIoPortAlloc + 1, NULL);
260	AssertLogRelRCReturn(rc, rc);
261	AssertReturn(idx == pVM->iom.s.cIoPortRegs, VERR_IOM_IOPORT_IPE_1);
262	AssertReturn(idx < pVM->iom.s.cIoPortAlloc, VERR_IOM_IOPORT_IPE_2);
263	}
264
265	/*
266	* Enter it.
267	*/
268	pVM->iom.s.paIoPortRegs[idx].pvUser = pvUser;
269	pVM->iom.s.paIoPortRegs[idx].pDevIns = pDevIns;
270	pVM->iom.s.paIoPortRegs[idx].pfnOutCallback = pfnOut ? pfnOut : iomR3IOPortDummyNewOut;
271	pVM->iom.s.paIoPortRegs[idx].pfnInCallback = pfnIn ? pfnIn : iomR3IOPortDummyNewIn;
272	pVM->iom.s.paIoPortRegs[idx].pfnOutStrCallback = pfnOutStr ? pfnOutStr : iomR3IOPortDummyNewOutStr;
273	pVM->iom.s.paIoPortRegs[idx].pfnInStrCallback = pfnInStr ? pfnInStr : iomR3IOPortDummyNewInStr;
274	pVM->iom.s.paIoPortRegs[idx].pszDesc = pszDesc;
275	pVM->iom.s.paIoPortRegs[idx].paExtDescs = paExtDescs;
276	pVM->iom.s.paIoPortRegs[idx].pPciDev = pPciDev;
277	pVM->iom.s.paIoPortRegs[idx].iPciRegion = iPciRegion;
278	pVM->iom.s.paIoPortRegs[idx].cPorts = cPorts;
279	pVM->iom.s.paIoPortRegs[idx].uPort = UINT16_MAX;
280	pVM->iom.s.paIoPortRegs[idx].idxStats = (uint16_t)idxStats;
281	pVM->iom.s.paIoPortRegs[idx].fMapped = false;
282	pVM->iom.s.paIoPortRegs[idx].fFlags = (uint8_t)fFlags;
283	pVM->iom.s.paIoPortRegs[idx].idxSelf = idx;
284
285	pVM->iom.s.cIoPortRegs = idx + 1;
286	#ifdef VBOX_WITH_STATISTICS
287	pVM->iom.s.cIoPortStats = cNewIoPortStats;
288	#endif
289	*phIoPorts = idx;
290	return VINF_SUCCESS;
291	}
292
293
294	/**
295	* Worker for PDMDEVHLPR3::pfnIoPortMap.
296	*/
297	VMMR3_INT_DECL(int) IOMR3IoPortMap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts, RTIOPORT uPort)
298	{
299	/*
300	* Validate input and state.
301	*/
302	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
303	AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
304	PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
305	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
306
307	RTIOPORT const cPorts = pRegEntry->cPorts;
308	AssertMsgReturn(cPorts > 0 && cPorts <= _8K, ("cPorts=%s\n", cPorts), VERR_IOM_IOPORT_IPE_1);
309	AssertReturn((uint32_t)uPort + cPorts <= _64K, VERR_OUT_OF_RANGE);
310	RTIOPORT const uLastPort = uPort + cPorts - 1;
311
312	/*
313	* Do the mapping.
314	*/
315	int rc = VINF_SUCCESS;
316	IOM_LOCK_EXCL(pVM);
317
318	if (!pRegEntry->fMapped)
319	{
320	uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
321	Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
322
323	PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
324	PIOMIOPORTLOOKUPENTRY pEntry;
325	if (cEntries > 0)
326	{
327	uint32_t iFirst = 0;
328	uint32_t iEnd = cEntries;
329	uint32_t i = cEntries / 2;
330	for (;;)
331	{
332	pEntry = &paEntries[i];
333	if (pEntry->uLastPort < uPort)
334	{
335	i += 1;
336	if (i < iEnd)
337	iFirst = i;
338	else
339	{
340	/* Insert after the entry we just considered: */
341	pEntry += 1;
342	if (i < cEntries)
343	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
344	break;
345	}
346	}
347	else if (pEntry->uFirstPort > uLastPort)
348	{
349	if (i > iFirst)
350	iEnd = i;
351	else
352	{
353	/* Insert at the entry we just considered: */
354	if (i < cEntries)
355	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
356	break;
357	}
358	}
359	else
360	{
361	/* Oops! We've got a conflict. */
362	AssertLogRelMsgFailed(("%x..%x (%s) conflicts with existing mapping %x..%x (%s)\n",
363	uPort, uLastPort, pRegEntry->pszDesc,
364	pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
365	IOM_UNLOCK_EXCL(pVM);
366	return VERR_IOM_IOPORT_RANGE_CONFLICT;
367	}
368
369	i = iFirst + (iEnd - iFirst) / 2;
370	}
371	}
372	else
373	pEntry = paEntries;
374
375	/*
376	* Fill in the entry and bump the table size.
377	*/
378	pEntry->idx = hIoPorts;
379	pEntry->uFirstPort = uPort;
380	pEntry->uLastPort = uLastPort;
381	pVM->iom.s.cIoPortLookupEntries = cEntries + 1;
382
383	pRegEntry->uPort = uPort;
384	pRegEntry->fMapped = true;
385
386	#ifdef VBOX_WITH_STATISTICS
387	/* Don't register stats here when we're creating the VM as the
388	statistics table may still be reallocated. */
389	if (pVM->enmVMState >= VMSTATE_CREATED)
390	iomR3IoPortRegStats(pVM, pRegEntry);
391	#endif
392
393	#ifdef VBOX_STRICT
394	/*
395	* Assert table sanity.
396	*/
397	AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
398	AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
399
400	RTIOPORT uPortPrev = paEntries[0].uLastPort;
401	for (size_t i = 1; i <= cEntries; i++)
402	{
403	AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
404	AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
405	AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
406	uPortPrev = paEntries[i].uLastPort;
407	}
408	#endif
409	}
410	else
411	{
412	AssertFailed();
413	rc = VERR_IOM_IOPORTS_ALREADY_MAPPED;
414	}
415
416	IOM_UNLOCK_EXCL(pVM);
417	return rc;
418	}
419
420
421	/**
422	* Worker for PDMDEVHLPR3::pfnIoPortUnmap.
423	*/
424	VMMR3_INT_DECL(int) IOMR3IoPortUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
425	{
426	/*
427	* Validate input and state.
428	*/
429	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
430	AssertReturn(hIoPorts < pVM->iom.s.cIoPortRegs, VERR_IOM_INVALID_IOPORT_HANDLE);
431	PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
432	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
433
434	/*
435	* Do the mapping.
436	*/
437	int rc;
438	IOM_LOCK_EXCL(pVM);
439
440	if (pRegEntry->fMapped)
441	{
442	RTIOPORT const uPort = pRegEntry->uPort;
443	RTIOPORT const uLastPort = uPort + pRegEntry->cPorts - 1;
444	uint32_t const cEntries = RT_MIN(pVM->iom.s.cIoPortLookupEntries, pVM->iom.s.cIoPortRegs);
445	Assert(pVM->iom.s.cIoPortLookupEntries == cEntries);
446	Assert(cEntries > 0);
447
448	PIOMIOPORTLOOKUPENTRY paEntries = pVM->iom.s.paIoPortLookup;
449	uint32_t iFirst = 0;
450	uint32_t iEnd = cEntries;
451	uint32_t i = cEntries / 2;
452	for (;;)
453	{
454	PIOMIOPORTLOOKUPENTRY pEntry = &paEntries[i];
455	if (pEntry->uLastPort < uPort)
456	{
457	i += 1;
458	if (i < iEnd)
459	iFirst = i;
460	else
461	{
462	rc = VERR_IOM_IOPORT_IPE_1;
463	AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
464	}
465	}
466	else if (pEntry->uFirstPort > uLastPort)
467	{
468	if (i > iFirst)
469	iEnd = i;
470	else
471	{
472	rc = VERR_IOM_IOPORT_IPE_1;
473	AssertLogRelMsgFailedBreak(("%x..%x (%s) not found!\n", uPort, uLastPort, pRegEntry->pszDesc));
474	}
475	}
476	else if (pEntry->idx == hIoPorts)
477	{
478	Assert(pEntry->uFirstPort == uPort);
479	Assert(pEntry->uLastPort == uLastPort);
480	#ifdef VBOX_WITH_STATISTICS
481	iomR3IoPortDeregStats(pVM, pRegEntry, uPort);
482	#endif
483	if (i + 1 < cEntries)
484	memmove(pEntry, pEntry + 1, sizeof(pEntry) (cEntries - i - 1));
485	pVM->iom.s.cIoPortLookupEntries = cEntries - 1;
486	pRegEntry->uPort = UINT16_MAX;
487	pRegEntry->fMapped = false;
488	rc = VINF_SUCCESS;
489	break;
490	}
491	else
492	{
493	AssertLogRelMsgFailed(("Lookig for %x..%x (%s), found %x..%x (%s) instead!\n",
494	uPort, uLastPort, pRegEntry->pszDesc,
495	pEntry->uFirstPort, pEntry->uLastPort, pVM->iom.s.paIoPortRegs[pEntry->idx].pszDesc));
496	rc = VERR_IOM_IOPORT_IPE_1;
497	break;
498	}
499
500	i = iFirst + (iEnd - iFirst) / 2;
501	}
502
503	#ifdef VBOX_STRICT
504	/*
505	* Assert table sanity.
506	*/
507	AssertMsg(paEntries[0].uLastPort >= paEntries[0].uFirstPort, ("%#x %#x\n", paEntries[0].uLastPort, paEntries[0].uFirstPort));
508	AssertMsg(paEntries[0].idx < pVM->iom.s.cIoPortRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cIoPortRegs));
509
510	RTIOPORT uPortPrev = paEntries[0].uLastPort;
511	for (i = 1; i < cEntries - 1; i++)
512	{
513	AssertMsg(paEntries[i].uLastPort >= paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, paEntries[i].uLastPort, paEntries[i].uFirstPort));
514	AssertMsg(paEntries[i].idx < pVM->iom.s.cIoPortRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cIoPortRegs));
515	AssertMsg(uPortPrev < paEntries[i].uFirstPort, ("%u: %#x %#x\n", i, uPortPrev, paEntries[i].uFirstPort));
516	uPortPrev = paEntries[i].uLastPort;
517	}
518	#endif
519	}
520	else
521	{
522	AssertFailed();
523	rc = VERR_IOM_IOPORTS_NOT_MAPPED;
524	}
525
526	IOM_UNLOCK_EXCL(pVM);
527	return rc;
528	}
529
530
531	/**
532	* Validates @a hIoPorts, making sure it belongs to @a pDevIns.
533	*
534	* @returns VBox status code.
535	* @param pVM The cross context VM structure.
536	* @param pDevIns The device which allegedly owns @a hIoPorts.
537	* @param hIoPorts The handle to validate.
538	*/
539	VMMR3_INT_DECL(int) IOMR3IoPortValidateHandle(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
540	{
541	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
542	AssertReturn(hIoPorts < RT_MIN(pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc), VERR_IOM_INVALID_IOPORT_HANDLE);
543	PIOMIOPORTENTRYR3 const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
544	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_IOPORT_HANDLE);
545	return VINF_SUCCESS;
546	}
547
548
549	/**
550	* Gets the mapping address of I/O ports @a hIoPorts.
551	*
552	* @returns Mapping address if mapped, UINT32_MAX if not mapped or invalid
553	* input.
554	* @param pVM The cross context VM structure.
555	* @param pDevIns The device which allegedly owns @a hRegion.
556	* @param hIoPorts The handle to I/O port region.
557	*/
558	VMMR3_INT_DECL(uint32_t) IOMR3IoPortGetMappingAddress(PVM pVM, PPDMDEVINS pDevIns, IOMIOPORTHANDLE hIoPorts)
559	{
560	AssertPtrReturn(pDevIns, UINT32_MAX);
561	AssertReturn(hIoPorts < RT_MIN(pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc), UINT32_MAX);
562	IOMIOPORTENTRYR3 volatile * const pRegEntry = &pVM->iom.s.paIoPortRegs[hIoPorts];
563	AssertReturn(pRegEntry->pDevIns == pDevIns, UINT32_MAX);
564	for (uint32_t iTry = 0; ; iTry++)
565	{
566	bool fMapped = pRegEntry->fMapped;
567	RTIOPORT uPort = pRegEntry->uPort;
568	if ( ( ASMAtomicReadBool(&pRegEntry->fMapped) == fMapped
569	&& uPort == pRegEntry->uPort)
570	\|\| iTry > 1024)
571	return fMapped ? uPort : UINT32_MAX;
572	ASMNopPause();
573	}
574	}
575
576
577	/**
578	* Display a single I/O port ring-3 range.
579	*
580	* @returns 0
581	* @param pNode Pointer to I/O port HC range.
582	* @param pvUser Pointer to info output callback structure.
583	*/
584	static DECLCALLBACK(int) iomR3IOPortInfoOneR3(PAVLROIOPORTNODECORE pNode, void *pvUser)
585	{
586	PIOMIOPORTRANGER3 pRange = (PIOMIOPORTRANGER3)pNode;
587	PCDBGFINFOHLP pHlp = (PCDBGFINFOHLP)pvUser;
588	pHlp->pfnPrintf(pHlp,
589	"%04x-%04x %p %p %p %p %s\n",
590	pRange->Core.Key,
591	pRange->Core.KeyLast,
592	pRange->pDevIns,
593	pRange->pfnInCallback,
594	pRange->pfnOutCallback,
595	pRange->pvUser,
596	pRange->pszDesc);
597	return 0;
598	}
599
600
601	/**
602	* Display all registered I/O port ranges.
603	*
604	* @param pVM The cross context VM structure.
605	* @param pHlp The info helpers.
606	* @param pszArgs Arguments, ignored.
607	*/
608	DECLCALLBACK(void) iomR3IoPortInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
609	{
610	/* No locking needed here as registerations are only happening during VMSTATE_CREATING. */
611	pHlp->pfnPrintf(pHlp,
612	"I/O port registrations: %u (%u allocated)\n"
613	" ## Ctx Ports Mapping PCI Description\n",
614	pVM->iom.s.cIoPortRegs, pVM->iom.s.cIoPortAlloc);
615	PIOMIOPORTENTRYR3 paRegs = pVM->iom.s.paIoPortRegs;
616	for (uint32_t i = 0; i < pVM->iom.s.cIoPortRegs; i++)
617	{
618	const char * const pszRing = paRegs[i].fRing0 ? paRegs[i].fRawMode ? "+0+C" : "+0 "
619	: paRegs[i].fRawMode ? "+C " : " ";
620	if (paRegs[i].fMapped && paRegs[i].pPciDev)
621	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
622	paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1,
623	paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
624	else if (paRegs[i].fMapped && !paRegs[i].pPciDev)
625	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x %04x-%04x %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
626	paRegs[i].uPort, paRegs[i].uPort + paRegs[i].cPorts - 1, paRegs[i].pszDesc);
627	else if (paRegs[i].pPciDev)
628	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cPorts,
629	paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
630	else
631	pHlp->pfnPrintf(pHlp, "%3u R3%s %04x unmapped %s\n",
632	paRegs[i].idxSelf, pszRing, paRegs[i].cPorts, paRegs[i].pszDesc);
633	}
634
635	/* Legacy registration: */
636	NOREF(pszArgs);
637	pHlp->pfnPrintf(pHlp,
638	"I/O Port R3 ranges (pVM=%p)\n"
639	"Range %.s %.s %.s %.s Description\n",
640	pVM,
641	sizeof(RTHCPTR) * 2, "pDevIns ",
642	sizeof(RTHCPTR) * 2, "In ",
643	sizeof(RTHCPTR) * 2, "Out ",
644	sizeof(RTHCPTR) * 2, "pvUser ");
645	IOM_LOCK_SHARED(pVM);
646	RTAvlroIOPortDoWithAll(&pVM->iom.s.pTreesR3->IOPortTreeR3, true, iomR3IOPortInfoOneR3, (void *)pHlp);
647	IOM_UNLOCK_SHARED(pVM);
648
649	pHlp->pfnPrintf(pHlp,
650	"I/O Port R0 ranges (pVM=%p)\n"
651	"Range %.s %.s %.s %.s Description\n",
652	pVM,
653	sizeof(RTHCPTR) * 2, "pDevIns ",
654	sizeof(RTHCPTR) * 2, "In ",
655	sizeof(RTHCPTR) * 2, "Out ",
656	sizeof(RTHCPTR) * 2, "pvUser ");
657	IOM_LOCK_SHARED(pVM);
658	RTAvlroIOPortDoWithAll(&pVM->iom.s.pTreesR3->IOPortTreeR0, true, iomR3IOPortInfoOneR3, (void *)pHlp);
659	IOM_UNLOCK_SHARED(pVM);
660	}
661

Note: See TracBrowser for help on using the repository browser.

source: vbox/trunk/src/VBox/VMM/VMMR3/IOMR3IoPort.cpp@ 81613

Download in other formats: