IOMR3Mmio.cpp@ 81388

Last change on this file since 81388 was 81383, checked in by vboxsync, 5 years ago
IOM: Split up the logging into two more groups, one for I/O ports and one for MMIO. bugref:9218
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1	/* $Id: IOMR3Mmio.cpp 81383 2019-10-19 23:58:44Z vboxsync $ */
2	/** @file
3	* IOM - Input / Output Monitor, MMIO related APIs.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_IOM_MMIO
23	#include <VBox/vmm/iom.h>
24	#include <VBox/sup.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/stam.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include "IOMInternal.h"
31	#include <VBox/vmm/vm.h>
32
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38
39	#include "IOMInline.h"
40
41
42	#ifdef VBOX_WITH_STATISTICS
43
44	/**
45	* Register statistics for a MMIO entry.
46	*/
47	void iomR3MmioRegStats(PVM pVM, PIOMMMIOENTRYR3 pRegEntry)
48	{
49	PIOMMMIOSTATSENTRY pStats = &pVM->iom.s.paMmioStats[pRegEntry->idxStats];
50
51	/* Format the prefix: */
52	char szName[80];
53	size_t cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/NewMmio/%RGp-%RGp",
54	pRegEntry->GCPhysMapping, pRegEntry->GCPhysMapping + pRegEntry->cbRegion - 1);
55
56	/* Mangle the description if this isn't the first device instance: */
57	const char *pszDesc = pRegEntry->pszDesc;
58	char *pszFreeDesc = NULL;
59	if (pRegEntry->pDevIns && pRegEntry->pDevIns->iInstance > 0 && pszDesc)
60	pszDesc = pszFreeDesc = RTStrAPrintf2("%u / %s", pRegEntry->pDevIns->iInstance, pszDesc);
61
62	/* Register statistics: */
63	int rc = STAMR3Register(pVM, &pRegEntry->idxSelf, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_NONE, pszDesc); AssertRC(rc);
64	RTStrFree(pszFreeDesc);
65
66	# define SET_NM_SUFFIX(a_sz) memcpy(&szName[cchPrefix], a_sz, sizeof(a_sz))
67	SET_NM_SUFFIX("/Read-Complicated");
68	rc = STAMR3Register(pVM, &pStats->ComplicatedReads, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
69	SET_NM_SUFFIX("/Read-FFor00");
70	rc = STAMR3Register(pVM, &pStats->FFor00Reads, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
71	SET_NM_SUFFIX("/Read-R3");
72	rc = STAMR3Register(pVM, &pStats->ProfReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
73	SET_NM_SUFFIX("/Read-RZ");
74	rc = STAMR3Register(pVM, &pStats->ProfReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
75	SET_NM_SUFFIX("/Read-RZtoR3");
76	rc = STAMR3Register(pVM, &pStats->ReadRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
77	SET_NM_SUFFIX("/Read-Total");
78	rc = STAMR3Register(pVM, &pStats->Reads, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
79
80	SET_NM_SUFFIX("/Write-Complicated");
81	rc = STAMR3Register(pVM, &pStats->ComplicatedWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
82	SET_NM_SUFFIX("/Write-R3");
83	rc = STAMR3Register(pVM, &pStats->ProfWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
84	SET_NM_SUFFIX("/Write-RZ");
85	rc = STAMR3Register(pVM, &pStats->ProfWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
86	SET_NM_SUFFIX("/Write-RZtoR3");
87	rc = STAMR3Register(pVM, &pStats->WriteRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
88	SET_NM_SUFFIX("/Write-RZtoR3-Commit");
89	rc = STAMR3Register(pVM, &pStats->CommitRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
90	SET_NM_SUFFIX("/Write-Total");
91	rc = STAMR3Register(pVM, &pStats->Writes, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
92	}
93
94
95	/**
96	* Deregister statistics for a MMIO entry.
97	*/
98	static void iomR3MmioDeregStats(PVM pVM, PIOMMMIOENTRYR3 pRegEntry, RTGCPHYS GCPhys)
99	{
100	char szPrefix[80];
101	RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/NewMmio/%RGp-%RGp", GCPhys, GCPhys + pRegEntry->cbRegion - 1);
102	STAMR3DeregisterByPrefix(pVM->pUVM, szPrefix);
103	}
104
105	#endif /* VBOX_WITH_STATISTICS */
106
107
108	/**
109	* Worker for PDMDEVHLPR3::pfnMmioCreateEx.
110	*/
111	VMMR3_INT_DECL(int) IOMR3MmioCreate(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS cbRegion, uint32_t fFlags, PPDMPCIDEV pPciDev,
112	uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
113	PFNIOMMMIONEWFILL pfnFill, void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
114	{
115	/*
116	* Validate input.
117	*/
118	AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
119	*phRegion = UINT32_MAX;
120	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
121	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
122
123	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
124
125	AssertMsgReturn(cbRegion > 0 && cbRegion <= MM_MMIO_64_MAX, ("cbRegion=%#RGp (max %#RGp)\n", cbRegion, MM_MMIO_64_MAX),
126	VERR_OUT_OF_RANGE);
127	AssertMsgReturn(!(cbRegion & PAGE_OFFSET_MASK), ("cbRegion=%#RGp\n", cbRegion), VERR_UNSUPPORTED_ALIGNMENT);
128
129	AssertMsgReturn( !(fFlags & ~IOMMMIO_FLAGS_VALID_MASK)
130	&& (fFlags & IOMMMIO_FLAGS_READ_MODE) <= IOMMMIO_FLAGS_READ_DWORD_QWORD
131	&& (fFlags & IOMMMIO_FLAGS_WRITE_MODE) <= IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
132	("%#x\n", fFlags),
133	VERR_INVALID_FLAGS);
134
135	AssertReturn(pfnWrite \|\| pfnRead, VERR_INVALID_PARAMETER);
136	AssertPtrNullReturn(pfnWrite, VERR_INVALID_POINTER);
137	AssertPtrNullReturn(pfnRead, VERR_INVALID_POINTER);
138	AssertPtrNullReturn(pfnFill, VERR_INVALID_POINTER);
139
140	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
141	AssertReturn(*pszDesc != '\0', VERR_INVALID_POINTER);
142	AssertReturn(strlen(pszDesc) < 128, VERR_INVALID_POINTER);
143
144	/*
145	* Ensure that we've got table space for it.
146	*/
147	#ifndef VBOX_WITH_STATISTICS
148	uint16_t const idxStats = UINT16_MAX;
149	#else
150	uint32_t const idxStats = pVM->iom.s.cMmioStats;
151	uint32_t const cNewMmioStats = idxStats + 1;
152	AssertReturn(cNewMmioStats <= _64K, VERR_IOM_TOO_MANY_MMIO_REGISTRATIONS);
153	if (cNewMmioStats > pVM->iom.s.cMmioStatsAllocation)
154	{
155	int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_MMIO_STATS, cNewMmioStats, NULL);
156	AssertLogRelRCReturn(rc, rc);
157	AssertReturn(idxStats == pVM->iom.s.cMmioStats, VERR_IOM_MMIO_IPE_1);
158	AssertReturn(cNewMmioStats <= pVM->iom.s.cMmioStatsAllocation, VERR_IOM_MMIO_IPE_2);
159	}
160	#endif
161
162	uint32_t idx = pVM->iom.s.cMmioRegs;
163	if (idx >= pVM->iom.s.cMmioAlloc)
164	{
165	int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_MMIO_REGS, pVM->iom.s.cMmioAlloc + 1, NULL);
166	AssertLogRelRCReturn(rc, rc);
167	AssertReturn(idx == pVM->iom.s.cMmioRegs, VERR_IOM_MMIO_IPE_1);
168	AssertReturn(idx < pVM->iom.s.cMmioAlloc, VERR_IOM_MMIO_IPE_2);
169	}
170
171	/*
172	* Enter it.
173	*/
174	pVM->iom.s.paMmioRegs[idx].cbRegion = cbRegion;
175	pVM->iom.s.paMmioRegs[idx].GCPhysMapping = NIL_RTGCPHYS;
176	pVM->iom.s.paMmioRegs[idx].pvUser = pvUser;
177	pVM->iom.s.paMmioRegs[idx].pDevIns = pDevIns;
178	pVM->iom.s.paMmioRegs[idx].pfnWriteCallback = pfnWrite;
179	pVM->iom.s.paMmioRegs[idx].pfnReadCallback = pfnRead;
180	pVM->iom.s.paMmioRegs[idx].pfnFillCallback = pfnFill;
181	pVM->iom.s.paMmioRegs[idx].pszDesc = pszDesc;
182	pVM->iom.s.paMmioRegs[idx].pPciDev = pPciDev;
183	pVM->iom.s.paMmioRegs[idx].iPciRegion = iPciRegion;
184	pVM->iom.s.paMmioRegs[idx].idxStats = (uint16_t)idxStats;
185	pVM->iom.s.paMmioRegs[idx].fMapped = false;
186	pVM->iom.s.paMmioRegs[idx].fFlags = fFlags;
187	pVM->iom.s.paMmioRegs[idx].idxSelf = idx;
188
189	pVM->iom.s.cMmioRegs = idx + 1;
190	*phRegion = idx;
191	return VINF_SUCCESS;
192	}
193
194
195	/**
196	* Worker for PDMDEVHLPR3::pfnMmioMap.
197	*/
198	VMMR3_INT_DECL(int) IOMR3MmioMap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
199	{
200	/*
201	* Validate input and state.
202	*/
203	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
204	AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE);
205	PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
206	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_MMIO_HANDLE);
207
208	RTGCPHYS const cbRegion = pRegEntry->cbRegion;
209	AssertMsgReturn(cbRegion > 0 && cbRegion <= MM_MMIO_64_MAX, ("cbRegion=%RGp\n", cbRegion), VERR_IOM_MMIO_IPE_1);
210	RTGCPHYS const GCPhysLast = GCPhys + cbRegion - 1;
211
212	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK),
213	("Misaligned! GCPhys=%RGp LB %RGp %s (%s[#%u])\n",
214	GCPhys, cbRegion, pRegEntry->pszDesc, pDevIns->pReg->szName, pDevIns->iInstance),
215	VERR_IOM_INVALID_MMIO_RANGE);
216	AssertLogRelMsgReturn(GCPhysLast > GCPhys,
217	("Wrapped! GCPhys=%RGp LB %RGp %s (%s[#%u])\n",
218	GCPhys, cbRegion, pRegEntry->pszDesc, pDevIns->pReg->szName, pDevIns->iInstance),
219	VERR_IOM_INVALID_MMIO_RANGE);
220
221	/*
222	* Do the mapping.
223	*/
224	int rc = VINF_SUCCESS;
225	IOM_LOCK_EXCL(pVM);
226
227	if (!pRegEntry->fMapped)
228	{
229	uint32_t const cEntries = RT_MIN(pVM->iom.s.cMmioLookupEntries, pVM->iom.s.cMmioRegs);
230	Assert(pVM->iom.s.cMmioLookupEntries == cEntries);
231
232	PIOMMMIOLOOKUPENTRY paEntries = pVM->iom.s.paMmioLookup;
233	PIOMMMIOLOOKUPENTRY pEntry;
234	if (cEntries > 0)
235	{
236	uint32_t iFirst = 0;
237	uint32_t iEnd = cEntries;
238	uint32_t i = cEntries / 2;
239	for (;;)
240	{
241	pEntry = &paEntries[i];
242	if (pEntry->GCPhysLast < GCPhys)
243	{
244	i += 1;
245	if (i < iEnd)
246	iFirst = i;
247	else
248	{
249	/* Register with PGM before we shuffle the array: */
250	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
251	rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
252	(void *)(uintptr_t)hRegion, hRegion, hRegion, pRegEntry->pszDesc);
253	AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
254
255	/* Insert after the entry we just considered: */
256	pEntry += 1;
257	if (i < cEntries)
258	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
259	break;
260	}
261	}
262	else if (pEntry->GCPhysFirst > GCPhysLast)
263	{
264	if (i > iFirst)
265	iEnd = i;
266	else
267	{
268	/* Register with PGM before we shuffle the array: */
269	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
270	rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
271	(void *)(uintptr_t)hRegion, hRegion, hRegion, pRegEntry->pszDesc);
272	AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
273
274	/* Insert at the entry we just considered: */
275	if (i < cEntries)
276	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
277	break;
278	}
279	}
280	else
281	{
282	/* Oops! We've got a conflict. */
283	AssertLogRelMsgFailed(("%RGp..%RGp (%s) conflicts with existing mapping %RGp..%RGp (%s)\n",
284	GCPhys, GCPhysLast, pRegEntry->pszDesc,
285	pEntry->GCPhysFirst, pEntry->GCPhysLast, pVM->iom.s.paMmioRegs[pEntry->idx].pszDesc));
286	IOM_UNLOCK_EXCL(pVM);
287	return VERR_IOM_MMIO_RANGE_CONFLICT;
288	}
289
290	i = iFirst + (iEnd - iFirst) / 2;
291	}
292	}
293	else
294	{
295	/* First entry in the lookup table: */
296	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
297	rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
298	(void *)(uintptr_t)hRegion, hRegion, hRegion, pRegEntry->pszDesc);
299	AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
300
301	pEntry = paEntries;
302	}
303
304	/*
305	* Fill in the entry and bump the table size.
306	*/
307	pRegEntry->fMapped = true;
308	pEntry->idx = hRegion;
309	pEntry->GCPhysFirst = GCPhys;
310	pEntry->GCPhysLast = GCPhysLast;
311	pVM->iom.s.cMmioLookupEntries = cEntries + 1;
312
313	#ifdef VBOX_WITH_STATISTICS
314	/* Don't register stats here when we're creating the VM as the
315	statistics table may still be reallocated. */
316	if (pVM->enmVMState >= VMSTATE_CREATED)
317	iomR3MmioRegStats(pVM, pRegEntry);
318	#endif
319
320	#ifdef VBOX_STRICT
321	/*
322	* Assert table sanity.
323	*/
324	AssertMsg(paEntries[0].GCPhysLast >= paEntries[0].GCPhysFirst, ("%RGp %RGp\n", paEntries[0].GCPhysLast, paEntries[0].GCPhysFirst));
325	AssertMsg(paEntries[0].idx < pVM->iom.s.cMmioRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cMmioRegs));
326
327	RTGCPHYS GCPhysPrev = paEntries[0].GCPhysLast;
328	for (size_t i = 1; i <= cEntries; i++)
329	{
330	AssertMsg(paEntries[i].GCPhysLast >= paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, paEntries[i].GCPhysLast, paEntries[i].GCPhysFirst));
331	AssertMsg(paEntries[i].idx < pVM->iom.s.cMmioRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cMmioRegs));
332	AssertMsg(GCPhysPrev < paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, GCPhysPrev, paEntries[i].GCPhysFirst));
333	GCPhysPrev = paEntries[i].GCPhysLast;
334	}
335	#endif
336	}
337	else
338	{
339	AssertFailed();
340	rc = VERR_IOM_MMIO_REGION_ALREADY_MAPPED;
341	}
342
343	IOM_UNLOCK_EXCL(pVM);
344	return rc;
345	}
346
347
348	/**
349	* Worker for PDMDEVHLPR3::pfnMmioUnmap.
350	*/
351	VMMR3_INT_DECL(int) IOMR3MmioUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
352	{
353	/*
354	* Validate input and state.
355	*/
356	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
357	AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE);
358	PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
359	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_MMIO_HANDLE);
360
361	/*
362	* Do the mapping.
363	*/
364	int rc;
365	IOM_LOCK_EXCL(pVM);
366
367	if (pRegEntry->fMapped)
368	{
369	RTGCPHYS const GCPhys = pRegEntry->GCPhysMapping;
370	RTGCPHYS const GCPhysLast = GCPhys + pRegEntry->cbRegion - 1;
371	uint32_t const cEntries = RT_MIN(pVM->iom.s.cMmioLookupEntries, pVM->iom.s.cMmioRegs);
372	Assert(pVM->iom.s.cMmioLookupEntries == cEntries);
373	Assert(cEntries > 0);
374
375	PIOMMMIOLOOKUPENTRY paEntries = pVM->iom.s.paMmioLookup;
376	uint32_t iFirst = 0;
377	uint32_t iEnd = cEntries;
378	uint32_t i = cEntries / 2;
379	for (;;)
380	{
381	PIOMMMIOLOOKUPENTRY pEntry = &paEntries[i];
382	if (pEntry->GCPhysLast < GCPhys)
383	{
384	i += 1;
385	if (i < iEnd)
386	iFirst = i;
387	else
388	{
389	rc = VERR_IOM_MMIO_IPE_1;
390	AssertLogRelMsgFailedBreak(("%RGp..%RGp (%s) not found!\n", GCPhys, GCPhysLast, pRegEntry->pszDesc));
391	}
392	}
393	else if (pEntry->GCPhysFirst > GCPhysLast)
394	{
395	if (i > iFirst)
396	iEnd = i;
397	else
398	{
399	rc = VERR_IOM_MMIO_IPE_1;
400	AssertLogRelMsgFailedBreak(("%RGp..%RGp (%s) not found!\n", GCPhys, GCPhysLast, pRegEntry->pszDesc));
401	}
402	}
403	else if (pEntry->idx == hRegion)
404	{
405	Assert(pEntry->GCPhysFirst == GCPhys);
406	Assert(pEntry->GCPhysLast == GCPhysLast);
407	#ifdef VBOX_WITH_STATISTICS
408	iomR3MmioDeregStats(pVM, pRegEntry, GCPhys);
409	#endif
410	if (i + 1 < cEntries)
411	memmove(pEntry, pEntry + 1, sizeof(pEntry) (cEntries - i - 1));
412	pVM->iom.s.cMmioLookupEntries = cEntries - 1;
413
414	rc = PGMR3PhysMMIODeregister(pVM, GCPhys, pRegEntry->cbRegion);
415	AssertRC(rc);
416
417	pRegEntry->fMapped = false;
418	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS);
419	break;
420	}
421	else
422	{
423	AssertLogRelMsgFailed(("Lookig for %RGp..%RGp (%s), found %RGp..%RGp (%s) instead!\n",
424	GCPhys, GCPhysLast, pRegEntry->pszDesc,
425	pEntry->GCPhysFirst, pEntry->GCPhysLast, pVM->iom.s.paMmioRegs[pEntry->idx].pszDesc));
426	rc = VERR_IOM_MMIO_IPE_1;
427	break;
428	}
429
430	i = iFirst + (iEnd - iFirst) / 2;
431	}
432
433	#ifdef VBOX_STRICT
434	/*
435	* Assert table sanity.
436	*/
437	AssertMsg(paEntries[0].GCPhysLast >= paEntries[0].GCPhysFirst, ("%RGp %RGp\n", paEntries[0].GCPhysLast, paEntries[0].GCPhysFirst));
438	AssertMsg(paEntries[0].idx < pVM->iom.s.cMmioRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cMmioRegs));
439
440	RTGCPHYS GCPhysPrev = paEntries[0].GCPhysLast;
441	for (i = 1; i < cEntries - 1; i++)
442	{
443	AssertMsg(paEntries[i].GCPhysLast >= paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, paEntries[i].GCPhysLast, paEntries[i].GCPhysFirst));
444	AssertMsg(paEntries[i].idx < pVM->iom.s.cMmioRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cMmioRegs));
445	AssertMsg(GCPhysPrev < paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, GCPhysPrev, paEntries[i].GCPhysFirst));
446	GCPhysPrev = paEntries[i].GCPhysLast;
447	}
448	#endif
449	}
450	else
451	{
452	AssertFailed();
453	rc = VERR_IOM_MMIO_REGION_NOT_MAPPED;
454	}
455
456	IOM_UNLOCK_EXCL(pVM);
457	return rc;
458	}
459
460
461	VMMR3_INT_DECL(int) IOMR3MmioReduce(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
462	{
463	RT_NOREF(pVM, pDevIns, hRegion, cbRegion);
464	return VERR_NOT_IMPLEMENTED;
465	}
466
467
468	/**
469	* Validates @a hRegion, making sure it belongs to @a pDevIns.
470	*
471	* @returns VBox status code.
472	* @param pVM The cross context VM structure.
473	* @param pDevIns The device which allegedly owns @a hRegion.
474	* @param hRegion The handle to validate.
475	*/
476	VMMR3_INT_DECL(int) IOMR3MmioValidateHandle(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
477	{
478	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
479	AssertReturn(hRegion < RT_MIN(pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc), VERR_IOM_INVALID_MMIO_HANDLE);
480	PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
481	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_MMIO_HANDLE);
482	return VINF_SUCCESS;
483	}
484
485
486	/**
487	* Display a single MMIO range.
488	*
489	* @returns 0
490	* @param pNode Pointer to MMIO R3 range.
491	* @param pvUser Pointer to info output callback structure.
492	*/
493	static DECLCALLBACK(int) iomR3MmioInfoOne(PAVLROGCPHYSNODECORE pNode, void *pvUser)
494	{
495	PIOMMMIORANGE pRange = (PIOMMMIORANGE)pNode;
496	PCDBGFINFOHLP pHlp = (PCDBGFINFOHLP)pvUser;
497	pHlp->pfnPrintf(pHlp,
498	"%RGp-%RGp %RHv %RHv %RHv %RHv %RHv %s\n",
499	pRange->Core.Key,
500	pRange->Core.KeyLast,
501	pRange->pDevInsR3,
502	pRange->pfnReadCallbackR3,
503	pRange->pfnWriteCallbackR3,
504	pRange->pfnFillCallbackR3,
505	pRange->pvUserR3,
506	pRange->pszDesc);
507	pHlp->pfnPrintf(pHlp,
508	"%*s %RHv %RHv %RHv %RHv %RHv\n",
509	sizeof(RTGCPHYS) * 2 * 2 + 1, "R0",
510	pRange->pDevInsR0,
511	pRange->pfnReadCallbackR0,
512	pRange->pfnWriteCallbackR0,
513	pRange->pfnFillCallbackR0,
514	pRange->pvUserR0);
515	#if 0
516	pHlp->pfnPrintf(pHlp,
517	"%*s %RRv %RRv %RRv %RRv %RRv\n",
518	sizeof(RTGCPHYS) * 2 * 2 + 1, "RC",
519	pRange->pDevInsRC,
520	pRange->pfnReadCallbackRC,
521	pRange->pfnWriteCallbackRC,
522	pRange->pfnFillCallbackRC,
523	pRange->pvUserRC);
524	#endif
525	return 0;
526	}
527
528
529	/**
530	* Display all registered MMIO ranges.
531	*
532	* @param pVM The cross context VM structure.
533	* @param pHlp The info helpers.
534	* @param pszArgs Arguments, ignored.
535	*/
536	DECLCALLBACK(void) iomR3MmioInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
537	{
538	/* No locking needed here as registerations are only happening during VMSTATE_CREATING. */
539	pHlp->pfnPrintf(pHlp,
540	"MMIO registrations: %u (%u allocated)\n"
541	" ## Ctx %.s %.s PCI Description\n",
542	pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc,
543	sizeof(RTGCPHYS) * 2, "Size",
544	sizeof(RTGCPHYS) * 2 * 2 + 1, "Mapping");
545	PIOMMMIOENTRYR3 paRegs = pVM->iom.s.paMmioRegs;
546	for (uint32_t i = 0; i < pVM->iom.s.cMmioRegs; i++)
547	{
548	const char * const pszRing = paRegs[i].fRing0 ? paRegs[i].fRawMode ? "+0+C" : "+0 "
549	: paRegs[i].fRawMode ? "+C " : " ";
550	if (paRegs[i].fMapped && paRegs[i].pPciDev)
551	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %RGp-%RGp pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
552	paRegs[i].GCPhysMapping, paRegs[i].GCPhysMapping + paRegs[i].cbRegion - 1,
553	paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
554	else if (paRegs[i].fMapped && !paRegs[i].pPciDev)
555	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %RGp-%RGp %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
556	paRegs[i].GCPhysMapping, paRegs[i].GCPhysMapping + paRegs[i].cbRegion - 1, paRegs[i].pszDesc);
557	else if (paRegs[i].pPciDev)
558	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %.*s pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
559	sizeof(RTGCPHYS) * 2, "unmapped", paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
560	else
561	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %.*s %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
562	sizeof(RTGCPHYS) * 2, "unmapped", paRegs[i].pszDesc);
563	}
564
565	/* Legacy registration: */
566	NOREF(pszArgs);
567	pHlp->pfnPrintf(pHlp,
568	"MMIO ranges (pVM=%p)\n"
569	"%.s %.s %.s %.s %.s %.s %s\n",
570	pVM,
571	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
572	sizeof(RTHCPTR) * 2, "pDevIns ",
573	sizeof(RTHCPTR) * 2, "Read ",
574	sizeof(RTHCPTR) * 2, "Write ",
575	sizeof(RTHCPTR) * 2, "Fill ",
576	sizeof(RTHCPTR) * 2, "pvUser ",
577	"Description");
578	IOM_LOCK_SHARED(pVM);
579	RTAvlroGCPhysDoWithAll(&pVM->iom.s.pTreesR3->MMIOTree, true, iomR3MmioInfoOne, (void *)pHlp);
580	IOM_UNLOCK_SHARED(pVM);
581	}
582

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source: vbox/trunk/src/VBox/VMM/VMMR3/IOMR3Mmio.cpp@ 81388

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