IOMR3Mmio.cpp@ 81525

Last change on this file since 81525 was 81461, checked in by vboxsync, 5 years ago
IOM: Stat allocation fixes.
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File size: 24.7 KB

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1	/* $Id: IOMR3Mmio.cpp 81461 2019-10-22 21:09:55Z vboxsync $ */
2	/** @file
3	* IOM - Input / Output Monitor, MMIO related APIs.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_IOM_MMIO
23	#include <VBox/vmm/iom.h>
24	#include <VBox/sup.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/stam.h>
27	#include <VBox/vmm/dbgf.h>
28	#include <VBox/vmm/pdmapi.h>
29	#include <VBox/vmm/pdmdev.h>
30	#include "IOMInternal.h"
31	#include <VBox/vmm/vm.h>
32
33	#include <VBox/param.h>
34	#include <iprt/assert.h>
35	#include <iprt/string.h>
36	#include <VBox/log.h>
37	#include <VBox/err.h>
38
39	#include "IOMInline.h"
40
41
42	#ifdef VBOX_WITH_STATISTICS
43
44	/**
45	* Register statistics for a MMIO entry.
46	*/
47	void iomR3MmioRegStats(PVM pVM, PIOMMMIOENTRYR3 pRegEntry)
48	{
49	PIOMMMIOSTATSENTRY pStats = &pVM->iom.s.paMmioStats[pRegEntry->idxStats];
50
51	/* Format the prefix: */
52	char szName[80];
53	size_t cchPrefix = RTStrPrintf(szName, sizeof(szName), "/IOM/NewMmio/%RGp-%RGp",
54	pRegEntry->GCPhysMapping, pRegEntry->GCPhysMapping + pRegEntry->cbRegion - 1);
55
56	/* Mangle the description if this isn't the first device instance: */
57	const char *pszDesc = pRegEntry->pszDesc;
58	char *pszFreeDesc = NULL;
59	if (pRegEntry->pDevIns && pRegEntry->pDevIns->iInstance > 0 && pszDesc)
60	pszDesc = pszFreeDesc = RTStrAPrintf2("%u / %s", pRegEntry->pDevIns->iInstance, pszDesc);
61
62	/* Register statistics: */
63	int rc = STAMR3Register(pVM, &pRegEntry->idxSelf, STAMTYPE_U16, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_NONE, pszDesc); AssertRC(rc);
64	RTStrFree(pszFreeDesc);
65
66	# define SET_NM_SUFFIX(a_sz) memcpy(&szName[cchPrefix], a_sz, sizeof(a_sz))
67	SET_NM_SUFFIX("/Read-Complicated");
68	rc = STAMR3Register(pVM, &pStats->ComplicatedReads, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
69	SET_NM_SUFFIX("/Read-FFor00");
70	rc = STAMR3Register(pVM, &pStats->FFor00Reads, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
71	SET_NM_SUFFIX("/Read-R3");
72	rc = STAMR3Register(pVM, &pStats->ProfReadR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
73	SET_NM_SUFFIX("/Read-RZ");
74	rc = STAMR3Register(pVM, &pStats->ProfReadRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
75	SET_NM_SUFFIX("/Read-RZtoR3");
76	rc = STAMR3Register(pVM, &pStats->ReadRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
77	SET_NM_SUFFIX("/Read-Total");
78	rc = STAMR3Register(pVM, &pStats->Reads, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
79
80	SET_NM_SUFFIX("/Write-Complicated");
81	rc = STAMR3Register(pVM, &pStats->ComplicatedWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
82	SET_NM_SUFFIX("/Write-R3");
83	rc = STAMR3Register(pVM, &pStats->ProfWriteR3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
84	SET_NM_SUFFIX("/Write-RZ");
85	rc = STAMR3Register(pVM, &pStats->ProfWriteRZ, STAMTYPE_PROFILE, STAMVISIBILITY_USED, szName, STAMUNIT_TICKS_PER_CALL, NULL); AssertRC(rc);
86	SET_NM_SUFFIX("/Write-RZtoR3");
87	rc = STAMR3Register(pVM, &pStats->WriteRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
88	SET_NM_SUFFIX("/Write-RZtoR3-Commit");
89	rc = STAMR3Register(pVM, &pStats->CommitRZToR3, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
90	SET_NM_SUFFIX("/Write-Total");
91	rc = STAMR3Register(pVM, &pStats->Writes, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, NULL); AssertRC(rc);
92	}
93
94
95	/**
96	* Deregister statistics for a MMIO entry.
97	*/
98	static void iomR3MmioDeregStats(PVM pVM, PIOMMMIOENTRYR3 pRegEntry, RTGCPHYS GCPhys)
99	{
100	char szPrefix[80];
101	RTStrPrintf(szPrefix, sizeof(szPrefix), "/IOM/NewMmio/%RGp-%RGp", GCPhys, GCPhys + pRegEntry->cbRegion - 1);
102	STAMR3DeregisterByPrefix(pVM->pUVM, szPrefix);
103	}
104
105	#endif /* VBOX_WITH_STATISTICS */
106
107
108	/**
109	* Worker for PDMDEVHLPR3::pfnMmioCreateEx.
110	*/
111	VMMR3_INT_DECL(int) IOMR3MmioCreate(PVM pVM, PPDMDEVINS pDevIns, RTGCPHYS cbRegion, uint32_t fFlags, PPDMPCIDEV pPciDev,
112	uint32_t iPciRegion, PFNIOMMMIONEWWRITE pfnWrite, PFNIOMMMIONEWREAD pfnRead,
113	PFNIOMMMIONEWFILL pfnFill, void pvUser, const char pszDesc, PIOMMMIOHANDLE phRegion)
114	{
115	/*
116	* Validate input.
117	*/
118	AssertPtrReturn(phRegion, VERR_INVALID_POINTER);
119	*phRegion = UINT32_MAX;
120	VM_ASSERT_EMT0_RETURN(pVM, VERR_VM_THREAD_NOT_EMT);
121	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_VM_INVALID_VM_STATE);
122
123	AssertPtrReturn(pDevIns, VERR_INVALID_POINTER);
124
125	AssertMsgReturn(cbRegion > 0 && cbRegion <= MM_MMIO_64_MAX, ("cbRegion=%#RGp (max %#RGp)\n", cbRegion, MM_MMIO_64_MAX),
126	VERR_OUT_OF_RANGE);
127	AssertMsgReturn(!(cbRegion & PAGE_OFFSET_MASK), ("cbRegion=%#RGp\n", cbRegion), VERR_UNSUPPORTED_ALIGNMENT);
128
129	AssertMsgReturn( !(fFlags & ~IOMMMIO_FLAGS_VALID_MASK)
130	&& (fFlags & IOMMMIO_FLAGS_READ_MODE) <= IOMMMIO_FLAGS_READ_DWORD_QWORD
131	&& (fFlags & IOMMMIO_FLAGS_WRITE_MODE) <= IOMMMIO_FLAGS_WRITE_ONLY_DWORD_QWORD,
132	("%#x\n", fFlags),
133	VERR_INVALID_FLAGS);
134
135	AssertReturn(pfnWrite \|\| pfnRead, VERR_INVALID_PARAMETER);
136	AssertPtrNullReturn(pfnWrite, VERR_INVALID_POINTER);
137	AssertPtrNullReturn(pfnRead, VERR_INVALID_POINTER);
138	AssertPtrNullReturn(pfnFill, VERR_INVALID_POINTER);
139
140	AssertPtrReturn(pszDesc, VERR_INVALID_POINTER);
141	AssertReturn(*pszDesc != '\0', VERR_INVALID_POINTER);
142	AssertReturn(strlen(pszDesc) < 128, VERR_INVALID_POINTER);
143
144	/*
145	* Ensure that we've got table space for it.
146	*/
147	#ifndef VBOX_WITH_STATISTICS
148	uint16_t const idxStats = UINT16_MAX;
149	#else
150	uint32_t const idxStats = pVM->iom.s.cMmioStats;
151	uint32_t const cNewMmioStats = idxStats + 1;
152	AssertReturn(cNewMmioStats <= _64K, VERR_IOM_TOO_MANY_MMIO_REGISTRATIONS);
153	if (cNewMmioStats > pVM->iom.s.cMmioStatsAllocation)
154	{
155	int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_MMIO_STATS, cNewMmioStats, NULL);
156	AssertLogRelRCReturn(rc, rc);
157	AssertReturn(idxStats == pVM->iom.s.cMmioStats, VERR_IOM_MMIO_IPE_1);
158	AssertReturn(cNewMmioStats <= pVM->iom.s.cMmioStatsAllocation, VERR_IOM_MMIO_IPE_2);
159	}
160	#endif
161
162	uint32_t idx = pVM->iom.s.cMmioRegs;
163	if (idx >= pVM->iom.s.cMmioAlloc)
164	{
165	int rc = VMMR3CallR0Emt(pVM, pVM->apCpusR3[0], VMMR0_DO_IOM_GROW_MMIO_REGS, pVM->iom.s.cMmioAlloc + 1, NULL);
166	AssertLogRelRCReturn(rc, rc);
167	AssertReturn(idx == pVM->iom.s.cMmioRegs, VERR_IOM_MMIO_IPE_1);
168	AssertReturn(idx < pVM->iom.s.cMmioAlloc, VERR_IOM_MMIO_IPE_2);
169	}
170
171	/*
172	* Enter it.
173	*/
174	pVM->iom.s.paMmioRegs[idx].cbRegion = cbRegion;
175	pVM->iom.s.paMmioRegs[idx].GCPhysMapping = NIL_RTGCPHYS;
176	pVM->iom.s.paMmioRegs[idx].pvUser = pvUser;
177	pVM->iom.s.paMmioRegs[idx].pDevIns = pDevIns;
178	pVM->iom.s.paMmioRegs[idx].pfnWriteCallback = pfnWrite;
179	pVM->iom.s.paMmioRegs[idx].pfnReadCallback = pfnRead;
180	pVM->iom.s.paMmioRegs[idx].pfnFillCallback = pfnFill;
181	pVM->iom.s.paMmioRegs[idx].pszDesc = pszDesc;
182	pVM->iom.s.paMmioRegs[idx].pPciDev = pPciDev;
183	pVM->iom.s.paMmioRegs[idx].iPciRegion = iPciRegion;
184	pVM->iom.s.paMmioRegs[idx].idxStats = (uint16_t)idxStats;
185	pVM->iom.s.paMmioRegs[idx].fMapped = false;
186	pVM->iom.s.paMmioRegs[idx].fFlags = fFlags;
187	pVM->iom.s.paMmioRegs[idx].idxSelf = idx;
188
189	pVM->iom.s.cMmioRegs = idx + 1;
190	#ifdef VBOX_WITH_STATISTICS
191	pVM->iom.s.cMmioStats = cNewMmioStats;
192	#endif
193	*phRegion = idx;
194	return VINF_SUCCESS;
195	}
196
197
198	/**
199	* Worker for PDMDEVHLPR3::pfnMmioMap.
200	*/
201	VMMR3_INT_DECL(int) IOMR3MmioMap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS GCPhys)
202	{
203	/*
204	* Validate input and state.
205	*/
206	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
207	AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE);
208	PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
209	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_MMIO_HANDLE);
210
211	RTGCPHYS const cbRegion = pRegEntry->cbRegion;
212	AssertMsgReturn(cbRegion > 0 && cbRegion <= MM_MMIO_64_MAX, ("cbRegion=%RGp\n", cbRegion), VERR_IOM_MMIO_IPE_1);
213	RTGCPHYS const GCPhysLast = GCPhys + cbRegion - 1;
214
215	AssertLogRelMsgReturn(!(GCPhys & PAGE_OFFSET_MASK),
216	("Misaligned! GCPhys=%RGp LB %RGp %s (%s[#%u])\n",
217	GCPhys, cbRegion, pRegEntry->pszDesc, pDevIns->pReg->szName, pDevIns->iInstance),
218	VERR_IOM_INVALID_MMIO_RANGE);
219	AssertLogRelMsgReturn(GCPhysLast > GCPhys,
220	("Wrapped! GCPhys=%RGp LB %RGp %s (%s[#%u])\n",
221	GCPhys, cbRegion, pRegEntry->pszDesc, pDevIns->pReg->szName, pDevIns->iInstance),
222	VERR_IOM_INVALID_MMIO_RANGE);
223
224	/*
225	* Do the mapping.
226	*/
227	int rc = VINF_SUCCESS;
228	IOM_LOCK_EXCL(pVM);
229
230	if (!pRegEntry->fMapped)
231	{
232	uint32_t const cEntries = RT_MIN(pVM->iom.s.cMmioLookupEntries, pVM->iom.s.cMmioRegs);
233	Assert(pVM->iom.s.cMmioLookupEntries == cEntries);
234
235	PIOMMMIOLOOKUPENTRY paEntries = pVM->iom.s.paMmioLookup;
236	PIOMMMIOLOOKUPENTRY pEntry;
237	if (cEntries > 0)
238	{
239	uint32_t iFirst = 0;
240	uint32_t iEnd = cEntries;
241	uint32_t i = cEntries / 2;
242	for (;;)
243	{
244	pEntry = &paEntries[i];
245	if (pEntry->GCPhysLast < GCPhys)
246	{
247	i += 1;
248	if (i < iEnd)
249	iFirst = i;
250	else
251	{
252	/* Register with PGM before we shuffle the array: */
253	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
254	rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
255	(void *)(uintptr_t)hRegion, hRegion, hRegion, pRegEntry->pszDesc);
256	AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
257
258	/* Insert after the entry we just considered: */
259	pEntry += 1;
260	if (i < cEntries)
261	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
262	break;
263	}
264	}
265	else if (pEntry->GCPhysFirst > GCPhysLast)
266	{
267	if (i > iFirst)
268	iEnd = i;
269	else
270	{
271	/* Register with PGM before we shuffle the array: */
272	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
273	rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
274	(void *)(uintptr_t)hRegion, hRegion, hRegion, pRegEntry->pszDesc);
275	AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
276
277	/* Insert at the entry we just considered: */
278	if (i < cEntries)
279	memmove(pEntry + 1, pEntry, sizeof(pEntry) (cEntries - i));
280	break;
281	}
282	}
283	else
284	{
285	/* Oops! We've got a conflict. */
286	AssertLogRelMsgFailed(("%RGp..%RGp (%s) conflicts with existing mapping %RGp..%RGp (%s)\n",
287	GCPhys, GCPhysLast, pRegEntry->pszDesc,
288	pEntry->GCPhysFirst, pEntry->GCPhysLast, pVM->iom.s.paMmioRegs[pEntry->idx].pszDesc));
289	IOM_UNLOCK_EXCL(pVM);
290	return VERR_IOM_MMIO_RANGE_CONFLICT;
291	}
292
293	i = iFirst + (iEnd - iFirst) / 2;
294	}
295	}
296	else
297	{
298	/* First entry in the lookup table: */
299	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, GCPhys);
300	rc = PGMR3PhysMMIORegister(pVM, GCPhys, cbRegion, pVM->iom.s.hNewMmioHandlerType,
301	(void *)(uintptr_t)hRegion, hRegion, hRegion, pRegEntry->pszDesc);
302	AssertRCReturnStmt(rc, ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS); IOM_UNLOCK_EXCL(pVM), rc);
303
304	pEntry = paEntries;
305	}
306
307	/*
308	* Fill in the entry and bump the table size.
309	*/
310	pRegEntry->fMapped = true;
311	pEntry->idx = hRegion;
312	pEntry->GCPhysFirst = GCPhys;
313	pEntry->GCPhysLast = GCPhysLast;
314	pVM->iom.s.cMmioLookupEntries = cEntries + 1;
315
316	#ifdef VBOX_WITH_STATISTICS
317	/* Don't register stats here when we're creating the VM as the
318	statistics table may still be reallocated. */
319	if (pVM->enmVMState >= VMSTATE_CREATED)
320	iomR3MmioRegStats(pVM, pRegEntry);
321	#endif
322
323	#ifdef VBOX_STRICT
324	/*
325	* Assert table sanity.
326	*/
327	AssertMsg(paEntries[0].GCPhysLast >= paEntries[0].GCPhysFirst, ("%RGp %RGp\n", paEntries[0].GCPhysLast, paEntries[0].GCPhysFirst));
328	AssertMsg(paEntries[0].idx < pVM->iom.s.cMmioRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cMmioRegs));
329
330	RTGCPHYS GCPhysPrev = paEntries[0].GCPhysLast;
331	for (size_t i = 1; i <= cEntries; i++)
332	{
333	AssertMsg(paEntries[i].GCPhysLast >= paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, paEntries[i].GCPhysLast, paEntries[i].GCPhysFirst));
334	AssertMsg(paEntries[i].idx < pVM->iom.s.cMmioRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cMmioRegs));
335	AssertMsg(GCPhysPrev < paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, GCPhysPrev, paEntries[i].GCPhysFirst));
336	GCPhysPrev = paEntries[i].GCPhysLast;
337	}
338	#endif
339	}
340	else
341	{
342	AssertFailed();
343	rc = VERR_IOM_MMIO_REGION_ALREADY_MAPPED;
344	}
345
346	IOM_UNLOCK_EXCL(pVM);
347	return rc;
348	}
349
350
351	/**
352	* Worker for PDMDEVHLPR3::pfnMmioUnmap.
353	*/
354	VMMR3_INT_DECL(int) IOMR3MmioUnmap(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
355	{
356	/*
357	* Validate input and state.
358	*/
359	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
360	AssertReturn(hRegion < pVM->iom.s.cMmioRegs, VERR_IOM_INVALID_MMIO_HANDLE);
361	PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
362	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_MMIO_HANDLE);
363
364	/*
365	* Do the mapping.
366	*/
367	int rc;
368	IOM_LOCK_EXCL(pVM);
369
370	if (pRegEntry->fMapped)
371	{
372	RTGCPHYS const GCPhys = pRegEntry->GCPhysMapping;
373	RTGCPHYS const GCPhysLast = GCPhys + pRegEntry->cbRegion - 1;
374	uint32_t const cEntries = RT_MIN(pVM->iom.s.cMmioLookupEntries, pVM->iom.s.cMmioRegs);
375	Assert(pVM->iom.s.cMmioLookupEntries == cEntries);
376	Assert(cEntries > 0);
377
378	PIOMMMIOLOOKUPENTRY paEntries = pVM->iom.s.paMmioLookup;
379	uint32_t iFirst = 0;
380	uint32_t iEnd = cEntries;
381	uint32_t i = cEntries / 2;
382	for (;;)
383	{
384	PIOMMMIOLOOKUPENTRY pEntry = &paEntries[i];
385	if (pEntry->GCPhysLast < GCPhys)
386	{
387	i += 1;
388	if (i < iEnd)
389	iFirst = i;
390	else
391	{
392	rc = VERR_IOM_MMIO_IPE_1;
393	AssertLogRelMsgFailedBreak(("%RGp..%RGp (%s) not found!\n", GCPhys, GCPhysLast, pRegEntry->pszDesc));
394	}
395	}
396	else if (pEntry->GCPhysFirst > GCPhysLast)
397	{
398	if (i > iFirst)
399	iEnd = i;
400	else
401	{
402	rc = VERR_IOM_MMIO_IPE_1;
403	AssertLogRelMsgFailedBreak(("%RGp..%RGp (%s) not found!\n", GCPhys, GCPhysLast, pRegEntry->pszDesc));
404	}
405	}
406	else if (pEntry->idx == hRegion)
407	{
408	Assert(pEntry->GCPhysFirst == GCPhys);
409	Assert(pEntry->GCPhysLast == GCPhysLast);
410	#ifdef VBOX_WITH_STATISTICS
411	iomR3MmioDeregStats(pVM, pRegEntry, GCPhys);
412	#endif
413	if (i + 1 < cEntries)
414	memmove(pEntry, pEntry + 1, sizeof(pEntry) (cEntries - i - 1));
415	pVM->iom.s.cMmioLookupEntries = cEntries - 1;
416
417	rc = PGMR3PhysMMIODeregister(pVM, GCPhys, pRegEntry->cbRegion);
418	AssertRC(rc);
419
420	pRegEntry->fMapped = false;
421	ASMAtomicWriteU64(&pRegEntry->GCPhysMapping, NIL_RTGCPHYS);
422	break;
423	}
424	else
425	{
426	AssertLogRelMsgFailed(("Lookig for %RGp..%RGp (%s), found %RGp..%RGp (%s) instead!\n",
427	GCPhys, GCPhysLast, pRegEntry->pszDesc,
428	pEntry->GCPhysFirst, pEntry->GCPhysLast, pVM->iom.s.paMmioRegs[pEntry->idx].pszDesc));
429	rc = VERR_IOM_MMIO_IPE_1;
430	break;
431	}
432
433	i = iFirst + (iEnd - iFirst) / 2;
434	}
435
436	#ifdef VBOX_STRICT
437	/*
438	* Assert table sanity.
439	*/
440	AssertMsg(paEntries[0].GCPhysLast >= paEntries[0].GCPhysFirst, ("%RGp %RGp\n", paEntries[0].GCPhysLast, paEntries[0].GCPhysFirst));
441	AssertMsg(paEntries[0].idx < pVM->iom.s.cMmioRegs, ("%#x %#x\n", paEntries[0].idx, pVM->iom.s.cMmioRegs));
442
443	RTGCPHYS GCPhysPrev = paEntries[0].GCPhysLast;
444	for (i = 1; i < cEntries - 1; i++)
445	{
446	AssertMsg(paEntries[i].GCPhysLast >= paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, paEntries[i].GCPhysLast, paEntries[i].GCPhysFirst));
447	AssertMsg(paEntries[i].idx < pVM->iom.s.cMmioRegs, ("%u: %#x %#x\n", i, paEntries[i].idx, pVM->iom.s.cMmioRegs));
448	AssertMsg(GCPhysPrev < paEntries[i].GCPhysFirst, ("%u: %RGp %RGp\n", i, GCPhysPrev, paEntries[i].GCPhysFirst));
449	GCPhysPrev = paEntries[i].GCPhysLast;
450	}
451	#endif
452	}
453	else
454	{
455	AssertFailed();
456	rc = VERR_IOM_MMIO_REGION_NOT_MAPPED;
457	}
458
459	IOM_UNLOCK_EXCL(pVM);
460	return rc;
461	}
462
463
464	VMMR3_INT_DECL(int) IOMR3MmioReduce(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion, RTGCPHYS cbRegion)
465	{
466	RT_NOREF(pVM, pDevIns, hRegion, cbRegion);
467	return VERR_NOT_IMPLEMENTED;
468	}
469
470
471	/**
472	* Validates @a hRegion, making sure it belongs to @a pDevIns.
473	*
474	* @returns VBox status code.
475	* @param pVM The cross context VM structure.
476	* @param pDevIns The device which allegedly owns @a hRegion.
477	* @param hRegion The handle to validate.
478	*/
479	VMMR3_INT_DECL(int) IOMR3MmioValidateHandle(PVM pVM, PPDMDEVINS pDevIns, IOMMMIOHANDLE hRegion)
480	{
481	AssertPtrReturn(pDevIns, VERR_INVALID_HANDLE);
482	AssertReturn(hRegion < RT_MIN(pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc), VERR_IOM_INVALID_MMIO_HANDLE);
483	PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
484	AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_IOM_INVALID_MMIO_HANDLE);
485	return VINF_SUCCESS;
486	}
487
488
489	/**
490	* Display a single MMIO range.
491	*
492	* @returns 0
493	* @param pNode Pointer to MMIO R3 range.
494	* @param pvUser Pointer to info output callback structure.
495	*/
496	static DECLCALLBACK(int) iomR3MmioInfoOne(PAVLROGCPHYSNODECORE pNode, void *pvUser)
497	{
498	PIOMMMIORANGE pRange = (PIOMMMIORANGE)pNode;
499	PCDBGFINFOHLP pHlp = (PCDBGFINFOHLP)pvUser;
500	pHlp->pfnPrintf(pHlp,
501	"%RGp-%RGp %RHv %RHv %RHv %RHv %RHv %s\n",
502	pRange->Core.Key,
503	pRange->Core.KeyLast,
504	pRange->pDevInsR3,
505	pRange->pfnReadCallbackR3,
506	pRange->pfnWriteCallbackR3,
507	pRange->pfnFillCallbackR3,
508	pRange->pvUserR3,
509	pRange->pszDesc);
510	pHlp->pfnPrintf(pHlp,
511	"%*s %RHv %RHv %RHv %RHv %RHv\n",
512	sizeof(RTGCPHYS) * 2 * 2 + 1, "R0",
513	pRange->pDevInsR0,
514	pRange->pfnReadCallbackR0,
515	pRange->pfnWriteCallbackR0,
516	pRange->pfnFillCallbackR0,
517	pRange->pvUserR0);
518	#if 0
519	pHlp->pfnPrintf(pHlp,
520	"%*s %RRv %RRv %RRv %RRv %RRv\n",
521	sizeof(RTGCPHYS) * 2 * 2 + 1, "RC",
522	pRange->pDevInsRC,
523	pRange->pfnReadCallbackRC,
524	pRange->pfnWriteCallbackRC,
525	pRange->pfnFillCallbackRC,
526	pRange->pvUserRC);
527	#endif
528	return 0;
529	}
530
531
532	/**
533	* Display all registered MMIO ranges.
534	*
535	* @param pVM The cross context VM structure.
536	* @param pHlp The info helpers.
537	* @param pszArgs Arguments, ignored.
538	*/
539	DECLCALLBACK(void) iomR3MmioInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
540	{
541	/* No locking needed here as registerations are only happening during VMSTATE_CREATING. */
542	pHlp->pfnPrintf(pHlp,
543	"MMIO registrations: %u (%u allocated)\n"
544	" ## Ctx %.s %.s PCI Description\n",
545	pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc,
546	sizeof(RTGCPHYS) * 2, "Size",
547	sizeof(RTGCPHYS) * 2 * 2 + 1, "Mapping");
548	PIOMMMIOENTRYR3 paRegs = pVM->iom.s.paMmioRegs;
549	for (uint32_t i = 0; i < pVM->iom.s.cMmioRegs; i++)
550	{
551	const char * const pszRing = paRegs[i].fRing0 ? paRegs[i].fRawMode ? "+0+C" : "+0 "
552	: paRegs[i].fRawMode ? "+C " : " ";
553	if (paRegs[i].fMapped && paRegs[i].pPciDev)
554	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %RGp-%RGp pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
555	paRegs[i].GCPhysMapping, paRegs[i].GCPhysMapping + paRegs[i].cbRegion - 1,
556	paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
557	else if (paRegs[i].fMapped && !paRegs[i].pPciDev)
558	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %RGp-%RGp %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
559	paRegs[i].GCPhysMapping, paRegs[i].GCPhysMapping + paRegs[i].cbRegion - 1, paRegs[i].pszDesc);
560	else if (paRegs[i].pPciDev)
561	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %.*s pci%u/%u %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
562	sizeof(RTGCPHYS) * 2, "unmapped", paRegs[i].pPciDev->idxSubDev, paRegs[i].iPciRegion, paRegs[i].pszDesc);
563	else
564	pHlp->pfnPrintf(pHlp, "%3u R3%s %RGp %.*s %s\n", paRegs[i].idxSelf, pszRing, paRegs[i].cbRegion,
565	sizeof(RTGCPHYS) * 2, "unmapped", paRegs[i].pszDesc);
566	}
567
568	/* Legacy registration: */
569	NOREF(pszArgs);
570	pHlp->pfnPrintf(pHlp,
571	"MMIO ranges (pVM=%p)\n"
572	"%.s %.s %.s %.s %.s %.s %s\n",
573	pVM,
574	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
575	sizeof(RTHCPTR) * 2, "pDevIns ",
576	sizeof(RTHCPTR) * 2, "Read ",
577	sizeof(RTHCPTR) * 2, "Write ",
578	sizeof(RTHCPTR) * 2, "Fill ",
579	sizeof(RTHCPTR) * 2, "pvUser ",
580	"Description");
581	IOM_LOCK_SHARED(pVM);
582	RTAvlroGCPhysDoWithAll(&pVM->iom.s.pTreesR3->MMIOTree, true, iomR3MmioInfoOne, (void *)pHlp);
583	IOM_UNLOCK_SHARED(pVM);
584	}
585

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source: vbox/trunk/src/VBox/VMM/VMMR3/IOMR3Mmio.cpp@ 81525

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