VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 72526

Last change on this file since 72526 was 72526, checked in by vboxsync, 7 years ago

NEM,TM: More TSC adjustments for NEM/win. bugref:9044
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1/* $Id: NEMR3.cpp 72526 2018-06-12 13:06:02Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager.
4 */
5
6/*
7 * Copyright (C) 2018 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_nem NEM - Native Execution Manager.
19 *
20 * This is an alternative execution manage to HM and raw-mode. On one host
21 * (Windows) we're forced to use this, on the others we just do it because we
22 * can. Since this is host specific in nature, information about an
23 * implementation is contained in the NEMR3Native-xxxx.cpp files.
24 *
25 * @ref pg_nem_win
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_NEM
33#include <VBox/vmm/nem.h>
34#include <VBox/vmm/gim.h>
35#include "NEMInternal.h"
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38
39#include <iprt/asm.h>
40
41
42
43/**
44 * Basic init and configuration reading.
45 *
46 * Always call NEMR3Term after calling this.
47 *
48 * @returns VBox status code.
49 * @param pVM The cross context VM structure.
50 */
51VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
52{
53 LogFlow(("NEMR3Init\n"));
54
55 /*
56 * Assert alignment and sizes.
57 */
58 AssertCompileMemberAlignment(VM, nem.s, 64);
59 AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
60
61 /*
62 * Initialize state info so NEMR3Term will always be happy.
63 * No returning prior to setting magics!
64 */
65 pVM->nem.s.u32Magic = NEM_MAGIC;
66 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
67 pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC;
68
69 /*
70 * Read configuration.
71 */
72 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
73
74 /*
75 * Validate the NEM settings.
76 */
77 int rc = CFGMR3ValidateConfig(pCfgNem,
78 "/NEM/",
79 "Enabled"
80 "|Allow64BitGuests",
81 "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
82 if (RT_FAILURE(rc))
83 return rc;
84
85 /** @cfgm{/NEM/NEMEnabled, bool, true}
86 * Whether NEM is enabled. */
87 rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
88 AssertLogRelRCReturn(rc, rc);
89
90
91#ifdef VBOX_WITH_64_BITS_GUESTS
92 /** @cfgm{/HM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
93 * Enables AMD64 CPU features.
94 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
95 * already have the support. */
96 rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
97 AssertLogRelRCReturn(rc, rc);
98#else
99 pVM->nem.s.fAllow64BitGuests = false;
100#endif
101
102
103 return VINF_SUCCESS;
104}
105
106
107/**
108 * This is called by HMR3Init() when HM cannot be used.
109 *
110 * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
111 * native hypervisor API to execute the VM.
112 *
113 * @returns VBox status code.
114 * @param pVM The cross context VM structure.
115 * @param fFallback Whether this is a fallback call. Cleared if the VM is
116 * configured to use NEM instead of HM.
117 * @param fForced Whether /HM/HMForced was set. If set and we fail to
118 * enable NEM, we'll return a failure status code.
119 * Otherwise we'll assume HMR3Init falls back on raw-mode.
120 */
121VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
122{
123 Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
124 int rc;
125 if (pVM->nem.s.fEnabled)
126 {
127#ifdef VBOX_WITH_NATIVE_NEM
128 rc = nemR3NativeInit(pVM, fFallback, fForced);
129 ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
130#else
131 RT_NOREF(fFallback);
132 rc = VINF_SUCCESS;
133#endif
134 if (RT_SUCCESS(rc))
135 {
136 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
137 LogRel(("NEM: NEMR3Init: Active.\n"));
138 else
139 {
140 LogRel(("NEM: NEMR3Init: Not available.\n"));
141 if (fForced)
142 rc = VERR_NEM_NOT_AVAILABLE;
143 }
144 }
145 else
146 LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
147 }
148 else
149 {
150 LogRel(("NEM: NEMR3Init: Disabled.\n"));
151 rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
152 }
153 return rc;
154}
155
156
157/**
158 * Perform initialization that depends on CPUM working.
159 *
160 * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
161 *
162 * @returns VBox status code.
163 * @param pVM The cross context VM structure.
164 */
165VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
166{
167 int rc = VINF_SUCCESS;
168 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
169 {
170 /*
171 * Enable CPU features making general ASSUMPTIONS (there are two similar
172 * blocks of code in HM.cpp), to avoid duplicating this code. The
173 * native backend can make check capabilities and adjust as needed.
174 */
175 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
176 if (CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD)
177 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
178 if (pVM->nem.s.fAllow64BitGuests)
179 {
180 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
181 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
182 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
183 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
184 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
185 }
186 /* Turn on NXE if PAE has been enabled. */
187 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
188 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
189
190 /*
191 * Do native after-CPUM init.
192 */
193#ifdef VBOX_WITH_NATIVE_NEM
194 rc = nemR3NativeInitAfterCPUM(pVM);
195#else
196 RT_NOREF(pVM);
197#endif
198 }
199 return rc;
200}
201
202
203/**
204 * Called when a init phase has completed.
205 *
206 * @returns VBox status code.
207 * @param pVM The cross context VM structure.
208 * @param enmWhat The phase that completed.
209 */
210VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
211{
212 /*
213 * Check if GIM needs #UD, since that applies to everyone.
214 */
215 if (enmWhat == VMINITCOMPLETED_RING3)
216 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
217 pVM->aCpus[iCpu].nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(&pVM->aCpus[iCpu]);
218
219 /*
220 * Call native code.
221 */
222 int rc = VINF_SUCCESS;
223#ifdef VBOX_WITH_NATIVE_NEM
224 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
225 rc = nemR3NativeInitCompleted(pVM, enmWhat);
226#else
227 RT_NOREF(pVM, enmWhat);
228#endif
229 return rc;
230}
231
232
233/**
234 *
235 * @returns VBox status code.
236 * @param pVM The cross context VM structure.
237 */
238VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
239{
240 AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
241 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
242 AssertReturn(pVM->aCpus[iCpu].nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
243
244 /* Do native termination. */
245 int rc = VINF_SUCCESS;
246#ifdef VBOX_WITH_NATIVE_NEM
247 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
248 rc = nemR3NativeTerm(pVM);
249#endif
250
251 /* Mark it as terminated. */
252 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
253 pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
254 pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
255 return rc;
256}
257
258/**
259 * External interface for querying whether native execution API is used.
260 *
261 * @returns true if NEM is being used, otherwise false.
262 * @param pUVM The user mode VM handle.
263 * @sa HMR3IsEnabled
264 */
265VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
266{
267 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
268 PVM pVM = pUVM->pVM;
269 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
270 return VM_IS_NEM_ENABLED(pVM);
271}
272
273
274/**
275 * The VM is being reset.
276 *
277 * @param pVM The cross context VM structure.
278 */
279VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
280{
281#ifdef VBOX_WITH_NATIVE_NEM
282 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
283 nemR3NativeReset(pVM);
284#else
285 RT_NOREF(pVM);
286#endif
287}
288
289
290/**
291 * Resets a virtual CPU.
292 *
293 * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
294 *
295 * @param pVCpu The cross context virtual CPU structure to reset.
296 * @param fInitIpi Set if being reset due to INIT IPI.
297 */
298VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
299{
300#ifdef VBOX_WITH_NATIVE_NEM
301 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
302 nemR3NativeResetCpu(pVCpu, fInitIpi);
303#else
304 RT_NOREF(pVCpu, fInitIpi);
305#endif
306}
307
308
309/**
310 * Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
311 *
312 * @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
313 * @param pVM The cross context VM structure.
314 */
315VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
316{
317#ifdef VBOX_WITH_NATIVE_NEM
318# ifdef RT_OS_WINDOWS
319 if (VM_IS_NEM_ENABLED(pVM))
320 return true;
321# endif
322#else
323 RT_NOREF(pVM);
324#endif
325 return false;
326}
327
328
329
330VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
331{
332 Assert(VM_IS_NEM_ENABLED(pVM));
333#ifdef VBOX_WITH_NATIVE_NEM
334 return nemR3NativeRunGC(pVM, pVCpu);
335#else
336 NOREF(pVM); NOREF(pVCpu);
337 return VERR_INTERNAL_ERROR_3;
338#endif
339}
340
341
342VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
343{
344 Assert(VM_IS_NEM_ENABLED(pVM));
345#ifdef VBOX_WITH_NATIVE_NEM
346 return nemR3NativeCanExecuteGuest(pVM, pVCpu, pCtx);
347#else
348 NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
349 return false;
350#endif
351}
352
353
354VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
355{
356 Assert(VM_IS_NEM_ENABLED(pVM));
357#ifdef VBOX_WITH_NATIVE_NEM
358 return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
359#else
360 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
361 return false;
362#endif
363}
364
365
366VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
367{
368 AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
369#ifdef VBOX_WITH_NATIVE_NEM
370 nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
371#else
372 RT_NOREF(pVM, pVCpu, fFlags);
373#endif
374}
375
376
377
378
379VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
380{
381 int rc = VINF_SUCCESS;
382#ifdef VBOX_WITH_NATIVE_NEM
383 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
384 rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
385#else
386 NOREF(pVM); NOREF(GCPhys); NOREF(cb);
387#endif
388 return rc;
389}
390
391
392VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
393{
394 int rc = VINF_SUCCESS;
395#ifdef VBOX_WITH_NATIVE_NEM
396 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
397 rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
398#else
399 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
400#endif
401 return rc;
402}
403
404
405VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
406{
407 int rc = VINF_SUCCESS;
408#ifdef VBOX_WITH_NATIVE_NEM
409 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
410 rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
411#else
412 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
413#endif
414 return rc;
415}
416
417
418VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
419{
420 int rc = VINF_SUCCESS;
421#ifdef VBOX_WITH_NATIVE_NEM
422 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
423 rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
424#else
425 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
426#endif
427 return rc;
428}
429
430
431/**
432 * Called after the ROM range has been fully completed.
433 *
434 * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
435 * number of NEMHCNotifyPhysPageProtChanged calls.
436 *
437 * @returns VBox status code
438 * @param pVM The cross context VM structure.
439 * @param GCPhys The ROM address (page aligned).
440 * @param cb The size (page aligned).
441 * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
442 */
443VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
444{
445 int rc = VINF_SUCCESS;
446#ifdef VBOX_WITH_NATIVE_NEM
447 if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
448 rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
449#else
450 NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
451#endif
452 return rc;
453}
454
455
456VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
457{
458#ifdef VBOX_WITH_NATIVE_NEM
459 if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
460 nemR3NativeNotifySetA20(pVCpu, fEnabled);
461#else
462 NOREF(pVCpu); NOREF(fEnabled);
463#endif
464}
465
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