NEMR3.cpp@ 93725

Last change on this file since 93725 was 93722, checked in by vboxsync, 3 years ago
VMM/NEMR3Native-darwin: Implement support for the pause loop exiting optimization and last branch recording, bugref:9044
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1	/* $Id: NEMR3.cpp 93722 2022-02-14 12:52:49Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager.
4	*/
5
6	/*
7	* Copyright (C) 2018-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_nem NEM - Native Execution Manager.
19	*
20	* This is an alternative execution manage to HM and raw-mode. On one host
21	* (Windows) we're forced to use this, on the others we just do it because we
22	* can. Since this is host specific in nature, information about an
23	* implementation is contained in the NEMR3Native-xxxx.cpp files.
24	*
25	* @ref pg_nem_win
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_NEM
33	#include <VBox/vmm/nem.h>
34	#include <VBox/vmm/gim.h>
35	#include "NEMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/uvm.h>
38	#include <VBox/err.h>
39
40	#include <iprt/asm.h>
41
42
43
44	/**
45	* Basic init and configuration reading.
46	*
47	* Always call NEMR3Term after calling this.
48	*
49	* @returns VBox status code.
50	* @param pVM The cross context VM structure.
51	*/
52	VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
53	{
54	LogFlow(("NEMR3Init\n"));
55
56	/*
57	* Assert alignment and sizes.
58	*/
59	AssertCompileMemberAlignment(VM, nem.s, 64);
60	AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
61
62	/*
63	* Initialize state info so NEMR3Term will always be happy.
64	* No returning prior to setting magics!
65	*/
66	pVM->nem.s.u32Magic = NEM_MAGIC;
67	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
68	{
69	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
70	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
71	}
72
73	/*
74	* Read configuration.
75	*/
76	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
77
78	/*
79	* Validate the NEM settings.
80	*/
81	int rc = CFGMR3ValidateConfig(pCfgNem,
82	"/NEM/",
83	"Enabled"
84	"\|Allow64BitGuests"
85	"\|LovelyMesaDrvWorkaround"
86	#ifdef RT_OS_WINDOWS
87	"\|UseRing0Runloop"
88	#elif defined(RT_OS_DARWIN)
89	"\|VmxPleGap"
90	"\|VmxPleWindow"
91	"\|VmxLbr"
92	#endif
93	,
94	"" /* pszValidNodes /, "NEM" / pszWho /, 0 / uInstance */);
95	if (RT_FAILURE(rc))
96	return rc;
97
98	/** @cfgm{/NEM/NEMEnabled, bool, true}
99	* Whether NEM is enabled. */
100	rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
101	AssertLogRelRCReturn(rc, rc);
102
103
104	#ifdef VBOX_WITH_64_BITS_GUESTS
105	/** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
106	* Enables AMD64 CPU features.
107	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
108	* already have the support. */
109	rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
110	AssertLogRelRCReturn(rc, rc);
111	#else
112	pVM->nem.s.fAllow64BitGuests = false;
113	#endif
114
115	/** @cfgm{/NEM/LovelyMesaDrvWorkaround, bool, false}
116	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
117	* the hypervisor it is running under. */
118	bool f;
119	rc = CFGMR3QueryBoolDef(pCfgNem, "LovelyMesaDrvWorkaround", &f, false);
120	AssertLogRelRCReturn(rc, rc);
121	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
122	{
123	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
124	pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv = f;
125	}
126
127	return VINF_SUCCESS;
128	}
129
130
131	/**
132	* This is called by HMR3Init() when HM cannot be used.
133	*
134	* Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
135	* native hypervisor API to execute the VM.
136	*
137	* @returns VBox status code.
138	* @param pVM The cross context VM structure.
139	* @param fFallback Whether this is a fallback call. Cleared if the VM is
140	* configured to use NEM instead of HM.
141	* @param fForced Whether /HM/HMForced was set. If set and we fail to
142	* enable NEM, we'll return a failure status code.
143	* Otherwise we'll assume HMR3Init falls back on raw-mode.
144	*/
145	VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
146	{
147	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
148	int rc;
149	if (pVM->nem.s.fEnabled)
150	{
151	#ifdef VBOX_WITH_NATIVE_NEM
152	rc = nemR3NativeInit(pVM, fFallback, fForced);
153	ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
154	#else
155	RT_NOREF(fFallback);
156	rc = VINF_SUCCESS;
157	#endif
158	if (RT_SUCCESS(rc))
159	{
160	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
161	{
162	#ifdef RT_OS_WINDOWS /* The WHv* API is extremely slow at handling VM exits. The AppleHv and
163	KVM APIs are much faster, thus the different mode name. :-) */
164	LogRel(("NEM:\n"
165	"NEM: NEMR3Init: Snail execution mode is active!\n"
166	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
167	"NEM: To see VirtualBox run at max speed you need to disable all Windows features\n"
168	"NEM: making use of Hyper-V. That is a moving target, so google how and carefully\n"
169	"NEM: consider the consequences of disabling these features.\n"
170	"NEM:\n"));
171	#else
172	LogRel(("NEM:\n"
173	"NEM: NEMR3Init: Turtle execution mode is active!\n"
174	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
175	"NEM:\n"));
176	#endif
177	}
178	else
179	{
180	LogRel(("NEM: NEMR3Init: Not available.\n"));
181	if (fForced)
182	rc = VERR_NEM_NOT_AVAILABLE;
183	}
184	}
185	else
186	LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
187	}
188	else
189	{
190	LogRel(("NEM: NEMR3Init: Disabled.\n"));
191	rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
192	}
193	return rc;
194	}
195
196
197	/**
198	* Perform initialization that depends on CPUM working.
199	*
200	* This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
201	*
202	* @returns VBox status code.
203	* @param pVM The cross context VM structure.
204	*/
205	VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
206	{
207	int rc = VINF_SUCCESS;
208	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
209	{
210	/*
211	* Enable CPU features making general ASSUMPTIONS (there are two similar
212	* blocks of code in HM.cpp), to avoid duplicating this code. The
213	* native backend can make check capabilities and adjust as needed.
214	*/
215	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
216	if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
217	\|\| CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
218	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
219	if (pVM->nem.s.fAllow64BitGuests)
220	{
221	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
222	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
223	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
224	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
225	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
226	}
227	/* Turn on NXE if PAE has been enabled. */
228	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
229	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
230
231	/*
232	* Do native after-CPUM init.
233	*/
234	#ifdef VBOX_WITH_NATIVE_NEM
235	rc = nemR3NativeInitAfterCPUM(pVM);
236	#else
237	RT_NOREF(pVM);
238	#endif
239	}
240	return rc;
241	}
242
243
244	/**
245	* Called when a init phase has completed.
246	*
247	* @returns VBox status code.
248	* @param pVM The cross context VM structure.
249	* @param enmWhat The phase that completed.
250	*/
251	VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
252	{
253	/*
254	* Check if GIM needs #UD, since that applies to everyone.
255	*/
256	if (enmWhat == VMINITCOMPLETED_RING3)
257	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
258	{
259	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
260	pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
261	}
262
263	/*
264	* Call native code.
265	*/
266	int rc = VINF_SUCCESS;
267	#ifdef VBOX_WITH_NATIVE_NEM
268	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
269	rc = nemR3NativeInitCompleted(pVM, enmWhat);
270	#else
271	RT_NOREF(pVM, enmWhat);
272	#endif
273	return rc;
274	}
275
276
277	/**
278	*
279	* @returns VBox status code.
280	* @param pVM The cross context VM structure.
281	*/
282	VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
283	{
284	AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
285	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
286	AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
287
288	/* Do native termination. */
289	int rc = VINF_SUCCESS;
290	#ifdef VBOX_WITH_NATIVE_NEM
291	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
292	rc = nemR3NativeTerm(pVM);
293	#endif
294
295	/* Mark it as terminated. */
296	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
297	{
298	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
299	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
300	}
301	pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
302	return rc;
303	}
304
305	/**
306	* External interface for querying whether native execution API is used.
307	*
308	* @returns true if NEM is being used, otherwise false.
309	* @param pUVM The user mode VM handle.
310	* @sa HMR3IsEnabled
311	*/
312	VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
313	{
314	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
315	PVM pVM = pUVM->pVM;
316	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
317	return VM_IS_NEM_ENABLED(pVM);
318	}
319
320
321	/**
322	* The VM is being reset.
323	*
324	* @param pVM The cross context VM structure.
325	*/
326	VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
327	{
328	#ifdef VBOX_WITH_NATIVE_NEM
329	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
330	nemR3NativeReset(pVM);
331	#else
332	RT_NOREF(pVM);
333	#endif
334	}
335
336
337	/**
338	* Resets a virtual CPU.
339	*
340	* Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
341	*
342	* @param pVCpu The cross context virtual CPU structure to reset.
343	* @param fInitIpi Set if being reset due to INIT IPI.
344	*/
345	VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
346	{
347	#ifdef VBOX_WITH_NATIVE_NEM
348	if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
349	nemR3NativeResetCpu(pVCpu, fInitIpi);
350	#else
351	RT_NOREF(pVCpu, fInitIpi);
352	#endif
353	}
354
355
356	/**
357	* Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
358	*
359	* @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
360	* @param pVM The cross context VM structure.
361	*/
362	VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
363	{
364	#ifdef VBOX_WITH_NATIVE_NEM
365	if (VM_IS_NEM_ENABLED(pVM))
366	return true;
367	#else
368	RT_NOREF(pVM);
369	#endif
370	return false;
371	}
372
373
374	/**
375	* Gets the name of a generic NEM exit code.
376	*
377	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
378	* @param uExit The NEM exit to name.
379	*/
380	VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
381	{
382	switch ((NEMEXITTYPE)uExit)
383	{
384	case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
385	case NEMEXITTYPE_HALT: return "NEM halt";
386
387	case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
388	case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
389	case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
390	case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
391	case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
392	case NEMEXITTYPE_CANCELED: return "NEM canceled";
393	case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
394
395	case NEMEXITTYPE_INTERNAL_ERROR_EMULATION: return "NEM emulation IPE";
396	case NEMEXITTYPE_INTERNAL_ERROR_FATAL: return "NEM fatal IPE";
397	case NEMEXITTYPE_INTERRUPTED: return "NEM interrupted";
398	case NEMEXITTYPE_FAILED_ENTRY: return "NEM failed VT-x/AMD-V entry";
399
400	case NEMEXITTYPE_INVALID:
401	case NEMEXITTYPE_END:
402	break;
403	}
404
405	return NULL;
406	}
407
408
409	VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
410	{
411	Assert(VM_IS_NEM_ENABLED(pVM));
412	#ifdef VBOX_WITH_NATIVE_NEM
413	return nemR3NativeRunGC(pVM, pVCpu);
414	#else
415	NOREF(pVM); NOREF(pVCpu);
416	return VERR_INTERNAL_ERROR_3;
417	#endif
418	}
419
420
421	#ifndef VBOX_WITH_NATIVE_NEM
422	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
423	{
424	RT_NOREF(pVM, pVCpu);
425	return false;
426	}
427	#endif
428
429
430	VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
431	{
432	Assert(VM_IS_NEM_ENABLED(pVM));
433	#ifdef VBOX_WITH_NATIVE_NEM
434	return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
435	#else
436	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
437	return false;
438	#endif
439	}
440
441
442	VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
443	{
444	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
445	#ifdef VBOX_WITH_NATIVE_NEM
446	nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
447	#else
448	RT_NOREF(pVM, pVCpu, fFlags);
449	#endif
450	}
451
452
453	#ifndef VBOX_WITH_NATIVE_NEM
454	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
455	{
456	RT_NOREF(pVCpu, fEnabled);
457	}
458	#endif
459

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 93725

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