1 | /* $Id: NEMR3.cpp 72343 2018-05-25 13:24:28Z vboxsync $ */
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2 | /** @file
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3 | * NEM - Native execution manager.
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4 | */
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5 |
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6 | /*
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7 | * Copyright (C) 2018 Oracle Corporation
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8 | *
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9 | * This file is part of VirtualBox Open Source Edition (OSE), as
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10 | * available from http://www.virtualbox.org. This file is free software;
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11 | * you can redistribute it and/or modify it under the terms of the GNU
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12 | * General Public License (GPL) as published by the Free Software
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13 | * Foundation, in version 2 as it comes in the "COPYING" file of the
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14 | * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
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15 | * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
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16 | */
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17 |
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18 | /** @page pg_nem NEM - Native Execution Manager.
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19 | *
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20 | * This is an alternative execution manage to HM and raw-mode. On one host
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21 | * (Windows) we're forced to use this, on the others we just do it because we
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22 | * can. Since this is host specific in nature, information about an
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23 | * implementation is contained in the NEMR3Native-xxxx.cpp files.
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24 | *
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25 | * @ref pg_nem_win
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26 | */
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27 |
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28 |
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29 | /*********************************************************************************************************************************
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30 | * Header Files *
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31 | *********************************************************************************************************************************/
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32 | #define LOG_GROUP LOG_GROUP_NEM
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33 | #include <VBox/vmm/nem.h>
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34 | #include "NEMInternal.h"
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35 | #include <VBox/vmm/vm.h>
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36 | #include <VBox/vmm/uvm.h>
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37 |
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38 | #include <iprt/asm.h>
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39 |
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40 |
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41 |
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42 | /**
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43 | * Basic init and configuration reading.
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44 | *
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45 | * Always call NEMR3Term after calling this.
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46 | *
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47 | * @returns VBox status code.
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48 | * @param pVM The cross context VM structure.
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49 | */
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50 | VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
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51 | {
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52 | LogFlow(("NEMR3Init\n"));
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53 |
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54 | /*
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55 | * Assert alignment and sizes.
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56 | */
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57 | AssertCompileMemberAlignment(VM, nem.s, 64);
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58 | AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
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59 |
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60 | /*
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61 | * Initialize state info so NEMR3Term will always be happy.
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62 | * No returning prior to setting magics!
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63 | */
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64 | pVM->nem.s.u32Magic = NEM_MAGIC;
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65 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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66 | pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC;
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67 |
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68 | /*
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69 | * Read configuration.
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70 | */
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71 | PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
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72 |
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73 | /*
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74 | * Validate the NEM settings.
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75 | */
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76 | int rc = CFGMR3ValidateConfig(pCfgNem,
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77 | "/NEM/",
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78 | "Enabled"
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79 | "|Allow64BitGuests",
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80 | "" /* pszValidNodes */, "NEM" /* pszWho */, 0 /* uInstance */);
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81 | if (RT_FAILURE(rc))
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82 | return rc;
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83 |
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84 | /** @cfgm{/NEM/NEMEnabled, bool, true}
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85 | * Whether NEM is enabled. */
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86 | rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
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87 | AssertLogRelRCReturn(rc, rc);
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88 |
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89 |
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90 | #ifdef VBOX_WITH_64_BITS_GUESTS
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91 | /** @cfgm{/HM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
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92 | * Enables AMD64 CPU features.
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93 | * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
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94 | * already have the support. */
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95 | rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
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96 | AssertLogRelRCReturn(rc, rc);
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97 | #else
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98 | pVM->nem.s.fAllow64BitGuests = false;
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99 | #endif
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100 |
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101 |
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102 | return VINF_SUCCESS;
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103 | }
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104 |
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105 |
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106 | /**
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107 | * This is called by HMR3Init() when HM cannot be used.
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108 | *
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109 | * Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
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110 | * native hypervisor API to execute the VM.
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111 | *
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112 | * @returns VBox status code.
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113 | * @param pVM The cross context VM structure.
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114 | * @param fFallback Whether this is a fallback call. Cleared if the VM is
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115 | * configured to use NEM instead of HM.
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116 | * @param fForced Whether /HM/HMForced was set. If set and we fail to
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117 | * enable NEM, we'll return a failure status code.
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118 | * Otherwise we'll assume HMR3Init falls back on raw-mode.
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119 | */
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120 | VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
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121 | {
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122 | Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
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123 | int rc;
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124 | if (pVM->nem.s.fEnabled)
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125 | {
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126 | #ifdef VBOX_WITH_NATIVE_NEM
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127 | rc = nemR3NativeInit(pVM, fFallback, fForced);
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128 | ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
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129 | #else
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130 | RT_NOREF(fFallback);
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131 | rc = VINF_SUCCESS;
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132 | #endif
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133 | if (RT_SUCCESS(rc))
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134 | {
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135 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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136 | LogRel(("NEM: NEMR3Init: Active.\n"));
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137 | else
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138 | {
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139 | LogRel(("NEM: NEMR3Init: Not available.\n"));
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140 | if (fForced)
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141 | rc = VERR_NEM_NOT_AVAILABLE;
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142 | }
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143 | }
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144 | else
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145 | LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
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146 | }
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147 | else
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148 | {
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149 | LogRel(("NEM: NEMR3Init: Disabled.\n"));
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150 | rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
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151 | }
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152 | return rc;
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153 | }
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154 |
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155 |
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156 | /**
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157 | * Perform initialization that depends on CPUM working.
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158 | *
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159 | * This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
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160 | *
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161 | * @returns VBox status code.
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162 | * @param pVM The cross context VM structure.
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163 | */
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164 | VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
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165 | {
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166 | int rc = VINF_SUCCESS;
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167 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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168 | {
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169 | /*
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170 | * Enable CPU features making general ASSUMPTIONS (there are two similar
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171 | * blocks of code in HM.cpp), to avoid duplicating this code. The
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172 | * native backend can make check capabilities and adjust as needed.
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173 | */
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174 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
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175 | if (CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD)
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176 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
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177 | if (pVM->nem.s.fAllow64BitGuests)
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178 | {
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179 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
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180 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
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181 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
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182 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
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183 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
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184 | }
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185 | /* Turn on NXE if PAE has been enabled. */
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186 | else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
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187 | CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
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188 |
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189 | /*
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190 | * Do native after-CPUM init.
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191 | */
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192 | #ifdef VBOX_WITH_NATIVE_NEM
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193 | rc = nemR3NativeInitAfterCPUM(pVM);
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194 | #else
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195 | RT_NOREF(pVM);
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196 | #endif
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197 | }
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198 | return rc;
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199 | }
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200 |
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201 |
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202 | /**
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203 | * Called when a init phase has completed.
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204 | *
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205 | * @returns VBox status code.
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206 | * @param pVM The cross context VM structure.
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207 | * @param enmWhat The phase that completed.
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208 | */
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209 | VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
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210 | {
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211 | int rc = VINF_SUCCESS;
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212 | #ifdef VBOX_WITH_NATIVE_NEM
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213 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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214 | rc = nemR3NativeInitCompleted(pVM, enmWhat);
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215 | #else
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216 | RT_NOREF(pVM, enmWhat);
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217 | #endif
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218 | return rc;
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219 | }
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220 |
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221 |
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222 | /**
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223 | *
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224 | * @returns VBox status code.
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225 | * @param pVM The cross context VM structure.
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226 | */
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227 | VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
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228 | {
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229 | AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
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230 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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231 | AssertReturn(pVM->aCpus[iCpu].nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
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232 |
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233 | /* Do native termination. */
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234 | int rc = VINF_SUCCESS;
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235 | #ifdef VBOX_WITH_NATIVE_NEM
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236 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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237 | rc = nemR3NativeTerm(pVM);
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238 | #endif
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239 |
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240 | /* Mark it as terminated. */
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241 | for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
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242 | pVM->aCpus[iCpu].nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
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243 | pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
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244 | return rc;
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245 | }
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246 |
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247 | /**
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248 | * External interface for querying whether native execution API is used.
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249 | *
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250 | * @returns true if NEM is being used, otherwise false.
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251 | * @param pUVM The user mode VM handle.
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252 | * @sa HMR3IsEnabled
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253 | */
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254 | VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
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255 | {
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256 | UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
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257 | PVM pVM = pUVM->pVM;
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258 | VM_ASSERT_VALID_EXT_RETURN(pVM, false);
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259 | return VM_IS_NEM_ENABLED(pVM);
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260 | }
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261 |
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262 |
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263 | /**
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264 | * The VM is being reset.
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265 | *
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266 | * @param pVM The cross context VM structure.
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267 | */
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268 | VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
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269 | {
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270 | #ifdef VBOX_WITH_NATIVE_NEM
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271 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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272 | nemR3NativeReset(pVM);
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273 | #else
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274 | RT_NOREF(pVM);
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275 | #endif
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276 | }
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277 |
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278 |
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279 | /**
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280 | * Resets a virtual CPU.
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281 | *
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282 | * Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
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283 | *
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284 | * @param pVCpu The cross context virtual CPU structure to reset.
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285 | * @param fInitIpi Set if being reset due to INIT IPI.
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286 | */
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287 | VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
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288 | {
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289 | #ifdef VBOX_WITH_NATIVE_NEM
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290 | if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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291 | nemR3NativeResetCpu(pVCpu, fInitIpi);
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292 | #else
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293 | RT_NOREF(pVCpu, fInitIpi);
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294 | #endif
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295 | }
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296 |
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297 |
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298 | VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
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299 | {
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300 | Assert(VM_IS_NEM_ENABLED(pVM));
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301 | #ifdef VBOX_WITH_NATIVE_NEM
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302 | return nemR3NativeRunGC(pVM, pVCpu);
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303 | #else
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304 | NOREF(pVM); NOREF(pVCpu);
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305 | return VERR_INTERNAL_ERROR_3;
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306 | #endif
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307 | }
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308 |
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309 |
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310 | VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
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311 | {
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312 | Assert(VM_IS_NEM_ENABLED(pVM));
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313 | #ifdef VBOX_WITH_NATIVE_NEM
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314 | return nemR3NativeCanExecuteGuest(pVM, pVCpu, pCtx);
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315 | #else
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316 | NOREF(pVM); NOREF(pVCpu); NOREF(pCtx);
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317 | return false;
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318 | #endif
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319 | }
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320 |
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321 |
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322 | VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
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323 | {
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324 | Assert(VM_IS_NEM_ENABLED(pVM));
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325 | #ifdef VBOX_WITH_NATIVE_NEM
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326 | return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
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327 | #else
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328 | NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
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329 | return false;
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330 | #endif
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331 | }
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332 |
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333 |
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334 | VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
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335 | {
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336 | AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
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337 | #ifdef VBOX_WITH_NATIVE_NEM
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338 | nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
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339 | #else
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340 | RT_NOREF(pVM, pVCpu, fFlags);
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341 | #endif
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342 | }
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343 |
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344 |
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345 |
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346 |
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347 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb)
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348 | {
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349 | int rc = VINF_SUCCESS;
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350 | #ifdef VBOX_WITH_NATIVE_NEM
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351 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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352 | rc = nemR3NativeNotifyPhysRamRegister(pVM, GCPhys, cb);
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353 | #else
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354 | NOREF(pVM); NOREF(GCPhys); NOREF(cb);
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355 | #endif
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356 | return rc;
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357 | }
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358 |
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359 |
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360 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvMmio2)
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361 | {
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362 | int rc = VINF_SUCCESS;
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363 | #ifdef VBOX_WITH_NATIVE_NEM
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364 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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365 | rc = nemR3NativeNotifyPhysMmioExMap(pVM, GCPhys, cb, fFlags, pvMmio2);
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366 | #else
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367 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags); NOREF(pvMmio2);
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368 | #endif
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369 | return rc;
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370 | }
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371 |
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372 |
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373 | VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
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374 | {
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375 | int rc = VINF_SUCCESS;
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376 | #ifdef VBOX_WITH_NATIVE_NEM
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377 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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378 | rc = nemR3NativeNotifyPhysMmioExUnmap(pVM, GCPhys, cb, fFlags);
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379 | #else
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380 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
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381 | #endif
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382 | return rc;
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383 | }
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384 |
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385 |
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386 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
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387 | {
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388 | int rc = VINF_SUCCESS;
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389 | #ifdef VBOX_WITH_NATIVE_NEM
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390 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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391 | rc = nemR3NativeNotifyPhysRomRegisterEarly(pVM, GCPhys, cb, fFlags);
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392 | #else
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393 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
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394 | #endif
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395 | return rc;
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396 | }
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397 |
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398 |
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399 | /**
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400 | * Called after the ROM range has been fully completed.
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401 | *
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402 | * This will be preceeded by a NEMR3NotifyPhysRomRegisterEarly() call as well a
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403 | * number of NEMHCNotifyPhysPageProtChanged calls.
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404 | *
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405 | * @returns VBox status code
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406 | * @param pVM The cross context VM structure.
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407 | * @param GCPhys The ROM address (page aligned).
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408 | * @param cb The size (page aligned).
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409 | * @param fFlags NEM_NOTIFY_PHYS_ROM_F_XXX.
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410 | */
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411 | VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags)
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412 | {
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413 | int rc = VINF_SUCCESS;
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414 | #ifdef VBOX_WITH_NATIVE_NEM
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415 | if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
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416 | rc = nemR3NativeNotifyPhysRomRegisterLate(pVM, GCPhys, cb, fFlags);
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417 | #else
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418 | NOREF(pVM); NOREF(GCPhys); NOREF(cb); NOREF(fFlags);
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419 | #endif
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420 | return rc;
|
---|
421 | }
|
---|
422 |
|
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423 |
|
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424 | VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
|
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425 | {
|
---|
426 | #ifdef VBOX_WITH_NATIVE_NEM
|
---|
427 | if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
|
---|
428 | nemR3NativeNotifySetA20(pVCpu, fEnabled);
|
---|
429 | #else
|
---|
430 | NOREF(pVCpu); NOREF(fEnabled);
|
---|
431 | #endif
|
---|
432 | }
|
---|
433 |
|
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