NEMR3.cpp@ 91848

Last change on this file since 91848 was 91848, checked in by vboxsync, 3 years ago
VMM/NEM,PGM: First bunch changes for watered down guest memory managment for NEM. (Gets stuck in bios.) bugref:10122
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1	/* $Id: NEMR3.cpp 91848 2021-10-19 23:18:13Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager.
4	*/
5
6	/*
7	* Copyright (C) 2018-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_nem NEM - Native Execution Manager.
19	*
20	* This is an alternative execution manage to HM and raw-mode. On one host
21	* (Windows) we're forced to use this, on the others we just do it because we
22	* can. Since this is host specific in nature, information about an
23	* implementation is contained in the NEMR3Native-xxxx.cpp files.
24	*
25	* @ref pg_nem_win
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_NEM
33	#include <VBox/vmm/nem.h>
34	#include <VBox/vmm/gim.h>
35	#include "NEMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/uvm.h>
38	#include <VBox/err.h>
39
40	#include <iprt/asm.h>
41
42
43
44	/**
45	* Basic init and configuration reading.
46	*
47	* Always call NEMR3Term after calling this.
48	*
49	* @returns VBox status code.
50	* @param pVM The cross context VM structure.
51	*/
52	VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
53	{
54	LogFlow(("NEMR3Init\n"));
55
56	/*
57	* Assert alignment and sizes.
58	*/
59	AssertCompileMemberAlignment(VM, nem.s, 64);
60	AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
61
62	/*
63	* Initialize state info so NEMR3Term will always be happy.
64	* No returning prior to setting magics!
65	*/
66	pVM->nem.s.u32Magic = NEM_MAGIC;
67	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
68	{
69	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
70	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
71	}
72
73	/*
74	* Read configuration.
75	*/
76	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
77
78	/*
79	* Validate the NEM settings.
80	*/
81	int rc = CFGMR3ValidateConfig(pCfgNem,
82	"/NEM/",
83	"Enabled"
84	"\|Allow64BitGuests"
85	"\|LovelyMesaDrvWorkaround"
86	#ifdef RT_OS_WINDOWS
87	"\|UseRing0Runloop"
88	#endif
89	,
90	"" /* pszValidNodes /, "NEM" / pszWho /, 0 / uInstance */);
91	if (RT_FAILURE(rc))
92	return rc;
93
94	/** @cfgm{/NEM/NEMEnabled, bool, true}
95	* Whether NEM is enabled. */
96	rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
97	AssertLogRelRCReturn(rc, rc);
98
99
100	#ifdef VBOX_WITH_64_BITS_GUESTS
101	/** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
102	* Enables AMD64 CPU features.
103	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
104	* already have the support. */
105	rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
106	AssertLogRelRCReturn(rc, rc);
107	#else
108	pVM->nem.s.fAllow64BitGuests = false;
109	#endif
110
111	/** @cfgm{/NEM/LovelyMesaDrvWorkaround, bool, false}
112	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
113	* the hypervisor it is running under. */
114	bool f;
115	rc = CFGMR3QueryBoolDef(pCfgNem, "LovelyMesaDrvWorkaround", &f, false);
116	AssertLogRelRCReturn(rc, rc);
117	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
118	{
119	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
120	pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv = f;
121	}
122
123	#ifdef RT_OS_WINDOWS
124	/** @cfgm{/NEM/UseRing0Runloop, bool, true}
125	* Whether to use the ring-0 runloop (if enabled in the build) or the ring-3 one.
126	* The latter is generally slower. This option serves as a way out in case
127	* something breaks in the ring-0 loop. */
128	# ifdef NEM_WIN_USE_RING0_RUNLOOP_BY_DEFAULT
129	bool fUseRing0Runloop = true;
130	# else
131	bool fUseRing0Runloop = false;
132	# endif
133	rc = CFGMR3QueryBoolDef(pCfgNem, "UseRing0Runloop", &fUseRing0Runloop, fUseRing0Runloop);
134	AssertLogRelRCReturn(rc, rc);
135	pVM->nem.s.fUseRing0Runloop = fUseRing0Runloop;
136	#endif
137
138	return VINF_SUCCESS;
139	}
140
141
142	/**
143	* This is called by HMR3Init() when HM cannot be used.
144	*
145	* Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
146	* native hypervisor API to execute the VM.
147	*
148	* @returns VBox status code.
149	* @param pVM The cross context VM structure.
150	* @param fFallback Whether this is a fallback call. Cleared if the VM is
151	* configured to use NEM instead of HM.
152	* @param fForced Whether /HM/HMForced was set. If set and we fail to
153	* enable NEM, we'll return a failure status code.
154	* Otherwise we'll assume HMR3Init falls back on raw-mode.
155	*/
156	VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
157	{
158	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
159	int rc;
160	if (pVM->nem.s.fEnabled)
161	{
162	#ifdef VBOX_WITH_NATIVE_NEM
163	rc = nemR3NativeInit(pVM, fFallback, fForced);
164	ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
165	#else
166	RT_NOREF(fFallback);
167	rc = VINF_SUCCESS;
168	#endif
169	if (RT_SUCCESS(rc))
170	{
171	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
172	LogRel(("NEM: NEMR3Init: Active.\n"));
173	else
174	{
175	LogRel(("NEM: NEMR3Init: Not available.\n"));
176	if (fForced)
177	rc = VERR_NEM_NOT_AVAILABLE;
178	}
179	}
180	else
181	LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
182	}
183	else
184	{
185	LogRel(("NEM: NEMR3Init: Disabled.\n"));
186	rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
187	}
188	return rc;
189	}
190
191
192	/**
193	* Perform initialization that depends on CPUM working.
194	*
195	* This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
196	*
197	* @returns VBox status code.
198	* @param pVM The cross context VM structure.
199	*/
200	VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
201	{
202	int rc = VINF_SUCCESS;
203	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
204	{
205	/*
206	* Enable CPU features making general ASSUMPTIONS (there are two similar
207	* blocks of code in HM.cpp), to avoid duplicating this code. The
208	* native backend can make check capabilities and adjust as needed.
209	*/
210	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
211	if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
212	\|\| CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
213	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
214	if (pVM->nem.s.fAllow64BitGuests)
215	{
216	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
217	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
218	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
219	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
220	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
221	}
222	/* Turn on NXE if PAE has been enabled. */
223	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
224	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
225
226	/*
227	* Do native after-CPUM init.
228	*/
229	#ifdef VBOX_WITH_NATIVE_NEM
230	rc = nemR3NativeInitAfterCPUM(pVM);
231	#else
232	RT_NOREF(pVM);
233	#endif
234	}
235	return rc;
236	}
237
238
239	/**
240	* Called when a init phase has completed.
241	*
242	* @returns VBox status code.
243	* @param pVM The cross context VM structure.
244	* @param enmWhat The phase that completed.
245	*/
246	VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
247	{
248	/*
249	* Check if GIM needs #UD, since that applies to everyone.
250	*/
251	if (enmWhat == VMINITCOMPLETED_RING3)
252	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
253	{
254	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
255	pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
256	}
257
258	/*
259	* Call native code.
260	*/
261	int rc = VINF_SUCCESS;
262	#ifdef VBOX_WITH_NATIVE_NEM
263	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
264	rc = nemR3NativeInitCompleted(pVM, enmWhat);
265	#else
266	RT_NOREF(pVM, enmWhat);
267	#endif
268	return rc;
269	}
270
271
272	/**
273	*
274	* @returns VBox status code.
275	* @param pVM The cross context VM structure.
276	*/
277	VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
278	{
279	AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
280	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
281	AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
282
283	/* Do native termination. */
284	int rc = VINF_SUCCESS;
285	#ifdef VBOX_WITH_NATIVE_NEM
286	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
287	rc = nemR3NativeTerm(pVM);
288	#endif
289
290	/* Mark it as terminated. */
291	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
292	{
293	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
294	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
295	}
296	pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
297	return rc;
298	}
299
300	/**
301	* External interface for querying whether native execution API is used.
302	*
303	* @returns true if NEM is being used, otherwise false.
304	* @param pUVM The user mode VM handle.
305	* @sa HMR3IsEnabled
306	*/
307	VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
308	{
309	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
310	PVM pVM = pUVM->pVM;
311	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
312	return VM_IS_NEM_ENABLED(pVM);
313	}
314
315
316	/**
317	* The VM is being reset.
318	*
319	* @param pVM The cross context VM structure.
320	*/
321	VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
322	{
323	#ifdef VBOX_WITH_NATIVE_NEM
324	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
325	nemR3NativeReset(pVM);
326	#else
327	RT_NOREF(pVM);
328	#endif
329	}
330
331
332	/**
333	* Resets a virtual CPU.
334	*
335	* Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
336	*
337	* @param pVCpu The cross context virtual CPU structure to reset.
338	* @param fInitIpi Set if being reset due to INIT IPI.
339	*/
340	VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
341	{
342	#ifdef VBOX_WITH_NATIVE_NEM
343	if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
344	nemR3NativeResetCpu(pVCpu, fInitIpi);
345	#else
346	RT_NOREF(pVCpu, fInitIpi);
347	#endif
348	}
349
350
351	/**
352	* Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
353	*
354	* @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
355	* @param pVM The cross context VM structure.
356	*/
357	VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
358	{
359	#ifdef VBOX_WITH_NATIVE_NEM
360	# ifdef RT_OS_WINDOWS
361	if (VM_IS_NEM_ENABLED(pVM))
362	return true;
363	# endif
364	#else
365	RT_NOREF(pVM);
366	#endif
367	return false;
368	}
369
370
371	/**
372	* Gets the name of a generic NEM exit code.
373	*
374	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
375	* @param uExit The NEM exit to name.
376	*/
377	VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
378	{
379	switch ((NEMEXITTYPE)uExit)
380	{
381	case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
382	case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
383	case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
384	case NEMEXITTYPE_HALT: return "NEM halt";
385	case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
386	case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
387	case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
388	case NEMEXITTYPE_CANCELED: return "NEM canceled";
389	case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
390	}
391
392	return NULL;
393	}
394
395
396	VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
397	{
398	Assert(VM_IS_NEM_ENABLED(pVM));
399	#ifdef VBOX_WITH_NATIVE_NEM
400	return nemR3NativeRunGC(pVM, pVCpu);
401	#else
402	NOREF(pVM); NOREF(pVCpu);
403	return VERR_INTERNAL_ERROR_3;
404	#endif
405	}
406
407
408	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
409	{
410	Assert(VM_IS_NEM_ENABLED(pVM));
411	#ifdef VBOX_WITH_NATIVE_NEM
412	return nemR3NativeCanExecuteGuest(pVM, pVCpu);
413	#else
414	NOREF(pVM); NOREF(pVCpu);
415	return false;
416	#endif
417	}
418
419
420	VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
421	{
422	Assert(VM_IS_NEM_ENABLED(pVM));
423	#ifdef VBOX_WITH_NATIVE_NEM
424	return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
425	#else
426	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
427	return false;
428	#endif
429	}
430
431
432	VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
433	{
434	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
435	#ifdef VBOX_WITH_NATIVE_NEM
436	nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
437	#else
438	RT_NOREF(pVM, pVCpu, fFlags);
439	#endif
440	}
441
442
443	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
444	{
445	#ifdef VBOX_WITH_NATIVE_NEM
446	if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
447	nemR3NativeNotifySetA20(pVCpu, fEnabled);
448	#else
449	NOREF(pVCpu); NOREF(fEnabled);
450	#endif
451	}
452

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 91848

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