NEMR3.cpp@ 93612

Last change on this file since 93612 was 93351, checked in by vboxsync, 3 years ago
VMM/NEM-win: Kicked out most of the ring-0 code because bugref:10118 + bugref:10162 means we won't use it again.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 14.0 KB

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1	/* $Id: NEMR3.cpp 93351 2022-01-19 23:35:13Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager.
4	*/
5
6	/*
7	* Copyright (C) 2018-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_nem NEM - Native Execution Manager.
19	*
20	* This is an alternative execution manage to HM and raw-mode. On one host
21	* (Windows) we're forced to use this, on the others we just do it because we
22	* can. Since this is host specific in nature, information about an
23	* implementation is contained in the NEMR3Native-xxxx.cpp files.
24	*
25	* @ref pg_nem_win
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_NEM
33	#include <VBox/vmm/nem.h>
34	#include <VBox/vmm/gim.h>
35	#include "NEMInternal.h"
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/uvm.h>
38	#include <VBox/err.h>
39
40	#include <iprt/asm.h>
41
42
43
44	/**
45	* Basic init and configuration reading.
46	*
47	* Always call NEMR3Term after calling this.
48	*
49	* @returns VBox status code.
50	* @param pVM The cross context VM structure.
51	*/
52	VMMR3_INT_DECL(int) NEMR3InitConfig(PVM pVM)
53	{
54	LogFlow(("NEMR3Init\n"));
55
56	/*
57	* Assert alignment and sizes.
58	*/
59	AssertCompileMemberAlignment(VM, nem.s, 64);
60	AssertCompile(sizeof(pVM->nem.s) <= sizeof(pVM->nem.padding));
61
62	/*
63	* Initialize state info so NEMR3Term will always be happy.
64	* No returning prior to setting magics!
65	*/
66	pVM->nem.s.u32Magic = NEM_MAGIC;
67	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
68	{
69	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
70	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC;
71	}
72
73	/*
74	* Read configuration.
75	*/
76	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
77
78	/*
79	* Validate the NEM settings.
80	*/
81	int rc = CFGMR3ValidateConfig(pCfgNem,
82	"/NEM/",
83	"Enabled"
84	"\|Allow64BitGuests"
85	"\|LovelyMesaDrvWorkaround"
86	#ifdef RT_OS_WINDOWS
87	"\|UseRing0Runloop"
88	#endif
89	,
90	"" /* pszValidNodes /, "NEM" / pszWho /, 0 / uInstance */);
91	if (RT_FAILURE(rc))
92	return rc;
93
94	/** @cfgm{/NEM/NEMEnabled, bool, true}
95	* Whether NEM is enabled. */
96	rc = CFGMR3QueryBoolDef(pCfgNem, "Enabled", &pVM->nem.s.fEnabled, true);
97	AssertLogRelRCReturn(rc, rc);
98
99
100	#ifdef VBOX_WITH_64_BITS_GUESTS
101	/** @cfgm{/NEM/Allow64BitGuests, bool, 32-bit:false, 64-bit:true}
102	* Enables AMD64 CPU features.
103	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
104	* already have the support. */
105	rc = CFGMR3QueryBoolDef(pCfgNem, "Allow64BitGuests", &pVM->nem.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
106	AssertLogRelRCReturn(rc, rc);
107	#else
108	pVM->nem.s.fAllow64BitGuests = false;
109	#endif
110
111	/** @cfgm{/NEM/LovelyMesaDrvWorkaround, bool, false}
112	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
113	* the hypervisor it is running under. */
114	bool f;
115	rc = CFGMR3QueryBoolDef(pCfgNem, "LovelyMesaDrvWorkaround", &f, false);
116	AssertLogRelRCReturn(rc, rc);
117	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
118	{
119	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
120	pVCpu->nem.s.fTrapXcptGpForLovelyMesaDrv = f;
121	}
122
123	return VINF_SUCCESS;
124	}
125
126
127	/**
128	* This is called by HMR3Init() when HM cannot be used.
129	*
130	* Sets VM::bMainExecutionEngine to VM_EXEC_ENGINE_NATIVE_API if we can use a
131	* native hypervisor API to execute the VM.
132	*
133	* @returns VBox status code.
134	* @param pVM The cross context VM structure.
135	* @param fFallback Whether this is a fallback call. Cleared if the VM is
136	* configured to use NEM instead of HM.
137	* @param fForced Whether /HM/HMForced was set. If set and we fail to
138	* enable NEM, we'll return a failure status code.
139	* Otherwise we'll assume HMR3Init falls back on raw-mode.
140	*/
141	VMMR3_INT_DECL(int) NEMR3Init(PVM pVM, bool fFallback, bool fForced)
142	{
143	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API);
144	int rc;
145	if (pVM->nem.s.fEnabled)
146	{
147	#ifdef VBOX_WITH_NATIVE_NEM
148	rc = nemR3NativeInit(pVM, fFallback, fForced);
149	ASMCompilerBarrier(); /* May have changed bMainExecutionEngine. */
150	#else
151	RT_NOREF(fFallback);
152	rc = VINF_SUCCESS;
153	#endif
154	if (RT_SUCCESS(rc))
155	{
156	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
157	{
158	#ifdef RT_OS_WINDOWS /* The WHv* API is extremely slow at handling VM exits. The AppleHv and
159	KVM APIs are much faster, thus the different mode name. :-) */
160	LogRel(("NEM:\n"
161	"NEM: NEMR3Init: Snail execution mode is active!\n"
162	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
163	"NEM: To see VirtualBox run at max speed you need to disable all Windows features\n"
164	"NEM: making use of Hyper-V. That is a moving target, so google how and carefully\n"
165	"NEM: consider the consequences of disabling these features.\n"
166	"NEM:\n"));
167	#else
168	LogRel(("NEM:\n"
169	"NEM: NEMR3Init: Turtle execution mode is active!\n"
170	"NEM: Note! VirtualBox is not able to run at its full potential in this execution mode.\n"
171	"NEM:\n"));
172	#endif
173	}
174	else
175	{
176	LogRel(("NEM: NEMR3Init: Not available.\n"));
177	if (fForced)
178	rc = VERR_NEM_NOT_AVAILABLE;
179	}
180	}
181	else
182	LogRel(("NEM: NEMR3Init: Native init failed: %Rrc.\n", rc));
183	}
184	else
185	{
186	LogRel(("NEM: NEMR3Init: Disabled.\n"));
187	rc = fForced ? VERR_NEM_NOT_ENABLED : VINF_SUCCESS;
188	}
189	return rc;
190	}
191
192
193	/**
194	* Perform initialization that depends on CPUM working.
195	*
196	* This is a noop if NEM wasn't activated by a previous NEMR3Init() call.
197	*
198	* @returns VBox status code.
199	* @param pVM The cross context VM structure.
200	*/
201	VMMR3_INT_DECL(int) NEMR3InitAfterCPUM(PVM pVM)
202	{
203	int rc = VINF_SUCCESS;
204	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
205	{
206	/*
207	* Enable CPU features making general ASSUMPTIONS (there are two similar
208	* blocks of code in HM.cpp), to avoid duplicating this code. The
209	* native backend can make check capabilities and adjust as needed.
210	*/
211	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
212	if ( CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_AMD
213	\|\| CPUMGetGuestCpuVendor(pVM) == CPUMCPUVENDOR_HYGON)
214	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
215	if (pVM->nem.s.fAllow64BitGuests)
216	{
217	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
218	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
219	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
220	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
221	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
222	}
223	/* Turn on NXE if PAE has been enabled. */
224	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
225	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
226
227	/*
228	* Do native after-CPUM init.
229	*/
230	#ifdef VBOX_WITH_NATIVE_NEM
231	rc = nemR3NativeInitAfterCPUM(pVM);
232	#else
233	RT_NOREF(pVM);
234	#endif
235	}
236	return rc;
237	}
238
239
240	/**
241	* Called when a init phase has completed.
242	*
243	* @returns VBox status code.
244	* @param pVM The cross context VM structure.
245	* @param enmWhat The phase that completed.
246	*/
247	VMMR3_INT_DECL(int) NEMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
248	{
249	/*
250	* Check if GIM needs #UD, since that applies to everyone.
251	*/
252	if (enmWhat == VMINITCOMPLETED_RING3)
253	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
254	{
255	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
256	pVCpu->nem.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu);
257	}
258
259	/*
260	* Call native code.
261	*/
262	int rc = VINF_SUCCESS;
263	#ifdef VBOX_WITH_NATIVE_NEM
264	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
265	rc = nemR3NativeInitCompleted(pVM, enmWhat);
266	#else
267	RT_NOREF(pVM, enmWhat);
268	#endif
269	return rc;
270	}
271
272
273	/**
274	*
275	* @returns VBox status code.
276	* @param pVM The cross context VM structure.
277	*/
278	VMMR3_INT_DECL(int) NEMR3Term(PVM pVM)
279	{
280	AssertReturn(pVM->nem.s.u32Magic == NEM_MAGIC, VERR_WRONG_ORDER);
281	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
282	AssertReturn(pVM->apCpusR3[idCpu]->nem.s.u32Magic == NEMCPU_MAGIC, VERR_WRONG_ORDER);
283
284	/* Do native termination. */
285	int rc = VINF_SUCCESS;
286	#ifdef VBOX_WITH_NATIVE_NEM
287	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
288	rc = nemR3NativeTerm(pVM);
289	#endif
290
291	/* Mark it as terminated. */
292	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
293	{
294	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
295	pVCpu->nem.s.u32Magic = NEMCPU_MAGIC_DEAD;
296	}
297	pVM->nem.s.u32Magic = NEM_MAGIC_DEAD;
298	return rc;
299	}
300
301	/**
302	* External interface for querying whether native execution API is used.
303	*
304	* @returns true if NEM is being used, otherwise false.
305	* @param pUVM The user mode VM handle.
306	* @sa HMR3IsEnabled
307	*/
308	VMMR3DECL(bool) NEMR3IsEnabled(PUVM pUVM)
309	{
310	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
311	PVM pVM = pUVM->pVM;
312	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
313	return VM_IS_NEM_ENABLED(pVM);
314	}
315
316
317	/**
318	* The VM is being reset.
319	*
320	* @param pVM The cross context VM structure.
321	*/
322	VMMR3_INT_DECL(void) NEMR3Reset(PVM pVM)
323	{
324	#ifdef VBOX_WITH_NATIVE_NEM
325	if (pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
326	nemR3NativeReset(pVM);
327	#else
328	RT_NOREF(pVM);
329	#endif
330	}
331
332
333	/**
334	* Resets a virtual CPU.
335	*
336	* Used to bring up secondary CPUs on SMP as well as CPU hot plugging.
337	*
338	* @param pVCpu The cross context virtual CPU structure to reset.
339	* @param fInitIpi Set if being reset due to INIT IPI.
340	*/
341	VMMR3_INT_DECL(void) NEMR3ResetCpu(PVMCPU pVCpu, bool fInitIpi)
342	{
343	#ifdef VBOX_WITH_NATIVE_NEM
344	if (pVCpu->pVMR3->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API)
345	nemR3NativeResetCpu(pVCpu, fInitIpi);
346	#else
347	RT_NOREF(pVCpu, fInitIpi);
348	#endif
349	}
350
351
352	/**
353	* Indicates to TM that TMTSCMODE_NATIVE_API should be used for TSC.
354	*
355	* @returns true if TMTSCMODE_NATIVE_API must be used, otherwise @c false.
356	* @param pVM The cross context VM structure.
357	*/
358	VMMR3_INT_DECL(bool) NEMR3NeedSpecialTscMode(PVM pVM)
359	{
360	#ifdef VBOX_WITH_NATIVE_NEM
361	if (VM_IS_NEM_ENABLED(pVM))
362	return true;
363	#else
364	RT_NOREF(pVM);
365	#endif
366	return false;
367	}
368
369
370	/**
371	* Gets the name of a generic NEM exit code.
372	*
373	* @returns Pointer to read only string if @a uExit is known, otherwise NULL.
374	* @param uExit The NEM exit to name.
375	*/
376	VMMR3DECL(const char *) NEMR3GetExitName(uint32_t uExit)
377	{
378	switch ((NEMEXITTYPE)uExit)
379	{
380	case NEMEXITTYPE_INTTERRUPT_WINDOW: return "NEM interrupt window";
381	case NEMEXITTYPE_HALT: return "NEM halt";
382
383	case NEMEXITTYPE_UNRECOVERABLE_EXCEPTION: return "NEM unrecoverable exception";
384	case NEMEXITTYPE_INVALID_VP_REGISTER_VALUE: return "NEM invalid vp register value";
385	case NEMEXITTYPE_XCPT_UD: return "NEM #UD";
386	case NEMEXITTYPE_XCPT_DB: return "NEM #DB";
387	case NEMEXITTYPE_XCPT_BP: return "NEM #BP";
388	case NEMEXITTYPE_CANCELED: return "NEM canceled";
389	case NEMEXITTYPE_MEMORY_ACCESS: return "NEM memory access";
390
391	case NEMEXITTYPE_INTERNAL_ERROR_EMULATION: return "NEM emulation IPE";
392	case NEMEXITTYPE_INTERNAL_ERROR_FATAL: return "NEM fatal IPE";
393	case NEMEXITTYPE_INTERRUPTED: return "NEM interrupted";
394	case NEMEXITTYPE_FAILED_ENTRY: return "NEM failed VT-x/AMD-V entry";
395
396	case NEMEXITTYPE_INVALID:
397	case NEMEXITTYPE_END:
398	break;
399	}
400
401	return NULL;
402	}
403
404
405	VMMR3_INT_DECL(VBOXSTRICTRC) NEMR3RunGC(PVM pVM, PVMCPU pVCpu)
406	{
407	Assert(VM_IS_NEM_ENABLED(pVM));
408	#ifdef VBOX_WITH_NATIVE_NEM
409	return nemR3NativeRunGC(pVM, pVCpu);
410	#else
411	NOREF(pVM); NOREF(pVCpu);
412	return VERR_INTERNAL_ERROR_3;
413	#endif
414	}
415
416
417	#ifndef VBOX_WITH_NATIVE_NEM
418	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
419	{
420	RT_NOREF(pVM, pVCpu);
421	return false;
422	}
423	#endif
424
425
426	VMMR3_INT_DECL(bool) NEMR3SetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
427	{
428	Assert(VM_IS_NEM_ENABLED(pVM));
429	#ifdef VBOX_WITH_NATIVE_NEM
430	return nemR3NativeSetSingleInstruction(pVM, pVCpu, fEnable);
431	#else
432	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
433	return false;
434	#endif
435	}
436
437
438	VMMR3_INT_DECL(void) NEMR3NotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
439	{
440	AssertLogRelReturnVoid(VM_IS_NEM_ENABLED(pVM));
441	#ifdef VBOX_WITH_NATIVE_NEM
442	nemR3NativeNotifyFF(pVM, pVCpu, fFlags);
443	#else
444	RT_NOREF(pVM, pVCpu, fFlags);
445	#endif
446	}
447
448
449	#ifndef VBOX_WITH_NATIVE_NEM
450	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
451	{
452	RT_NOREF(pVCpu, fEnabled);
453	}
454	#endif
455

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3.cpp@ 93612

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