NEMR3Native-darwin-armv8.cpp@ 105695

Last change on this file since 105695 was 105695, checked in by vboxsync, 7 months ago
VMMArm/NEM: Resolve hv_vm_config_create() dynamically as it is only available since 13.0, fixes building with older SDKs, bugref:10747
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1	/* $Id: NEMR3Native-darwin-armv8.cpp 105695 2024-08-15 16:24:06Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2023 Oracle and/or its affiliates.
12	*
13	* This file is part of VirtualBox base platform packages, as
14	* available from https://www.virtualbox.org.
15	*
16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License
18	* as published by the Free Software Foundation, in version 3 of the
19	* License.
20	*
21	* This program is distributed in the hope that it will be useful, but
22	* WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24	* General Public License for more details.
25	*
26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, see <https://www.gnu.org/licenses>.
28	*
29	* SPDX-License-Identifier: GPL-3.0-only
30	*/
31
32
33	/*********************************************************************************************************************************
34	* Header Files *
35	*********************************************************************************************************************************/
36	#define LOG_GROUP LOG_GROUP_NEM
37	#define VMCPU_INCL_CPUM_GST_CTX
38	#include <VBox/vmm/nem.h>
39	#include <VBox/vmm/iem.h>
40	#include <VBox/vmm/em.h>
41	#include <VBox/vmm/gic.h>
42	#include <VBox/vmm/pdm.h>
43	#include <VBox/vmm/dbgftrace.h>
44	#include <VBox/vmm/gcm.h>
45	#include "NEMInternal.h"
46	#include <VBox/vmm/vmcc.h>
47	#include <VBox/vmm/vmm.h>
48	#include <VBox/gic.h>
49	#include "dtrace/VBoxVMM.h"
50
51	#include <iprt/armv8.h>
52	#include <iprt/asm.h>
53	#include <iprt/asm-arm.h>
54	#include <iprt/asm-math.h>
55	#include <iprt/ldr.h>
56	#include <iprt/mem.h>
57	#include <iprt/path.h>
58	#include <iprt/string.h>
59	#include <iprt/system.h>
60	#include <iprt/utf16.h>
61
62	#include <iprt/formats/arm-psci.h>
63
64	#include <mach/mach_time.h>
65	#include <mach/kern_return.h>
66
67	#include <Hypervisor/Hypervisor.h>
68
69
70	/*********************************************************************************************************************************
71	* Defined Constants And Macros *
72	*********************************************************************************************************************************/
73
74
75	/*********************************************************************************************************************************
76	* Structures and Typedefs *
77	*********************************************************************************************************************************/
78
79	#if MAC_OS_X_VERSION_MIN_REQUIRED < 150000
80
81	/* Since 15.0+ */
82	typedef enum hv_gic_distributor_reg_t : uint16_t
83	{
84	HV_GIC_DISTRIBUTOR_REG_GICD_CTLR,
85	HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0
86	/** @todo */
87	} hv_gic_distributor_reg_t;
88
89
90	typedef enum hv_gic_icc_reg_t : uint16_t
91	{
92	HV_GIC_ICC_REG_AP0R0_EL1
93	/** @todo */
94	} hv_gic_icc_reg_t;
95
96
97	typedef enum hv_gic_ich_reg_t : uint16_t
98	{
99	HV_GIC_ICH_REG_AP0R0_EL2
100	/** @todo */
101	} hv_gic_ich_reg_t;
102
103
104	typedef enum hv_gic_icv_reg_t : uint16_t
105	{
106	HV_GIC_ICV_REG_AP0R0_EL1
107	/** @todo */
108	} hv_gic_icv_reg_t;
109
110
111	typedef enum hv_gic_msi_reg_t : uint16_t
112	{
113	HV_GIC_REG_GICM_SET_SPI_NSR
114	/** @todo */
115	} hv_gic_msi_reg_t;
116
117
118	typedef enum hv_gic_redistributor_reg_t : uint16_t
119	{
120	HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0
121	/** @todo */
122	} hv_gic_redistributor_reg_t;
123
124
125	typedef enum hv_gic_intid_t : uint16_t
126	{
127	HV_GIC_INT_EL1_PHYSICAL_TIMER = 23,
128	HV_GIC_INT_EL1_VIRTUAL_TIMER = 25,
129	HV_GIC_INT_EL2_PHYSICAL_TIMER = 26,
130	HV_GIC_INT_MAINTENANCE = 27,
131	HV_GIC_INT_PERFORMANCE_MONITOR = 30
132	} hv_gic_intid_t;
133
134	#endif
135
136	typedef hv_vm_config_t FN_HV_VM_CONFIG_CREATE(void);
137	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_SUPPORTED(bool *el2_supported);
138	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_ENABLED(hv_vm_config_t config, bool *el2_enabled);
139	typedef hv_return_t FN_HV_VM_CONFIG_SET_EL2_ENABLED(hv_vm_config_t config, bool el2_enabled);
140
141	typedef struct hv_gic_config_s *hv_gic_config_t;
142	typedef hv_return_t FN_HV_GIC_CREATE(hv_gic_config_t gic_config);
143	typedef hv_return_t FN_HV_GIC_RESET(void);
144	typedef hv_gic_config_t FN_HV_GIC_CONFIG_CREATE(void);
145	typedef hv_return_t FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t distributor_base_address);
146	typedef hv_return_t FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t redistributor_base_address);
147	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE(hv_gic_config_t config, hv_ipa_t msi_region_base_address);
148	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE(hv_gic_config_t config, uint32_t msi_intid_base, uint32_t msi_intid_count);
149
150	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE(hv_vcpu_t vcpu, hv_ipa_t *redistributor_base_address);
151	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE(size_t *redistributor_region_size);
152	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_SIZE(size_t *redistributor_size);
153	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_SIZE(size_t *distributor_size);
154	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT(size_t *distributor_base_alignment);
155	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT(size_t *redistributor_base_alignment);
156	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT(size_t *msi_region_base_alignment);
157	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_SIZE(size_t *msi_region_size);
158	typedef hv_return_t FN_HV_GIC_GET_SPI_INTERRUPT_RANGE(uint32_t spi_intid_base, uint32_t spi_intid_count);
159
160	typedef struct hv_gic_state_s *hv_gic_state_t;
161	typedef hv_gic_state_t FN_HV_GIC_STATE_CREATE(void);
162	typedef hv_return_t FN_HV_GIC_SET_STATE(const void *gic_state_data, size_t gic_state_size);
163	typedef hv_return_t FN_HV_GIC_STATE_GET_SIZE(hv_gic_state_t state, size_t *gic_state_size);
164	typedef hv_return_t FN_HV_GIC_STATE_GET_DATA(hv_gic_state_t state, void *gic_state_data);
165
166	typedef hv_return_t FN_HV_GIC_SEND_MSI(hv_ipa_t address, uint32_t intid);
167	typedef hv_return_t FN_HV_GIC_SET_SPI(uint32_t intid, bool level);
168
169	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t *value);
170	typedef hv_return_t FN_HV_GIC_GET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t *value);
171	typedef hv_return_t FN_HV_GIC_GET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t *value);
172	typedef hv_return_t FN_HV_GIC_GET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t *value);
173	typedef hv_return_t FN_HV_GIC_GET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t *value);
174	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t *value);
175
176	typedef hv_return_t FN_HV_GIC_SET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t value);
177	typedef hv_return_t FN_HV_GIC_SET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t value);
178	typedef hv_return_t FN_HV_GIC_SET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t value);
179	typedef hv_return_t FN_HV_GIC_SET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t value);
180	typedef hv_return_t FN_HV_GIC_SET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t value);
181	typedef hv_return_t FN_HV_GIC_SET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t value);
182
183	typedef hv_return_t FN_HV_GIC_GET_INTID(hv_gic_intid_t interrupt, uint32_t *intid);
184
185
186	/*********************************************************************************************************************************
187	* Global Variables *
188	*********************************************************************************************************************************/
189	/** @name Optional APIs imported from Hypervisor.framework.
190	* @{ */
191	static FN_HV_VM_CONFIG_CREATE g_pfnHvVmConfigCreate = NULL; / Since 13.0 */
192	static FN_HV_VM_CONFIG_GET_EL2_SUPPORTED g_pfnHvVmConfigGetEl2Supported = NULL; / Since 15.0 */
193	static FN_HV_VM_CONFIG_GET_EL2_ENABLED g_pfnHvVmConfigGetEl2Enabled = NULL; / Since 15.0 */
194	static FN_HV_VM_CONFIG_SET_EL2_ENABLED g_pfnHvVmConfigSetEl2Enabled = NULL; / Since 15.0 */
195
196	static FN_HV_GIC_CREATE g_pfnHvGicCreate = NULL; / Since 15.0 */
197	static FN_HV_GIC_RESET g_pfnHvGicReset = NULL; / Since 15.0 */
198	static FN_HV_GIC_CONFIG_CREATE g_pfnHvGicConfigCreate = NULL; / Since 15.0 */
199	static FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE g_pfnHvGicConfigSetDistributorBase = NULL; / Since 15.0 */
200	static FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE g_pfnHvGicConfigSetRedistributorBase = NULL; / Since 15.0 */
201	static FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE g_pfnHvGicConfigSetMsiRegionBase = NULL; / Since 15.0 */
202	static FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE g_pfnHvGicConfigSetMsiInterruptRange = NULL; / Since 15.0 */
203	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE g_pfnHvGicGetRedistributorBase = NULL; / Since 15.0 */
204	static FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE g_pfnHvGicGetRedistributorRegionSize = NULL; / Since 15.0 */
205	static FN_HV_GIC_GET_REDISTRIBUTOR_SIZE g_pfnHvGicGetRedistributorSize = NULL; / Since 15.0 */
206	static FN_HV_GIC_GET_DISTRIBUTOR_SIZE g_pfnHvGicGetDistributorSize = NULL; / Since 15.0 */
207	static FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetDistributorBaseAlignment = NULL; / Since 15.0 */
208	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetRedistributorBaseAlignment = NULL; / Since 15.0 */
209	static FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT g_pfnHvGicGetMsiRegionBaseAlignment = NULL; / Since 15.0 */
210	static FN_HV_GIC_GET_MSI_REGION_SIZE g_pfnHvGicGetMsiRegionSize = NULL; / Since 15.0 */
211	static FN_HV_GIC_GET_SPI_INTERRUPT_RANGE g_pfnHvGicGetSpiInterruptRange = NULL; / Since 15.0 */
212	static FN_HV_GIC_STATE_CREATE g_pfnHvGicStateCreate = NULL; / Since 15.0 */
213	static FN_HV_GIC_SET_STATE g_pfnHvGicSetState = NULL; / Since 15.0 */
214	static FN_HV_GIC_STATE_GET_SIZE g_pfnHvGicStateGetSize = NULL; / Since 15.0 */
215	static FN_HV_GIC_STATE_GET_DATA g_pfnHvGicStateGetData = NULL; / Since 15.0 */
216	static FN_HV_GIC_SEND_MSI g_pfnHvGicSendMsi = NULL; / Since 15.0 */
217	static FN_HV_GIC_SET_SPI g_pfnHvGicSetSpi = NULL; / Since 15.0 */
218	static FN_HV_GIC_GET_DISTRIBUTOR_REG g_pfnHvGicGetDistributorReg = NULL; / Since 15.0 */
219	static FN_HV_GIC_GET_MSI_REG g_pfnHvGicGetMsiReg = NULL; / Since 15.0 */
220	static FN_HV_GIC_GET_ICC_REG g_pfnHvGicGetIccReg = NULL; / Since 15.0 */
221	static FN_HV_GIC_GET_ICH_REG g_pfnHvGicGetIchReg = NULL; / Since 15.0 */
222	static FN_HV_GIC_GET_ICV_REG g_pfnHvGicGetIcvReg = NULL; / Since 15.0 */
223	static FN_HV_GIC_GET_REDISTRIBUTOR_REG g_pfnHvGicGetRedistributorReg = NULL; / Since 15.0 */
224	static FN_HV_GIC_SET_DISTRIBUTOR_REG g_pfnHvGicSetDistributorReg = NULL; / Since 15.0 */
225	static FN_HV_GIC_SET_MSI_REG g_pfnHvGicSetMsiReg = NULL; / Since 15.0 */
226	static FN_HV_GIC_SET_ICC_REG g_pfnHvGicSetIccReg = NULL; / Since 15.0 */
227	static FN_HV_GIC_SET_ICH_REG g_pfnHvGicSetIchReg = NULL; / Since 15.0 */
228	static FN_HV_GIC_SET_ICV_REG g_pfnHvGicSetIcvReg = NULL; / Since 15.0 */
229	static FN_HV_GIC_SET_REDISTRIBUTOR_REG g_pfnHvGicSetRedistributorReg = NULL; / Since 15.0 */
230	static FN_HV_GIC_GET_INTID g_pfnHvGicGetIntid = NULL; / Since 15.0 */
231	/** @} */
232
233
234	/**
235	* Import instructions.
236	*/
237	static const struct
238	{
239	void ppfn; /< The function pointer variable. */
240	const char pszName; /< The function name. /
241	} g_aImports[] =
242	{
243	#define NEM_DARWIN_IMPORT(a_Pfn, a_Name) { (void **)&(a_Pfn), #a_Name }
244	NEM_DARWIN_IMPORT(g_pfnHvVmConfigCreate, hv_vm_config_create),
245	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Supported, hv_vm_config_get_el2_supported),
246	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Enabled, hv_vm_config_get_el2_enabled),
247	NEM_DARWIN_IMPORT(g_pfnHvVmConfigSetEl2Enabled, hv_vm_config_set_el2_enabled),
248
249	NEM_DARWIN_IMPORT(g_pfnHvGicCreate, hv_gic_create),
250	NEM_DARWIN_IMPORT(g_pfnHvGicReset, hv_gic_reset),
251	NEM_DARWIN_IMPORT(g_pfnHvGicConfigCreate, hv_gic_config_create),
252	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetDistributorBase, hv_gic_config_set_distributor_base),
253	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetRedistributorBase, hv_gic_config_set_redistributor_base),
254	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiRegionBase, hv_gic_config_set_msi_region_base),
255	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiInterruptRange, hv_gic_config_set_msi_interrupt_range),
256	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBase, hv_gic_get_redistributor_base),
257	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorRegionSize, hv_gic_get_redistributor_region_size),
258	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorSize, hv_gic_get_redistributor_size),
259	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorSize, hv_gic_get_distributor_size),
260	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorBaseAlignment, hv_gic_get_distributor_base_alignment),
261	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBaseAlignment, hv_gic_get_redistributor_base_alignment),
262	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionBaseAlignment, hv_gic_get_msi_region_base_alignment),
263	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionSize, hv_gic_get_msi_region_size),
264	NEM_DARWIN_IMPORT(g_pfnHvGicGetSpiInterruptRange, hv_gic_get_spi_interrupt_range),
265	NEM_DARWIN_IMPORT(g_pfnHvGicStateCreate, hv_gic_state_create),
266	NEM_DARWIN_IMPORT(g_pfnHvGicSetState, hv_gic_set_state),
267	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetSize, hv_gic_state_get_size),
268	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetData, hv_gic_state_get_data),
269	NEM_DARWIN_IMPORT(g_pfnHvGicSendMsi, hv_gic_send_msi),
270	NEM_DARWIN_IMPORT(g_pfnHvGicSetSpi, hv_gic_set_spi),
271	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorReg, hv_gic_get_distributor_reg),
272	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiReg, hv_gic_get_msi_reg),
273	NEM_DARWIN_IMPORT(g_pfnHvGicGetIccReg, hv_gic_get_icc_reg),
274	NEM_DARWIN_IMPORT(g_pfnHvGicGetIchReg, hv_gic_get_ich_reg),
275	NEM_DARWIN_IMPORT(g_pfnHvGicGetIcvReg, hv_gic_get_icv_reg),
276	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorReg, hv_gic_get_redistributor_reg),
277	NEM_DARWIN_IMPORT(g_pfnHvGicSetDistributorReg, hv_gic_set_distributor_reg),
278	NEM_DARWIN_IMPORT(g_pfnHvGicSetMsiReg, hv_gic_set_msi_reg),
279	NEM_DARWIN_IMPORT(g_pfnHvGicSetIccReg, hv_gic_set_icc_reg),
280	NEM_DARWIN_IMPORT(g_pfnHvGicSetIchReg, hv_gic_set_ich_reg),
281	NEM_DARWIN_IMPORT(g_pfnHvGicSetIcvReg, hv_gic_set_icv_reg),
282	NEM_DARWIN_IMPORT(g_pfnHvGicSetRedistributorReg, hv_gic_set_redistributor_reg),
283	NEM_DARWIN_IMPORT(g_pfnHvGicGetIntid, hv_gic_get_intid)
284	#undef NEM_DARWIN_IMPORT
285	};
286
287
288	/*
289	* Let the preprocessor alias the APIs to import variables for better autocompletion.
290	*/
291	#ifndef IN_SLICKEDIT
292	# define hv_vm_config_create g_pfnHvVmConfigCreate
293	# define hv_vm_config_get_el2_supported g_pfnHvVmConfigGetEl2Supported
294	# define hv_vm_config_get_el2_enabled g_pfnHvVmConfigGetEl2Enabled
295	# define hv_vm_config_set_el2_enabled g_pfnHvVmConfigSetEl2Enabled
296
297	# define hv_gic_create g_pfnHvGicCreate
298	# define hv_gic_reset g_pfnHvGicReset
299	# define hv_gic_config_create g_pfnHvGicConfigCreate
300	# define hv_gic_config_set_distributor_base g_pfnHvGicConfigSetDistributorBase
301	# define hv_gic_config_set_redistributor_base g_pfnHvGicConfigSetRedistributorBase
302	# define hv_gic_config_set_msi_region_base g_pfnHvGicConfigSetMsiRegionBase
303	# define hv_gic_config_set_msi_interrupt_range g_pfnHvGicConfigSetMsiInterruptRange
304	# define hv_gic_get_redistributor_base g_pfnHvGicGetRedistributorBase
305	# define hv_gic_get_redistributor_region_size g_pfnHvGicGetRedistributorRegionSize
306	# define hv_gic_get_redistributor_size g_pfnHvGicGetRedistributorSize
307	# define hv_gic_get_distributor_size g_pfnHvGicGetDistributorSize
308	# define hv_gic_get_distributor_base_alignment g_pfnHvGicGetDistributorBaseAlignment
309	# define hv_gic_get_redistributor_base_alignment g_pfnHvGicGetRedistributorBaseAlignment
310	# define hv_gic_get_msi_region_base_alignment g_pfnHvGicGetMsiRegionBaseAlignment
311	# define hv_gic_get_msi_region_size g_pfnHvGicGetMsiRegionSize
312	# define hv_gic_get_spi_interrupt_range g_pfnHvGicGetSpiInterruptRange
313	# define hv_gic_state_create g_pfnHvGicStateCreate
314	# define hv_gic_set_state g_pfnHvGicSetState
315	# define hv_gic_state_get_size g_pfnHvGicStateGetSize
316	# define hv_gic_state_get_data g_pfnHvGicStateGetData
317	# define hv_gic_send_msi g_pfnHvGicSendMsi
318	# define hv_gic_set_spi g_pfnHvGicSetSpi
319	# define hv_gic_get_distributor_reg g_pfnHvGicGetDistributorReg
320	# define hv_gic_get_msi_reg g_pfnHvGicGetMsiReg
321	# define hv_gic_get_icc_reg g_pfnHvGicGetIccReg
322	# define hv_gic_get_ich_reg g_pfnHvGicGetIchReg
323	# define hv_gic_get_icv_reg g_pfnHvGicGetIcvReg
324	# define hv_gic_get_redistributor_reg g_pfnHvGicGetRedistributorReg
325	# define hv_gic_set_distributor_reg g_pfnHvGicSetDistributorReg
326	# define hv_gic_set_msi_reg g_pfnHvGicSetMsiReg
327	# define hv_gic_set_icc_reg g_pfnHvGicSetIccReg
328	# define hv_gic_set_ich_reg g_pfnHvGicSetIchReg
329	# define hv_gic_set_icv_reg g_pfnHvGicSetIcvReg
330	# define hv_gic_set_redistributor_reg g_pfnHvGicSetRedistributorReg
331	# define hv_gic_get_intid g_pfnHvGicGetIntid
332	#endif
333
334
335	/** The general registers. */
336	static const struct
337	{
338	hv_reg_t enmHvReg;
339	uint32_t fCpumExtrn;
340	uint32_t offCpumCtx;
341	} s_aCpumRegs[] =
342	{
343	#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
344	#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
345	CPUM_GREG_EMIT_X0_X3(0),
346	CPUM_GREG_EMIT_X0_X3(1),
347	CPUM_GREG_EMIT_X0_X3(2),
348	CPUM_GREG_EMIT_X0_X3(3),
349	CPUM_GREG_EMIT_X4_X28(4),
350	CPUM_GREG_EMIT_X4_X28(5),
351	CPUM_GREG_EMIT_X4_X28(6),
352	CPUM_GREG_EMIT_X4_X28(7),
353	CPUM_GREG_EMIT_X4_X28(8),
354	CPUM_GREG_EMIT_X4_X28(9),
355	CPUM_GREG_EMIT_X4_X28(10),
356	CPUM_GREG_EMIT_X4_X28(11),
357	CPUM_GREG_EMIT_X4_X28(12),
358	CPUM_GREG_EMIT_X4_X28(13),
359	CPUM_GREG_EMIT_X4_X28(14),
360	CPUM_GREG_EMIT_X4_X28(15),
361	CPUM_GREG_EMIT_X4_X28(16),
362	CPUM_GREG_EMIT_X4_X28(17),
363	CPUM_GREG_EMIT_X4_X28(18),
364	CPUM_GREG_EMIT_X4_X28(19),
365	CPUM_GREG_EMIT_X4_X28(20),
366	CPUM_GREG_EMIT_X4_X28(21),
367	CPUM_GREG_EMIT_X4_X28(22),
368	CPUM_GREG_EMIT_X4_X28(23),
369	CPUM_GREG_EMIT_X4_X28(24),
370	CPUM_GREG_EMIT_X4_X28(25),
371	CPUM_GREG_EMIT_X4_X28(26),
372	CPUM_GREG_EMIT_X4_X28(27),
373	CPUM_GREG_EMIT_X4_X28(28),
374	{ HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
375	{ HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
376	{ HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
377	{ HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
378	{ HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
379	#undef CPUM_GREG_EMIT_X0_X3
380	#undef CPUM_GREG_EMIT_X4_X28
381	};
382	/** SIMD/FP registers. */
383	static const struct
384	{
385	hv_simd_fp_reg_t enmHvReg;
386	uint32_t offCpumCtx;
387	} s_aCpumFpRegs[] =
388	{
389	#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
390	CPUM_VREG_EMIT(0),
391	CPUM_VREG_EMIT(1),
392	CPUM_VREG_EMIT(2),
393	CPUM_VREG_EMIT(3),
394	CPUM_VREG_EMIT(4),
395	CPUM_VREG_EMIT(5),
396	CPUM_VREG_EMIT(6),
397	CPUM_VREG_EMIT(7),
398	CPUM_VREG_EMIT(8),
399	CPUM_VREG_EMIT(9),
400	CPUM_VREG_EMIT(10),
401	CPUM_VREG_EMIT(11),
402	CPUM_VREG_EMIT(12),
403	CPUM_VREG_EMIT(13),
404	CPUM_VREG_EMIT(14),
405	CPUM_VREG_EMIT(15),
406	CPUM_VREG_EMIT(16),
407	CPUM_VREG_EMIT(17),
408	CPUM_VREG_EMIT(18),
409	CPUM_VREG_EMIT(19),
410	CPUM_VREG_EMIT(20),
411	CPUM_VREG_EMIT(21),
412	CPUM_VREG_EMIT(22),
413	CPUM_VREG_EMIT(23),
414	CPUM_VREG_EMIT(24),
415	CPUM_VREG_EMIT(25),
416	CPUM_VREG_EMIT(26),
417	CPUM_VREG_EMIT(27),
418	CPUM_VREG_EMIT(28),
419	CPUM_VREG_EMIT(29),
420	CPUM_VREG_EMIT(30),
421	CPUM_VREG_EMIT(31)
422	#undef CPUM_VREG_EMIT
423	};
424	/** Debug system registers. */
425	static const struct
426	{
427	hv_sys_reg_t enmHvReg;
428	uint32_t offCpumCtx;
429	} s_aCpumDbgRegs[] =
430	{
431	#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
432	{ HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
433	{ HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
434	/* Breakpoint registers. */
435	CPUM_DBGREG_EMIT(B, 0),
436	CPUM_DBGREG_EMIT(B, 1),
437	CPUM_DBGREG_EMIT(B, 2),
438	CPUM_DBGREG_EMIT(B, 3),
439	CPUM_DBGREG_EMIT(B, 4),
440	CPUM_DBGREG_EMIT(B, 5),
441	CPUM_DBGREG_EMIT(B, 6),
442	CPUM_DBGREG_EMIT(B, 7),
443	CPUM_DBGREG_EMIT(B, 8),
444	CPUM_DBGREG_EMIT(B, 9),
445	CPUM_DBGREG_EMIT(B, 10),
446	CPUM_DBGREG_EMIT(B, 11),
447	CPUM_DBGREG_EMIT(B, 12),
448	CPUM_DBGREG_EMIT(B, 13),
449	CPUM_DBGREG_EMIT(B, 14),
450	CPUM_DBGREG_EMIT(B, 15),
451	/* Watchpoint registers. */
452	CPUM_DBGREG_EMIT(W, 0),
453	CPUM_DBGREG_EMIT(W, 1),
454	CPUM_DBGREG_EMIT(W, 2),
455	CPUM_DBGREG_EMIT(W, 3),
456	CPUM_DBGREG_EMIT(W, 4),
457	CPUM_DBGREG_EMIT(W, 5),
458	CPUM_DBGREG_EMIT(W, 6),
459	CPUM_DBGREG_EMIT(W, 7),
460	CPUM_DBGREG_EMIT(W, 8),
461	CPUM_DBGREG_EMIT(W, 9),
462	CPUM_DBGREG_EMIT(W, 10),
463	CPUM_DBGREG_EMIT(W, 11),
464	CPUM_DBGREG_EMIT(W, 12),
465	CPUM_DBGREG_EMIT(W, 13),
466	CPUM_DBGREG_EMIT(W, 14),
467	CPUM_DBGREG_EMIT(W, 15),
468	{ HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
469	#undef CPUM_DBGREG_EMIT
470	};
471	/** PAuth key system registers. */
472	static const struct
473	{
474	hv_sys_reg_t enmHvReg;
475	uint32_t offCpumCtx;
476	} s_aCpumPAuthKeyRegs[] =
477	{
478	{ HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
479	{ HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
480	{ HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
481	{ HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
482	{ HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
483	{ HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
484	{ HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
485	{ HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
486	{ HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
487	{ HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
488	};
489	/** System registers. */
490	static const struct
491	{
492	hv_sys_reg_t enmHvReg;
493	uint32_t fCpumExtrn;
494	uint32_t offCpumCtx;
495	} s_aCpumSysRegs[] =
496	{
497	{ HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
498	{ HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
499	{ HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
500	{ HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
501	{ HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
502	{ HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
503	{ HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
504	{ HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
505	{ HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
506	{ HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
507	{ HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
508	{ HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
509	{ HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
510	{ HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
511	{ HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
512	{ HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
513	{ HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
514	{ HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
515	{ HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
516	{ HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
517	{ HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
518	{ HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
519	{ HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
520	{ HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
521
522	};
523	/** EL2 support system registers. */
524	static const struct
525	{
526	uint16_t idSysReg;
527	uint32_t offCpumCtx;
528	} s_aCpumEl2SysRegs[] =
529	{
530	{ ARMV8_AARCH64_SYSREG_CNTHCTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHCtlEl2.u64) },
531	{ ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCtlEl2.u64) },
532	{ ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCValEl2.u64) },
533	{ ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpTValEl2.u64) },
534	{ ARMV8_AARCH64_SYSREG_CNTVOFF_EL2, RT_UOFFSETOF(CPUMCTX, CntVOffEl2.u64) },
535	{ ARMV8_AARCH64_SYSREG_CPTR_EL2, RT_UOFFSETOF(CPUMCTX, CptrEl2.u64) },
536	{ ARMV8_AARCH64_SYSREG_ELR_EL2, RT_UOFFSETOF(CPUMCTX, ElrEl2.u64) },
537	{ ARMV8_AARCH64_SYSREG_ESR_EL2, RT_UOFFSETOF(CPUMCTX, EsrEl2.u64) },
538	{ ARMV8_AARCH64_SYSREG_FAR_EL2, RT_UOFFSETOF(CPUMCTX, FarEl2.u64) },
539	{ ARMV8_AARCH64_SYSREG_HCR_EL2, RT_UOFFSETOF(CPUMCTX, HcrEl2.u64) },
540	{ ARMV8_AARCH64_SYSREG_HPFAR_EL2, RT_UOFFSETOF(CPUMCTX, HpFarEl2.u64) },
541	{ ARMV8_AARCH64_SYSREG_MAIR_EL2, RT_UOFFSETOF(CPUMCTX, MairEl2.u64) },
542	//{ ARMV8_AARCH64_SYSREG_MDCR_EL2, RT_UOFFSETOF(CPUMCTX, MdcrEl2.u64) },
543	{ ARMV8_AARCH64_SYSREG_SCTLR_EL2, RT_UOFFSETOF(CPUMCTX, SctlrEl2.u64) },
544	{ ARMV8_AARCH64_SYSREG_SPSR_EL2, RT_UOFFSETOF(CPUMCTX, SpsrEl2.u64) },
545	{ ARMV8_AARCH64_SYSREG_SP_EL2, RT_UOFFSETOF(CPUMCTX, SpEl2.u64) },
546	{ ARMV8_AARCH64_SYSREG_TCR_EL2, RT_UOFFSETOF(CPUMCTX, TcrEl2.u64) },
547	{ ARMV8_AARCH64_SYSREG_TPIDR_EL2, RT_UOFFSETOF(CPUMCTX, TpidrEl2.u64) },
548	{ ARMV8_AARCH64_SYSREG_TTBR0_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr0El2.u64) },
549	{ ARMV8_AARCH64_SYSREG_TTBR1_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr1El2.u64) },
550	{ ARMV8_AARCH64_SYSREG_VBAR_EL2, RT_UOFFSETOF(CPUMCTX, VBarEl2.u64) },
551	{ ARMV8_AARCH64_SYSREG_VMPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VMpidrEl2.u64) },
552	{ ARMV8_AARCH64_SYSREG_VPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VPidrEl2.u64) },
553	{ ARMV8_AARCH64_SYSREG_VTCR_EL2, RT_UOFFSETOF(CPUMCTX, VTcrEl2.u64) },
554	{ ARMV8_AARCH64_SYSREG_VTTBR_EL2, RT_UOFFSETOF(CPUMCTX, VTtbrEl2.u64) }
555	};
556	/** ID registers. */
557	static const struct
558	{
559	hv_feature_reg_t enmHvReg;
560	uint32_t offIdStruct;
561	} s_aIdRegs[] =
562	{
563	{ HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr0El1) },
564	{ HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr1El1) },
565	{ HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar0El1) },
566	{ HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar1El1) },
567	{ HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr0El1) },
568	{ HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr1El1) },
569	{ HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr2El1) },
570	{ HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr0El1) },
571	{ HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr1El1) },
572	{ HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegClidrEl1) },
573	{ HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegCtrEl0) },
574	{ HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegDczidEl0) }
575	};
576
577
578	/*********************************************************************************************************************************
579	* Internal Functions *
580	*********************************************************************************************************************************/
581
582
583	/**
584	* Converts a HV return code to a VBox status code.
585	*
586	* @returns VBox status code.
587	* @param hrc The HV return code to convert.
588	*/
589	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
590	{
591	if (hrc == HV_SUCCESS)
592	return VINF_SUCCESS;
593
594	switch (hrc)
595	{
596	case HV_ERROR: return VERR_INVALID_STATE;
597	case HV_BUSY: return VERR_RESOURCE_BUSY;
598	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
599	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
600	case HV_NO_DEVICE: return VERR_NOT_FOUND;
601	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
602	}
603
604	return VERR_IPE_UNEXPECTED_STATUS;
605	}
606
607
608	/**
609	* Returns a human readable string of the given exception class.
610	*
611	* @returns Pointer to the string matching the given EC.
612	* @param u32Ec The exception class to return the string for.
613	*/
614	static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
615	{
616	switch (u32Ec)
617	{
618	#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
619	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
620	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
621	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
622	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
623	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
624	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
625	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
626	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
627	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
628	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
629	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
630	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
631	ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
632	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
633	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
634	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
635	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
636	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
637	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
638	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
639	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
640	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
641	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
642	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
643	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
644	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
645	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
646	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
647	ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
648	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
649	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
650	ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
651	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
652	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
653	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
654	ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
655	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
656	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
657	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
658	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
659	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
660	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
661	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
662	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
663	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
664	#undef ARMV8_EC_CASE
665	default:
666	break;
667	}
668
669	return "<INVALID>";
670	}
671
672
673	/**
674	* Resolves a NEM page state from the given protection flags.
675	*
676	* @returns NEM page state.
677	* @param fPageProt The page protection flags.
678	*/
679	DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
680	{
681	switch (fPageProt)
682	{
683	case NEM_PAGE_PROT_NONE:
684	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
685	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE:
686	return NEM_DARWIN_PAGE_STATE_RX;
687	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE:
688	return NEM_DARWIN_PAGE_STATE_RW;
689	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE:
690	return NEM_DARWIN_PAGE_STATE_RWX;
691	default:
692	break;
693	}
694
695	AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
696	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
697	}
698
699
700	/**
701	* Unmaps the given guest physical address range (page aligned).
702	*
703	* @returns VBox status code.
704	* @param pVM The cross context VM structure.
705	* @param GCPhys The guest physical address to start unmapping at.
706	* @param cb The size of the range to unmap in bytes.
707	* @param pu2State Where to store the new state of the unmappd page, optional.
708	*/
709	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
710	{
711	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
712	{
713	Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
714	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
715	return VINF_SUCCESS;
716	}
717
718	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
719	hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
720	if (RT_LIKELY(hrc == HV_SUCCESS))
721	{
722	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
723	if (pu2State)
724	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
725	Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
726	return VINF_SUCCESS;
727	}
728
729	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
730	LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
731	GCPhys, hrc));
732	return VERR_NEM_IPE_6;
733	}
734
735
736	/**
737	* Maps a given guest physical address range backed by the given memory with the given
738	* protection flags.
739	*
740	* @returns VBox status code.
741	* @param pVM The cross context VM structure.
742	* @param GCPhys The guest physical address to start mapping.
743	* @param pvRam The R3 pointer of the memory to back the range with.
744	* @param cb The size of the range, page aligned.
745	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
746	* @param pu2State Where to store the state for the new page, optional.
747	*/
748	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void pvRam, size_t cb, uint32_t fPageProt, uint8_t pu2State)
749	{
750	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
751
752	Assert(fPageProt != NEM_PAGE_PROT_NONE);
753	RT_NOREF(pVM);
754
755	hv_memory_flags_t fHvMemProt = 0;
756	if (fPageProt & NEM_PAGE_PROT_READ)
757	fHvMemProt \|= HV_MEMORY_READ;
758	if (fPageProt & NEM_PAGE_PROT_WRITE)
759	fHvMemProt \|= HV_MEMORY_WRITE;
760	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
761	fHvMemProt \|= HV_MEMORY_EXEC;
762
763	hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
764	if (hrc == HV_SUCCESS)
765	{
766	if (pu2State)
767	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
768	return VINF_SUCCESS;
769	}
770
771	return nemR3DarwinHvSts2Rc(hrc);
772	}
773
774
775	/**
776	* Changes the protection flags for the given guest physical address range.
777	*
778	* @returns VBox status code.
779	* @param GCPhys The guest physical address to start mapping.
780	* @param cb The size of the range, page aligned.
781	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
782	* @param pu2State Where to store the state for the new page, optional.
783	*/
784	DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
785	{
786	hv_memory_flags_t fHvMemProt = 0;
787	if (fPageProt & NEM_PAGE_PROT_READ)
788	fHvMemProt \|= HV_MEMORY_READ;
789	if (fPageProt & NEM_PAGE_PROT_WRITE)
790	fHvMemProt \|= HV_MEMORY_WRITE;
791	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
792	fHvMemProt \|= HV_MEMORY_EXEC;
793
794	hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
795	if (hrc == HV_SUCCESS)
796	{
797	if (pu2State)
798	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
799	return VINF_SUCCESS;
800	}
801
802	LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
803	GCPhys, cb, fPageProt, hrc));
804	return nemR3DarwinHvSts2Rc(hrc);
805	}
806
807
808	#ifdef LOG_ENABLED
809	/**
810	* Logs the current CPU state.
811	*/
812	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
813	{
814	if (LogIs3Enabled())
815	{
816	char szRegs[4096];
817	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
818	"x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
819	"x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
820	"x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
821	"x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
822	"x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
823	"x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
824	"x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
825	"x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
826	"pc=%016VR{pc} pstate=%016VR{pstate}\n"
827	"sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
828	"sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
829	"ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
830	"vbar_el1=%016VR{vbar_el1}\n"
831	);
832	char szInstr[256]; RT_ZERO(szInstr);
833	#if 0
834	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
835	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
836	szInstr, sizeof(szInstr), NULL);
837	#endif
838	Log3(("%s%s\n", szRegs, szInstr));
839
840	if (pVM->nem.s.fEl2Enabled)
841	{
842	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
843	"sp_el2=%016VR{sp_el2} elr_el2=%016VR{elr_el2}\n"
844	"spsr_el2=%016VR{spsr_el2} tpidr_el2=%016VR{tpidr_el2}\n"
845	"sctlr_el2=%016VR{sctlr_el2} tcr_el2=%016VR{tcr_el2}\n"
846	"ttbr0_el2=%016VR{ttbr0_el2} ttbr1_el2=%016VR{ttbr1_el2}\n"
847	"esr_el2=%016VR{esr_el2} far_el2=%016VR{far_el2}\n"
848	"hcr_el2=%016VR{hcr_el2} tcr_el2=%016VR{tcr_el2}\n"
849	"vbar_el2=%016VR{vbar_el2} cptr_el2=%016VR{cptr_el2}\n"
850	);
851	}
852	Log3(("%s%s\n", szRegs));
853	}
854	}
855	#endif /* LOG_ENABLED */
856
857
858	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
859	{
860	RT_NOREF(pVM);
861
862	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
863	if (hrc == HV_SUCCESS)
864	hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
865
866	if ( hrc == HV_SUCCESS
867	&& (fWhat & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR)))
868	{
869	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
870	{
871	if (s_aCpumRegs[i].fCpumExtrn & fWhat)
872	{
873	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
874	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
875	}
876	}
877	}
878
879	if ( hrc == HV_SUCCESS
880	&& (fWhat & CPUMCTX_EXTRN_V0_V31))
881	{
882	/* SIMD/FP registers. */
883	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
884	{
885	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
886	hrc \|= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
887	}
888	}
889
890	if ( hrc == HV_SUCCESS
891	&& (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
892	{
893	/* Debug registers. */
894	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
895	{
896	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
897	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
898	}
899	}
900
901	if ( hrc == HV_SUCCESS
902	&& (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
903	{
904	/* Debug registers. */
905	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
906	{
907	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
908	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
909	}
910	}
911
912	if ( hrc == HV_SUCCESS
913	&& (fWhat & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC)))
914	{
915	/* System registers. */
916	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
917	{
918	if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
919	{
920	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
921	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
922	}
923	}
924	}
925
926	if ( hrc == HV_SUCCESS
927	&& (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
928	&& pVM->nem.s.fEl2Enabled)
929	{
930	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
931	{
932	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
933	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, pu64);
934	}
935	}
936
937	if ( hrc == HV_SUCCESS
938	&& (fWhat & CPUMCTX_EXTRN_PSTATE))
939	{
940	uint64_t u64Tmp;
941	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
942	if (hrc == HV_SUCCESS)
943	pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
944	}
945
946	/* Almost done, just update extern flags. */
947	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
948	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
949	pVCpu->cpum.GstCtx.fExtrn = 0;
950
951	return nemR3DarwinHvSts2Rc(hrc);
952	}
953
954
955	/**
956	* Exports the guest state to HV for execution.
957	*
958	* @returns VBox status code.
959	* @param pVM The cross context VM structure.
960	* @param pVCpu The cross context virtual CPU structure of the
961	* calling EMT.
962	*/
963	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
964	{
965	RT_NOREF(pVM);
966	hv_return_t hrc = HV_SUCCESS;
967
968	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
969	!= (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
970	{
971	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
972	{
973	if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
974	{
975	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
976	hrc \|= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
977	}
978	}
979	}
980
981	if ( hrc == HV_SUCCESS
982	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
983	{
984	/* SIMD/FP registers. */
985	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
986	{
987	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
988	hrc \|= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
989	}
990	}
991
992	if ( hrc == HV_SUCCESS
993	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
994	{
995	/* Debug registers. */
996	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
997	{
998	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
999	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
1000	}
1001	}
1002
1003	if ( hrc == HV_SUCCESS
1004	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
1005	{
1006	/* Debug registers. */
1007	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
1008	{
1009	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
1010	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
1011	}
1012	}
1013
1014	if ( hrc == HV_SUCCESS
1015	&& (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1016	!= (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1017	{
1018	/* System registers. */
1019	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
1020	{
1021	if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1022	{
1023	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
1024	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
1025	}
1026	}
1027	}
1028
1029	if ( hrc == HV_SUCCESS
1030	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_EL2)
1031	&& pVM->nem.s.fEl2Enabled)
1032	{
1033	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1034	{
1035	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1036	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, *pu64);
1037	Assert(hrc == HV_SUCCESS);
1038	}
1039	}
1040
1041	if ( hrc == HV_SUCCESS
1042	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
1043	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
1044
1045	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
1046	return nemR3DarwinHvSts2Rc(hrc);
1047	}
1048
1049
1050	/**
1051	* Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1052	*
1053	* @returns VBox status code.
1054	* @param pErrInfo Where to always return error info.
1055	*/
1056	static int nemR3DarwinLoadHv(PRTERRINFO pErrInfo)
1057	{
1058	RTLDRMOD hMod = NIL_RTLDRMOD;
1059	static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1060
1061	int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD \| RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1062	if (RT_SUCCESS(rc))
1063	{
1064	for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1065	{
1066	int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1067	if (RT_SUCCESS(rc2))
1068	{
1069	LogRel(("NEM: info: Found optional import Hypervisor!%s.\n",
1070	g_aImports[i].pszName));
1071	}
1072	else
1073	{
1074	*g_aImports[i].ppfn = NULL;
1075
1076	LogRel(("NEM: info: Failed to import Hypervisor!%s: %Rrc\n",
1077	g_aImports[i].pszName, rc2));
1078	}
1079	}
1080	if (RT_SUCCESS(rc))
1081	{
1082	Assert(!RTErrInfoIsSet(pErrInfo));
1083	}
1084
1085	RTLdrClose(hMod);
1086	}
1087	else
1088	{
1089	RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1090	rc = VERR_NEM_INIT_FAILED;
1091	}
1092
1093	return rc;
1094	}
1095
1096
1097	/**
1098	* Dumps some GIC information to the release log.
1099	*/
1100	static void nemR3DarwinDumpGicInfo(void)
1101	{
1102	size_t val = 0;
1103	hv_return_t hrc = hv_gic_get_redistributor_size(&val);
1104	LogRel(("GICNem: hv_gic_get_redistributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1105	hrc = hv_gic_get_distributor_size(&val);
1106	LogRel(("GICNem: hv_gic_get_distributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1107	hrc = hv_gic_get_distributor_base_alignment(&val);
1108	LogRel(("GICNem: hv_gic_get_distributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1109	hrc = hv_gic_get_redistributor_base_alignment(&val);
1110	LogRel(("GICNem: hv_gic_get_redistributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1111	hrc = hv_gic_get_msi_region_base_alignment(&val);
1112	LogRel(("GICNem: hv_gic_get_msi_region_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1113	hrc = hv_gic_get_msi_region_size(&val);
1114	LogRel(("GICNem: hv_gic_get_msi_region_size() -> hrc=%#x / size=%zu\n", hrc, val));
1115	uint32_t u32SpiIntIdBase = 0;
1116	uint32_t cSpiIntIds = 0;
1117	hrc = hv_gic_get_spi_interrupt_range(&u32SpiIntIdBase, &cSpiIntIds);
1118	LogRel(("GICNem: hv_gic_get_spi_interrupt_range() -> hrc=%#x / SpiIntIdBase=%u, cSpiIntIds=%u\n", hrc, u32SpiIntIdBase, cSpiIntIds));
1119
1120	uint32_t u32IntId = 0;
1121	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER, &u32IntId);
1122	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1123	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER, &u32IntId);
1124	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1125	hrc = hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER, &u32IntId);
1126	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1127	hrc = hv_gic_get_intid(HV_GIC_INT_MAINTENANCE, &u32IntId);
1128	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_MAINTENANCE) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1129	hrc = hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR, &u32IntId);
1130	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1131	}
1132
1133
1134	/**
1135	* Sets the given SPI inside the in-kernel KVM GIC.
1136	*
1137	* @returns VBox status code.
1138	* @param pVM The VM instance.
1139	* @param uIntId The SPI ID to update.
1140	* @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1141	*/
1142	VMMR3_INT_DECL(int) GICR3NemSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
1143	{
1144	RT_NOREF(pVM);
1145	Assert(hv_gic_set_spi);
1146
1147	hv_return_t hrc = hv_gic_set_spi(uIntId + GIC_INTID_RANGE_SPI_START, fAsserted);
1148	return nemR3DarwinHvSts2Rc(hrc);
1149	}
1150
1151
1152	/**
1153	* Sets the given PPI inside the in-kernel KVM GIC.
1154	*
1155	* @returns VBox status code.
1156	* @param pVCpu The vCPU for whih the PPI state is updated.
1157	* @param uIntId The PPI ID to update.
1158	* @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1159	*/
1160	VMMR3_INT_DECL(int) GICR3NemPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
1161	{
1162	RT_NOREF(pVCpu, uIntId, fAsserted);
1163
1164	/* Should never be called as the PPIs are handled entirely in Hypervisor.framework/AppleHV. */
1165	AssertFailed();
1166	return VERR_NEM_IPE_9;
1167	}
1168
1169
1170	static int nemR3DarwinGicCreate(PVM pVM)
1171	{
1172	nemR3DarwinDumpGicInfo();
1173
1174	//PCFGMNODE pGicDev = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic/0");
1175	PCFGMNODE pGicCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0/Config");
1176
1177	hv_gic_config_t hGicCfg = hv_gic_config_create();
1178
1179	/*
1180	* Query the MMIO ranges.
1181	*/
1182	RTGCPHYS GCPhysMmioBaseDist = 0;
1183	int rc = CFGMR3QueryU64(pGicCfg, "DistributorMmioBase", &GCPhysMmioBaseDist);
1184	if (RT_FAILURE(rc))
1185	return VMSetError(pVM, rc, RT_SRC_POS,
1186	"Configuration error: Failed to get the \"DistributorMmioBase\" value\n");
1187
1188	RTGCPHYS GCPhysMmioBaseReDist = 0;
1189	rc = CFGMR3QueryU64(pGicCfg, "RedistributorMmioBase", &GCPhysMmioBaseReDist);
1190	if (RT_FAILURE(rc))
1191	return VMSetError(pVM, rc, RT_SRC_POS,
1192	"Configuration error: Failed to get the \"RedistributorMmioBase\" value\n");
1193
1194	hv_return_t hrc = hv_gic_config_set_distributor_base(hGicCfg, GCPhysMmioBaseDist);
1195	if (hrc != HV_SUCCESS)
1196	return nemR3DarwinHvSts2Rc(hrc);
1197
1198	hrc = hv_gic_config_set_redistributor_base(hGicCfg, GCPhysMmioBaseReDist);
1199	if (hrc != HV_SUCCESS)
1200	return nemR3DarwinHvSts2Rc(hrc);
1201
1202	hrc = hv_gic_create(hGicCfg);
1203	os_release(hGicCfg);
1204	if (hrc != HV_SUCCESS)
1205	return nemR3DarwinHvSts2Rc(hrc);
1206
1207	/* Make sure the device is not instantiated as Hypervisor.framework provides it. */
1208	//CFGMR3RemoveNode(pGicDev);
1209	return rc;
1210	}
1211
1212
1213	/**
1214	* Try initialize the native API.
1215	*
1216	* This may only do part of the job, more can be done in
1217	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
1218	*
1219	* @returns VBox status code.
1220	* @param pVM The cross context VM structure.
1221	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
1222	* the latter we'll fail if we cannot initialize.
1223	* @param fForced Whether the HMForced flag is set and we should
1224	* fail if we cannot initialize.
1225	*/
1226	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
1227	{
1228	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
1229
1230	/*
1231	* Some state init.
1232	*/
1233	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
1234	RT_NOREF(pCfgNem);
1235
1236	/*
1237	* Error state.
1238	* The error message will be non-empty on failure and 'rc' will be set too.
1239	*/
1240	RTERRINFOSTATIC ErrInfo;
1241	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
1242
1243	/* Resolve optional imports */
1244	int rc = nemR3DarwinLoadHv(pErrInfo);
1245	if (RT_FAILURE(rc))
1246	return rc;
1247
1248	/*
1249	* Need to enable nested virt here if supported and reset the CFGM value to false
1250	* if not supported. This ASSUMES that NEM is initialized before CPUM.
1251	*/
1252	PCFGMNODE pCfgCpum = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/");
1253	hv_vm_config_t hVmCfg = NULL;
1254
1255	if ( hv_vm_config_create
1256	&& hv_vm_config_get_el2_supported)
1257	{
1258	hVmCfg = hv_vm_config_create();
1259
1260	bool fHvEl2Supported = false;
1261	hv_return_t hrc = hv_vm_config_get_el2_supported(&fHvEl2Supported);
1262	if ( hrc == HV_SUCCESS
1263	&& fHvEl2Supported)
1264	{
1265	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
1266	* Whether to expose the hardware virtualization (EL2/VHE) feature to the guest.
1267	* The default is false. Only supported on M3 and later and macOS 15.0+ (Sonoma).
1268	*/
1269	bool fNestedHWVirt = false;
1270	rc = CFGMR3QueryBoolDef(pCfgCpum, "NestedHWVirt", &fNestedHWVirt, false);
1271	AssertLogRelRCReturn(rc, rc);
1272	if (fNestedHWVirt)
1273	{
1274	hrc = hv_vm_config_set_el2_enabled(hVmCfg, fNestedHWVirt);
1275	if (hrc != HV_SUCCESS)
1276	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
1277	"Cannot enable nested virtualization (hrc=%#x)!\n", hrc);
1278	else
1279	{
1280	pVM->nem.s.fEl2Enabled = true;
1281	LogRel(("NEM: Enabled nested virtualization (EL2) support\n"));
1282	}
1283	}
1284	}
1285	else
1286	{
1287	/* Ensure nested virt is not set. */
1288	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1289
1290	LogRel(("NEM: The host doesn't supported nested virtualization! (hrc=%#x fHvEl2Supported=%RTbool)\n",
1291	hrc, fHvEl2Supported));
1292	}
1293	}
1294	else
1295	{
1296	/* Ensure nested virt is not set. */
1297	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1298	LogRel(("NEM: Hypervisor.framework doesn't supported nested virtualization!\n"));
1299	}
1300
1301	hv_return_t hrc = hv_vm_create(hVmCfg);
1302	os_release(hVmCfg);
1303	if (hrc == HV_SUCCESS)
1304	{
1305	pVM->nem.s.fCreatedVm = true;
1306	pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
1307
1308	/* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
1309	pVM->nem.s.u64VTimerOff = 0;
1310
1311	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
1312	Log(("NEM: Marked active!\n"));
1313	PGMR3EnableNemMode(pVM);
1314	}
1315	else
1316	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
1317	"hv_vm_create() failed: %#x", hrc);
1318
1319	/*
1320	* We only fail if in forced mode, otherwise just log the complaint and return.
1321	*/
1322	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
1323	if ( (fForced \|\| !fFallback)
1324	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
1325	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1326
1327	if (RTErrInfoIsSet(pErrInfo))
1328	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
1329	return VINF_SUCCESS;
1330	}
1331
1332
1333	/**
1334	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
1335	*
1336	* @returns VBox status code
1337	* @param pVM The VM handle.
1338	* @param pVCpu The vCPU handle.
1339	* @param idCpu ID of the CPU to create.
1340	*/
1341	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
1342	{
1343	if (idCpu == 0)
1344	{
1345	Assert(pVM->nem.s.hVCpuCfg == NULL);
1346
1347	/* Create a new vCPU config and query the ID registers. */
1348	pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
1349	if (!pVM->nem.s.hVCpuCfg)
1350	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1351	"Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
1352
1353	/* Query ID registers and hand them to CPUM. */
1354	CPUMIDREGS IdRegs; RT_ZERO(IdRegs);
1355	for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
1356	{
1357	uint64_t pu64 = (uint64_t )((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
1358	hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
1359	if (hrc != HV_SUCCESS)
1360	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1361	"Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
1362	}
1363
1364	int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
1365	if (RT_FAILURE(rc))
1366	return rc;
1367	}
1368
1369	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
1370	if (hrc != HV_SUCCESS)
1371	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1372	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1373
1374	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
1375	if (hrc != HV_SUCCESS)
1376	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1377	"Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1378
1379	return VINF_SUCCESS;
1380	}
1381
1382
1383	/**
1384	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
1385	*
1386	* @returns VBox status code.
1387	* @param pVM The VM handle.
1388	* @param pVCpu The vCPU handle.
1389	*/
1390	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
1391	{
1392	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1393	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1394
1395	if (pVCpu->idCpu == 0)
1396	{
1397	os_release(pVM->nem.s.hVCpuCfg);
1398	pVM->nem.s.hVCpuCfg = NULL;
1399	}
1400	return VINF_SUCCESS;
1401	}
1402
1403
1404	/**
1405	* This is called after CPUMR3Init is done.
1406	*
1407	* @returns VBox status code.
1408	* @param pVM The VM handle..
1409	*/
1410	int nemR3NativeInitAfterCPUM(PVM pVM)
1411	{
1412	/*
1413	* Validate sanity.
1414	*/
1415	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
1416	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
1417
1418	/* Need to create the GIC here before any vCPU is created according to the Apple docs. */
1419	if (hv_gic_create)
1420	{
1421	int rc = nemR3DarwinGicCreate(pVM);
1422	if (RT_FAILURE(rc))
1423	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Creating the GIC failed: %Rrc", rc);
1424	}
1425
1426	/*
1427	* Setup the EMTs.
1428	*/
1429	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1430	{
1431	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1432
1433	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
1434	if (RT_FAILURE(rc))
1435	{
1436	/* Rollback. */
1437	while (idCpu--)
1438	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
1439
1440	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
1441	}
1442	}
1443
1444	pVM->nem.s.fCreatedEmts = true;
1445	return VINF_SUCCESS;
1446	}
1447
1448
1449	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1450	{
1451	RT_NOREF(pVM, enmWhat);
1452	return VINF_SUCCESS;
1453	}
1454
1455
1456	int nemR3NativeTerm(PVM pVM)
1457	{
1458	/*
1459	* Delete the VM.
1460	*/
1461
1462	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
1463	{
1464	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1465
1466	/*
1467	* Apple's documentation states that the vCPU should be destroyed
1468	* on the thread running the vCPU but as all the other EMTs are gone
1469	* at this point, destroying the VM would hang.
1470	*
1471	* We seem to be at luck here though as destroying apparently works
1472	* from EMT(0) as well.
1473	*/
1474	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1475	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1476	}
1477
1478	pVM->nem.s.fCreatedEmts = false;
1479	if (pVM->nem.s.fCreatedVm)
1480	{
1481	hv_return_t hrc = hv_vm_destroy();
1482	if (hrc != HV_SUCCESS)
1483	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
1484
1485	pVM->nem.s.fCreatedVm = false;
1486	}
1487	return VINF_SUCCESS;
1488	}
1489
1490
1491	/**
1492	* VM reset notification.
1493	*
1494	* @param pVM The cross context VM structure.
1495	*/
1496	void nemR3NativeReset(PVM pVM)
1497	{
1498	RT_NOREF(pVM);
1499	}
1500
1501
1502	/**
1503	* Reset CPU due to INIT IPI or hot (un)plugging.
1504	*
1505	* @param pVCpu The cross context virtual CPU structure of the CPU being
1506	* reset.
1507	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
1508	*/
1509	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
1510	{
1511	RT_NOREF(pVCpu, fInitIpi);
1512	}
1513
1514
1515	/**
1516	* Returns the byte size from the given access SAS value.
1517	*
1518	* @returns Number of bytes to transfer.
1519	* @param uSas The SAS value to convert.
1520	*/
1521	DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
1522	{
1523	switch (uSas)
1524	{
1525	case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
1526	case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
1527	case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
1528	case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
1529	default:
1530	AssertReleaseFailed();
1531	}
1532
1533	return 0;
1534	}
1535
1536
1537	/**
1538	* Sets the given general purpose register to the given value.
1539	*
1540	* @param pVCpu The cross context virtual CPU structure of the
1541	* calling EMT.
1542	* @param uReg The register index.
1543	* @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
1544	* @param fSignExtend Flag whether to sign extend the value.
1545	* @param u64Val The value.
1546	*/
1547	DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
1548	{
1549	AssertReturnVoid(uReg < 31);
1550
1551	if (f64BitReg)
1552	pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
1553	else
1554	pVCpu->cpum.GstCtx.aGRegs[uReg].w = fSignExtend ? (int32_t)u64Val : u64Val; /** @todo Does this clear the upper half on real hardware? */
1555
1556	/* Mark the register as not extern anymore. */
1557	switch (uReg)
1558	{
1559	case 0:
1560	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1561	break;
1562	case 1:
1563	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1564	break;
1565	case 2:
1566	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1567	break;
1568	case 3:
1569	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1570	break;
1571	default:
1572	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1573	/** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1574	}
1575	}
1576
1577
1578	/**
1579	* Gets the given general purpose register and returns the value.
1580	*
1581	* @returns Value from the given register.
1582	* @param pVCpu The cross context virtual CPU structure of the
1583	* calling EMT.
1584	* @param uReg The register index.
1585	*/
1586	DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1587	{
1588	AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
1589
1590	if (uReg == ARMV8_AARCH64_REG_ZR)
1591	return 0;
1592
1593	/** @todo Import the register if extern. */
1594	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1595
1596	return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1597	}
1598
1599
1600	/**
1601	* Works on the data abort exception (which will be a MMIO access most of the time).
1602	*
1603	* @returns VBox strict status code.
1604	* @param pVM The cross context VM structure.
1605	* @param pVCpu The cross context virtual CPU structure of the
1606	* calling EMT.
1607	* @param uIss The instruction specific syndrome value.
1608	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1609	* @param GCPtrDataAbrt The virtual GC address causing the data abort.
1610	* @param GCPhysDataAbrt The physical GC address which caused the data abort.
1611	*/
1612	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1613	RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1614	{
1615	bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1616	bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1617	bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1618	bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1619	bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1620	uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1621	uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1622	size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1623	LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1624	fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1625
1626	RT_NOREF(fL2Fault, GCPtrDataAbrt);
1627
1628	if (fWrite)
1629	{
1630	/*
1631	* Check whether this is one of the dirty tracked regions, mark it as dirty
1632	* and enable write support for this region again.
1633	*
1634	* This is required for proper VRAM tracking or the display might not get updated
1635	* and it is impossible to use the PGM generic facility as it operates on guest page sizes
1636	* but setting protection flags with Hypervisor.framework works only host page sized regions, so
1637	* we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1638	* which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1639	* write access again (due to a missing interpreter right now).
1640	*/
1641	for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1642	{
1643	PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1644
1645	if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1646	&& GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1647	{
1648	pMmio2Region->fDirty = true;
1649
1650	uint8_t u2State;
1651	int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1652	NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE \| NEM_PAGE_PROT_WRITE, &u2State);
1653
1654	/* Restart the instruction if there is no instruction syndrome available. */
1655	if (RT_FAILURE(rc) \|\| !fIsv)
1656	return rc;
1657	}
1658	}
1659	}
1660
1661	AssertReturn(fIsv, VERR_NOT_SUPPORTED); /** @todo Implement using IEM when this should occur. */
1662
1663	EMHistoryAddExit(pVCpu,
1664	fWrite
1665	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1666	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1667	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1668
1669	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1670	uint64_t u64Val = 0;
1671	if (fWrite)
1672	{
1673	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1674	rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1675	Log4(("MmioExit/%u: %08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1676	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1677	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1678	}
1679	else
1680	{
1681	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1682	Log4(("MmioExit/%u: %08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1683	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1684	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1685	if (rcStrict == VINF_SUCCESS)
1686	nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1687	}
1688
1689	if (rcStrict == VINF_SUCCESS)
1690	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1691
1692	return rcStrict;
1693	}
1694
1695
1696	/**
1697	* Works on the trapped MRS, MSR and system instruction exception.
1698	*
1699	* @returns VBox strict status code.
1700	* @param pVM The cross context VM structure.
1701	* @param pVCpu The cross context virtual CPU structure of the
1702	* calling EMT.
1703	* @param uIss The instruction specific syndrome value.
1704	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1705	*/
1706	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1707	{
1708	bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1709	uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1710	uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1711	uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1712	uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1713	uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1714	uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1715	uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1716	LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1717	fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1718
1719	/** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1720	EMHistoryAddExit(pVCpu,
1721	fRead
1722	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1723	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1724	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1725
1726	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1727	uint64_t u64Val = 0;
1728	if (fRead)
1729	{
1730	RT_NOREF(pVM);
1731	rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1732	Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1733	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1734	VBOXSTRICTRC_VAL(rcStrict) ));
1735	if (rcStrict == VINF_SUCCESS)
1736	nemR3DarwinSetGReg(pVCpu, uReg, true /f64BitReg/, false /fSignExtend/, u64Val);
1737	}
1738	else
1739	{
1740	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1741	rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1742	Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1743	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1744	VBOXSTRICTRC_VAL(rcStrict) ));
1745	}
1746
1747	if (rcStrict == VINF_SUCCESS)
1748	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1749
1750	return rcStrict;
1751	}
1752
1753
1754	/**
1755	* Works on the trapped HVC instruction exception.
1756	*
1757	* @returns VBox strict status code.
1758	* @param pVM The cross context VM structure.
1759	* @param pVCpu The cross context virtual CPU structure of the
1760	* calling EMT.
1761	* @param uIss The instruction specific syndrome value.
1762	* @param fAdvancePc Flag whether to advance the guest program counter.
1763	*/
1764	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fAdvancePc = false)
1765	{
1766	uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1767	LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1768
1769	#if 0 /** @todo For later */
1770	EMHistoryAddExit(pVCpu,
1771	fRead
1772	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1773	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1774	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1775	#endif
1776
1777	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1778	if (u16Imm == 0)
1779	{
1780	/** @todo Raise exception to EL1 if PSCI not configured. */
1781	/** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1782	uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_AARCH64_REG_X0].w;
1783	bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1784	uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1785	uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1786	if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1787	{
1788	switch (uFunNum)
1789	{
1790	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1791	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
1792	break;
1793	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1794	rcStrict = VMR3PowerOff(pVM->pUVM);
1795	break;
1796	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1797	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1798	{
1799	bool fHaltOnReset;
1800	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
1801	if (RT_SUCCESS(rc) && fHaltOnReset)
1802	{
1803	Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
1804	rc = VINF_EM_HALT;
1805	}
1806	else
1807	{
1808	/** @todo pVM->pdm.s.fResetFlags = fFlags; */
1809	VM_FF_SET(pVM, VM_FF_RESET);
1810	rc = VINF_EM_RESET;
1811	}
1812	break;
1813	}
1814	case ARM_PSCI_FUNC_ID_CPU_ON:
1815	{
1816	uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1817	RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X2);
1818	uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X3);
1819	VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
1820	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /f64BitReg/, false /fSignExtend/, ARM_PSCI_STS_SUCCESS);
1821	break;
1822	}
1823	case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
1824	{
1825	uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1826	switch (u32FunNum)
1827	{
1828	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1829	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1830	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1831	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1832	case ARM_PSCI_FUNC_ID_CPU_ON:
1833	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1834	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1835	false /f64BitReg/, false /fSignExtend/,
1836	(uint64_t)ARM_PSCI_STS_SUCCESS);
1837	break;
1838	default:
1839	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1840	false /f64BitReg/, false /fSignExtend/,
1841	(uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1842	}
1843	break;
1844	}
1845	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1846	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_MIGRATE_INFO_TYPE_TOS_NOT_PRESENT);
1847	break;
1848	default:
1849	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1850	}
1851	}
1852	else
1853	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1854	}
1855	/** @todo What to do if immediate is != 0? */
1856
1857	if ( rcStrict == VINF_SUCCESS
1858	&& fAdvancePc)
1859	pVCpu->cpum.GstCtx.Pc.u64 += sizeof(uint32_t);
1860
1861	return rcStrict;
1862	}
1863
1864
1865	/**
1866	* Handles an exception VM exit.
1867	*
1868	* @returns VBox strict status code.
1869	* @param pVM The cross context VM structure.
1870	* @param pVCpu The cross context virtual CPU structure of the
1871	* calling EMT.
1872	* @param pExit Pointer to the exit information.
1873	*/
1874	static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
1875	{
1876	uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
1877	uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
1878	bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
1879
1880	LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1881	pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1882
1883	switch (uEc)
1884	{
1885	case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
1886	return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
1887	pExit->exception.physical_address);
1888	case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
1889	return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
1890	case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
1891	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
1892	case ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN:
1893	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss, true);
1894	case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
1895	{
1896	/* No need to halt if there is an interrupt pending already. */
1897	if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ)))
1898	return VINF_SUCCESS;
1899
1900	/* Set the vTimer expiration in order to get out of the halt at the right point in time. */
1901	if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
1902	&& !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
1903	{
1904	uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
1905
1906	/* Check whether it expired and start executing guest code. */
1907	if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
1908	return VINF_SUCCESS;
1909
1910	uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
1911	uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
1912
1913	/*
1914	* Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
1915	* + scheduling overhead which would increase the wakeup latency.
1916	* So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
1917	* between CPU load when the guest is idle and performance).
1918	*/
1919	if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
1920	return VINF_SUCCESS;
1921
1922	LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
1923	cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
1924	TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
1925	}
1926	else
1927	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1928
1929	return VINF_EM_HALT;
1930	}
1931	case ARMV8_ESR_EL2_EC_UNKNOWN:
1932	default:
1933	LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1934	uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1935	AssertReleaseFailed();
1936	return VERR_NOT_IMPLEMENTED;
1937	}
1938
1939	return VINF_SUCCESS;
1940	}
1941
1942
1943	/**
1944	* Handles an exit from hv_vcpu_run().
1945	*
1946	* @returns VBox strict status code.
1947	* @param pVM The cross context VM structure.
1948	* @param pVCpu The cross context virtual CPU structure of the
1949	* calling EMT.
1950	*/
1951	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
1952	{
1953	int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
1954	if (RT_FAILURE(rc))
1955	return rc;
1956
1957	#ifdef LOG_ENABLED
1958	if (LogIs3Enabled())
1959	nemR3DarwinLogState(pVM, pVCpu);
1960	#endif
1961
1962	hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
1963	switch (pExit->reason)
1964	{
1965	case HV_EXIT_REASON_CANCELED:
1966	return VINF_EM_RAW_INTERRUPT;
1967	case HV_EXIT_REASON_EXCEPTION:
1968	return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
1969	case HV_EXIT_REASON_VTIMER_ACTIVATED:
1970	{
1971	LogFlowFunc(("vTimer got activated\n"));
1972	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1973	pVCpu->nem.s.fVTimerActivated = true;
1974	return GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /fAsserted/);
1975	}
1976	default:
1977	AssertReleaseFailed();
1978	break;
1979	}
1980
1981	return VERR_INVALID_STATE;
1982	}
1983
1984
1985	/**
1986	* Runs the guest once until an exit occurs.
1987	*
1988	* @returns HV status code.
1989	* @param pVM The cross context VM structure.
1990	* @param pVCpu The cross context virtual CPU structure.
1991	*/
1992	static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
1993	{
1994	TMNotifyStartOfExecution(pVM, pVCpu);
1995
1996	hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
1997
1998	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
1999
2000	return hrc;
2001	}
2002
2003
2004	/**
2005	* Prepares the VM to run the guest.
2006	*
2007	* @returns Strict VBox status code.
2008	* @param pVM The cross context VM structure.
2009	* @param pVCpu The cross context virtual CPU structure.
2010	* @param fSingleStepping Flag whether we run in single stepping mode.
2011	*/
2012	static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
2013	{
2014	#ifdef LOG_ENABLED
2015	bool fIrq = false;
2016	bool fFiq = false;
2017
2018	if (LogIs3Enabled())
2019	nemR3DarwinLogState(pVM, pVCpu);
2020	#endif
2021
2022	/** @todo */ RT_NOREF(fSingleStepping);
2023	int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
2024	AssertRCReturn(rc, rc);
2025
2026	/* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
2027	if (pVCpu->nem.s.fVTimerActivated)
2028	{
2029	/* Read the CNTV_CTL_EL0 register. */
2030	uint64_t u64CntvCtl = 0;
2031
2032	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
2033	AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2034
2035	if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_IMASK \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2036	!= (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2037	{
2038	/* Clear the interrupt. */
2039	GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /fAsserted/);
2040
2041	pVCpu->nem.s.fVTimerActivated = false;
2042	hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /vtimer_is_masked/);
2043	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2044	}
2045	}
2046
2047	/* Set the pending interrupt state. */
2048	hv_return_t hrc = HV_SUCCESS;
2049	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
2050	{
2051	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
2052	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2053	#ifdef LOG_ENABLED
2054	fIrq = true;
2055	#endif
2056	}
2057	else
2058	{
2059	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
2060	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2061	}
2062
2063	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
2064	{
2065	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
2066	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2067	#ifdef LOG_ENABLED
2068	fFiq = true;
2069	#endif
2070	}
2071	else
2072	{
2073	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
2074	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2075	}
2076
2077	LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
2078	pVCpu->nem.s.fEventPending = false;
2079	return VINF_SUCCESS;
2080	}
2081
2082
2083	/**
2084	* The normal runloop (no debugging features enabled).
2085	*
2086	* @returns Strict VBox status code.
2087	* @param pVM The cross context VM structure.
2088	* @param pVCpu The cross context virtual CPU structure.
2089	*/
2090	static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
2091	{
2092	/*
2093	* The run loop.
2094	*
2095	* Current approach to state updating to use the sledgehammer and sync
2096	* everything every time. This will be optimized later.
2097	*/
2098
2099	/* Update the vTimer offset after resuming if instructed. */
2100	if (pVCpu->nem.s.fVTimerOffUpdate)
2101	{
2102	hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2103	if (hrc != HV_SUCCESS)
2104	return nemR3DarwinHvSts2Rc(hrc);
2105
2106	pVCpu->nem.s.fVTimerOffUpdate = false;
2107
2108	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2109	if (hrc == HV_SUCCESS)
2110	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2111	if (hrc != HV_SUCCESS)
2112	return nemR3DarwinHvSts2Rc(hrc);
2113	}
2114
2115	/*
2116	* Poll timers and run for a bit.
2117	*/
2118	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2119	* the whole polling job when timers have changed... */
2120	uint64_t offDeltaIgnored;
2121	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2122	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2123	for (unsigned iLoop = 0;; iLoop++)
2124	{
2125	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
2126	if (rcStrict != VINF_SUCCESS)
2127	break;
2128
2129	hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2130	if (hrc == HV_SUCCESS)
2131	{
2132	/*
2133	* Deal with the message.
2134	*/
2135	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2136	if (rcStrict == VINF_SUCCESS)
2137	{ /* hopefully likely */ }
2138	else
2139	{
2140	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2141	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2142	break;
2143	}
2144	}
2145	else
2146	{
2147	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2148	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2149	}
2150	} /* the run loop */
2151
2152	return rcStrict;
2153	}
2154
2155
2156	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2157	{
2158	#ifdef LOG_ENABLED
2159	if (LogIs3Enabled())
2160	nemR3DarwinLogState(pVM, pVCpu);
2161	#endif
2162
2163	AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
2164
2165	if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
2166	{
2167	/*
2168	* Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
2169	* Need to do it here and not during the init because loading a saved state might change the ID registers from what
2170	* done in the call to CPUMR3PopulateFeaturesByIdRegisters().
2171	*/
2172	static const struct
2173	{
2174	const char *pszIdReg;
2175	hv_sys_reg_t enmHvReg;
2176	uint32_t offIdStruct;
2177	} s_aSysIdRegs[] =
2178	{
2179	#define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMIDREGS, a_CpumIdReg) }
2180	ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
2181	ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
2182	ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
2183	ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
2184	ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
2185	ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
2186	ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
2187	ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
2188	ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
2189	#undef ID_SYS_REG_CREATE
2190	};
2191
2192	PCCPUMIDREGS pIdRegsGst = NULL;
2193	int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
2194	AssertRCReturn(rc, rc);
2195
2196	for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
2197	{
2198	uint64_t pu64 = (uint64_t )((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
2199	hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
2200	if (hrc != HV_SUCCESS)
2201	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2202	"Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2203	}
2204
2205	pVCpu->nem.s.fIdRegsSynced = true;
2206	}
2207
2208	/*
2209	* Try switch to NEM runloop state.
2210	*/
2211	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2212	{ /* likely */ }
2213	else
2214	{
2215	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2216	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2217	return VINF_SUCCESS;
2218	}
2219
2220	VBOXSTRICTRC rcStrict;
2221	#if 0
2222	if ( !pVCpu->nem.s.fUseDebugLoop
2223	&& !nemR3DarwinAnyExpensiveProbesEnabled()
2224	&& !DBGFIsStepping(pVCpu)
2225	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledInt3Breakpoints)
2226	#endif
2227	rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
2228	#if 0
2229	else
2230	rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
2231	#endif
2232
2233	if (rcStrict == VINF_EM_RAW_TO_R3)
2234	rcStrict = VINF_SUCCESS;
2235
2236	/*
2237	* Convert any pending HM events back to TRPM due to premature exits.
2238	*
2239	* This is because execution may continue from IEM and we would need to inject
2240	* the event from there (hence place it back in TRPM).
2241	*/
2242	if (pVCpu->nem.s.fEventPending)
2243	{
2244	/** @todo */
2245	}
2246
2247
2248	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2249	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2250
2251	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2252	{
2253	/* Try anticipate what we might need. */
2254	uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2255	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2256	\|\| RT_FAILURE(rcStrict))
2257	fImport = CPUMCTX_EXTRN_ALL;
2258	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ
2259	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2260	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2261
2262	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2263	{
2264	/* Only import what is external currently. */
2265	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2266	if (RT_SUCCESS(rc2))
2267	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2268	else if (RT_SUCCESS(rcStrict))
2269	rcStrict = rc2;
2270	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2271	pVCpu->cpum.GstCtx.fExtrn = 0;
2272	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2273	}
2274	else
2275	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2276	}
2277	else
2278	{
2279	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2280	pVCpu->cpum.GstCtx.fExtrn = 0;
2281	}
2282
2283	return rcStrict;
2284	}
2285
2286
2287	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2288	{
2289	RT_NOREF(pVM, pVCpu);
2290	return true; /** @todo Are there any cases where we have to emulate? */
2291	}
2292
2293
2294	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2295	{
2296	VMCPU_ASSERT_EMT(pVCpu);
2297	bool fOld = pVCpu->nem.s.fSingleInstruction;
2298	pVCpu->nem.s.fSingleInstruction = fEnable;
2299	pVCpu->nem.s.fUseDebugLoop = fEnable \|\| pVM->nem.s.fUseDebugLoop;
2300	return fOld;
2301	}
2302
2303
2304	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2305	{
2306	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2307
2308	RT_NOREF(pVM, fFlags);
2309
2310	hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
2311	if (hrc != HV_SUCCESS)
2312	LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
2313	}
2314
2315
2316	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
2317	{
2318	RT_NOREF(pVM, fUseDebugLoop);
2319	//AssertReleaseFailed();
2320	return false;
2321	}
2322
2323
2324	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
2325	{
2326	RT_NOREF(pVM, pVCpu, fUseDebugLoop);
2327	return fUseDebugLoop;
2328	}
2329
2330
2331	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2332	uint8_t pu2State, uint32_t puNemRange)
2333	{
2334	RT_NOREF(pVM, puNemRange);
2335
2336	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2337	#if defined(VBOX_WITH_PGM_NEM_MODE)
2338	if (pvR3)
2339	{
2340	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2341	if (RT_FAILURE(rc))
2342	{
2343	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2344	return VERR_NEM_MAP_PAGES_FAILED;
2345	}
2346	}
2347	return VINF_SUCCESS;
2348	#else
2349	RT_NOREF(pVM, GCPhys, cb, pvR3);
2350	return VERR_NEM_MAP_PAGES_FAILED;
2351	#endif
2352	}
2353
2354
2355	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2356	{
2357	RT_NOREF(pVM);
2358	return true;
2359	}
2360
2361
2362	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2363	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
2364	{
2365	RT_NOREF(pvRam);
2366
2367	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2368	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2369
2370	#if defined(VBOX_WITH_PGM_NEM_MODE)
2371	/*
2372	* Unmap the RAM we're replacing.
2373	*/
2374	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2375	{
2376	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2377	if (RT_SUCCESS(rc))
2378	{ /* likely */ }
2379	else if (pvMmio2)
2380	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2381	GCPhys, cb, fFlags, rc));
2382	else
2383	{
2384	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2385	GCPhys, cb, fFlags, rc));
2386	return VERR_NEM_UNMAP_PAGES_FAILED;
2387	}
2388	}
2389
2390	/*
2391	* Map MMIO2 if any.
2392	*/
2393	if (pvMmio2)
2394	{
2395	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2396
2397	/* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
2398	uint32_t fProt = NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE;
2399	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2400	{
2401	/* Find a slot for dirty tracking. */
2402	PNEMHVMMIO2REGION pMmio2Region = NULL;
2403	uint32_t idSlot;
2404	for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
2405	{
2406	if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
2407	&& pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
2408	{
2409	pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
2410	break;
2411	}
2412	}
2413
2414	if (!pMmio2Region)
2415	{
2416	LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
2417	return VERR_NEM_MAP_PAGES_FAILED;
2418	}
2419
2420	pMmio2Region->GCPhysStart = GCPhys;
2421	pMmio2Region->GCPhysLast = GCPhys + cb - 1;
2422	pMmio2Region->fDirty = false;
2423	*puNemRange = idSlot;
2424	}
2425	else
2426	fProt \|= NEM_PAGE_PROT_WRITE;
2427
2428	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
2429	if (RT_FAILURE(rc))
2430	{
2431	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2432	GCPhys, cb, fFlags, pvMmio2, rc));
2433	return VERR_NEM_MAP_PAGES_FAILED;
2434	}
2435	}
2436	else
2437	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2438
2439	#else
2440	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2441	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2442	#endif
2443	return VINF_SUCCESS;
2444	}
2445
2446
2447	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2448	void pvRam, void pvMmio2, uint32_t *puNemRange)
2449	{
2450	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2451	return VINF_SUCCESS;
2452	}
2453
2454
2455	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2456	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
2457	{
2458	RT_NOREF(pVM, puNemRange);
2459
2460	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
2461	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
2462
2463	int rc = VINF_SUCCESS;
2464	#if defined(VBOX_WITH_PGM_NEM_MODE)
2465	/*
2466	* Unmap the MMIO2 pages.
2467	*/
2468	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2469	* we may have more stuff to unmap even in case of pure MMIO... */
2470	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2471	{
2472	rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2473	if (RT_FAILURE(rc))
2474	{
2475	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2476	GCPhys, cb, fFlags, rc));
2477	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2478	}
2479
2480	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2481	{
2482	/* Reset tracking structure. */
2483	uint32_t idSlot = *puNemRange;
2484	*puNemRange = UINT32_MAX;
2485
2486	Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2487	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
2488	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
2489	pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
2490	}
2491	}
2492
2493	/* Ensure the page is masked as unmapped if relevant. */
2494	Assert(!pu2State \|\| *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
2495
2496	/*
2497	* Restore the RAM we replaced.
2498	*/
2499	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2500	{
2501	AssertPtr(pvRam);
2502	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2503	if (RT_SUCCESS(rc))
2504	{ /* likely */ }
2505	else
2506	{
2507	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2508	rc = VERR_NEM_MAP_PAGES_FAILED;
2509	}
2510	}
2511
2512	RT_NOREF(pvMmio2);
2513	#else
2514	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2515	if (pu2State)
2516	*pu2State = UINT8_MAX;
2517	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2518	#endif
2519	return rc;
2520	}
2521
2522
2523	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2524	void *pvBitmap, size_t cbBitmap)
2525	{
2526	LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
2527	Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2528
2529	/* Keep it simple for now and mark everything as dirty if it is. */
2530	int rc = VINF_SUCCESS;
2531	if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
2532	{
2533	ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
2534
2535	pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
2536	/* Restore as RX only. */
2537	uint8_t u2State;
2538	rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, &u2State);
2539	}
2540	else
2541	ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
2542
2543	return rc;
2544	}
2545
2546
2547	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2548	uint8_t pu2State, uint32_t puNemRange)
2549	{
2550	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2551
2552	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2553	*pu2State = UINT8_MAX;
2554	*puNemRange = 0;
2555	return VINF_SUCCESS;
2556	}
2557
2558
2559	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2560	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
2561	{
2562	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
2563	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
2564	*pu2State = UINT8_MAX;
2565
2566	#if defined(VBOX_WITH_PGM_NEM_MODE)
2567	/*
2568	* (Re-)map readonly.
2569	*/
2570	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2571
2572	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2573	AssertRC(rc);
2574
2575	rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, pu2State);
2576	if (RT_FAILURE(rc))
2577	{
2578	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2579	GCPhys, cb, pvPages, fFlags, rc));
2580	return VERR_NEM_MAP_PAGES_FAILED;
2581	}
2582	RT_NOREF(fFlags, puNemRange);
2583	return VINF_SUCCESS;
2584	#else
2585	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2586	return VERR_NEM_MAP_PAGES_FAILED;
2587	#endif
2588	}
2589
2590
2591	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2592	RTR3PTR pvMemR3, uint8_t *pu2State)
2593	{
2594	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2595	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2596
2597	*pu2State = UINT8_MAX;
2598	#if defined(VBOX_WITH_PGM_NEM_MODE)
2599	if (pvMemR3)
2600	{
2601	/* Unregister what was there before. */
2602	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2603	AssertRC(rc);
2604
2605	rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2606	AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
2607	pvMemR3, GCPhys, cb, rc));
2608	}
2609	RT_NOREF(enmKind);
2610	#else
2611	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
2612	AssertFailed();
2613	#endif
2614	}
2615
2616
2617	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2618	{
2619	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2620	RT_NOREF(pVCpu, fEnabled);
2621	}
2622
2623
2624	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2625	{
2626	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2627	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2628	}
2629
2630
2631	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2632	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2633	{
2634	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2635	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2636	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2637	}
2638
2639
2640	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2641	PGMPAGETYPE enmType, uint8_t *pu2State)
2642	{
2643	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2644	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2645	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
2646
2647	AssertFailed();
2648	return VINF_SUCCESS;
2649	}
2650
2651
2652	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
2653	PGMPAGETYPE enmType, uint8_t *pu2State)
2654	{
2655	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2656	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2657	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
2658	}
2659
2660
2661	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2662	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2663	{
2664	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2665	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2666	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
2667
2668	AssertFailed();
2669	}
2670
2671
2672	/**
2673	* Interface for importing state on demand (used by IEM).
2674	*
2675	* @returns VBox status code.
2676	* @param pVCpu The cross context CPU structure.
2677	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2678	*/
2679	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2680	{
2681	LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
2682	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
2683
2684	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
2685	}
2686
2687
2688	/**
2689	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
2690	*
2691	* @returns VBox status code.
2692	* @param pVCpu The cross context CPU structure.
2693	* @param pcTicks Where to return the CPU tick count.
2694	* @param puAux Where to return the TSC_AUX register value.
2695	*/
2696	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
2697	{
2698	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
2699	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
2700
2701	if (puAux)
2702	*puAux = 0;
2703	pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; / This is the host timer minus the offset. */
2704	return VINF_SUCCESS;
2705	}
2706
2707
2708	/**
2709	* Resumes CPU clock (TSC) on all virtual CPUs.
2710	*
2711	* This is called by TM when the VM is started, restored, resumed or similar.
2712	*
2713	* @returns VBox status code.
2714	* @param pVM The cross context VM structure.
2715	* @param pVCpu The cross context CPU structure of the calling EMT.
2716	* @param uPausedTscValue The TSC value at the time of pausing.
2717	*/
2718	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
2719	{
2720	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
2721	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
2722	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
2723
2724	/*
2725	* Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
2726	* the new offset to let the guest not notice the pause.
2727	*/
2728	uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
2729	Assert(u64TscNew >= uPausedTscValue);
2730	LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
2731	pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
2732	pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
2733
2734	pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
2735
2736	/*
2737	* Set the flag to update the vTimer offset when the vCPU resumes for the first time
2738	* (needs to be done on the actual EMT).
2739	*/
2740	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2741	{
2742	PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
2743	pVCpuDst->nem.s.fVTimerOffUpdate = true;
2744	}
2745
2746	return VINF_SUCCESS;
2747	}
2748
2749
2750	/**
2751	* Returns features supported by the NEM backend.
2752	*
2753	* @returns Flags of features supported by the native NEM backend.
2754	* @param pVM The cross context VM structure.
2755	*/
2756	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
2757	{
2758	RT_NOREF(pVM);
2759	/*
2760	* Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
2761	* and unrestricted guest execution support so we can safely return these flags here always.
2762	*/
2763	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC \| NEM_FEAT_F_XSAVE_XRSTOR;
2764	}
2765
2766
2767	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
2768	*
2769	* @todo Add notes as the implementation progresses...
2770	*/
2771

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 105695

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