NEMR3Native-darwin-armv8.cpp@ 106743

Last change on this file since 106743 was 106743, checked in by vboxsync, 3 months ago
VMM/ARM: Make the control flow graph generator work with ARMv8 A64 to some extent, bugref:10393
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1	/* $Id: NEMR3Native-darwin-armv8.cpp 106743 2024-10-28 11:43:04Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
12	*
13	* This file is part of VirtualBox base platform packages, as
14	* available from https://www.virtualbox.org.
15	*
16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License
18	* as published by the Free Software Foundation, in version 3 of the
19	* License.
20	*
21	* This program is distributed in the hope that it will be useful, but
22	* WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24	* General Public License for more details.
25	*
26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, see <https://www.gnu.org/licenses>.
28	*
29	* SPDX-License-Identifier: GPL-3.0-only
30	*/
31
32
33	/*********************************************************************************************************************************
34	* Header Files *
35	*********************************************************************************************************************************/
36	#define LOG_GROUP LOG_GROUP_NEM
37	#define VMCPU_INCL_CPUM_GST_CTX
38	#include <VBox/vmm/nem.h>
39	#include <VBox/vmm/iem.h>
40	#include <VBox/vmm/em.h>
41	#include <VBox/vmm/gic.h>
42	#include <VBox/vmm/pdm.h>
43	#include <VBox/vmm/dbgftrace.h>
44	#include <VBox/vmm/gcm.h>
45	#include "NEMInternal.h"
46	#include <VBox/vmm/vmcc.h>
47	#include <VBox/vmm/vmm.h>
48	#include <VBox/dis.h>
49	#include <VBox/gic.h>
50	#include "dtrace/VBoxVMM.h"
51
52	#include <iprt/armv8.h>
53	#include <iprt/asm.h>
54	#include <iprt/asm-arm.h>
55	#include <iprt/asm-math.h>
56	#include <iprt/ldr.h>
57	#include <iprt/mem.h>
58	#include <iprt/path.h>
59	#include <iprt/string.h>
60	#include <iprt/system.h>
61	#include <iprt/utf16.h>
62
63	#include <iprt/formats/arm-psci.h>
64
65	#include <mach/mach_time.h>
66	#include <mach/kern_return.h>
67
68	#include <Hypervisor/Hypervisor.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74
75
76	/*********************************************************************************************************************************
77	* Structures and Typedefs *
78	*********************************************************************************************************************************/
79
80	#if MAC_OS_X_VERSION_MIN_REQUIRED < 150000
81
82	/* Since 15.0+ */
83	typedef enum hv_gic_distributor_reg_t : uint16_t
84	{
85	HV_GIC_DISTRIBUTOR_REG_GICD_CTLR,
86	HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0
87	/** @todo */
88	} hv_gic_distributor_reg_t;
89
90
91	typedef enum hv_gic_icc_reg_t : uint16_t
92	{
93	HV_GIC_ICC_REG_AP0R0_EL1
94	/** @todo */
95	} hv_gic_icc_reg_t;
96
97
98	typedef enum hv_gic_ich_reg_t : uint16_t
99	{
100	HV_GIC_ICH_REG_AP0R0_EL2
101	/** @todo */
102	} hv_gic_ich_reg_t;
103
104
105	typedef enum hv_gic_icv_reg_t : uint16_t
106	{
107	HV_GIC_ICV_REG_AP0R0_EL1
108	/** @todo */
109	} hv_gic_icv_reg_t;
110
111
112	typedef enum hv_gic_msi_reg_t : uint16_t
113	{
114	HV_GIC_REG_GICM_SET_SPI_NSR
115	/** @todo */
116	} hv_gic_msi_reg_t;
117
118
119	typedef enum hv_gic_redistributor_reg_t : uint16_t
120	{
121	HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0
122	/** @todo */
123	} hv_gic_redistributor_reg_t;
124
125
126	typedef enum hv_gic_intid_t : uint16_t
127	{
128	HV_GIC_INT_EL1_PHYSICAL_TIMER = 23,
129	HV_GIC_INT_EL1_VIRTUAL_TIMER = 25,
130	HV_GIC_INT_EL2_PHYSICAL_TIMER = 26,
131	HV_GIC_INT_MAINTENANCE = 27,
132	HV_GIC_INT_PERFORMANCE_MONITOR = 30
133	} hv_gic_intid_t;
134
135	#endif
136
137	typedef hv_vm_config_t FN_HV_VM_CONFIG_CREATE(void);
138	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_SUPPORTED(bool *el2_supported);
139	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_ENABLED(hv_vm_config_t config, bool *el2_enabled);
140	typedef hv_return_t FN_HV_VM_CONFIG_SET_EL2_ENABLED(hv_vm_config_t config, bool el2_enabled);
141
142	typedef struct hv_gic_config_s *hv_gic_config_t;
143	typedef hv_return_t FN_HV_GIC_CREATE(hv_gic_config_t gic_config);
144	typedef hv_return_t FN_HV_GIC_RESET(void);
145	typedef hv_gic_config_t FN_HV_GIC_CONFIG_CREATE(void);
146	typedef hv_return_t FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t distributor_base_address);
147	typedef hv_return_t FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t redistributor_base_address);
148	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE(hv_gic_config_t config, hv_ipa_t msi_region_base_address);
149	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE(hv_gic_config_t config, uint32_t msi_intid_base, uint32_t msi_intid_count);
150
151	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE(hv_vcpu_t vcpu, hv_ipa_t *redistributor_base_address);
152	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE(size_t *redistributor_region_size);
153	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_SIZE(size_t *redistributor_size);
154	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_SIZE(size_t *distributor_size);
155	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT(size_t *distributor_base_alignment);
156	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT(size_t *redistributor_base_alignment);
157	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT(size_t *msi_region_base_alignment);
158	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_SIZE(size_t *msi_region_size);
159	typedef hv_return_t FN_HV_GIC_GET_SPI_INTERRUPT_RANGE(uint32_t spi_intid_base, uint32_t spi_intid_count);
160
161	typedef struct hv_gic_state_s *hv_gic_state_t;
162	typedef hv_gic_state_t FN_HV_GIC_STATE_CREATE(void);
163	typedef hv_return_t FN_HV_GIC_SET_STATE(const void *gic_state_data, size_t gic_state_size);
164	typedef hv_return_t FN_HV_GIC_STATE_GET_SIZE(hv_gic_state_t state, size_t *gic_state_size);
165	typedef hv_return_t FN_HV_GIC_STATE_GET_DATA(hv_gic_state_t state, void *gic_state_data);
166
167	typedef hv_return_t FN_HV_GIC_SEND_MSI(hv_ipa_t address, uint32_t intid);
168	typedef hv_return_t FN_HV_GIC_SET_SPI(uint32_t intid, bool level);
169
170	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t *value);
171	typedef hv_return_t FN_HV_GIC_GET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t *value);
172	typedef hv_return_t FN_HV_GIC_GET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t *value);
173	typedef hv_return_t FN_HV_GIC_GET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t *value);
174	typedef hv_return_t FN_HV_GIC_GET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t *value);
175	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t *value);
176
177	typedef hv_return_t FN_HV_GIC_SET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t value);
178	typedef hv_return_t FN_HV_GIC_SET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t value);
179	typedef hv_return_t FN_HV_GIC_SET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t value);
180	typedef hv_return_t FN_HV_GIC_SET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t value);
181	typedef hv_return_t FN_HV_GIC_SET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t value);
182	typedef hv_return_t FN_HV_GIC_SET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t value);
183
184	typedef hv_return_t FN_HV_GIC_GET_INTID(hv_gic_intid_t interrupt, uint32_t *intid);
185
186
187	/*********************************************************************************************************************************
188	* Global Variables *
189	*********************************************************************************************************************************/
190	/** @name Optional APIs imported from Hypervisor.framework.
191	* @{ */
192	static FN_HV_VM_CONFIG_CREATE g_pfnHvVmConfigCreate = NULL; / Since 13.0 */
193	static FN_HV_VM_CONFIG_GET_EL2_SUPPORTED g_pfnHvVmConfigGetEl2Supported = NULL; / Since 15.0 */
194	static FN_HV_VM_CONFIG_GET_EL2_ENABLED g_pfnHvVmConfigGetEl2Enabled = NULL; / Since 15.0 */
195	static FN_HV_VM_CONFIG_SET_EL2_ENABLED g_pfnHvVmConfigSetEl2Enabled = NULL; / Since 15.0 */
196
197	static FN_HV_GIC_CREATE g_pfnHvGicCreate = NULL; / Since 15.0 */
198	static FN_HV_GIC_RESET g_pfnHvGicReset = NULL; / Since 15.0 */
199	static FN_HV_GIC_CONFIG_CREATE g_pfnHvGicConfigCreate = NULL; / Since 15.0 */
200	static FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE g_pfnHvGicConfigSetDistributorBase = NULL; / Since 15.0 */
201	static FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE g_pfnHvGicConfigSetRedistributorBase = NULL; / Since 15.0 */
202	static FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE g_pfnHvGicConfigSetMsiRegionBase = NULL; / Since 15.0 */
203	static FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE g_pfnHvGicConfigSetMsiInterruptRange = NULL; / Since 15.0 */
204	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE g_pfnHvGicGetRedistributorBase = NULL; / Since 15.0 */
205	static FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE g_pfnHvGicGetRedistributorRegionSize = NULL; / Since 15.0 */
206	static FN_HV_GIC_GET_REDISTRIBUTOR_SIZE g_pfnHvGicGetRedistributorSize = NULL; / Since 15.0 */
207	static FN_HV_GIC_GET_DISTRIBUTOR_SIZE g_pfnHvGicGetDistributorSize = NULL; / Since 15.0 */
208	static FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetDistributorBaseAlignment = NULL; / Since 15.0 */
209	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetRedistributorBaseAlignment = NULL; / Since 15.0 */
210	static FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT g_pfnHvGicGetMsiRegionBaseAlignment = NULL; / Since 15.0 */
211	static FN_HV_GIC_GET_MSI_REGION_SIZE g_pfnHvGicGetMsiRegionSize = NULL; / Since 15.0 */
212	static FN_HV_GIC_GET_SPI_INTERRUPT_RANGE g_pfnHvGicGetSpiInterruptRange = NULL; / Since 15.0 */
213	static FN_HV_GIC_STATE_CREATE g_pfnHvGicStateCreate = NULL; / Since 15.0 */
214	static FN_HV_GIC_SET_STATE g_pfnHvGicSetState = NULL; / Since 15.0 */
215	static FN_HV_GIC_STATE_GET_SIZE g_pfnHvGicStateGetSize = NULL; / Since 15.0 */
216	static FN_HV_GIC_STATE_GET_DATA g_pfnHvGicStateGetData = NULL; / Since 15.0 */
217	static FN_HV_GIC_SEND_MSI g_pfnHvGicSendMsi = NULL; / Since 15.0 */
218	static FN_HV_GIC_SET_SPI g_pfnHvGicSetSpi = NULL; / Since 15.0 */
219	static FN_HV_GIC_GET_DISTRIBUTOR_REG g_pfnHvGicGetDistributorReg = NULL; / Since 15.0 */
220	static FN_HV_GIC_GET_MSI_REG g_pfnHvGicGetMsiReg = NULL; / Since 15.0 */
221	static FN_HV_GIC_GET_ICC_REG g_pfnHvGicGetIccReg = NULL; / Since 15.0 */
222	static FN_HV_GIC_GET_ICH_REG g_pfnHvGicGetIchReg = NULL; / Since 15.0 */
223	static FN_HV_GIC_GET_ICV_REG g_pfnHvGicGetIcvReg = NULL; / Since 15.0 */
224	static FN_HV_GIC_GET_REDISTRIBUTOR_REG g_pfnHvGicGetRedistributorReg = NULL; / Since 15.0 */
225	static FN_HV_GIC_SET_DISTRIBUTOR_REG g_pfnHvGicSetDistributorReg = NULL; / Since 15.0 */
226	static FN_HV_GIC_SET_MSI_REG g_pfnHvGicSetMsiReg = NULL; / Since 15.0 */
227	static FN_HV_GIC_SET_ICC_REG g_pfnHvGicSetIccReg = NULL; / Since 15.0 */
228	static FN_HV_GIC_SET_ICH_REG g_pfnHvGicSetIchReg = NULL; / Since 15.0 */
229	static FN_HV_GIC_SET_ICV_REG g_pfnHvGicSetIcvReg = NULL; / Since 15.0 */
230	static FN_HV_GIC_SET_REDISTRIBUTOR_REG g_pfnHvGicSetRedistributorReg = NULL; / Since 15.0 */
231	static FN_HV_GIC_GET_INTID g_pfnHvGicGetIntid = NULL; / Since 15.0 */
232	/** @} */
233
234
235	/**
236	* Import instructions.
237	*/
238	static const struct
239	{
240	void ppfn; /< The function pointer variable. */
241	const char pszName; /< The function name. /
242	} g_aImports[] =
243	{
244	#define NEM_DARWIN_IMPORT(a_Pfn, a_Name) { (void **)&(a_Pfn), #a_Name }
245	NEM_DARWIN_IMPORT(g_pfnHvVmConfigCreate, hv_vm_config_create),
246	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Supported, hv_vm_config_get_el2_supported),
247	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Enabled, hv_vm_config_get_el2_enabled),
248	NEM_DARWIN_IMPORT(g_pfnHvVmConfigSetEl2Enabled, hv_vm_config_set_el2_enabled),
249
250	NEM_DARWIN_IMPORT(g_pfnHvGicCreate, hv_gic_create),
251	NEM_DARWIN_IMPORT(g_pfnHvGicReset, hv_gic_reset),
252	NEM_DARWIN_IMPORT(g_pfnHvGicConfigCreate, hv_gic_config_create),
253	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetDistributorBase, hv_gic_config_set_distributor_base),
254	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetRedistributorBase, hv_gic_config_set_redistributor_base),
255	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiRegionBase, hv_gic_config_set_msi_region_base),
256	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiInterruptRange, hv_gic_config_set_msi_interrupt_range),
257	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBase, hv_gic_get_redistributor_base),
258	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorRegionSize, hv_gic_get_redistributor_region_size),
259	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorSize, hv_gic_get_redistributor_size),
260	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorSize, hv_gic_get_distributor_size),
261	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorBaseAlignment, hv_gic_get_distributor_base_alignment),
262	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBaseAlignment, hv_gic_get_redistributor_base_alignment),
263	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionBaseAlignment, hv_gic_get_msi_region_base_alignment),
264	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionSize, hv_gic_get_msi_region_size),
265	NEM_DARWIN_IMPORT(g_pfnHvGicGetSpiInterruptRange, hv_gic_get_spi_interrupt_range),
266	NEM_DARWIN_IMPORT(g_pfnHvGicStateCreate, hv_gic_state_create),
267	NEM_DARWIN_IMPORT(g_pfnHvGicSetState, hv_gic_set_state),
268	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetSize, hv_gic_state_get_size),
269	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetData, hv_gic_state_get_data),
270	NEM_DARWIN_IMPORT(g_pfnHvGicSendMsi, hv_gic_send_msi),
271	NEM_DARWIN_IMPORT(g_pfnHvGicSetSpi, hv_gic_set_spi),
272	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorReg, hv_gic_get_distributor_reg),
273	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiReg, hv_gic_get_msi_reg),
274	NEM_DARWIN_IMPORT(g_pfnHvGicGetIccReg, hv_gic_get_icc_reg),
275	NEM_DARWIN_IMPORT(g_pfnHvGicGetIchReg, hv_gic_get_ich_reg),
276	NEM_DARWIN_IMPORT(g_pfnHvGicGetIcvReg, hv_gic_get_icv_reg),
277	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorReg, hv_gic_get_redistributor_reg),
278	NEM_DARWIN_IMPORT(g_pfnHvGicSetDistributorReg, hv_gic_set_distributor_reg),
279	NEM_DARWIN_IMPORT(g_pfnHvGicSetMsiReg, hv_gic_set_msi_reg),
280	NEM_DARWIN_IMPORT(g_pfnHvGicSetIccReg, hv_gic_set_icc_reg),
281	NEM_DARWIN_IMPORT(g_pfnHvGicSetIchReg, hv_gic_set_ich_reg),
282	NEM_DARWIN_IMPORT(g_pfnHvGicSetIcvReg, hv_gic_set_icv_reg),
283	NEM_DARWIN_IMPORT(g_pfnHvGicSetRedistributorReg, hv_gic_set_redistributor_reg),
284	NEM_DARWIN_IMPORT(g_pfnHvGicGetIntid, hv_gic_get_intid)
285	#undef NEM_DARWIN_IMPORT
286	};
287
288
289	/*
290	* Let the preprocessor alias the APIs to import variables for better autocompletion.
291	*/
292	#ifndef IN_SLICKEDIT
293	# define hv_vm_config_create g_pfnHvVmConfigCreate
294	# define hv_vm_config_get_el2_supported g_pfnHvVmConfigGetEl2Supported
295	# define hv_vm_config_get_el2_enabled g_pfnHvVmConfigGetEl2Enabled
296	# define hv_vm_config_set_el2_enabled g_pfnHvVmConfigSetEl2Enabled
297
298	# define hv_gic_create g_pfnHvGicCreate
299	# define hv_gic_reset g_pfnHvGicReset
300	# define hv_gic_config_create g_pfnHvGicConfigCreate
301	# define hv_gic_config_set_distributor_base g_pfnHvGicConfigSetDistributorBase
302	# define hv_gic_config_set_redistributor_base g_pfnHvGicConfigSetRedistributorBase
303	# define hv_gic_config_set_msi_region_base g_pfnHvGicConfigSetMsiRegionBase
304	# define hv_gic_config_set_msi_interrupt_range g_pfnHvGicConfigSetMsiInterruptRange
305	# define hv_gic_get_redistributor_base g_pfnHvGicGetRedistributorBase
306	# define hv_gic_get_redistributor_region_size g_pfnHvGicGetRedistributorRegionSize
307	# define hv_gic_get_redistributor_size g_pfnHvGicGetRedistributorSize
308	# define hv_gic_get_distributor_size g_pfnHvGicGetDistributorSize
309	# define hv_gic_get_distributor_base_alignment g_pfnHvGicGetDistributorBaseAlignment
310	# define hv_gic_get_redistributor_base_alignment g_pfnHvGicGetRedistributorBaseAlignment
311	# define hv_gic_get_msi_region_base_alignment g_pfnHvGicGetMsiRegionBaseAlignment
312	# define hv_gic_get_msi_region_size g_pfnHvGicGetMsiRegionSize
313	# define hv_gic_get_spi_interrupt_range g_pfnHvGicGetSpiInterruptRange
314	# define hv_gic_state_create g_pfnHvGicStateCreate
315	# define hv_gic_set_state g_pfnHvGicSetState
316	# define hv_gic_state_get_size g_pfnHvGicStateGetSize
317	# define hv_gic_state_get_data g_pfnHvGicStateGetData
318	# define hv_gic_send_msi g_pfnHvGicSendMsi
319	# define hv_gic_set_spi g_pfnHvGicSetSpi
320	# define hv_gic_get_distributor_reg g_pfnHvGicGetDistributorReg
321	# define hv_gic_get_msi_reg g_pfnHvGicGetMsiReg
322	# define hv_gic_get_icc_reg g_pfnHvGicGetIccReg
323	# define hv_gic_get_ich_reg g_pfnHvGicGetIchReg
324	# define hv_gic_get_icv_reg g_pfnHvGicGetIcvReg
325	# define hv_gic_get_redistributor_reg g_pfnHvGicGetRedistributorReg
326	# define hv_gic_set_distributor_reg g_pfnHvGicSetDistributorReg
327	# define hv_gic_set_msi_reg g_pfnHvGicSetMsiReg
328	# define hv_gic_set_icc_reg g_pfnHvGicSetIccReg
329	# define hv_gic_set_ich_reg g_pfnHvGicSetIchReg
330	# define hv_gic_set_icv_reg g_pfnHvGicSetIcvReg
331	# define hv_gic_set_redistributor_reg g_pfnHvGicSetRedistributorReg
332	# define hv_gic_get_intid g_pfnHvGicGetIntid
333	#endif
334
335
336	/** The general registers. */
337	static const struct
338	{
339	hv_reg_t enmHvReg;
340	uint32_t fCpumExtrn;
341	uint32_t offCpumCtx;
342	} s_aCpumRegs[] =
343	{
344	#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
345	#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
346	CPUM_GREG_EMIT_X0_X3(0),
347	CPUM_GREG_EMIT_X0_X3(1),
348	CPUM_GREG_EMIT_X0_X3(2),
349	CPUM_GREG_EMIT_X0_X3(3),
350	CPUM_GREG_EMIT_X4_X28(4),
351	CPUM_GREG_EMIT_X4_X28(5),
352	CPUM_GREG_EMIT_X4_X28(6),
353	CPUM_GREG_EMIT_X4_X28(7),
354	CPUM_GREG_EMIT_X4_X28(8),
355	CPUM_GREG_EMIT_X4_X28(9),
356	CPUM_GREG_EMIT_X4_X28(10),
357	CPUM_GREG_EMIT_X4_X28(11),
358	CPUM_GREG_EMIT_X4_X28(12),
359	CPUM_GREG_EMIT_X4_X28(13),
360	CPUM_GREG_EMIT_X4_X28(14),
361	CPUM_GREG_EMIT_X4_X28(15),
362	CPUM_GREG_EMIT_X4_X28(16),
363	CPUM_GREG_EMIT_X4_X28(17),
364	CPUM_GREG_EMIT_X4_X28(18),
365	CPUM_GREG_EMIT_X4_X28(19),
366	CPUM_GREG_EMIT_X4_X28(20),
367	CPUM_GREG_EMIT_X4_X28(21),
368	CPUM_GREG_EMIT_X4_X28(22),
369	CPUM_GREG_EMIT_X4_X28(23),
370	CPUM_GREG_EMIT_X4_X28(24),
371	CPUM_GREG_EMIT_X4_X28(25),
372	CPUM_GREG_EMIT_X4_X28(26),
373	CPUM_GREG_EMIT_X4_X28(27),
374	CPUM_GREG_EMIT_X4_X28(28),
375	{ HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
376	{ HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
377	{ HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
378	{ HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
379	{ HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
380	#undef CPUM_GREG_EMIT_X0_X3
381	#undef CPUM_GREG_EMIT_X4_X28
382	};
383	/** SIMD/FP registers. */
384	static const struct
385	{
386	hv_simd_fp_reg_t enmHvReg;
387	uint32_t offCpumCtx;
388	} s_aCpumFpRegs[] =
389	{
390	#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
391	CPUM_VREG_EMIT(0),
392	CPUM_VREG_EMIT(1),
393	CPUM_VREG_EMIT(2),
394	CPUM_VREG_EMIT(3),
395	CPUM_VREG_EMIT(4),
396	CPUM_VREG_EMIT(5),
397	CPUM_VREG_EMIT(6),
398	CPUM_VREG_EMIT(7),
399	CPUM_VREG_EMIT(8),
400	CPUM_VREG_EMIT(9),
401	CPUM_VREG_EMIT(10),
402	CPUM_VREG_EMIT(11),
403	CPUM_VREG_EMIT(12),
404	CPUM_VREG_EMIT(13),
405	CPUM_VREG_EMIT(14),
406	CPUM_VREG_EMIT(15),
407	CPUM_VREG_EMIT(16),
408	CPUM_VREG_EMIT(17),
409	CPUM_VREG_EMIT(18),
410	CPUM_VREG_EMIT(19),
411	CPUM_VREG_EMIT(20),
412	CPUM_VREG_EMIT(21),
413	CPUM_VREG_EMIT(22),
414	CPUM_VREG_EMIT(23),
415	CPUM_VREG_EMIT(24),
416	CPUM_VREG_EMIT(25),
417	CPUM_VREG_EMIT(26),
418	CPUM_VREG_EMIT(27),
419	CPUM_VREG_EMIT(28),
420	CPUM_VREG_EMIT(29),
421	CPUM_VREG_EMIT(30),
422	CPUM_VREG_EMIT(31)
423	#undef CPUM_VREG_EMIT
424	};
425	/** Debug system registers. */
426	static const struct
427	{
428	hv_sys_reg_t enmHvReg;
429	uint32_t offCpumCtx;
430	} s_aCpumDbgRegs[] =
431	{
432	#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
433	{ HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
434	{ HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
435	/* Breakpoint registers. */
436	CPUM_DBGREG_EMIT(B, 0),
437	CPUM_DBGREG_EMIT(B, 1),
438	CPUM_DBGREG_EMIT(B, 2),
439	CPUM_DBGREG_EMIT(B, 3),
440	CPUM_DBGREG_EMIT(B, 4),
441	CPUM_DBGREG_EMIT(B, 5),
442	CPUM_DBGREG_EMIT(B, 6),
443	CPUM_DBGREG_EMIT(B, 7),
444	CPUM_DBGREG_EMIT(B, 8),
445	CPUM_DBGREG_EMIT(B, 9),
446	CPUM_DBGREG_EMIT(B, 10),
447	CPUM_DBGREG_EMIT(B, 11),
448	CPUM_DBGREG_EMIT(B, 12),
449	CPUM_DBGREG_EMIT(B, 13),
450	CPUM_DBGREG_EMIT(B, 14),
451	CPUM_DBGREG_EMIT(B, 15),
452	/* Watchpoint registers. */
453	CPUM_DBGREG_EMIT(W, 0),
454	CPUM_DBGREG_EMIT(W, 1),
455	CPUM_DBGREG_EMIT(W, 2),
456	CPUM_DBGREG_EMIT(W, 3),
457	CPUM_DBGREG_EMIT(W, 4),
458	CPUM_DBGREG_EMIT(W, 5),
459	CPUM_DBGREG_EMIT(W, 6),
460	CPUM_DBGREG_EMIT(W, 7),
461	CPUM_DBGREG_EMIT(W, 8),
462	CPUM_DBGREG_EMIT(W, 9),
463	CPUM_DBGREG_EMIT(W, 10),
464	CPUM_DBGREG_EMIT(W, 11),
465	CPUM_DBGREG_EMIT(W, 12),
466	CPUM_DBGREG_EMIT(W, 13),
467	CPUM_DBGREG_EMIT(W, 14),
468	CPUM_DBGREG_EMIT(W, 15),
469	{ HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
470	#undef CPUM_DBGREG_EMIT
471	};
472	/** PAuth key system registers. */
473	static const struct
474	{
475	hv_sys_reg_t enmHvReg;
476	uint32_t offCpumCtx;
477	} s_aCpumPAuthKeyRegs[] =
478	{
479	{ HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
480	{ HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
481	{ HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
482	{ HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
483	{ HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
484	{ HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
485	{ HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
486	{ HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
487	{ HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
488	{ HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
489	};
490	/** System registers. */
491	static const struct
492	{
493	hv_sys_reg_t enmHvReg;
494	uint32_t fCpumExtrn;
495	uint32_t offCpumCtx;
496	} s_aCpumSysRegs[] =
497	{
498	{ HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
499	{ HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
500	{ HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
501	{ HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
502	{ HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
503	{ HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
504	{ HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
505	{ HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
506	{ HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
507	{ HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
508	{ HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
509	{ HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
510	{ HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
511	{ HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
512	{ HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
513	{ HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
514	{ HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
515	{ HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
516	{ HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
517	{ HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
518	{ HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
519	{ HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
520	{ HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
521	{ HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
522
523	};
524	/** EL2 support system registers. */
525	static const struct
526	{
527	uint16_t idSysReg;
528	uint32_t offCpumCtx;
529	} s_aCpumEl2SysRegs[] =
530	{
531	{ ARMV8_AARCH64_SYSREG_CNTHCTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHCtlEl2.u64) },
532	{ ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCtlEl2.u64) },
533	{ ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCValEl2.u64) },
534	{ ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpTValEl2.u64) },
535	{ ARMV8_AARCH64_SYSREG_CNTVOFF_EL2, RT_UOFFSETOF(CPUMCTX, CntVOffEl2.u64) },
536	{ ARMV8_AARCH64_SYSREG_CPTR_EL2, RT_UOFFSETOF(CPUMCTX, CptrEl2.u64) },
537	{ ARMV8_AARCH64_SYSREG_ELR_EL2, RT_UOFFSETOF(CPUMCTX, ElrEl2.u64) },
538	{ ARMV8_AARCH64_SYSREG_ESR_EL2, RT_UOFFSETOF(CPUMCTX, EsrEl2.u64) },
539	{ ARMV8_AARCH64_SYSREG_FAR_EL2, RT_UOFFSETOF(CPUMCTX, FarEl2.u64) },
540	{ ARMV8_AARCH64_SYSREG_HCR_EL2, RT_UOFFSETOF(CPUMCTX, HcrEl2.u64) },
541	{ ARMV8_AARCH64_SYSREG_HPFAR_EL2, RT_UOFFSETOF(CPUMCTX, HpFarEl2.u64) },
542	{ ARMV8_AARCH64_SYSREG_MAIR_EL2, RT_UOFFSETOF(CPUMCTX, MairEl2.u64) },
543	//{ ARMV8_AARCH64_SYSREG_MDCR_EL2, RT_UOFFSETOF(CPUMCTX, MdcrEl2.u64) },
544	{ ARMV8_AARCH64_SYSREG_SCTLR_EL2, RT_UOFFSETOF(CPUMCTX, SctlrEl2.u64) },
545	{ ARMV8_AARCH64_SYSREG_SPSR_EL2, RT_UOFFSETOF(CPUMCTX, SpsrEl2.u64) },
546	{ ARMV8_AARCH64_SYSREG_SP_EL2, RT_UOFFSETOF(CPUMCTX, SpEl2.u64) },
547	{ ARMV8_AARCH64_SYSREG_TCR_EL2, RT_UOFFSETOF(CPUMCTX, TcrEl2.u64) },
548	{ ARMV8_AARCH64_SYSREG_TPIDR_EL2, RT_UOFFSETOF(CPUMCTX, TpidrEl2.u64) },
549	{ ARMV8_AARCH64_SYSREG_TTBR0_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr0El2.u64) },
550	{ ARMV8_AARCH64_SYSREG_TTBR1_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr1El2.u64) },
551	{ ARMV8_AARCH64_SYSREG_VBAR_EL2, RT_UOFFSETOF(CPUMCTX, VBarEl2.u64) },
552	{ ARMV8_AARCH64_SYSREG_VMPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VMpidrEl2.u64) },
553	{ ARMV8_AARCH64_SYSREG_VPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VPidrEl2.u64) },
554	{ ARMV8_AARCH64_SYSREG_VTCR_EL2, RT_UOFFSETOF(CPUMCTX, VTcrEl2.u64) },
555	{ ARMV8_AARCH64_SYSREG_VTTBR_EL2, RT_UOFFSETOF(CPUMCTX, VTtbrEl2.u64) }
556	};
557	/** ID registers. */
558	static const struct
559	{
560	hv_feature_reg_t enmHvReg;
561	uint32_t offIdStruct;
562	} s_aIdRegs[] =
563	{
564	{ HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr0El1) },
565	{ HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr1El1) },
566	{ HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar0El1) },
567	{ HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar1El1) },
568	{ HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr0El1) },
569	{ HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr1El1) },
570	{ HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr2El1) },
571	{ HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr0El1) },
572	{ HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr1El1) },
573	{ HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegClidrEl1) },
574	{ HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegCtrEl0) },
575	{ HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegDczidEl0) }
576	};
577
578
579	/*********************************************************************************************************************************
580	* Internal Functions *
581	*********************************************************************************************************************************/
582
583
584	/**
585	* Converts a HV return code to a VBox status code.
586	*
587	* @returns VBox status code.
588	* @param hrc The HV return code to convert.
589	*/
590	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
591	{
592	if (hrc == HV_SUCCESS)
593	return VINF_SUCCESS;
594
595	switch (hrc)
596	{
597	case HV_ERROR: return VERR_INVALID_STATE;
598	case HV_BUSY: return VERR_RESOURCE_BUSY;
599	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
600	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
601	case HV_NO_DEVICE: return VERR_NOT_FOUND;
602	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
603	}
604
605	return VERR_IPE_UNEXPECTED_STATUS;
606	}
607
608
609	/**
610	* Returns a human readable string of the given exception class.
611	*
612	* @returns Pointer to the string matching the given EC.
613	* @param u32Ec The exception class to return the string for.
614	*/
615	static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
616	{
617	switch (u32Ec)
618	{
619	#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
620	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
621	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
622	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
623	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
624	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
625	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
626	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
627	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
628	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
629	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
630	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
631	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
632	ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
633	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
634	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
635	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
636	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
637	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
638	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
639	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
640	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
641	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
642	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
643	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
644	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
645	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
646	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
647	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
648	ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
649	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
650	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
651	ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
652	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
653	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
654	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
655	ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
656	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
657	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
658	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
659	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
660	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
661	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
662	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
663	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
664	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
665	#undef ARMV8_EC_CASE
666	default:
667	break;
668	}
669
670	return "<INVALID>";
671	}
672
673
674	/**
675	* Resolves a NEM page state from the given protection flags.
676	*
677	* @returns NEM page state.
678	* @param fPageProt The page protection flags.
679	*/
680	DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
681	{
682	switch (fPageProt)
683	{
684	case NEM_PAGE_PROT_NONE:
685	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
686	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE:
687	return NEM_DARWIN_PAGE_STATE_RX;
688	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE:
689	return NEM_DARWIN_PAGE_STATE_RW;
690	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE:
691	return NEM_DARWIN_PAGE_STATE_RWX;
692	default:
693	break;
694	}
695
696	AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
697	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
698	}
699
700
701	/**
702	* Unmaps the given guest physical address range (page aligned).
703	*
704	* @returns VBox status code.
705	* @param pVM The cross context VM structure.
706	* @param GCPhys The guest physical address to start unmapping at.
707	* @param cb The size of the range to unmap in bytes.
708	* @param pu2State Where to store the new state of the unmappd page, optional.
709	*/
710	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
711	{
712	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
713	{
714	Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
715	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
716	return VINF_SUCCESS;
717	}
718
719	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
720	hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
721	if (RT_LIKELY(hrc == HV_SUCCESS))
722	{
723	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
724	if (pu2State)
725	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
726	Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
727	return VINF_SUCCESS;
728	}
729
730	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
731	LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
732	GCPhys, hrc));
733	return VERR_NEM_IPE_6;
734	}
735
736
737	/**
738	* Maps a given guest physical address range backed by the given memory with the given
739	* protection flags.
740	*
741	* @returns VBox status code.
742	* @param pVM The cross context VM structure.
743	* @param GCPhys The guest physical address to start mapping.
744	* @param pvRam The R3 pointer of the memory to back the range with.
745	* @param cb The size of the range, page aligned.
746	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
747	* @param pu2State Where to store the state for the new page, optional.
748	*/
749	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void pvRam, size_t cb, uint32_t fPageProt, uint8_t pu2State)
750	{
751	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
752
753	Assert(fPageProt != NEM_PAGE_PROT_NONE);
754	RT_NOREF(pVM);
755
756	hv_memory_flags_t fHvMemProt = 0;
757	if (fPageProt & NEM_PAGE_PROT_READ)
758	fHvMemProt \|= HV_MEMORY_READ;
759	if (fPageProt & NEM_PAGE_PROT_WRITE)
760	fHvMemProt \|= HV_MEMORY_WRITE;
761	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
762	fHvMemProt \|= HV_MEMORY_EXEC;
763
764	hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
765	if (hrc == HV_SUCCESS)
766	{
767	if (pu2State)
768	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
769	return VINF_SUCCESS;
770	}
771
772	return nemR3DarwinHvSts2Rc(hrc);
773	}
774
775
776	/**
777	* Changes the protection flags for the given guest physical address range.
778	*
779	* @returns VBox status code.
780	* @param GCPhys The guest physical address to start mapping.
781	* @param cb The size of the range, page aligned.
782	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
783	* @param pu2State Where to store the state for the new page, optional.
784	*/
785	DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
786	{
787	hv_memory_flags_t fHvMemProt = 0;
788	if (fPageProt & NEM_PAGE_PROT_READ)
789	fHvMemProt \|= HV_MEMORY_READ;
790	if (fPageProt & NEM_PAGE_PROT_WRITE)
791	fHvMemProt \|= HV_MEMORY_WRITE;
792	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
793	fHvMemProt \|= HV_MEMORY_EXEC;
794
795	hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
796	if (hrc == HV_SUCCESS)
797	{
798	if (pu2State)
799	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
800	return VINF_SUCCESS;
801	}
802
803	LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
804	GCPhys, cb, fPageProt, hrc));
805	return nemR3DarwinHvSts2Rc(hrc);
806	}
807
808
809	#ifdef LOG_ENABLED
810	/**
811	* Logs the current CPU state.
812	*/
813	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
814	{
815	if (LogIs3Enabled())
816	{
817	char szRegs[4096];
818	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
819	"x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
820	"x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
821	"x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
822	"x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
823	"x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
824	"x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
825	"x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
826	"x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
827	"pc=%016VR{pc} pstate=%016VR{pstate}\n"
828	"sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
829	"sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
830	"ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
831	"vbar_el1=%016VR{vbar_el1}\n"
832	);
833	if (pVM->nem.s.fEl2Enabled)
834	{
835	Log3(("%s\n", szRegs));
836	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
837	"sp_el2=%016VR{sp_el2} elr_el2=%016VR{elr_el2}\n"
838	"spsr_el2=%016VR{spsr_el2} tpidr_el2=%016VR{tpidr_el2}\n"
839	"sctlr_el2=%016VR{sctlr_el2} tcr_el2=%016VR{tcr_el2}\n"
840	"ttbr0_el2=%016VR{ttbr0_el2} ttbr1_el2=%016VR{ttbr1_el2}\n"
841	"esr_el2=%016VR{esr_el2} far_el2=%016VR{far_el2}\n"
842	"hcr_el2=%016VR{hcr_el2} tcr_el2=%016VR{tcr_el2}\n"
843	"vbar_el2=%016VR{vbar_el2} cptr_el2=%016VR{cptr_el2}\n"
844	);
845	}
846	char szInstr[256]; RT_ZERO(szInstr);
847	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
848	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
849	szInstr, sizeof(szInstr), NULL);
850	Log3(("%s%s\n", szRegs, szInstr));
851	}
852	}
853	#endif /* LOG_ENABLED */
854
855
856	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
857	{
858	RT_NOREF(pVM);
859
860	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
861	if (hrc == HV_SUCCESS)
862	hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
863
864	if ( hrc == HV_SUCCESS
865	&& (fWhat & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR)))
866	{
867	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
868	{
869	if (s_aCpumRegs[i].fCpumExtrn & fWhat)
870	{
871	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
872	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
873	}
874	}
875	}
876
877	if ( hrc == HV_SUCCESS
878	&& (fWhat & CPUMCTX_EXTRN_V0_V31))
879	{
880	/* SIMD/FP registers. */
881	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
882	{
883	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
884	hrc \|= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
885	}
886	}
887
888	if ( hrc == HV_SUCCESS
889	&& (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
890	{
891	/* Debug registers. */
892	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
893	{
894	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
895	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
896	}
897	}
898
899	if ( hrc == HV_SUCCESS
900	&& (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
901	{
902	/* Debug registers. */
903	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
904	{
905	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
906	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
907	}
908	}
909
910	if ( hrc == HV_SUCCESS
911	&& (fWhat & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC)))
912	{
913	/* System registers. */
914	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
915	{
916	if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
917	{
918	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
919	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
920	}
921	}
922	}
923
924	if ( hrc == HV_SUCCESS
925	&& (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
926	&& pVM->nem.s.fEl2Enabled)
927	{
928	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
929	{
930	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
931	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, pu64);
932	}
933	}
934
935	if ( hrc == HV_SUCCESS
936	&& (fWhat & CPUMCTX_EXTRN_PSTATE))
937	{
938	uint64_t u64Tmp;
939	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
940	if (hrc == HV_SUCCESS)
941	pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
942	}
943
944	/* Almost done, just update extern flags. */
945	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
946	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
947	pVCpu->cpum.GstCtx.fExtrn = 0;
948
949	return nemR3DarwinHvSts2Rc(hrc);
950	}
951
952
953	/**
954	* Exports the guest state to HV for execution.
955	*
956	* @returns VBox status code.
957	* @param pVM The cross context VM structure.
958	* @param pVCpu The cross context virtual CPU structure of the
959	* calling EMT.
960	*/
961	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
962	{
963	RT_NOREF(pVM);
964	hv_return_t hrc = HV_SUCCESS;
965
966	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
967	!= (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
968	{
969	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
970	{
971	if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
972	{
973	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
974	hrc \|= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
975	}
976	}
977	}
978
979	if ( hrc == HV_SUCCESS
980	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
981	{
982	/* SIMD/FP registers. */
983	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
984	{
985	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
986	hrc \|= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
987	}
988	}
989
990	if ( hrc == HV_SUCCESS
991	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
992	{
993	/* Debug registers. */
994	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
995	{
996	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
997	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
998	}
999	}
1000
1001	if ( hrc == HV_SUCCESS
1002	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
1003	{
1004	/* Debug registers. */
1005	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
1006	{
1007	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
1008	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
1009	}
1010	}
1011
1012	if ( hrc == HV_SUCCESS
1013	&& (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1014	!= (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1015	{
1016	/* System registers. */
1017	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
1018	{
1019	if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1020	{
1021	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
1022	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
1023	}
1024	}
1025	}
1026
1027	if ( hrc == HV_SUCCESS
1028	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_EL2)
1029	&& pVM->nem.s.fEl2Enabled)
1030	{
1031	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1032	{
1033	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1034	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, *pu64);
1035	Assert(hrc == HV_SUCCESS);
1036	}
1037	}
1038
1039	if ( hrc == HV_SUCCESS
1040	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
1041	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
1042
1043	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
1044	return nemR3DarwinHvSts2Rc(hrc);
1045	}
1046
1047
1048	/**
1049	* Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1050	*
1051	* @returns VBox status code.
1052	* @param pErrInfo Where to always return error info.
1053	*/
1054	static int nemR3DarwinLoadHv(PRTERRINFO pErrInfo)
1055	{
1056	RTLDRMOD hMod = NIL_RTLDRMOD;
1057	static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1058
1059	int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD \| RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1060	if (RT_SUCCESS(rc))
1061	{
1062	for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1063	{
1064	int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1065	if (RT_SUCCESS(rc2))
1066	{
1067	LogRel(("NEM: info: Found optional import Hypervisor!%s.\n",
1068	g_aImports[i].pszName));
1069	}
1070	else
1071	{
1072	*g_aImports[i].ppfn = NULL;
1073
1074	LogRel(("NEM: info: Failed to import Hypervisor!%s: %Rrc\n",
1075	g_aImports[i].pszName, rc2));
1076	}
1077	}
1078	if (RT_SUCCESS(rc))
1079	{
1080	Assert(!RTErrInfoIsSet(pErrInfo));
1081	}
1082
1083	RTLdrClose(hMod);
1084	}
1085	else
1086	{
1087	RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1088	rc = VERR_NEM_INIT_FAILED;
1089	}
1090
1091	return rc;
1092	}
1093
1094
1095	/**
1096	* Dumps some GIC information to the release log.
1097	*/
1098	static void nemR3DarwinDumpGicInfo(void)
1099	{
1100	size_t val = 0;
1101	hv_return_t hrc = hv_gic_get_redistributor_size(&val);
1102	LogRel(("GICNem: hv_gic_get_redistributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1103	hrc = hv_gic_get_distributor_size(&val);
1104	LogRel(("GICNem: hv_gic_get_distributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1105	hrc = hv_gic_get_distributor_base_alignment(&val);
1106	LogRel(("GICNem: hv_gic_get_distributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1107	hrc = hv_gic_get_redistributor_base_alignment(&val);
1108	LogRel(("GICNem: hv_gic_get_redistributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1109	hrc = hv_gic_get_msi_region_base_alignment(&val);
1110	LogRel(("GICNem: hv_gic_get_msi_region_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1111	hrc = hv_gic_get_msi_region_size(&val);
1112	LogRel(("GICNem: hv_gic_get_msi_region_size() -> hrc=%#x / size=%zu\n", hrc, val));
1113	uint32_t u32SpiIntIdBase = 0;
1114	uint32_t cSpiIntIds = 0;
1115	hrc = hv_gic_get_spi_interrupt_range(&u32SpiIntIdBase, &cSpiIntIds);
1116	LogRel(("GICNem: hv_gic_get_spi_interrupt_range() -> hrc=%#x / SpiIntIdBase=%u, cSpiIntIds=%u\n", hrc, u32SpiIntIdBase, cSpiIntIds));
1117
1118	uint32_t u32IntId = 0;
1119	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER, &u32IntId);
1120	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1121	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER, &u32IntId);
1122	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1123	hrc = hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER, &u32IntId);
1124	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1125	hrc = hv_gic_get_intid(HV_GIC_INT_MAINTENANCE, &u32IntId);
1126	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_MAINTENANCE) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1127	hrc = hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR, &u32IntId);
1128	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1129	}
1130
1131
1132	/**
1133	* Sets the given SPI inside the in-kernel KVM GIC.
1134	*
1135	* @returns VBox status code.
1136	* @param pVM The VM instance.
1137	* @param uIntId The SPI ID to update.
1138	* @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1139	*/
1140	VMMR3_INT_DECL(int) GICR3NemSpiSet(PVMCC pVM, uint32_t uIntId, bool fAsserted)
1141	{
1142	RT_NOREF(pVM);
1143	Assert(hv_gic_set_spi);
1144
1145	hv_return_t hrc = hv_gic_set_spi(uIntId + GIC_INTID_RANGE_SPI_START, fAsserted);
1146	return nemR3DarwinHvSts2Rc(hrc);
1147	}
1148
1149
1150	/**
1151	* Sets the given PPI inside the in-kernel KVM GIC.
1152	*
1153	* @returns VBox status code.
1154	* @param pVCpu The vCPU for whih the PPI state is updated.
1155	* @param uIntId The PPI ID to update.
1156	* @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1157	*/
1158	VMMR3_INT_DECL(int) GICR3NemPpiSet(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
1159	{
1160	RT_NOREF(pVCpu, uIntId, fAsserted);
1161
1162	/* Should never be called as the PPIs are handled entirely in Hypervisor.framework/AppleHV. */
1163	AssertFailed();
1164	return VERR_NEM_IPE_9;
1165	}
1166
1167
1168	static int nemR3DarwinGicCreate(PVM pVM)
1169	{
1170	nemR3DarwinDumpGicInfo();
1171
1172	//PCFGMNODE pGicDev = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic/0");
1173	PCFGMNODE pGicCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0/Config");
1174	AssertPtrReturn(pGicCfg, VERR_NEM_IPE_5);
1175
1176	hv_gic_config_t hGicCfg = hv_gic_config_create();
1177
1178	/*
1179	* Query the MMIO ranges.
1180	*/
1181	RTGCPHYS GCPhysMmioBaseDist = 0;
1182	int rc = CFGMR3QueryU64(pGicCfg, "DistributorMmioBase", &GCPhysMmioBaseDist);
1183	if (RT_FAILURE(rc))
1184	return VMSetError(pVM, rc, RT_SRC_POS,
1185	"Configuration error: Failed to get the \"DistributorMmioBase\" value\n");
1186
1187	RTGCPHYS GCPhysMmioBaseReDist = 0;
1188	rc = CFGMR3QueryU64(pGicCfg, "RedistributorMmioBase", &GCPhysMmioBaseReDist);
1189	if (RT_FAILURE(rc))
1190	return VMSetError(pVM, rc, RT_SRC_POS,
1191	"Configuration error: Failed to get the \"RedistributorMmioBase\" value\n");
1192
1193	hv_return_t hrc = hv_gic_config_set_distributor_base(hGicCfg, GCPhysMmioBaseDist);
1194	if (hrc != HV_SUCCESS)
1195	return nemR3DarwinHvSts2Rc(hrc);
1196
1197	hrc = hv_gic_config_set_redistributor_base(hGicCfg, GCPhysMmioBaseReDist);
1198	if (hrc != HV_SUCCESS)
1199	return nemR3DarwinHvSts2Rc(hrc);
1200
1201	hrc = hv_gic_create(hGicCfg);
1202	os_release(hGicCfg);
1203	if (hrc != HV_SUCCESS)
1204	return nemR3DarwinHvSts2Rc(hrc);
1205
1206	/* Make sure the device is not instantiated as Hypervisor.framework provides it. */
1207	//CFGMR3RemoveNode(pGicDev);
1208	return rc;
1209	}
1210
1211
1212	/**
1213	* Try initialize the native API.
1214	*
1215	* This may only do part of the job, more can be done in
1216	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
1217	*
1218	* @returns VBox status code.
1219	* @param pVM The cross context VM structure.
1220	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
1221	* the latter we'll fail if we cannot initialize.
1222	* @param fForced Whether the HMForced flag is set and we should
1223	* fail if we cannot initialize.
1224	*/
1225	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
1226	{
1227	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
1228
1229	/*
1230	* Some state init.
1231	*/
1232	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
1233	RT_NOREF(pCfgNem);
1234
1235	/*
1236	* Error state.
1237	* The error message will be non-empty on failure and 'rc' will be set too.
1238	*/
1239	RTERRINFOSTATIC ErrInfo;
1240	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
1241
1242	/* Resolve optional imports */
1243	int rc = nemR3DarwinLoadHv(pErrInfo);
1244	if (RT_FAILURE(rc))
1245	return rc;
1246
1247	/*
1248	* Need to enable nested virt here if supported and reset the CFGM value to false
1249	* if not supported. This ASSUMES that NEM is initialized before CPUM.
1250	*/
1251	PCFGMNODE pCfgCpum = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/");
1252	hv_vm_config_t hVmCfg = NULL;
1253
1254	if ( hv_vm_config_create
1255	&& hv_vm_config_get_el2_supported)
1256	{
1257	hVmCfg = hv_vm_config_create();
1258
1259	bool fHvEl2Supported = false;
1260	hv_return_t hrc = hv_vm_config_get_el2_supported(&fHvEl2Supported);
1261	if ( hrc == HV_SUCCESS
1262	&& fHvEl2Supported)
1263	{
1264	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
1265	* Whether to expose the hardware virtualization (EL2/VHE) feature to the guest.
1266	* The default is false. Only supported on M3 and later and macOS 15.0+ (Sonoma).
1267	*/
1268	bool fNestedHWVirt = false;
1269	rc = CFGMR3QueryBoolDef(pCfgCpum, "NestedHWVirt", &fNestedHWVirt, false);
1270	AssertLogRelRCReturn(rc, rc);
1271	if (fNestedHWVirt)
1272	{
1273	hrc = hv_vm_config_set_el2_enabled(hVmCfg, fNestedHWVirt);
1274	if (hrc != HV_SUCCESS)
1275	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
1276	"Cannot enable nested virtualization (hrc=%#x)!\n", hrc);
1277	else
1278	{
1279	pVM->nem.s.fEl2Enabled = true;
1280	LogRel(("NEM: Enabled nested virtualization (EL2) support\n"));
1281	}
1282	}
1283	}
1284	else
1285	{
1286	/* Ensure nested virt is not set. */
1287	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1288
1289	LogRel(("NEM: The host doesn't supported nested virtualization! (hrc=%#x fHvEl2Supported=%RTbool)\n",
1290	hrc, fHvEl2Supported));
1291	}
1292	}
1293	else
1294	{
1295	/* Ensure nested virt is not set. */
1296	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1297	LogRel(("NEM: Hypervisor.framework doesn't supported nested virtualization!\n"));
1298	}
1299
1300	hv_return_t hrc = hv_vm_create(hVmCfg);
1301	os_release(hVmCfg);
1302	if (hrc == HV_SUCCESS)
1303	{
1304	pVM->nem.s.fCreatedVm = true;
1305	pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
1306
1307	/* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
1308	pVM->nem.s.u64VTimerOff = 0;
1309
1310	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
1311	Log(("NEM: Marked active!\n"));
1312	PGMR3EnableNemMode(pVM);
1313	}
1314	else
1315	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
1316	"hv_vm_create() failed: %#x", hrc);
1317
1318	/*
1319	* We only fail if in forced mode, otherwise just log the complaint and return.
1320	*/
1321	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
1322	if ( (fForced \|\| !fFallback)
1323	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
1324	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1325
1326	if (RTErrInfoIsSet(pErrInfo))
1327	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
1328	return VINF_SUCCESS;
1329	}
1330
1331
1332	/**
1333	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
1334	*
1335	* @returns VBox status code
1336	* @param pVM The VM handle.
1337	* @param pVCpu The vCPU handle.
1338	* @param idCpu ID of the CPU to create.
1339	*/
1340	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
1341	{
1342	if (idCpu == 0)
1343	{
1344	Assert(pVM->nem.s.hVCpuCfg == NULL);
1345
1346	/* Create a new vCPU config and query the ID registers. */
1347	pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
1348	if (!pVM->nem.s.hVCpuCfg)
1349	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1350	"Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
1351
1352	/* Query ID registers and hand them to CPUM. */
1353	CPUMIDREGS IdRegs; RT_ZERO(IdRegs);
1354	for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
1355	{
1356	uint64_t pu64 = (uint64_t )((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
1357	hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
1358	if (hrc != HV_SUCCESS)
1359	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1360	"Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
1361	}
1362
1363	int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
1364	if (RT_FAILURE(rc))
1365	return rc;
1366	}
1367
1368	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
1369	if (hrc != HV_SUCCESS)
1370	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1371	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1372
1373	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
1374	if (hrc != HV_SUCCESS)
1375	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1376	"Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1377
1378	return VINF_SUCCESS;
1379	}
1380
1381
1382	/**
1383	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
1384	*
1385	* @returns VBox status code.
1386	* @param pVM The VM handle.
1387	* @param pVCpu The vCPU handle.
1388	*/
1389	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
1390	{
1391	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1392	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1393
1394	if (pVCpu->idCpu == 0)
1395	{
1396	os_release(pVM->nem.s.hVCpuCfg);
1397	pVM->nem.s.hVCpuCfg = NULL;
1398	}
1399	return VINF_SUCCESS;
1400	}
1401
1402
1403	/**
1404	* This is called after CPUMR3Init is done.
1405	*
1406	* @returns VBox status code.
1407	* @param pVM The VM handle..
1408	*/
1409	int nemR3NativeInitAfterCPUM(PVM pVM)
1410	{
1411	/*
1412	* Validate sanity.
1413	*/
1414	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
1415	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
1416
1417	/*
1418	* Need to create the GIC here if the NEM variant is configured
1419	* before any vCPU is created according to the Apple docs.
1420	*/
1421	if ( hv_gic_create
1422	&& CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0"))
1423	{
1424	int rc = nemR3DarwinGicCreate(pVM);
1425	if (RT_FAILURE(rc))
1426	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Creating the GIC failed: %Rrc", rc);
1427	}
1428
1429	/*
1430	* Setup the EMTs.
1431	*/
1432	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1433	{
1434	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1435
1436	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
1437	if (RT_FAILURE(rc))
1438	{
1439	/* Rollback. */
1440	while (idCpu--)
1441	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
1442
1443	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
1444	}
1445	}
1446
1447	pVM->nem.s.fCreatedEmts = true;
1448	return VINF_SUCCESS;
1449	}
1450
1451
1452	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1453	{
1454	RT_NOREF(pVM, enmWhat);
1455	return VINF_SUCCESS;
1456	}
1457
1458
1459	int nemR3NativeTerm(PVM pVM)
1460	{
1461	/*
1462	* Delete the VM.
1463	*/
1464
1465	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
1466	{
1467	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1468
1469	/*
1470	* Apple's documentation states that the vCPU should be destroyed
1471	* on the thread running the vCPU but as all the other EMTs are gone
1472	* at this point, destroying the VM would hang.
1473	*
1474	* We seem to be at luck here though as destroying apparently works
1475	* from EMT(0) as well.
1476	*/
1477	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1478	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1479	}
1480
1481	pVM->nem.s.fCreatedEmts = false;
1482	if (pVM->nem.s.fCreatedVm)
1483	{
1484	hv_return_t hrc = hv_vm_destroy();
1485	if (hrc != HV_SUCCESS)
1486	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
1487
1488	pVM->nem.s.fCreatedVm = false;
1489	}
1490	return VINF_SUCCESS;
1491	}
1492
1493
1494	/**
1495	* VM reset notification.
1496	*
1497	* @param pVM The cross context VM structure.
1498	*/
1499	void nemR3NativeReset(PVM pVM)
1500	{
1501	RT_NOREF(pVM);
1502	}
1503
1504
1505	/**
1506	* Reset CPU due to INIT IPI or hot (un)plugging.
1507	*
1508	* @param pVCpu The cross context virtual CPU structure of the CPU being
1509	* reset.
1510	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
1511	*/
1512	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
1513	{
1514	RT_NOREF(pVCpu, fInitIpi);
1515	}
1516
1517
1518	/**
1519	* Returns the byte size from the given access SAS value.
1520	*
1521	* @returns Number of bytes to transfer.
1522	* @param uSas The SAS value to convert.
1523	*/
1524	DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
1525	{
1526	switch (uSas)
1527	{
1528	case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
1529	case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
1530	case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
1531	case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
1532	default:
1533	AssertReleaseFailed();
1534	}
1535
1536	return 0;
1537	}
1538
1539
1540	/**
1541	* Sets the given general purpose register to the given value.
1542	*
1543	* @param pVCpu The cross context virtual CPU structure of the
1544	* calling EMT.
1545	* @param uReg The register index.
1546	* @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
1547	* @param fSignExtend Flag whether to sign extend the value.
1548	* @param u64Val The value.
1549	*/
1550	DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
1551	{
1552	AssertReturnVoid(uReg < 31);
1553
1554	if (f64BitReg)
1555	pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
1556	else
1557	pVCpu->cpum.GstCtx.aGRegs[uReg].w = fSignExtend ? (int32_t)u64Val : u64Val; /** @todo Does this clear the upper half on real hardware? */
1558
1559	/* Mark the register as not extern anymore. */
1560	switch (uReg)
1561	{
1562	case 0:
1563	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1564	break;
1565	case 1:
1566	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1567	break;
1568	case 2:
1569	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1570	break;
1571	case 3:
1572	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1573	break;
1574	default:
1575	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1576	/** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1577	}
1578	}
1579
1580
1581	/**
1582	* Gets the given general purpose register and returns the value.
1583	*
1584	* @returns Value from the given register.
1585	* @param pVCpu The cross context virtual CPU structure of the
1586	* calling EMT.
1587	* @param uReg The register index.
1588	*/
1589	DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1590	{
1591	AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
1592
1593	if (uReg == ARMV8_AARCH64_REG_ZR)
1594	return 0;
1595
1596	/** @todo Import the register if extern. */
1597	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1598
1599	return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1600	}
1601
1602
1603	/**
1604	* Works on the data abort exception (which will be a MMIO access most of the time).
1605	*
1606	* @returns VBox strict status code.
1607	* @param pVM The cross context VM structure.
1608	* @param pVCpu The cross context virtual CPU structure of the
1609	* calling EMT.
1610	* @param uIss The instruction specific syndrome value.
1611	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1612	* @param GCPtrDataAbrt The virtual GC address causing the data abort.
1613	* @param GCPhysDataAbrt The physical GC address which caused the data abort.
1614	*/
1615	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1616	RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1617	{
1618	bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1619	bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1620	bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1621	bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1622	bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1623	uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1624	uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1625	size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1626	LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1627	fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1628
1629	RT_NOREF(fL2Fault, GCPtrDataAbrt);
1630
1631	if (fWrite)
1632	{
1633	/*
1634	* Check whether this is one of the dirty tracked regions, mark it as dirty
1635	* and enable write support for this region again.
1636	*
1637	* This is required for proper VRAM tracking or the display might not get updated
1638	* and it is impossible to use the PGM generic facility as it operates on guest page sizes
1639	* but setting protection flags with Hypervisor.framework works only host page sized regions, so
1640	* we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1641	* which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1642	* write access again (due to a missing interpreter right now).
1643	*/
1644	for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1645	{
1646	PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1647
1648	if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1649	&& GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1650	{
1651	pMmio2Region->fDirty = true;
1652
1653	uint8_t u2State;
1654	int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1655	NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE \| NEM_PAGE_PROT_WRITE, &u2State);
1656
1657	/* Restart the instruction if there is no instruction syndrome available. */
1658	if (RT_FAILURE(rc) \|\| !fIsv)
1659	return rc;
1660	}
1661	}
1662	}
1663
1664	VBOXSTRICTRC rcStrict;
1665	if (fIsv)
1666	{
1667	EMHistoryAddExit(pVCpu,
1668	fWrite
1669	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1670	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1671	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1672
1673	uint64_t u64Val = 0;
1674	if (fWrite)
1675	{
1676	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1677	rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1678	Log4(("MmioExit/%u: %08RX64: WRITE %#RGp LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1679	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1680	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1681	}
1682	else
1683	{
1684	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1685	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1686	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1687	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1688	if (rcStrict == VINF_SUCCESS)
1689	nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1690	}
1691	}
1692	else
1693	{
1694	/** @todo Our UEFI firmware accesses the flash region with the following instruction
1695	* when the NVRAM actually contains data:
1696	* ldrb w9, [x6, #-0x0001]!
1697	* This is too complicated for the hardware so the ISV bit is not set. Until there
1698	* is a proper IEM implementation we just handle this here for now to avoid annoying
1699	* users too much.
1700	*/
1701	/* The following ASSUMES that the vCPU state is completely synced. */
1702
1703	/* Read instruction. */
1704	RTGCPTR GCPtrPage = pVCpu->cpum.GstCtx.Pc.u64 & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
1705	const void *pvPageR3 = NULL;
1706	PGMPAGEMAPLOCK PageMapLock;
1707
1708	rcStrict = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrPage, &pvPageR3, &PageMapLock);
1709	if (rcStrict == VINF_SUCCESS)
1710	{
1711	uint32_t u32Instr = (uint32_t )((uint8_t *)pvPageR3 + (pVCpu->cpum.GstCtx.Pc.u64 - GCPtrPage));
1712	PGMPhysReleasePageMappingLock(pVCpu->pVMR3, &PageMapLock);
1713
1714	DISSTATE Dis;
1715	rcStrict = DISInstrWithPrefetchedBytes((uintptr_t)pVCpu->cpum.GstCtx.Pc.u64, DISCPUMODE_ARMV8_A64, 0 /fFilter - none /,
1716	&u32Instr, sizeof(u32Instr), NULL, NULL, &Dis, NULL);
1717	if (rcStrict == VINF_SUCCESS)
1718	{
1719	if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDRB
1720	&& Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1721	&& Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1722	&& Dis.aParams[1].armv8.enmType == kDisArmv8OpParmAddrInGpr
1723	&& Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit
1724	&& (Dis.aParams[1].fUse & DISUSE_PRE_INDEXED))
1725	{
1726	/* The fault address is already the final address. */
1727	uint8_t bVal = 0;
1728	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &bVal, 1, PGMACCESSORIGIN_HM);
1729	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1730	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, sizeof(bVal), sizeof(bVal),
1731	&bVal, VBOXSTRICTRC_VAL(rcStrict) ));
1732	if (rcStrict == VINF_SUCCESS)
1733	{
1734	nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, bVal);
1735	/* Update the indexed register. */
1736	pVCpu->cpum.GstCtx.aGRegs[Dis.aParams[1].armv8.Op.Reg.idReg].x += Dis.aParams[1].armv8.u.offBase;
1737	}
1738	}
1739	else
1740	AssertFailedReturn(VERR_NOT_SUPPORTED);
1741	}
1742	}
1743	}
1744
1745	if (rcStrict == VINF_SUCCESS)
1746	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1747
1748	return rcStrict;
1749	}
1750
1751
1752	/**
1753	* Works on the trapped MRS, MSR and system instruction exception.
1754	*
1755	* @returns VBox strict status code.
1756	* @param pVM The cross context VM structure.
1757	* @param pVCpu The cross context virtual CPU structure of the
1758	* calling EMT.
1759	* @param uIss The instruction specific syndrome value.
1760	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1761	*/
1762	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1763	{
1764	bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1765	uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1766	uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1767	uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1768	uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1769	uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1770	uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1771	uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1772	LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1773	fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1774
1775	/** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1776	EMHistoryAddExit(pVCpu,
1777	fRead
1778	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1779	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1780	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1781
1782	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1783	uint64_t u64Val = 0;
1784	if (fRead)
1785	{
1786	RT_NOREF(pVM);
1787	rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1788	Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1789	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1790	VBOXSTRICTRC_VAL(rcStrict) ));
1791	if (rcStrict == VINF_SUCCESS)
1792	nemR3DarwinSetGReg(pVCpu, uReg, true /f64BitReg/, false /fSignExtend/, u64Val);
1793	}
1794	else
1795	{
1796	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1797	rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1798	Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1799	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1800	VBOXSTRICTRC_VAL(rcStrict) ));
1801	}
1802
1803	if (rcStrict == VINF_SUCCESS)
1804	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1805
1806	return rcStrict;
1807	}
1808
1809
1810	/**
1811	* Works on the trapped HVC instruction exception.
1812	*
1813	* @returns VBox strict status code.
1814	* @param pVM The cross context VM structure.
1815	* @param pVCpu The cross context virtual CPU structure of the
1816	* calling EMT.
1817	* @param uIss The instruction specific syndrome value.
1818	* @param fAdvancePc Flag whether to advance the guest program counter.
1819	*/
1820	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fAdvancePc = false)
1821	{
1822	uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1823	LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1824
1825	#if 0 /** @todo For later */
1826	EMHistoryAddExit(pVCpu,
1827	fRead
1828	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1829	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1830	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1831	#endif
1832
1833	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1834	if (u16Imm == 0)
1835	{
1836	/** @todo Raise exception to EL1 if PSCI not configured. */
1837	/** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1838	uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_AARCH64_REG_X0].w;
1839	bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1840	uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1841	uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1842	if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1843	{
1844	switch (uFunNum)
1845	{
1846	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1847	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
1848	break;
1849	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1850	rcStrict = VMR3PowerOff(pVM->pUVM);
1851	break;
1852	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1853	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1854	{
1855	bool fHaltOnReset;
1856	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
1857	if (RT_SUCCESS(rc) && fHaltOnReset)
1858	{
1859	Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
1860	rc = VINF_EM_HALT;
1861	}
1862	else
1863	{
1864	/** @todo pVM->pdm.s.fResetFlags = fFlags; */
1865	VM_FF_SET(pVM, VM_FF_RESET);
1866	rc = VINF_EM_RESET;
1867	}
1868	break;
1869	}
1870	case ARM_PSCI_FUNC_ID_CPU_ON:
1871	{
1872	uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1873	RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X2);
1874	uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X3);
1875	VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
1876	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /f64BitReg/, false /fSignExtend/, ARM_PSCI_STS_SUCCESS);
1877	break;
1878	}
1879	case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
1880	{
1881	uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
1882	switch (u32FunNum)
1883	{
1884	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1885	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1886	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1887	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1888	case ARM_PSCI_FUNC_ID_CPU_ON:
1889	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1890	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1891	false /f64BitReg/, false /fSignExtend/,
1892	(uint64_t)ARM_PSCI_STS_SUCCESS);
1893	break;
1894	default:
1895	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
1896	false /f64BitReg/, false /fSignExtend/,
1897	(uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1898	}
1899	break;
1900	}
1901	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1902	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_MIGRATE_INFO_TYPE_TOS_NOT_PRESENT);
1903	break;
1904	default:
1905	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1906	}
1907	}
1908	else
1909	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1910	}
1911
1912	/** @todo What to do if immediate is != 0? */
1913
1914	if ( rcStrict == VINF_SUCCESS
1915	&& fAdvancePc)
1916	pVCpu->cpum.GstCtx.Pc.u64 += sizeof(uint32_t);
1917
1918	return rcStrict;
1919	}
1920
1921
1922	/**
1923	* Handles an exception VM exit.
1924	*
1925	* @returns VBox strict status code.
1926	* @param pVM The cross context VM structure.
1927	* @param pVCpu The cross context virtual CPU structure of the
1928	* calling EMT.
1929	* @param pExit Pointer to the exit information.
1930	*/
1931	static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
1932	{
1933	uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
1934	uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
1935	bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
1936
1937	LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
1938	pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
1939
1940	switch (uEc)
1941	{
1942	case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
1943	return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
1944	pExit->exception.physical_address);
1945	case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
1946	return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
1947	case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
1948	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
1949	case ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN:
1950	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss, true);
1951	case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
1952	{
1953	/* No need to halt if there is an interrupt pending already. */
1954	if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ)))
1955	{
1956	LogFlowFunc(("IRQ \| FIQ set => VINF_SUCCESS\n"));
1957	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1958	return VINF_SUCCESS;
1959	}
1960
1961	/* Set the vTimer expiration in order to get out of the halt at the right point in time. */
1962	if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
1963	&& !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
1964	{
1965	uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
1966
1967	/* Check whether it expired and start executing guest code. */
1968	if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
1969	{
1970	LogFlowFunc(("Guest timer expired (cTicksVTimer=%RU64 CntvCValEl0=%RU64) => VINF_SUCCESS\n",
1971	cTicksVTimer, pVCpu->cpum.GstCtx.CntvCValEl0));
1972	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1973	return VINF_SUCCESS;
1974	}
1975
1976	uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
1977	uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
1978
1979	/*
1980	* Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
1981	* + scheduling overhead which would increase the wakeup latency.
1982	* So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
1983	* between CPU load when the guest is idle and performance).
1984	*/
1985	if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
1986	{
1987	LogFlowFunc(("Guest timer expiration < 2ms (cNanoSecsVTimerToExpire=%RU64) => VINF_SUCCESS\n",
1988	cNanoSecsVTimerToExpire));
1989	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1990	return VINF_SUCCESS;
1991	}
1992
1993	LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
1994	cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
1995	TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
1996	}
1997	else
1998	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
1999
2000	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2001	return VINF_EM_HALT;
2002	}
2003	case ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN:
2004	{
2005	VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx);
2006	/** @todo Forward genuine guest traps to the guest by either single stepping instruction with debug exception trapping turned off
2007	* or create instruction interpreter and inject exception ourselves. */
2008	Assert(rcStrict == VINF_EM_DBG_BREAKPOINT);
2009	return rcStrict;
2010	}
2011	case ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL:
2012	return VINF_EM_DBG_STEPPED;
2013	case ARMV8_ESR_EL2_EC_UNKNOWN:
2014	default:
2015	LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2016	uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2017	AssertReleaseFailed();
2018	return VERR_NOT_IMPLEMENTED;
2019	}
2020
2021	return VINF_SUCCESS;
2022	}
2023
2024
2025	/**
2026	* Handles an exit from hv_vcpu_run().
2027	*
2028	* @returns VBox strict status code.
2029	* @param pVM The cross context VM structure.
2030	* @param pVCpu The cross context virtual CPU structure of the
2031	* calling EMT.
2032	*/
2033	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
2034	{
2035	int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
2036	if (RT_FAILURE(rc))
2037	return rc;
2038
2039	#ifdef LOG_ENABLED
2040	if (LogIs3Enabled())
2041	nemR3DarwinLogState(pVM, pVCpu);
2042	#endif
2043
2044	hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
2045	switch (pExit->reason)
2046	{
2047	case HV_EXIT_REASON_CANCELED:
2048	return VINF_EM_RAW_INTERRUPT;
2049	case HV_EXIT_REASON_EXCEPTION:
2050	return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
2051	case HV_EXIT_REASON_VTIMER_ACTIVATED:
2052	{
2053	LogFlowFunc(("vTimer got activated\n"));
2054	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2055	pVCpu->nem.s.fVTimerActivated = true;
2056	return GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /fAsserted/);
2057	}
2058	default:
2059	AssertReleaseFailed();
2060	break;
2061	}
2062
2063	return VERR_INVALID_STATE;
2064	}
2065
2066
2067	/**
2068	* Runs the guest once until an exit occurs.
2069	*
2070	* @returns HV status code.
2071	* @param pVM The cross context VM structure.
2072	* @param pVCpu The cross context virtual CPU structure.
2073	*/
2074	static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
2075	{
2076	TMNotifyStartOfExecution(pVM, pVCpu);
2077
2078	hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
2079
2080	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2081
2082	return hrc;
2083	}
2084
2085
2086	/**
2087	* Prepares the VM to run the guest.
2088	*
2089	* @returns Strict VBox status code.
2090	* @param pVM The cross context VM structure.
2091	* @param pVCpu The cross context virtual CPU structure.
2092	* @param fSingleStepping Flag whether we run in single stepping mode.
2093	*/
2094	static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
2095	{
2096	#ifdef LOG_ENABLED
2097	bool fIrq = false;
2098	bool fFiq = false;
2099
2100	if (LogIs3Enabled())
2101	nemR3DarwinLogState(pVM, pVCpu);
2102	#endif
2103
2104	int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
2105	AssertRCReturn(rc, rc);
2106
2107	/* In single stepping mode we will re-read SPSR and MDSCR and enable the software step bits. */
2108	if (fSingleStepping)
2109	{
2110	uint64_t u64Tmp;
2111	hv_return_t hrc = hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
2112	if (hrc == HV_SUCCESS)
2113	{
2114	u64Tmp \|= ARMV8_SPSR_EL2_AARCH64_SS;
2115	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, u64Tmp);
2116	}
2117
2118	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, &u64Tmp);
2119	if (hrc == HV_SUCCESS)
2120	{
2121	u64Tmp \|= ARMV8_MDSCR_EL1_AARCH64_SS;
2122	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, u64Tmp);
2123	}
2124
2125	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2126	}
2127
2128	/* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
2129	if (pVCpu->nem.s.fVTimerActivated)
2130	{
2131	/* Read the CNTV_CTL_EL0 register. */
2132	uint64_t u64CntvCtl = 0;
2133
2134	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
2135	AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2136
2137	if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_IMASK \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2138	!= (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2139	{
2140	/* Clear the interrupt. */
2141	GICPpiSet(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /fAsserted/);
2142
2143	pVCpu->nem.s.fVTimerActivated = false;
2144	hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /vtimer_is_masked/);
2145	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2146	}
2147	}
2148
2149	/* Set the pending interrupt state. */
2150	hv_return_t hrc = HV_SUCCESS;
2151	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
2152	{
2153	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
2154	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2155	#ifdef LOG_ENABLED
2156	fIrq = true;
2157	#endif
2158	}
2159	else
2160	{
2161	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
2162	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2163	}
2164
2165	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
2166	{
2167	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
2168	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2169	#ifdef LOG_ENABLED
2170	fFiq = true;
2171	#endif
2172	}
2173	else
2174	{
2175	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
2176	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2177	}
2178
2179	LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
2180	pVCpu->nem.s.fEventPending = false;
2181	return VINF_SUCCESS;
2182	}
2183
2184
2185	/**
2186	* The normal runloop (no debugging features enabled).
2187	*
2188	* @returns Strict VBox status code.
2189	* @param pVM The cross context VM structure.
2190	* @param pVCpu The cross context virtual CPU structure.
2191	*/
2192	static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
2193	{
2194	/*
2195	* The run loop.
2196	*
2197	* Current approach to state updating to use the sledgehammer and sync
2198	* everything every time. This will be optimized later.
2199	*/
2200
2201	/* Update the vTimer offset after resuming if instructed. */
2202	if (pVCpu->nem.s.fVTimerOffUpdate)
2203	{
2204	hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2205	if (hrc != HV_SUCCESS)
2206	return nemR3DarwinHvSts2Rc(hrc);
2207
2208	pVCpu->nem.s.fVTimerOffUpdate = false;
2209
2210	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2211	if (hrc == HV_SUCCESS)
2212	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2213	if (hrc != HV_SUCCESS)
2214	return nemR3DarwinHvSts2Rc(hrc);
2215	}
2216
2217	/*
2218	* Poll timers and run for a bit.
2219	*/
2220	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2221	* the whole polling job when timers have changed... */
2222	uint64_t offDeltaIgnored;
2223	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2224	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2225	for (unsigned iLoop = 0;; iLoop++)
2226	{
2227	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
2228	if (rcStrict != VINF_SUCCESS)
2229	break;
2230
2231	hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2232	if (hrc == HV_SUCCESS)
2233	{
2234	/*
2235	* Deal with the message.
2236	*/
2237	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2238	if (rcStrict == VINF_SUCCESS)
2239	{ /* hopefully likely */ }
2240	else
2241	{
2242	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2243	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2244	break;
2245	}
2246	}
2247	else
2248	{
2249	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2250	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2251	}
2252	} /* the run loop */
2253
2254	return rcStrict;
2255	}
2256
2257
2258	/**
2259	* The debug runloop.
2260	*
2261	* @returns Strict VBox status code.
2262	* @param pVM The cross context VM structure.
2263	* @param pVCpu The cross context virtual CPU structure.
2264	*/
2265	static VBOXSTRICTRC nemR3DarwinRunGuestDebug(PVM pVM, PVMCPU pVCpu)
2266	{
2267	/*
2268	* The run loop.
2269	*
2270	* Current approach to state updating to use the sledgehammer and sync
2271	* everything every time. This will be optimized later.
2272	*/
2273
2274	bool const fSavedSingleInstruction = pVCpu->nem.s.fSingleInstruction;
2275	pVCpu->nem.s.fSingleInstruction = pVCpu->nem.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
2276	pVCpu->nem.s.fUsingDebugLoop = true;
2277
2278	/* Trap any debug exceptions. */
2279	hv_return_t hrc = hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, true);
2280	if (hrc != HV_SUCCESS)
2281	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2282	"Trapping debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2283
2284	/* Update the vTimer offset after resuming if instructed. */
2285	if (pVCpu->nem.s.fVTimerOffUpdate)
2286	{
2287	hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2288	if (hrc != HV_SUCCESS)
2289	return nemR3DarwinHvSts2Rc(hrc);
2290
2291	pVCpu->nem.s.fVTimerOffUpdate = false;
2292
2293	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2294	if (hrc == HV_SUCCESS)
2295	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2296	if (hrc != HV_SUCCESS)
2297	return nemR3DarwinHvSts2Rc(hrc);
2298	}
2299
2300	/* Save the guest MDSCR_EL1 */
2301	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG \| CPUMCTX_EXTRN_PSTATE);
2302	uint64_t u64RegMdscrEl1 = pVCpu->cpum.GstCtx.Mdscr.u64;
2303
2304	/*
2305	* Poll timers and run for a bit.
2306	*/
2307	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2308	* the whole polling job when timers have changed... */
2309	uint64_t offDeltaIgnored;
2310	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2311	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2312	for (unsigned iLoop = 0;; iLoop++)
2313	{
2314	bool const fStepping = pVCpu->nem.s.fSingleInstruction;
2315
2316	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, fStepping);
2317	if (rcStrict != VINF_SUCCESS)
2318	break;
2319
2320	hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2321	if (hrc == HV_SUCCESS)
2322	{
2323	/*
2324	* Deal with the message.
2325	*/
2326	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2327	if (rcStrict == VINF_SUCCESS)
2328	{ /* hopefully likely */ }
2329	else
2330	{
2331	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2332	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2333	break;
2334	}
2335	}
2336	else
2337	{
2338	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2339	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2340	}
2341	} /* the run loop */
2342
2343	/* Restore single stepping state. */
2344	if (pVCpu->nem.s.fSingleInstruction)
2345	{
2346	/** @todo This ASSUMES that guest code being single stepped is not modifying the MDSCR_EL1 register. */
2347	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG \| CPUMCTX_EXTRN_PSTATE);
2348	Assert(pVCpu->cpum.GstCtx.Mdscr.u64 & ARMV8_MDSCR_EL1_AARCH64_SS);
2349
2350	pVCpu->cpum.GstCtx.Mdscr.u64 = u64RegMdscrEl1;
2351	}
2352
2353	/* Restore debug exceptions trapping. */
2354	hrc != hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, false);
2355	if (hrc != HV_SUCCESS)
2356	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2357	"Clearing trapping of debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2358
2359	pVCpu->nem.s.fUsingDebugLoop = false;
2360	pVCpu->nem.s.fSingleInstruction = fSavedSingleInstruction;
2361
2362	return rcStrict;
2363
2364	}
2365
2366
2367	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2368	{
2369	#ifdef LOG_ENABLED
2370	if (LogIs3Enabled())
2371	nemR3DarwinLogState(pVM, pVCpu);
2372	#endif
2373
2374	AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
2375
2376	if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
2377	{
2378	/*
2379	* Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
2380	* Need to do it here and not during the init because loading a saved state might change the ID registers from what
2381	* done in the call to CPUMR3PopulateFeaturesByIdRegisters().
2382	*/
2383	static const struct
2384	{
2385	const char *pszIdReg;
2386	hv_sys_reg_t enmHvReg;
2387	uint32_t offIdStruct;
2388	} s_aSysIdRegs[] =
2389	{
2390	#define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMIDREGS, a_CpumIdReg) }
2391	ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
2392	ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
2393	ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
2394	ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
2395	ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
2396	ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
2397	ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
2398	ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
2399	ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
2400	#undef ID_SYS_REG_CREATE
2401	};
2402
2403	PCCPUMIDREGS pIdRegsGst = NULL;
2404	int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
2405	AssertRCReturn(rc, rc);
2406
2407	for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
2408	{
2409	uint64_t pu64 = (uint64_t )((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
2410	hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
2411	if (hrc != HV_SUCCESS)
2412	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2413	"Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2414	}
2415
2416	pVCpu->nem.s.fIdRegsSynced = true;
2417	}
2418
2419	/*
2420	* Try switch to NEM runloop state.
2421	*/
2422	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2423	{ /* likely */ }
2424	else
2425	{
2426	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2427	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2428	return VINF_SUCCESS;
2429	}
2430
2431	VBOXSTRICTRC rcStrict;
2432	if ( !pVCpu->nem.s.fUseDebugLoop
2433	/&& !nemR3DarwinAnyExpensiveProbesEnabled()/
2434	&& !DBGFIsStepping(pVCpu)
2435	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledSwBreakpoints)
2436	rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
2437	else
2438	rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
2439
2440	if (rcStrict == VINF_EM_RAW_TO_R3)
2441	rcStrict = VINF_SUCCESS;
2442
2443	/*
2444	* Convert any pending HM events back to TRPM due to premature exits.
2445	*
2446	* This is because execution may continue from IEM and we would need to inject
2447	* the event from there (hence place it back in TRPM).
2448	*/
2449	if (pVCpu->nem.s.fEventPending)
2450	{
2451	/** @todo */
2452	}
2453
2454
2455	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2456	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2457
2458	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2459	{
2460	/* Try anticipate what we might need. */
2461	uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2462	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2463	\|\| RT_FAILURE(rcStrict))
2464	fImport = CPUMCTX_EXTRN_ALL;
2465	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ
2466	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2467	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2468
2469	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2470	{
2471	/* Only import what is external currently. */
2472	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2473	if (RT_SUCCESS(rc2))
2474	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2475	else if (RT_SUCCESS(rcStrict))
2476	rcStrict = rc2;
2477	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2478	pVCpu->cpum.GstCtx.fExtrn = 0;
2479	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2480	}
2481	else
2482	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2483	}
2484	else
2485	{
2486	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2487	pVCpu->cpum.GstCtx.fExtrn = 0;
2488	}
2489
2490	return rcStrict;
2491	}
2492
2493
2494	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2495	{
2496	RT_NOREF(pVM, pVCpu);
2497	return true; /** @todo Are there any cases where we have to emulate? */
2498	}
2499
2500
2501	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2502	{
2503	VMCPU_ASSERT_EMT(pVCpu);
2504	bool fOld = pVCpu->nem.s.fSingleInstruction;
2505	pVCpu->nem.s.fSingleInstruction = fEnable;
2506	pVCpu->nem.s.fUseDebugLoop = fEnable \|\| pVM->nem.s.fUseDebugLoop;
2507	return fOld;
2508	}
2509
2510
2511	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2512	{
2513	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2514
2515	RT_NOREF(pVM, fFlags);
2516
2517	hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
2518	if (hrc != HV_SUCCESS)
2519	LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
2520	}
2521
2522
2523	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
2524	{
2525	RT_NOREF(pVM, fUseDebugLoop);
2526	//AssertReleaseFailed();
2527	return false;
2528	}
2529
2530
2531	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
2532	{
2533	RT_NOREF(pVM, pVCpu, fUseDebugLoop);
2534	return fUseDebugLoop;
2535	}
2536
2537
2538	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2539	uint8_t pu2State, uint32_t puNemRange)
2540	{
2541	RT_NOREF(pVM, puNemRange);
2542
2543	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2544	#if defined(VBOX_WITH_PGM_NEM_MODE)
2545	if (pvR3)
2546	{
2547	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2548	if (RT_FAILURE(rc))
2549	{
2550	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2551	return VERR_NEM_MAP_PAGES_FAILED;
2552	}
2553	}
2554	return VINF_SUCCESS;
2555	#else
2556	RT_NOREF(pVM, GCPhys, cb, pvR3);
2557	return VERR_NEM_MAP_PAGES_FAILED;
2558	#endif
2559	}
2560
2561
2562	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2563	{
2564	RT_NOREF(pVM);
2565	return true;
2566	}
2567
2568
2569	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2570	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
2571	{
2572	RT_NOREF(pvRam);
2573
2574	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2575	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2576
2577	#if defined(VBOX_WITH_PGM_NEM_MODE)
2578	/*
2579	* Unmap the RAM we're replacing.
2580	*/
2581	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2582	{
2583	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2584	if (RT_SUCCESS(rc))
2585	{ /* likely */ }
2586	else if (pvMmio2)
2587	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2588	GCPhys, cb, fFlags, rc));
2589	else
2590	{
2591	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2592	GCPhys, cb, fFlags, rc));
2593	return VERR_NEM_UNMAP_PAGES_FAILED;
2594	}
2595	}
2596
2597	/*
2598	* Map MMIO2 if any.
2599	*/
2600	if (pvMmio2)
2601	{
2602	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2603
2604	/* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
2605	uint32_t fProt = NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE;
2606	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2607	{
2608	/* Find a slot for dirty tracking. */
2609	PNEMHVMMIO2REGION pMmio2Region = NULL;
2610	uint32_t idSlot;
2611	for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
2612	{
2613	if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
2614	&& pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
2615	{
2616	pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
2617	break;
2618	}
2619	}
2620
2621	if (!pMmio2Region)
2622	{
2623	LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
2624	return VERR_NEM_MAP_PAGES_FAILED;
2625	}
2626
2627	pMmio2Region->GCPhysStart = GCPhys;
2628	pMmio2Region->GCPhysLast = GCPhys + cb - 1;
2629	pMmio2Region->fDirty = false;
2630	*puNemRange = idSlot;
2631	}
2632	else
2633	fProt \|= NEM_PAGE_PROT_WRITE;
2634
2635	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
2636	if (RT_FAILURE(rc))
2637	{
2638	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2639	GCPhys, cb, fFlags, pvMmio2, rc));
2640	return VERR_NEM_MAP_PAGES_FAILED;
2641	}
2642	}
2643	else
2644	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2645
2646	#else
2647	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2648	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2649	#endif
2650	return VINF_SUCCESS;
2651	}
2652
2653
2654	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2655	void pvRam, void pvMmio2, uint32_t *puNemRange)
2656	{
2657	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2658	return VINF_SUCCESS;
2659	}
2660
2661
2662	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2663	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
2664	{
2665	RT_NOREF(pVM, puNemRange);
2666
2667	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
2668	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
2669
2670	int rc = VINF_SUCCESS;
2671	#if defined(VBOX_WITH_PGM_NEM_MODE)
2672	/*
2673	* Unmap the MMIO2 pages.
2674	*/
2675	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2676	* we may have more stuff to unmap even in case of pure MMIO... */
2677	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2678	{
2679	rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2680	if (RT_FAILURE(rc))
2681	{
2682	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2683	GCPhys, cb, fFlags, rc));
2684	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2685	}
2686
2687	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2688	{
2689	/* Reset tracking structure. */
2690	uint32_t idSlot = *puNemRange;
2691	*puNemRange = UINT32_MAX;
2692
2693	Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2694	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
2695	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
2696	pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
2697	}
2698	}
2699
2700	/* Ensure the page is masked as unmapped if relevant. */
2701	Assert(!pu2State \|\| *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
2702
2703	/*
2704	* Restore the RAM we replaced.
2705	*/
2706	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2707	{
2708	AssertPtr(pvRam);
2709	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2710	if (RT_SUCCESS(rc))
2711	{ /* likely */ }
2712	else
2713	{
2714	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2715	rc = VERR_NEM_MAP_PAGES_FAILED;
2716	}
2717	}
2718
2719	RT_NOREF(pvMmio2);
2720	#else
2721	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2722	if (pu2State)
2723	*pu2State = UINT8_MAX;
2724	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2725	#endif
2726	return rc;
2727	}
2728
2729
2730	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2731	void *pvBitmap, size_t cbBitmap)
2732	{
2733	LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
2734	Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2735
2736	/* Keep it simple for now and mark everything as dirty if it is. */
2737	int rc = VINF_SUCCESS;
2738	if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
2739	{
2740	ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
2741
2742	pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
2743	/* Restore as RX only. */
2744	uint8_t u2State;
2745	rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, &u2State);
2746	}
2747	else
2748	ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
2749
2750	return rc;
2751	}
2752
2753
2754	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2755	uint8_t pu2State, uint32_t puNemRange)
2756	{
2757	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2758
2759	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2760	*pu2State = UINT8_MAX;
2761	*puNemRange = 0;
2762	return VINF_SUCCESS;
2763	}
2764
2765
2766	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2767	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
2768	{
2769	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
2770	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
2771	*pu2State = UINT8_MAX;
2772
2773	#if defined(VBOX_WITH_PGM_NEM_MODE)
2774	/*
2775	* (Re-)map readonly.
2776	*/
2777	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2778
2779	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2780	AssertRC(rc);
2781
2782	rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, pu2State);
2783	if (RT_FAILURE(rc))
2784	{
2785	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2786	GCPhys, cb, pvPages, fFlags, rc));
2787	return VERR_NEM_MAP_PAGES_FAILED;
2788	}
2789	RT_NOREF(fFlags, puNemRange);
2790	return VINF_SUCCESS;
2791	#else
2792	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2793	return VERR_NEM_MAP_PAGES_FAILED;
2794	#endif
2795	}
2796
2797
2798	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2799	RTR3PTR pvMemR3, uint8_t *pu2State)
2800	{
2801	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2802	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2803
2804	*pu2State = UINT8_MAX;
2805	#if defined(VBOX_WITH_PGM_NEM_MODE)
2806	if (pvMemR3)
2807	{
2808	/* Unregister what was there before. */
2809	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2810	AssertRC(rc);
2811
2812	rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2813	AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
2814	pvMemR3, GCPhys, cb, rc));
2815	}
2816	RT_NOREF(enmKind);
2817	#else
2818	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
2819	AssertFailed();
2820	#endif
2821	}
2822
2823
2824	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2825	{
2826	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2827	RT_NOREF(pVCpu, fEnabled);
2828	}
2829
2830
2831	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2832	{
2833	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2834	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2835	}
2836
2837
2838	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2839	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2840	{
2841	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2842	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2843	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2844	}
2845
2846
2847	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2848	PGMPAGETYPE enmType, uint8_t *pu2State)
2849	{
2850	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2851	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2852	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
2853
2854	AssertFailed();
2855	return VINF_SUCCESS;
2856	}
2857
2858
2859	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
2860	PGMPAGETYPE enmType, uint8_t *pu2State)
2861	{
2862	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2863	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2864	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
2865	}
2866
2867
2868	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2869	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2870	{
2871	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2872	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2873	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
2874
2875	AssertFailed();
2876	}
2877
2878
2879	/**
2880	* Interface for importing state on demand (used by IEM).
2881	*
2882	* @returns VBox status code.
2883	* @param pVCpu The cross context CPU structure.
2884	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2885	*/
2886	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2887	{
2888	LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
2889	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
2890
2891	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
2892	}
2893
2894
2895	/**
2896	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
2897	*
2898	* @returns VBox status code.
2899	* @param pVCpu The cross context CPU structure.
2900	* @param pcTicks Where to return the CPU tick count.
2901	* @param puAux Where to return the TSC_AUX register value.
2902	*/
2903	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
2904	{
2905	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
2906	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
2907
2908	if (puAux)
2909	*puAux = 0;
2910	pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; / This is the host timer minus the offset. */
2911	return VINF_SUCCESS;
2912	}
2913
2914
2915	/**
2916	* Resumes CPU clock (TSC) on all virtual CPUs.
2917	*
2918	* This is called by TM when the VM is started, restored, resumed or similar.
2919	*
2920	* @returns VBox status code.
2921	* @param pVM The cross context VM structure.
2922	* @param pVCpu The cross context CPU structure of the calling EMT.
2923	* @param uPausedTscValue The TSC value at the time of pausing.
2924	*/
2925	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
2926	{
2927	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
2928	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
2929	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
2930
2931	/*
2932	* Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
2933	* the new offset to let the guest not notice the pause.
2934	*/
2935	uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
2936	Assert(u64TscNew >= uPausedTscValue);
2937	LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
2938	pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
2939	pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
2940
2941	pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
2942
2943	/*
2944	* Set the flag to update the vTimer offset when the vCPU resumes for the first time
2945	* (needs to be done on the actual EMT).
2946	*/
2947	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2948	{
2949	PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
2950	pVCpuDst->nem.s.fVTimerOffUpdate = true;
2951	}
2952
2953	return VINF_SUCCESS;
2954	}
2955
2956
2957	/**
2958	* Returns features supported by the NEM backend.
2959	*
2960	* @returns Flags of features supported by the native NEM backend.
2961	* @param pVM The cross context VM structure.
2962	*/
2963	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
2964	{
2965	RT_NOREF(pVM);
2966	/*
2967	* Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
2968	* and unrestricted guest execution support so we can safely return these flags here always.
2969	*/
2970	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC \| NEM_FEAT_F_XSAVE_XRSTOR;
2971	}
2972
2973
2974	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
2975	*
2976	* @todo Add notes as the implementation progresses...
2977	*/
2978

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 106743

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