NEMR3Native-darwin-armv8.cpp@ 107316

Last change on this file since 107316 was 107316, checked in by vboxsync, 5 weeks ago
VMM: bugref:10759 Refactor GIC for use with different backends. [doxygen fix]
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1	/* $Id: NEMR3Native-darwin-armv8.cpp 107316 2024-12-13 09:14:27Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
12	*
13	* This file is part of VirtualBox base platform packages, as
14	* available from https://www.virtualbox.org.
15	*
16	* This program is free software; you can redistribute it and/or
17	* modify it under the terms of the GNU General Public License
18	* as published by the Free Software Foundation, in version 3 of the
19	* License.
20	*
21	* This program is distributed in the hope that it will be useful, but
22	* WITHOUT ANY WARRANTY; without even the implied warranty of
23	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24	* General Public License for more details.
25	*
26	* You should have received a copy of the GNU General Public License
27	* along with this program; if not, see <https://www.gnu.org/licenses>.
28	*
29	* SPDX-License-Identifier: GPL-3.0-only
30	*/
31
32
33	/*********************************************************************************************************************************
34	* Header Files *
35	*********************************************************************************************************************************/
36	#define LOG_GROUP LOG_GROUP_NEM
37	#define VMCPU_INCL_CPUM_GST_CTX
38	#include <VBox/vmm/nem.h>
39	#include <VBox/vmm/iem.h>
40	#include <VBox/vmm/em.h>
41	#include <VBox/vmm/pdmgic.h>
42	#include <VBox/vmm/pdm.h>
43	#include <VBox/vmm/dbgftrace.h>
44	#include <VBox/vmm/gcm.h>
45	#include "NEMInternal.h"
46	#include <VBox/vmm/vmcc.h>
47	#include <VBox/vmm/vmm.h>
48	#include <VBox/dis.h>
49	#include <VBox/gic.h>
50	#include "dtrace/VBoxVMM.h"
51
52	#include <iprt/armv8.h>
53	#include <iprt/asm.h>
54	#include <iprt/asm-arm.h>
55	#include <iprt/asm-math.h>
56	#include <iprt/ldr.h>
57	#include <iprt/mem.h>
58	#include <iprt/path.h>
59	#include <iprt/string.h>
60	#include <iprt/system.h>
61	#include <iprt/utf16.h>
62
63	#include <iprt/formats/arm-psci.h>
64
65	#include <mach/mach_time.h>
66	#include <mach/kern_return.h>
67
68	#include <Hypervisor/Hypervisor.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74
75
76	/*********************************************************************************************************************************
77	* Structures and Typedefs *
78	*********************************************************************************************************************************/
79
80	#if MAC_OS_X_VERSION_MIN_REQUIRED < 150000
81
82	/* Since 15.0+ */
83	typedef enum hv_gic_distributor_reg_t : uint16_t
84	{
85	HV_GIC_DISTRIBUTOR_REG_GICD_CTLR,
86	HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0
87	/** @todo */
88	} hv_gic_distributor_reg_t;
89
90
91	typedef enum hv_gic_icc_reg_t : uint16_t
92	{
93	HV_GIC_ICC_REG_PMR_EL1,
94	HV_GIC_ICC_REG_BPR0_EL1,
95	HV_GIC_ICC_REG_AP0R0_EL1,
96	HV_GIC_ICC_REG_AP1R0_EL1,
97	HV_GIC_ICC_REG_RPR_EL1,
98	HV_GIC_ICC_REG_BPR1_EL1,
99	HV_GIC_ICC_REG_CTLR_EL1,
100	HV_GIC_ICC_REG_SRE_EL1,
101	HV_GIC_ICC_REG_IGRPEN0_EL1,
102	HV_GIC_ICC_REG_IGRPEN1_EL1,
103	HV_GIC_ICC_REG_INVALID,
104	/** @todo */
105	} hv_gic_icc_reg_t;
106
107
108	typedef enum hv_gic_ich_reg_t : uint16_t
109	{
110	HV_GIC_ICH_REG_AP0R0_EL2
111	/** @todo */
112	} hv_gic_ich_reg_t;
113
114
115	typedef enum hv_gic_icv_reg_t : uint16_t
116	{
117	HV_GIC_ICV_REG_AP0R0_EL1
118	/** @todo */
119	} hv_gic_icv_reg_t;
120
121
122	typedef enum hv_gic_msi_reg_t : uint16_t
123	{
124	HV_GIC_REG_GICM_SET_SPI_NSR
125	/** @todo */
126	} hv_gic_msi_reg_t;
127
128
129	typedef enum hv_gic_redistributor_reg_t : uint16_t
130	{
131	HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0
132	/** @todo */
133	} hv_gic_redistributor_reg_t;
134
135
136	typedef enum hv_gic_intid_t : uint16_t
137	{
138	HV_GIC_INT_EL1_PHYSICAL_TIMER = 23,
139	HV_GIC_INT_EL1_VIRTUAL_TIMER = 25,
140	HV_GIC_INT_EL2_PHYSICAL_TIMER = 26,
141	HV_GIC_INT_MAINTENANCE = 27,
142	HV_GIC_INT_PERFORMANCE_MONITOR = 30
143	} hv_gic_intid_t;
144
145	#endif
146
147	typedef hv_vm_config_t FN_HV_VM_CONFIG_CREATE(void);
148	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_SUPPORTED(bool *el2_supported);
149	typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_ENABLED(hv_vm_config_t config, bool *el2_enabled);
150	typedef hv_return_t FN_HV_VM_CONFIG_SET_EL2_ENABLED(hv_vm_config_t config, bool el2_enabled);
151
152	typedef struct hv_gic_config_s *hv_gic_config_t;
153	typedef hv_return_t FN_HV_GIC_CREATE(hv_gic_config_t gic_config);
154	typedef hv_return_t FN_HV_GIC_RESET(void);
155	typedef hv_gic_config_t FN_HV_GIC_CONFIG_CREATE(void);
156	typedef hv_return_t FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t distributor_base_address);
157	typedef hv_return_t FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t redistributor_base_address);
158	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE(hv_gic_config_t config, hv_ipa_t msi_region_base_address);
159	typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE(hv_gic_config_t config, uint32_t msi_intid_base, uint32_t msi_intid_count);
160
161	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE(hv_vcpu_t vcpu, hv_ipa_t *redistributor_base_address);
162	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE(size_t *redistributor_region_size);
163	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_SIZE(size_t *redistributor_size);
164	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_SIZE(size_t *distributor_size);
165	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT(size_t *distributor_base_alignment);
166	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT(size_t *redistributor_base_alignment);
167	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT(size_t *msi_region_base_alignment);
168	typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_SIZE(size_t *msi_region_size);
169	typedef hv_return_t FN_HV_GIC_GET_SPI_INTERRUPT_RANGE(uint32_t spi_intid_base, uint32_t spi_intid_count);
170
171	typedef struct hv_gic_state_s *hv_gic_state_t;
172	typedef hv_gic_state_t FN_HV_GIC_STATE_CREATE(void);
173	typedef hv_return_t FN_HV_GIC_SET_STATE(const void *gic_state_data, size_t gic_state_size);
174	typedef hv_return_t FN_HV_GIC_STATE_GET_SIZE(hv_gic_state_t state, size_t *gic_state_size);
175	typedef hv_return_t FN_HV_GIC_STATE_GET_DATA(hv_gic_state_t state, void *gic_state_data);
176
177	typedef hv_return_t FN_HV_GIC_SEND_MSI(hv_ipa_t address, uint32_t intid);
178	typedef hv_return_t FN_HV_GIC_SET_SPI(uint32_t intid, bool level);
179
180	typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t *value);
181	typedef hv_return_t FN_HV_GIC_GET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t *value);
182	typedef hv_return_t FN_HV_GIC_GET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t *value);
183	typedef hv_return_t FN_HV_GIC_GET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t *value);
184	typedef hv_return_t FN_HV_GIC_GET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t *value);
185	typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t *value);
186
187	typedef hv_return_t FN_HV_GIC_SET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t value);
188	typedef hv_return_t FN_HV_GIC_SET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t value);
189	typedef hv_return_t FN_HV_GIC_SET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t value);
190	typedef hv_return_t FN_HV_GIC_SET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t value);
191	typedef hv_return_t FN_HV_GIC_SET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t value);
192	typedef hv_return_t FN_HV_GIC_SET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t value);
193
194	typedef hv_return_t FN_HV_GIC_GET_INTID(hv_gic_intid_t interrupt, uint32_t *intid);
195
196
197	/*********************************************************************************************************************************
198	* Global Variables *
199	*********************************************************************************************************************************/
200	/** @name Optional APIs imported from Hypervisor.framework.
201	* @{ */
202	static FN_HV_VM_CONFIG_CREATE g_pfnHvVmConfigCreate = NULL; / Since 13.0 */
203	static FN_HV_VM_CONFIG_GET_EL2_SUPPORTED g_pfnHvVmConfigGetEl2Supported = NULL; / Since 15.0 */
204	static FN_HV_VM_CONFIG_GET_EL2_ENABLED g_pfnHvVmConfigGetEl2Enabled = NULL; / Since 15.0 */
205	static FN_HV_VM_CONFIG_SET_EL2_ENABLED g_pfnHvVmConfigSetEl2Enabled = NULL; / Since 15.0 */
206
207	static FN_HV_GIC_CREATE g_pfnHvGicCreate = NULL; / Since 15.0 */
208	static FN_HV_GIC_RESET g_pfnHvGicReset = NULL; / Since 15.0 */
209	static FN_HV_GIC_CONFIG_CREATE g_pfnHvGicConfigCreate = NULL; / Since 15.0 */
210	static FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE g_pfnHvGicConfigSetDistributorBase = NULL; / Since 15.0 */
211	static FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE g_pfnHvGicConfigSetRedistributorBase = NULL; / Since 15.0 */
212	static FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE g_pfnHvGicConfigSetMsiRegionBase = NULL; / Since 15.0 */
213	static FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE g_pfnHvGicConfigSetMsiInterruptRange = NULL; / Since 15.0 */
214	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE g_pfnHvGicGetRedistributorBase = NULL; / Since 15.0 */
215	static FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE g_pfnHvGicGetRedistributorRegionSize = NULL; / Since 15.0 */
216	static FN_HV_GIC_GET_REDISTRIBUTOR_SIZE g_pfnHvGicGetRedistributorSize = NULL; / Since 15.0 */
217	static FN_HV_GIC_GET_DISTRIBUTOR_SIZE g_pfnHvGicGetDistributorSize = NULL; / Since 15.0 */
218	static FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetDistributorBaseAlignment = NULL; / Since 15.0 */
219	static FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT g_pfnHvGicGetRedistributorBaseAlignment = NULL; / Since 15.0 */
220	static FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT g_pfnHvGicGetMsiRegionBaseAlignment = NULL; / Since 15.0 */
221	static FN_HV_GIC_GET_MSI_REGION_SIZE g_pfnHvGicGetMsiRegionSize = NULL; / Since 15.0 */
222	static FN_HV_GIC_GET_SPI_INTERRUPT_RANGE g_pfnHvGicGetSpiInterruptRange = NULL; / Since 15.0 */
223	static FN_HV_GIC_STATE_CREATE g_pfnHvGicStateCreate = NULL; / Since 15.0 */
224	static FN_HV_GIC_SET_STATE g_pfnHvGicSetState = NULL; / Since 15.0 */
225	static FN_HV_GIC_STATE_GET_SIZE g_pfnHvGicStateGetSize = NULL; / Since 15.0 */
226	static FN_HV_GIC_STATE_GET_DATA g_pfnHvGicStateGetData = NULL; / Since 15.0 */
227	static FN_HV_GIC_SEND_MSI g_pfnHvGicSendMsi = NULL; / Since 15.0 */
228	static FN_HV_GIC_SET_SPI g_pfnHvGicSetSpi = NULL; / Since 15.0 */
229	static FN_HV_GIC_GET_DISTRIBUTOR_REG g_pfnHvGicGetDistributorReg = NULL; / Since 15.0 */
230	static FN_HV_GIC_GET_MSI_REG g_pfnHvGicGetMsiReg = NULL; / Since 15.0 */
231	static FN_HV_GIC_GET_ICC_REG g_pfnHvGicGetIccReg = NULL; / Since 15.0 */
232	static FN_HV_GIC_GET_ICH_REG g_pfnHvGicGetIchReg = NULL; / Since 15.0 */
233	static FN_HV_GIC_GET_ICV_REG g_pfnHvGicGetIcvReg = NULL; / Since 15.0 */
234	static FN_HV_GIC_GET_REDISTRIBUTOR_REG g_pfnHvGicGetRedistributorReg = NULL; / Since 15.0 */
235	static FN_HV_GIC_SET_DISTRIBUTOR_REG g_pfnHvGicSetDistributorReg = NULL; / Since 15.0 */
236	static FN_HV_GIC_SET_MSI_REG g_pfnHvGicSetMsiReg = NULL; / Since 15.0 */
237	static FN_HV_GIC_SET_ICC_REG g_pfnHvGicSetIccReg = NULL; / Since 15.0 */
238	static FN_HV_GIC_SET_ICH_REG g_pfnHvGicSetIchReg = NULL; / Since 15.0 */
239	static FN_HV_GIC_SET_ICV_REG g_pfnHvGicSetIcvReg = NULL; / Since 15.0 */
240	static FN_HV_GIC_SET_REDISTRIBUTOR_REG g_pfnHvGicSetRedistributorReg = NULL; / Since 15.0 */
241	static FN_HV_GIC_GET_INTID g_pfnHvGicGetIntid = NULL; / Since 15.0 */
242	/** @} */
243
244
245	/**
246	* Import instructions.
247	*/
248	static const struct
249	{
250	void ppfn; /< The function pointer variable. */
251	const char pszName; /< The function name. /
252	} g_aImports[] =
253	{
254	#define NEM_DARWIN_IMPORT(a_Pfn, a_Name) { (void **)&(a_Pfn), #a_Name }
255	NEM_DARWIN_IMPORT(g_pfnHvVmConfigCreate, hv_vm_config_create),
256	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Supported, hv_vm_config_get_el2_supported),
257	NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Enabled, hv_vm_config_get_el2_enabled),
258	NEM_DARWIN_IMPORT(g_pfnHvVmConfigSetEl2Enabled, hv_vm_config_set_el2_enabled),
259
260	NEM_DARWIN_IMPORT(g_pfnHvGicCreate, hv_gic_create),
261	NEM_DARWIN_IMPORT(g_pfnHvGicReset, hv_gic_reset),
262	NEM_DARWIN_IMPORT(g_pfnHvGicConfigCreate, hv_gic_config_create),
263	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetDistributorBase, hv_gic_config_set_distributor_base),
264	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetRedistributorBase, hv_gic_config_set_redistributor_base),
265	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiRegionBase, hv_gic_config_set_msi_region_base),
266	NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiInterruptRange, hv_gic_config_set_msi_interrupt_range),
267	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBase, hv_gic_get_redistributor_base),
268	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorRegionSize, hv_gic_get_redistributor_region_size),
269	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorSize, hv_gic_get_redistributor_size),
270	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorSize, hv_gic_get_distributor_size),
271	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorBaseAlignment, hv_gic_get_distributor_base_alignment),
272	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBaseAlignment, hv_gic_get_redistributor_base_alignment),
273	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionBaseAlignment, hv_gic_get_msi_region_base_alignment),
274	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionSize, hv_gic_get_msi_region_size),
275	NEM_DARWIN_IMPORT(g_pfnHvGicGetSpiInterruptRange, hv_gic_get_spi_interrupt_range),
276	NEM_DARWIN_IMPORT(g_pfnHvGicStateCreate, hv_gic_state_create),
277	NEM_DARWIN_IMPORT(g_pfnHvGicSetState, hv_gic_set_state),
278	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetSize, hv_gic_state_get_size),
279	NEM_DARWIN_IMPORT(g_pfnHvGicStateGetData, hv_gic_state_get_data),
280	NEM_DARWIN_IMPORT(g_pfnHvGicSendMsi, hv_gic_send_msi),
281	NEM_DARWIN_IMPORT(g_pfnHvGicSetSpi, hv_gic_set_spi),
282	NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorReg, hv_gic_get_distributor_reg),
283	NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiReg, hv_gic_get_msi_reg),
284	NEM_DARWIN_IMPORT(g_pfnHvGicGetIccReg, hv_gic_get_icc_reg),
285	NEM_DARWIN_IMPORT(g_pfnHvGicGetIchReg, hv_gic_get_ich_reg),
286	NEM_DARWIN_IMPORT(g_pfnHvGicGetIcvReg, hv_gic_get_icv_reg),
287	NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorReg, hv_gic_get_redistributor_reg),
288	NEM_DARWIN_IMPORT(g_pfnHvGicSetDistributorReg, hv_gic_set_distributor_reg),
289	NEM_DARWIN_IMPORT(g_pfnHvGicSetMsiReg, hv_gic_set_msi_reg),
290	NEM_DARWIN_IMPORT(g_pfnHvGicSetIccReg, hv_gic_set_icc_reg),
291	NEM_DARWIN_IMPORT(g_pfnHvGicSetIchReg, hv_gic_set_ich_reg),
292	NEM_DARWIN_IMPORT(g_pfnHvGicSetIcvReg, hv_gic_set_icv_reg),
293	NEM_DARWIN_IMPORT(g_pfnHvGicSetRedistributorReg, hv_gic_set_redistributor_reg),
294	NEM_DARWIN_IMPORT(g_pfnHvGicGetIntid, hv_gic_get_intid)
295	#undef NEM_DARWIN_IMPORT
296	};
297
298
299	/*
300	* Let the preprocessor alias the APIs to import variables for better autocompletion.
301	*/
302	#ifndef IN_SLICKEDIT
303	# define hv_vm_config_create g_pfnHvVmConfigCreate
304	# define hv_vm_config_get_el2_supported g_pfnHvVmConfigGetEl2Supported
305	# define hv_vm_config_get_el2_enabled g_pfnHvVmConfigGetEl2Enabled
306	# define hv_vm_config_set_el2_enabled g_pfnHvVmConfigSetEl2Enabled
307
308	# define hv_gic_create g_pfnHvGicCreate
309	# define hv_gic_reset g_pfnHvGicReset
310	# define hv_gic_config_create g_pfnHvGicConfigCreate
311	# define hv_gic_config_set_distributor_base g_pfnHvGicConfigSetDistributorBase
312	# define hv_gic_config_set_redistributor_base g_pfnHvGicConfigSetRedistributorBase
313	# define hv_gic_config_set_msi_region_base g_pfnHvGicConfigSetMsiRegionBase
314	# define hv_gic_config_set_msi_interrupt_range g_pfnHvGicConfigSetMsiInterruptRange
315	# define hv_gic_get_redistributor_base g_pfnHvGicGetRedistributorBase
316	# define hv_gic_get_redistributor_region_size g_pfnHvGicGetRedistributorRegionSize
317	# define hv_gic_get_redistributor_size g_pfnHvGicGetRedistributorSize
318	# define hv_gic_get_distributor_size g_pfnHvGicGetDistributorSize
319	# define hv_gic_get_distributor_base_alignment g_pfnHvGicGetDistributorBaseAlignment
320	# define hv_gic_get_redistributor_base_alignment g_pfnHvGicGetRedistributorBaseAlignment
321	# define hv_gic_get_msi_region_base_alignment g_pfnHvGicGetMsiRegionBaseAlignment
322	# define hv_gic_get_msi_region_size g_pfnHvGicGetMsiRegionSize
323	# define hv_gic_get_spi_interrupt_range g_pfnHvGicGetSpiInterruptRange
324	# define hv_gic_state_create g_pfnHvGicStateCreate
325	# define hv_gic_set_state g_pfnHvGicSetState
326	# define hv_gic_state_get_size g_pfnHvGicStateGetSize
327	# define hv_gic_state_get_data g_pfnHvGicStateGetData
328	# define hv_gic_send_msi g_pfnHvGicSendMsi
329	# define hv_gic_set_spi g_pfnHvGicSetSpi
330	# define hv_gic_get_distributor_reg g_pfnHvGicGetDistributorReg
331	# define hv_gic_get_msi_reg g_pfnHvGicGetMsiReg
332	# define hv_gic_get_icc_reg g_pfnHvGicGetIccReg
333	# define hv_gic_get_ich_reg g_pfnHvGicGetIchReg
334	# define hv_gic_get_icv_reg g_pfnHvGicGetIcvReg
335	# define hv_gic_get_redistributor_reg g_pfnHvGicGetRedistributorReg
336	# define hv_gic_set_distributor_reg g_pfnHvGicSetDistributorReg
337	# define hv_gic_set_msi_reg g_pfnHvGicSetMsiReg
338	# define hv_gic_set_icc_reg g_pfnHvGicSetIccReg
339	# define hv_gic_set_ich_reg g_pfnHvGicSetIchReg
340	# define hv_gic_set_icv_reg g_pfnHvGicSetIcvReg
341	# define hv_gic_set_redistributor_reg g_pfnHvGicSetRedistributorReg
342	# define hv_gic_get_intid g_pfnHvGicGetIntid
343	#endif
344
345
346	/** The general registers. */
347	static const struct
348	{
349	hv_reg_t enmHvReg;
350	uint32_t fCpumExtrn;
351	uint32_t offCpumCtx;
352	} s_aCpumRegs[] =
353	{
354	#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
355	#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
356	CPUM_GREG_EMIT_X0_X3(0),
357	CPUM_GREG_EMIT_X0_X3(1),
358	CPUM_GREG_EMIT_X0_X3(2),
359	CPUM_GREG_EMIT_X0_X3(3),
360	CPUM_GREG_EMIT_X4_X28(4),
361	CPUM_GREG_EMIT_X4_X28(5),
362	CPUM_GREG_EMIT_X4_X28(6),
363	CPUM_GREG_EMIT_X4_X28(7),
364	CPUM_GREG_EMIT_X4_X28(8),
365	CPUM_GREG_EMIT_X4_X28(9),
366	CPUM_GREG_EMIT_X4_X28(10),
367	CPUM_GREG_EMIT_X4_X28(11),
368	CPUM_GREG_EMIT_X4_X28(12),
369	CPUM_GREG_EMIT_X4_X28(13),
370	CPUM_GREG_EMIT_X4_X28(14),
371	CPUM_GREG_EMIT_X4_X28(15),
372	CPUM_GREG_EMIT_X4_X28(16),
373	CPUM_GREG_EMIT_X4_X28(17),
374	CPUM_GREG_EMIT_X4_X28(18),
375	CPUM_GREG_EMIT_X4_X28(19),
376	CPUM_GREG_EMIT_X4_X28(20),
377	CPUM_GREG_EMIT_X4_X28(21),
378	CPUM_GREG_EMIT_X4_X28(22),
379	CPUM_GREG_EMIT_X4_X28(23),
380	CPUM_GREG_EMIT_X4_X28(24),
381	CPUM_GREG_EMIT_X4_X28(25),
382	CPUM_GREG_EMIT_X4_X28(26),
383	CPUM_GREG_EMIT_X4_X28(27),
384	CPUM_GREG_EMIT_X4_X28(28),
385	{ HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
386	{ HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
387	{ HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
388	{ HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
389	{ HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
390	#undef CPUM_GREG_EMIT_X0_X3
391	#undef CPUM_GREG_EMIT_X4_X28
392	};
393	/** SIMD/FP registers. */
394	static const struct
395	{
396	hv_simd_fp_reg_t enmHvReg;
397	uint32_t offCpumCtx;
398	} s_aCpumFpRegs[] =
399	{
400	#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
401	CPUM_VREG_EMIT(0),
402	CPUM_VREG_EMIT(1),
403	CPUM_VREG_EMIT(2),
404	CPUM_VREG_EMIT(3),
405	CPUM_VREG_EMIT(4),
406	CPUM_VREG_EMIT(5),
407	CPUM_VREG_EMIT(6),
408	CPUM_VREG_EMIT(7),
409	CPUM_VREG_EMIT(8),
410	CPUM_VREG_EMIT(9),
411	CPUM_VREG_EMIT(10),
412	CPUM_VREG_EMIT(11),
413	CPUM_VREG_EMIT(12),
414	CPUM_VREG_EMIT(13),
415	CPUM_VREG_EMIT(14),
416	CPUM_VREG_EMIT(15),
417	CPUM_VREG_EMIT(16),
418	CPUM_VREG_EMIT(17),
419	CPUM_VREG_EMIT(18),
420	CPUM_VREG_EMIT(19),
421	CPUM_VREG_EMIT(20),
422	CPUM_VREG_EMIT(21),
423	CPUM_VREG_EMIT(22),
424	CPUM_VREG_EMIT(23),
425	CPUM_VREG_EMIT(24),
426	CPUM_VREG_EMIT(25),
427	CPUM_VREG_EMIT(26),
428	CPUM_VREG_EMIT(27),
429	CPUM_VREG_EMIT(28),
430	CPUM_VREG_EMIT(29),
431	CPUM_VREG_EMIT(30),
432	CPUM_VREG_EMIT(31)
433	#undef CPUM_VREG_EMIT
434	};
435	/** Debug system registers. */
436	static const struct
437	{
438	hv_sys_reg_t enmHvReg;
439	uint32_t offCpumCtx;
440	} s_aCpumDbgRegs[] =
441	{
442	#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
443	{ HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
444	{ HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
445	/* Breakpoint registers. */
446	CPUM_DBGREG_EMIT(B, 0),
447	CPUM_DBGREG_EMIT(B, 1),
448	CPUM_DBGREG_EMIT(B, 2),
449	CPUM_DBGREG_EMIT(B, 3),
450	CPUM_DBGREG_EMIT(B, 4),
451	CPUM_DBGREG_EMIT(B, 5),
452	CPUM_DBGREG_EMIT(B, 6),
453	CPUM_DBGREG_EMIT(B, 7),
454	CPUM_DBGREG_EMIT(B, 8),
455	CPUM_DBGREG_EMIT(B, 9),
456	CPUM_DBGREG_EMIT(B, 10),
457	CPUM_DBGREG_EMIT(B, 11),
458	CPUM_DBGREG_EMIT(B, 12),
459	CPUM_DBGREG_EMIT(B, 13),
460	CPUM_DBGREG_EMIT(B, 14),
461	CPUM_DBGREG_EMIT(B, 15),
462	/* Watchpoint registers. */
463	CPUM_DBGREG_EMIT(W, 0),
464	CPUM_DBGREG_EMIT(W, 1),
465	CPUM_DBGREG_EMIT(W, 2),
466	CPUM_DBGREG_EMIT(W, 3),
467	CPUM_DBGREG_EMIT(W, 4),
468	CPUM_DBGREG_EMIT(W, 5),
469	CPUM_DBGREG_EMIT(W, 6),
470	CPUM_DBGREG_EMIT(W, 7),
471	CPUM_DBGREG_EMIT(W, 8),
472	CPUM_DBGREG_EMIT(W, 9),
473	CPUM_DBGREG_EMIT(W, 10),
474	CPUM_DBGREG_EMIT(W, 11),
475	CPUM_DBGREG_EMIT(W, 12),
476	CPUM_DBGREG_EMIT(W, 13),
477	CPUM_DBGREG_EMIT(W, 14),
478	CPUM_DBGREG_EMIT(W, 15),
479	{ HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
480	#undef CPUM_DBGREG_EMIT
481	};
482	/** PAuth key system registers. */
483	static const struct
484	{
485	hv_sys_reg_t enmHvReg;
486	uint32_t offCpumCtx;
487	} s_aCpumPAuthKeyRegs[] =
488	{
489	{ HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
490	{ HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
491	{ HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
492	{ HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
493	{ HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
494	{ HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
495	{ HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
496	{ HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
497	{ HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
498	{ HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
499	};
500	/** System registers. */
501	static const struct
502	{
503	hv_sys_reg_t enmHvReg;
504	uint32_t fCpumExtrn;
505	uint32_t offCpumCtx;
506	} s_aCpumSysRegs[] =
507	{
508	{ HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
509	{ HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
510	{ HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
511	{ HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
512	{ HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
513	{ HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
514	{ HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
515	{ HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
516	{ HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
517	{ HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
518	{ HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
519	{ HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
520	{ HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
521	{ HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
522	{ HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
523	{ HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
524	{ HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
525	{ HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
526	{ HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
527	{ HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
528	{ HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
529	{ HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
530	{ HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
531	{ HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
532
533	};
534	/** EL2 support system registers. */
535	static const struct
536	{
537	uint16_t idSysReg;
538	uint32_t offCpumCtx;
539	} s_aCpumEl2SysRegs[] =
540	{
541	{ ARMV8_AARCH64_SYSREG_CNTHCTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHCtlEl2.u64) },
542	{ ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCtlEl2.u64) },
543	{ ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCValEl2.u64) },
544	{ ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpTValEl2.u64) },
545	{ ARMV8_AARCH64_SYSREG_CNTVOFF_EL2, RT_UOFFSETOF(CPUMCTX, CntVOffEl2.u64) },
546	{ ARMV8_AARCH64_SYSREG_CPTR_EL2, RT_UOFFSETOF(CPUMCTX, CptrEl2.u64) },
547	{ ARMV8_AARCH64_SYSREG_ELR_EL2, RT_UOFFSETOF(CPUMCTX, ElrEl2.u64) },
548	{ ARMV8_AARCH64_SYSREG_ESR_EL2, RT_UOFFSETOF(CPUMCTX, EsrEl2.u64) },
549	{ ARMV8_AARCH64_SYSREG_FAR_EL2, RT_UOFFSETOF(CPUMCTX, FarEl2.u64) },
550	{ ARMV8_AARCH64_SYSREG_HCR_EL2, RT_UOFFSETOF(CPUMCTX, HcrEl2.u64) },
551	{ ARMV8_AARCH64_SYSREG_HPFAR_EL2, RT_UOFFSETOF(CPUMCTX, HpFarEl2.u64) },
552	{ ARMV8_AARCH64_SYSREG_MAIR_EL2, RT_UOFFSETOF(CPUMCTX, MairEl2.u64) },
553	//{ ARMV8_AARCH64_SYSREG_MDCR_EL2, RT_UOFFSETOF(CPUMCTX, MdcrEl2.u64) },
554	{ ARMV8_AARCH64_SYSREG_SCTLR_EL2, RT_UOFFSETOF(CPUMCTX, SctlrEl2.u64) },
555	{ ARMV8_AARCH64_SYSREG_SPSR_EL2, RT_UOFFSETOF(CPUMCTX, SpsrEl2.u64) },
556	{ ARMV8_AARCH64_SYSREG_SP_EL2, RT_UOFFSETOF(CPUMCTX, SpEl2.u64) },
557	{ ARMV8_AARCH64_SYSREG_TCR_EL2, RT_UOFFSETOF(CPUMCTX, TcrEl2.u64) },
558	{ ARMV8_AARCH64_SYSREG_TPIDR_EL2, RT_UOFFSETOF(CPUMCTX, TpidrEl2.u64) },
559	{ ARMV8_AARCH64_SYSREG_TTBR0_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr0El2.u64) },
560	{ ARMV8_AARCH64_SYSREG_TTBR1_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr1El2.u64) },
561	{ ARMV8_AARCH64_SYSREG_VBAR_EL2, RT_UOFFSETOF(CPUMCTX, VBarEl2.u64) },
562	{ ARMV8_AARCH64_SYSREG_VMPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VMpidrEl2.u64) },
563	{ ARMV8_AARCH64_SYSREG_VPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VPidrEl2.u64) },
564	{ ARMV8_AARCH64_SYSREG_VTCR_EL2, RT_UOFFSETOF(CPUMCTX, VTcrEl2.u64) },
565	{ ARMV8_AARCH64_SYSREG_VTTBR_EL2, RT_UOFFSETOF(CPUMCTX, VTtbrEl2.u64) }
566	};
567	/** ID registers. */
568	static const struct
569	{
570	hv_feature_reg_t enmHvReg;
571	uint32_t offIdStruct;
572	} s_aIdRegs[] =
573	{
574	{ HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr0El1) },
575	{ HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Dfr1El1) },
576	{ HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar0El1) },
577	{ HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Isar1El1) },
578	{ HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr0El1) },
579	{ HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr1El1) },
580	{ HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Mmfr2El1) },
581	{ HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr0El1) },
582	{ HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegIdAa64Pfr1El1) },
583	{ HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMIDREGS, u64RegClidrEl1) },
584	{ HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegCtrEl0) },
585	{ HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMIDREGS, u64RegDczidEl0) }
586	};
587
588
589	/*********************************************************************************************************************************
590	* Internal Functions *
591	*********************************************************************************************************************************/
592
593
594	/**
595	* Converts a HV return code to a VBox status code.
596	*
597	* @returns VBox status code.
598	* @param hrc The HV return code to convert.
599	*/
600	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
601	{
602	if (hrc == HV_SUCCESS)
603	return VINF_SUCCESS;
604
605	switch (hrc)
606	{
607	case HV_ERROR: return VERR_INVALID_STATE;
608	case HV_BUSY: return VERR_RESOURCE_BUSY;
609	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
610	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
611	case HV_NO_DEVICE: return VERR_NOT_FOUND;
612	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
613	}
614
615	return VERR_IPE_UNEXPECTED_STATUS;
616	}
617
618
619	/** Puts a name to a hypervisor framework status code. */
620	static const char *nemR3DarwinHvStatusName(hv_return_t hrc)
621	{
622	switch (hrc)
623	{
624	RT_CASE_RET_STR(HV_SUCCESS);
625	RT_CASE_RET_STR(HV_ERROR);
626	RT_CASE_RET_STR(HV_BUSY);
627	RT_CASE_RET_STR(HV_BAD_ARGUMENT);
628	RT_CASE_RET_STR(HV_ILLEGAL_GUEST_STATE);
629	RT_CASE_RET_STR(HV_NO_RESOURCES);
630	RT_CASE_RET_STR(HV_NO_DEVICE);
631	RT_CASE_RET_STR(HV_DENIED);
632	RT_CASE_RET_STR(HV_UNSUPPORTED);
633	}
634	return "";
635	}
636
637
638	/**
639	* Converts an ICC system register into Darwin's Hypervisor.Framework equivalent.
640	*
641	* @returns HvF's ICC system register.
642	* @param u32Reg The ARMv8 ICC system register.
643	*/
644	static hv_gic_icc_reg_t nemR3DarwinIccRegFromSysReg(uint32_t u32Reg)
645	{
646	switch (u32Reg)
647	{
648	case ARMV8_AARCH64_SYSREG_ICC_PMR_EL1: return HV_GIC_ICC_REG_PMR_EL1;
649	case ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1: return HV_GIC_ICC_REG_INVALID;
650	case ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1: return HV_GIC_ICC_REG_INVALID;
651	case ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1: return HV_GIC_ICC_REG_INVALID;
652	case ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1: return HV_GIC_ICC_REG_BPR0_EL1;
653	case ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1: return HV_GIC_ICC_REG_AP0R0_EL1;
654	case ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1: return HV_GIC_ICC_REG_INVALID;
655	case ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1: return HV_GIC_ICC_REG_INVALID;
656	case ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1: return HV_GIC_ICC_REG_INVALID;
657	case ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1: return HV_GIC_ICC_REG_AP1R0_EL1;
658	case ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1: return HV_GIC_ICC_REG_INVALID;
659	case ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1: return HV_GIC_ICC_REG_INVALID;
660	case ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1: return HV_GIC_ICC_REG_INVALID;
661	case ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1: return HV_GIC_ICC_REG_INVALID;
662	case ARMV8_AARCH64_SYSREG_ICC_DIR_EL1: return HV_GIC_ICC_REG_INVALID;
663	case ARMV8_AARCH64_SYSREG_ICC_RPR_EL1: return HV_GIC_ICC_REG_RPR_EL1;
664	case ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1: return HV_GIC_ICC_REG_INVALID;
665	case ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1: return HV_GIC_ICC_REG_INVALID;
666	case ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1: return HV_GIC_ICC_REG_INVALID;
667	case ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1: return HV_GIC_ICC_REG_INVALID;
668	case ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1: return HV_GIC_ICC_REG_INVALID;
669	case ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1: return HV_GIC_ICC_REG_INVALID;
670	case ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1: return HV_GIC_ICC_REG_BPR1_EL1;
671	case ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1: return HV_GIC_ICC_REG_CTLR_EL1;
672	case ARMV8_AARCH64_SYSREG_ICC_SRE_EL1: return HV_GIC_ICC_REG_SRE_EL1;
673	case ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1: return HV_GIC_ICC_REG_IGRPEN0_EL1;
674	case ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1: return HV_GIC_ICC_REG_IGRPEN1_EL1;
675	}
676	AssertReleaseFailed();
677	return HV_GIC_ICC_REG_INVALID;
678	}
679
680
681	/**
682	* Returns a human readable string of the given exception class.
683	*
684	* @returns Pointer to the string matching the given EC.
685	* @param u32Ec The exception class to return the string for.
686	*/
687	static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
688	{
689	switch (u32Ec)
690	{
691	#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
692	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
693	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
694	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
695	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
696	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
697	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
698	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
699	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
700	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
701	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
702	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
703	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
704	ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
705	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
706	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
707	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
708	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
709	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
710	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
711	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
712	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
713	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
714	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
715	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
716	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
717	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
718	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
719	ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
720	ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
721	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
722	ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
723	ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
724	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
725	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
726	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
727	ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
728	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
729	ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
730	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
731	ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
732	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
733	ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
734	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
735	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
736	ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
737	#undef ARMV8_EC_CASE
738	default:
739	break;
740	}
741
742	return "<INVALID>";
743	}
744
745
746	/**
747	* Resolves a NEM page state from the given protection flags.
748	*
749	* @returns NEM page state.
750	* @param fPageProt The page protection flags.
751	*/
752	DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
753	{
754	switch (fPageProt)
755	{
756	case NEM_PAGE_PROT_NONE:
757	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
758	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE:
759	return NEM_DARWIN_PAGE_STATE_RX;
760	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE:
761	return NEM_DARWIN_PAGE_STATE_RW;
762	case NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE:
763	return NEM_DARWIN_PAGE_STATE_RWX;
764	default:
765	break;
766	}
767
768	AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
769	return NEM_DARWIN_PAGE_STATE_UNMAPPED;
770	}
771
772
773	/**
774	* Unmaps the given guest physical address range (page aligned).
775	*
776	* @returns VBox status code.
777	* @param pVM The cross context VM structure.
778	* @param GCPhys The guest physical address to start unmapping at.
779	* @param cb The size of the range to unmap in bytes.
780	* @param pu2State Where to store the new state of the unmappd page, optional.
781	*/
782	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
783	{
784	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
785	{
786	Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
787	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
788	return VINF_SUCCESS;
789	}
790
791	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
792	hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
793	if (RT_LIKELY(hrc == HV_SUCCESS))
794	{
795	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
796	if (pu2State)
797	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
798	Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
799	return VINF_SUCCESS;
800	}
801
802	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
803	LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
804	GCPhys, hrc));
805	return VERR_NEM_IPE_6;
806	}
807
808
809	/**
810	* Maps a given guest physical address range backed by the given memory with the given
811	* protection flags.
812	*
813	* @returns VBox status code.
814	* @param pVM The cross context VM structure.
815	* @param GCPhys The guest physical address to start mapping.
816	* @param pvRam The R3 pointer of the memory to back the range with.
817	* @param cb The size of the range, page aligned.
818	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
819	* @param pu2State Where to store the state for the new page, optional.
820	*/
821	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void pvRam, size_t cb, uint32_t fPageProt, uint8_t pu2State)
822	{
823	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
824
825	Assert(fPageProt != NEM_PAGE_PROT_NONE);
826	RT_NOREF(pVM);
827
828	hv_memory_flags_t fHvMemProt = 0;
829	if (fPageProt & NEM_PAGE_PROT_READ)
830	fHvMemProt \|= HV_MEMORY_READ;
831	if (fPageProt & NEM_PAGE_PROT_WRITE)
832	fHvMemProt \|= HV_MEMORY_WRITE;
833	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
834	fHvMemProt \|= HV_MEMORY_EXEC;
835
836	hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
837	if (hrc == HV_SUCCESS)
838	{
839	if (pu2State)
840	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
841	return VINF_SUCCESS;
842	}
843
844	return nemR3DarwinHvSts2Rc(hrc);
845	}
846
847
848	/**
849	* Changes the protection flags for the given guest physical address range.
850	*
851	* @returns VBox status code.
852	* @param GCPhys The guest physical address to start mapping.
853	* @param cb The size of the range, page aligned.
854	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
855	* @param pu2State Where to store the state for the new page, optional.
856	*/
857	DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
858	{
859	hv_memory_flags_t fHvMemProt = 0;
860	if (fPageProt & NEM_PAGE_PROT_READ)
861	fHvMemProt \|= HV_MEMORY_READ;
862	if (fPageProt & NEM_PAGE_PROT_WRITE)
863	fHvMemProt \|= HV_MEMORY_WRITE;
864	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
865	fHvMemProt \|= HV_MEMORY_EXEC;
866
867	hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
868	if (hrc == HV_SUCCESS)
869	{
870	if (pu2State)
871	*pu2State = nemR3DarwinPageStateFromProt(fPageProt);
872	return VINF_SUCCESS;
873	}
874
875	LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
876	GCPhys, cb, fPageProt, hrc));
877	return nemR3DarwinHvSts2Rc(hrc);
878	}
879
880
881	#ifdef LOG_ENABLED
882	/**
883	* Logs the current CPU state.
884	*/
885	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
886	{
887	if (LogIs3Enabled())
888	{
889	char szRegs[4096];
890	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
891	"x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
892	"x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
893	"x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
894	"x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
895	"x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
896	"x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
897	"x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
898	"x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
899	"pc=%016VR{pc} pstate=%016VR{pstate}\n"
900	"sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
901	"sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
902	"ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
903	"vbar_el1=%016VR{vbar_el1}\n"
904	);
905	if (pVM->nem.s.fEl2Enabled)
906	{
907	Log3(("%s\n", szRegs));
908	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
909	"sp_el2=%016VR{sp_el2} elr_el2=%016VR{elr_el2}\n"
910	"spsr_el2=%016VR{spsr_el2} tpidr_el2=%016VR{tpidr_el2}\n"
911	"sctlr_el2=%016VR{sctlr_el2} tcr_el2=%016VR{tcr_el2}\n"
912	"ttbr0_el2=%016VR{ttbr0_el2} ttbr1_el2=%016VR{ttbr1_el2}\n"
913	"esr_el2=%016VR{esr_el2} far_el2=%016VR{far_el2}\n"
914	"hcr_el2=%016VR{hcr_el2} tcr_el2=%016VR{tcr_el2}\n"
915	"vbar_el2=%016VR{vbar_el2} cptr_el2=%016VR{cptr_el2}\n"
916	);
917	}
918	char szInstr[256]; RT_ZERO(szInstr);
919	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
920	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
921	szInstr, sizeof(szInstr), NULL);
922	Log3(("%s%s\n", szRegs, szInstr));
923	}
924	}
925	#endif /* LOG_ENABLED */
926
927
928	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
929	{
930	RT_NOREF(pVM);
931
932	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
933	if (hrc == HV_SUCCESS)
934	hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
935
936	if ( hrc == HV_SUCCESS
937	&& (fWhat & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR)))
938	{
939	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
940	{
941	if (s_aCpumRegs[i].fCpumExtrn & fWhat)
942	{
943	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
944	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
945	}
946	}
947	}
948
949	if ( hrc == HV_SUCCESS
950	&& (fWhat & CPUMCTX_EXTRN_V0_V31))
951	{
952	/* SIMD/FP registers. */
953	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
954	{
955	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
956	hrc \|= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
957	}
958	}
959
960	if ( hrc == HV_SUCCESS
961	&& (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
962	{
963	/* Debug registers. */
964	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
965	{
966	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
967	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
968	}
969	}
970
971	if ( hrc == HV_SUCCESS
972	&& (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
973	{
974	/* Debug registers. */
975	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
976	{
977	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
978	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
979	}
980	}
981
982	if ( hrc == HV_SUCCESS
983	&& (fWhat & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC)))
984	{
985	/* System registers. */
986	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
987	{
988	if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
989	{
990	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
991	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
992	}
993	}
994	}
995
996	if ( hrc == HV_SUCCESS
997	&& (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
998	&& pVM->nem.s.fEl2Enabled)
999	{
1000	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1001	{
1002	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1003	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, pu64);
1004	}
1005	}
1006
1007	if ( hrc == HV_SUCCESS
1008	&& (fWhat & CPUMCTX_EXTRN_PSTATE))
1009	{
1010	uint64_t u64Tmp;
1011	hrc \|= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
1012	if (hrc == HV_SUCCESS)
1013	pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
1014	}
1015
1016	/* Almost done, just update extern flags. */
1017	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1018	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1019	pVCpu->cpum.GstCtx.fExtrn = 0;
1020
1021	return nemR3DarwinHvSts2Rc(hrc);
1022	}
1023
1024
1025	/**
1026	* Exports the guest state to HV for execution.
1027	*
1028	* @returns VBox status code.
1029	* @param pVM The cross context VM structure.
1030	* @param pVCpu The cross context virtual CPU structure of the
1031	* calling EMT.
1032	*/
1033	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
1034	{
1035	RT_NOREF(pVM);
1036	hv_return_t hrc = HV_SUCCESS;
1037
1038	if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
1039	!= (CPUMCTX_EXTRN_GPRS_MASK \| CPUMCTX_EXTRN_PC \| CPUMCTX_EXTRN_FPCR \| CPUMCTX_EXTRN_FPSR))
1040	{
1041	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
1042	{
1043	if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1044	{
1045	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
1046	hrc \|= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
1047	}
1048	}
1049	}
1050
1051	if ( hrc == HV_SUCCESS
1052	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
1053	{
1054	/* SIMD/FP registers. */
1055	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
1056	{
1057	hv_simd_fp_uchar16_t pu128 = (hv_simd_fp_uchar16_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
1058	hrc \|= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
1059	}
1060	}
1061
1062	if ( hrc == HV_SUCCESS
1063	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
1064	{
1065	/* Debug registers. */
1066	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
1067	{
1068	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
1069	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
1070	}
1071	}
1072
1073	if ( hrc == HV_SUCCESS
1074	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
1075	{
1076	/* Debug registers. */
1077	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
1078	{
1079	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
1080	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
1081	}
1082	}
1083
1084	if ( hrc == HV_SUCCESS
1085	&& (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1086	!= (CPUMCTX_EXTRN_SPSR \| CPUMCTX_EXTRN_ELR \| CPUMCTX_EXTRN_SP \| CPUMCTX_EXTRN_SCTLR_TCR_TTBR \| CPUMCTX_EXTRN_SYSREG_MISC))
1087	{
1088	/* System registers. */
1089	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
1090	{
1091	if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1092	{
1093	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
1094	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
1095	}
1096	}
1097	}
1098
1099	if ( hrc == HV_SUCCESS
1100	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_EL2)
1101	&& pVM->nem.s.fEl2Enabled)
1102	{
1103	for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1104	{
1105	uint64_t pu64 = (uint64_t )((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1106	hrc \|= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, *pu64);
1107	Assert(hrc == HV_SUCCESS);
1108	}
1109	}
1110
1111	if ( hrc == HV_SUCCESS
1112	&& !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
1113	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
1114
1115	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
1116	return nemR3DarwinHvSts2Rc(hrc);
1117	}
1118
1119
1120	/**
1121	* Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1122	*
1123	* @returns VBox status code.
1124	* @param pErrInfo Where to always return error info.
1125	*/
1126	static int nemR3DarwinLoadHv(PRTERRINFO pErrInfo)
1127	{
1128	RTLDRMOD hMod = NIL_RTLDRMOD;
1129	static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1130
1131	int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD \| RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1132	if (RT_SUCCESS(rc))
1133	{
1134	for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1135	{
1136	int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1137	if (RT_SUCCESS(rc2))
1138	LogRel(("NEM: info: Found optional import Hypervisor!%s.\n", g_aImports[i].pszName));
1139	else
1140	{
1141	*g_aImports[i].ppfn = NULL;
1142	LogRel(("NEM: info: Optional import Hypervisor!%s not found: %Rrc\n", g_aImports[i].pszName, rc2));
1143	}
1144	}
1145	Assert(RT_SUCCESS(rc) && !RTErrInfoIsSet(pErrInfo));
1146	RTLdrClose(hMod);
1147	}
1148	else
1149	{
1150	RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1151	rc = VERR_NEM_INIT_FAILED;
1152	}
1153
1154	return rc;
1155	}
1156
1157
1158	/**
1159	* Dumps some GIC information to the release log.
1160	*/
1161	static void nemR3DarwinDumpGicInfo(void)
1162	{
1163	size_t val = 0;
1164	hv_return_t hrc = hv_gic_get_redistributor_size(&val);
1165	LogRel(("GICNem: hv_gic_get_redistributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1166	hrc = hv_gic_get_distributor_size(&val);
1167	LogRel(("GICNem: hv_gic_get_distributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1168	hrc = hv_gic_get_distributor_base_alignment(&val);
1169	LogRel(("GICNem: hv_gic_get_distributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1170	hrc = hv_gic_get_redistributor_base_alignment(&val);
1171	LogRel(("GICNem: hv_gic_get_redistributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1172	hrc = hv_gic_get_msi_region_base_alignment(&val);
1173	LogRel(("GICNem: hv_gic_get_msi_region_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1174	hrc = hv_gic_get_msi_region_size(&val);
1175	LogRel(("GICNem: hv_gic_get_msi_region_size() -> hrc=%#x / size=%zu\n", hrc, val));
1176	uint32_t u32SpiIntIdBase = 0;
1177	uint32_t cSpiIntIds = 0;
1178	hrc = hv_gic_get_spi_interrupt_range(&u32SpiIntIdBase, &cSpiIntIds);
1179	LogRel(("GICNem: hv_gic_get_spi_interrupt_range() -> hrc=%#x / SpiIntIdBase=%u, cSpiIntIds=%u\n", hrc, u32SpiIntIdBase, cSpiIntIds));
1180
1181	uint32_t u32IntId = 0;
1182	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER, &u32IntId);
1183	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1184	hrc = hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER, &u32IntId);
1185	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1186	hrc = hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER, &u32IntId);
1187	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1188	hrc = hv_gic_get_intid(HV_GIC_INT_MAINTENANCE, &u32IntId);
1189	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_MAINTENANCE) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1190	hrc = hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR, &u32IntId);
1191	LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1192	}
1193
1194
1195	/**
1196	* Sets the given SPI inside the in-kernel HvF GIC.
1197	*
1198	* @returns VBox status code.
1199	* @param pVM The VM instance.
1200	* @param uIntId The SPI ID to update.
1201	* @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1202	*/
1203	VMM_INT_DECL(int) NEMR3GicSetSpi(PVMCC pVM, uint32_t uIntId, bool fAsserted)
1204	{
1205	RT_NOREF(pVM);
1206	Assert(hv_gic_set_spi);
1207
1208	hv_return_t hrc = hv_gic_set_spi(uIntId + GIC_INTID_RANGE_SPI_START, fAsserted);
1209	return nemR3DarwinHvSts2Rc(hrc);
1210	}
1211
1212
1213	/**
1214	* Sets the given PPI inside the in-kernel HvF GIC.
1215	*
1216	* @returns VBox status code.
1217	* @param pVCpu The vCPU for which the PPI state is to be updated.
1218	* @param uIntId The PPI ID to update.
1219	* @param fAsserted Flag whether the interrupt is asserted (true) or not (false).
1220	*/
1221	VMM_INT_DECL(int) NEMR3GicSetPpi(PVMCPUCC pVCpu, uint32_t uIntId, bool fAsserted)
1222	{
1223	RT_NOREF(pVCpu, uIntId, fAsserted);
1224
1225	/* Should never be called as the PPIs are handled entirely in Hypervisor.framework/AppleHV. */
1226	AssertFailed();
1227	return VERR_NEM_IPE_9;
1228	}
1229
1230
1231	/**
1232	* Writes a system ICC register inside the in-kernel HvF GIC.
1233	*
1234	* @returns VBox status code.
1235	* @param pVCpu The cross context virtual CPU structure.
1236	* @param u32Reg The ICC register.
1237	* @param u64Value The value being set.
1238	*/
1239	VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicWriteSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t u64Value)
1240	{
1241	hv_gic_icc_reg_t const enmIccReg = nemR3DarwinIccRegFromSysReg(u32Reg);
1242	hv_return_t const hrc = hv_gic_set_icc_reg(pVCpu->nem.s.hVCpu, enmIccReg, u64Value);
1243	return nemR3DarwinHvSts2Rc(hrc);
1244	}
1245
1246
1247	/**
1248	* Reads a system ICC register inside the in-kernel HvF GIC.
1249	*
1250	* @returns VBox status code.
1251	* @param pVCpu The cross context virtual CPU structure.
1252	* @param u32Reg The ICC register.
1253	* @param pu64Value Where to store value.
1254	*/
1255	VMM_INT_DECL(VBOXSTRICTRC) NEMR3GicReadSysReg(PVMCPUCC pVCpu, uint32_t u32Reg, uint64_t *pu64Value)
1256	{
1257	hv_gic_icc_reg_t const enmIccReg = nemR3DarwinIccRegFromSysReg(u32Reg);
1258	hv_return_t const hrc = hv_gic_get_icc_reg(pVCpu->nem.s.hVCpu, enmIccReg, pu64Value);
1259	return nemR3DarwinHvSts2Rc(hrc);
1260	}
1261
1262
1263	static int nemR3DarwinGicCreate(PVM pVM)
1264	{
1265	nemR3DarwinDumpGicInfo();
1266
1267	//PCFGMNODE pGicDev = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic/0");
1268	PCFGMNODE pGicCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0/Config");
1269	AssertPtrReturn(pGicCfg, VERR_NEM_IPE_5);
1270
1271	hv_gic_config_t hGicCfg = hv_gic_config_create();
1272
1273	/*
1274	* Query the MMIO ranges.
1275	*/
1276	RTGCPHYS GCPhysMmioBaseDist = 0;
1277	int rc = CFGMR3QueryU64(pGicCfg, "DistributorMmioBase", &GCPhysMmioBaseDist);
1278	if (RT_FAILURE(rc))
1279	return VMSetError(pVM, rc, RT_SRC_POS,
1280	"Configuration error: Failed to get the \"DistributorMmioBase\" value\n");
1281
1282	RTGCPHYS GCPhysMmioBaseReDist = 0;
1283	rc = CFGMR3QueryU64(pGicCfg, "RedistributorMmioBase", &GCPhysMmioBaseReDist);
1284	if (RT_FAILURE(rc))
1285	return VMSetError(pVM, rc, RT_SRC_POS,
1286	"Configuration error: Failed to get the \"RedistributorMmioBase\" value\n");
1287
1288	hv_return_t hrc = hv_gic_config_set_distributor_base(hGicCfg, GCPhysMmioBaseDist);
1289	if (hrc != HV_SUCCESS)
1290	return nemR3DarwinHvSts2Rc(hrc);
1291
1292	hrc = hv_gic_config_set_redistributor_base(hGicCfg, GCPhysMmioBaseReDist);
1293	if (hrc != HV_SUCCESS)
1294	return nemR3DarwinHvSts2Rc(hrc);
1295
1296	hrc = hv_gic_create(hGicCfg);
1297	os_release(hGicCfg);
1298	if (hrc != HV_SUCCESS)
1299	return nemR3DarwinHvSts2Rc(hrc);
1300
1301	/* Make sure the device is not instantiated as Hypervisor.framework provides it. */
1302	//CFGMR3RemoveNode(pGicDev);
1303	return rc;
1304	}
1305
1306
1307	/**
1308	* Try initialize the native API.
1309	*
1310	* This may only do part of the job, more can be done in
1311	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
1312	*
1313	* @returns VBox status code.
1314	* @param pVM The cross context VM structure.
1315	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
1316	* the latter we'll fail if we cannot initialize.
1317	* @param fForced Whether the HMForced flag is set and we should
1318	* fail if we cannot initialize.
1319	*/
1320	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
1321	{
1322	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
1323
1324	/*
1325	* Some state init.
1326	*/
1327	PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
1328	RT_NOREF(pCfgNem);
1329
1330	/*
1331	* Error state.
1332	* The error message will be non-empty on failure and 'rc' will be set too.
1333	*/
1334	RTERRINFOSTATIC ErrInfo;
1335	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
1336
1337	/* Resolve optional imports */
1338	int rc = nemR3DarwinLoadHv(pErrInfo);
1339	if (RT_FAILURE(rc))
1340	{
1341	if ((fForced \|\| !fFallback) && RTErrInfoIsSet(pErrInfo))
1342	return VMSetError(pVM, rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1343	return rc;
1344	}
1345
1346	/*
1347	* Need to enable nested virt here if supported and reset the CFGM value to false
1348	* if not supported. This ASSUMES that NEM is initialized before CPUM.
1349	*/
1350	PCFGMNODE pCfgCpum = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/");
1351
1352	hv_vm_config_t hVmCfg = NULL;
1353	if ( hv_vm_config_create
1354	&& hv_vm_config_get_el2_supported)
1355	{
1356	hVmCfg = hv_vm_config_create();
1357
1358	bool fHvEl2Supported = false;
1359	hv_return_t hrc = hv_vm_config_get_el2_supported(&fHvEl2Supported);
1360	if ( hrc == HV_SUCCESS
1361	&& fHvEl2Supported)
1362	{
1363	/** @cfgm{/CPUM/NestedHWVirt, bool, false}
1364	* Whether to expose the hardware virtualization (EL2/VHE) feature to the guest.
1365	* The default is false. Only supported on M3 and later and macOS 15.0+ (Sonoma).
1366	*/
1367	bool fNestedHWVirt = false;
1368	rc = CFGMR3QueryBoolDef(pCfgCpum, "NestedHWVirt", &fNestedHWVirt, false);
1369	AssertLogRelRCReturn(rc, rc);
1370	if (fNestedHWVirt)
1371	{
1372	hrc = hv_vm_config_set_el2_enabled(hVmCfg, fNestedHWVirt);
1373	if (hrc != HV_SUCCESS)
1374	return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
1375	"Cannot enable nested virtualization: hrc=%#x %s!\n", hrc, nemR3DarwinHvStatusName(hrc));
1376	pVM->nem.s.fEl2Enabled = true;
1377	LogRel(("NEM: Enabled nested virtualization (EL2) support\n"));
1378	}
1379	}
1380	else
1381	{
1382	/* Ensure nested virt is not set. */
1383	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1384	AssertLogRelRC(rc);
1385
1386	LogRel(("NEM: The host doesn't supported nested virtualization! (hrc=%#x fHvEl2Supported=%RTbool)\n",
1387	hrc, fHvEl2Supported));
1388	}
1389	}
1390	else
1391	{
1392	/* Ensure nested virt is not set. */
1393	rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1394	AssertLogRelRC(rc);
1395
1396	LogRel(("NEM: Hypervisor.framework doesn't supported nested virtualization!\n"));
1397	}
1398
1399	hv_return_t hrc = hv_vm_create(hVmCfg);
1400	os_release(hVmCfg);
1401	if (hrc == HV_SUCCESS)
1402	{
1403	pVM->nem.s.fCreatedVm = true;
1404	pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
1405
1406	/* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
1407	pVM->nem.s.u64VTimerOff = 0;
1408
1409	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
1410	Log(("NEM: Marked active!\n"));
1411	PGMR3EnableNemMode(pVM);
1412	return VINF_SUCCESS;
1413	}
1414
1415	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED, "hv_vm_create() failed: %#x %s", hrc, nemR3DarwinHvStatusName(hrc));
1416
1417	/*
1418	* We only fail if in forced mode, otherwise just log the complaint and return.
1419	*/
1420	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
1421	if ( (fForced \|\| !fFallback)
1422	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
1423	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1424
1425	if (RTErrInfoIsSet(pErrInfo))
1426	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
1427	return VINF_SUCCESS;
1428	}
1429
1430
1431	/**
1432	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
1433	*
1434	* @returns VBox status code
1435	* @param pVM The VM handle.
1436	* @param pVCpu The vCPU handle.
1437	* @param idCpu ID of the CPU to create.
1438	*/
1439	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
1440	{
1441	if (idCpu == 0)
1442	{
1443	Assert(pVM->nem.s.hVCpuCfg == NULL);
1444
1445	/* Create a new vCPU config and query the ID registers. */
1446	pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
1447	if (!pVM->nem.s.hVCpuCfg)
1448	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1449	"Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
1450
1451	/* Query ID registers and hand them to CPUM. */
1452	CPUMIDREGS IdRegs; RT_ZERO(IdRegs);
1453	for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
1454	{
1455	uint64_t pu64 = (uint64_t )((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
1456	hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
1457	if (hrc != HV_SUCCESS)
1458	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1459	"Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
1460	}
1461
1462	int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
1463	if (RT_FAILURE(rc))
1464	return rc;
1465	}
1466
1467	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
1468	if (hrc != HV_SUCCESS)
1469	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1470	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1471
1472	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
1473	if (hrc != HV_SUCCESS)
1474	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1475	"Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1476
1477	return VINF_SUCCESS;
1478	}
1479
1480
1481	/**
1482	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
1483	*
1484	* @returns VBox status code.
1485	* @param pVM The VM handle.
1486	* @param pVCpu The vCPU handle.
1487	*/
1488	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
1489	{
1490	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1491	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1492
1493	if (pVCpu->idCpu == 0)
1494	{
1495	os_release(pVM->nem.s.hVCpuCfg);
1496	pVM->nem.s.hVCpuCfg = NULL;
1497	}
1498	return VINF_SUCCESS;
1499	}
1500
1501
1502	/**
1503	* This is called after CPUMR3Init is done.
1504	*
1505	* @returns VBox status code.
1506	* @param pVM The VM handle..
1507	*/
1508	int nemR3NativeInitAfterCPUM(PVM pVM)
1509	{
1510	/*
1511	* Validate sanity.
1512	*/
1513	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
1514	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
1515
1516	/*
1517	* Need to create the GIC here if the NEM variant is configured
1518	* before any vCPU is created according to the Apple docs.
1519	*/
1520	if ( hv_gic_create
1521	&& CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0"))
1522	{
1523	int rc = nemR3DarwinGicCreate(pVM);
1524	if (RT_FAILURE(rc))
1525	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Creating the GIC failed: %Rrc", rc);
1526	}
1527
1528	/*
1529	* Setup the EMTs.
1530	*/
1531	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1532	{
1533	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1534
1535	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
1536	if (RT_FAILURE(rc))
1537	{
1538	/* Rollback. */
1539	while (idCpu--)
1540	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
1541
1542	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
1543	}
1544	}
1545
1546	pVM->nem.s.fCreatedEmts = true;
1547	return VINF_SUCCESS;
1548	}
1549
1550
1551	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1552	{
1553	RT_NOREF(pVM, enmWhat);
1554	return VINF_SUCCESS;
1555	}
1556
1557
1558	int nemR3NativeTerm(PVM pVM)
1559	{
1560	/*
1561	* Delete the VM.
1562	*/
1563
1564	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
1565	{
1566	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1567
1568	/*
1569	* Apple's documentation states that the vCPU should be destroyed
1570	* on the thread running the vCPU but as all the other EMTs are gone
1571	* at this point, destroying the VM would hang.
1572	*
1573	* We seem to be at luck here though as destroying apparently works
1574	* from EMT(0) as well.
1575	*/
1576	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1577	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1578	}
1579
1580	pVM->nem.s.fCreatedEmts = false;
1581	if (pVM->nem.s.fCreatedVm)
1582	{
1583	hv_return_t hrc = hv_vm_destroy();
1584	if (hrc != HV_SUCCESS)
1585	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
1586
1587	pVM->nem.s.fCreatedVm = false;
1588	}
1589	return VINF_SUCCESS;
1590	}
1591
1592
1593	/**
1594	* VM reset notification.
1595	*
1596	* @param pVM The cross context VM structure.
1597	*/
1598	void nemR3NativeReset(PVM pVM)
1599	{
1600	RT_NOREF(pVM);
1601	}
1602
1603
1604	/**
1605	* Reset CPU due to INIT IPI or hot (un)plugging.
1606	*
1607	* @param pVCpu The cross context virtual CPU structure of the CPU being
1608	* reset.
1609	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
1610	*/
1611	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
1612	{
1613	RT_NOREF(pVCpu, fInitIpi);
1614	}
1615
1616
1617	/**
1618	* Returns the byte size from the given access SAS value.
1619	*
1620	* @returns Number of bytes to transfer.
1621	* @param uSas The SAS value to convert.
1622	*/
1623	DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
1624	{
1625	switch (uSas)
1626	{
1627	case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
1628	case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
1629	case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
1630	case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
1631	default:
1632	AssertReleaseFailed();
1633	}
1634
1635	return 0;
1636	}
1637
1638
1639	/**
1640	* Sets the given general purpose register to the given value.
1641	*
1642	* @param pVCpu The cross context virtual CPU structure of the
1643	* calling EMT.
1644	* @param uReg The register index.
1645	* @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
1646	* @param fSignExtend Flag whether to sign extend the value.
1647	* @param u64Val The value.
1648	*/
1649	DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
1650	{
1651	AssertReturnVoid(uReg < 31);
1652
1653	if (f64BitReg)
1654	pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
1655	else
1656	pVCpu->cpum.GstCtx.aGRegs[uReg].x = (uint64_t)(fSignExtend ? (int32_t)u64Val : (uint32_t)u64Val);
1657
1658	/* Mark the register as not extern anymore. */
1659	switch (uReg)
1660	{
1661	case 0:
1662	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1663	break;
1664	case 1:
1665	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1666	break;
1667	case 2:
1668	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1669	break;
1670	case 3:
1671	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1672	break;
1673	default:
1674	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1675	/** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1676	}
1677	}
1678
1679
1680	/**
1681	* Gets the given general purpose register and returns the value.
1682	*
1683	* @returns Value from the given register.
1684	* @param pVCpu The cross context virtual CPU structure of the
1685	* calling EMT.
1686	* @param uReg The register index.
1687	*/
1688	DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1689	{
1690	AssertReturn(uReg <= ARMV8_AARCH64_REG_ZR, 0);
1691
1692	if (uReg == ARMV8_AARCH64_REG_ZR)
1693	return 0;
1694
1695	/** @todo Import the register if extern. */
1696	AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1697
1698	return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1699	}
1700
1701
1702	/**
1703	* Works on the data abort exception (which will be a MMIO access most of the time).
1704	*
1705	* @returns VBox strict status code.
1706	* @param pVM The cross context VM structure.
1707	* @param pVCpu The cross context virtual CPU structure of the
1708	* calling EMT.
1709	* @param uIss The instruction specific syndrome value.
1710	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1711	* @param GCPtrDataAbrt The virtual GC address causing the data abort.
1712	* @param GCPhysDataAbrt The physical GC address which caused the data abort.
1713	*/
1714	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1715	RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1716	{
1717	bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1718	bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1719	bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1720	bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1721	bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1722	uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1723	uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1724	size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1725	LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1726	fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1727
1728	RT_NOREF(fL2Fault, GCPtrDataAbrt);
1729
1730	if (fWrite)
1731	{
1732	/*
1733	* Check whether this is one of the dirty tracked regions, mark it as dirty
1734	* and enable write support for this region again.
1735	*
1736	* This is required for proper VRAM tracking or the display might not get updated
1737	* and it is impossible to use the PGM generic facility as it operates on guest page sizes
1738	* but setting protection flags with Hypervisor.framework works only host page sized regions, so
1739	* we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1740	* which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1741	* write access again (due to a missing interpreter right now).
1742	*/
1743	for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1744	{
1745	PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1746
1747	if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1748	&& GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1749	{
1750	pMmio2Region->fDirty = true;
1751
1752	uint8_t u2State;
1753	int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1754	NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE \| NEM_PAGE_PROT_WRITE, &u2State);
1755
1756	/* Restart the instruction if there is no instruction syndrome available. */
1757	if (RT_FAILURE(rc) \|\| !fIsv)
1758	return rc;
1759	}
1760	}
1761	}
1762
1763	VBOXSTRICTRC rcStrict;
1764	if (fIsv)
1765	{
1766	EMHistoryAddExit(pVCpu,
1767	fWrite
1768	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1769	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1770	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1771
1772	uint64_t u64Val = 0;
1773	if (fWrite)
1774	{
1775	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1776	rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1777	Log4(("MmioExit/%u: %08RX64: WRITE %#RGp LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1778	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1779	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1780	}
1781	else
1782	{
1783	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1784	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1785	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1786	&u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1787	if (rcStrict == VINF_SUCCESS)
1788	nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1789	}
1790	}
1791	else
1792	{
1793	/** @todo Our UEFI firmware accesses the flash region with the following instruction
1794	* when the NVRAM actually contains data:
1795	* ldrb w9, [x6, #-0x0001]!
1796	* This is too complicated for the hardware so the ISV bit is not set. Until there
1797	* is a proper IEM implementation we just handle this here for now to avoid annoying
1798	* users too much.
1799	*/
1800	/* The following ASSUMES that the vCPU state is completely synced. */
1801
1802	/* Read instruction. */
1803	RTGCPTR GCPtrPage = pVCpu->cpum.GstCtx.Pc.u64 & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
1804	const void *pvPageR3 = NULL;
1805	PGMPAGEMAPLOCK PageMapLock;
1806
1807	rcStrict = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrPage, &pvPageR3, &PageMapLock);
1808	if (rcStrict == VINF_SUCCESS)
1809	{
1810	uint32_t u32Instr = (uint32_t )((uint8_t *)pvPageR3 + (pVCpu->cpum.GstCtx.Pc.u64 - GCPtrPage));
1811	PGMPhysReleasePageMappingLock(pVCpu->pVMR3, &PageMapLock);
1812
1813	DISSTATE Dis;
1814	rcStrict = DISInstrWithPrefetchedBytes((uintptr_t)pVCpu->cpum.GstCtx.Pc.u64, DISCPUMODE_ARMV8_A64, 0 /fFilter - none /,
1815	&u32Instr, sizeof(u32Instr), NULL, NULL, &Dis, NULL);
1816	if (rcStrict == VINF_SUCCESS)
1817	{
1818	if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDRB
1819	&& Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1820	&& Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1821	&& Dis.aParams[1].armv8.enmType == kDisArmv8OpParmAddrInGpr
1822	&& Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit
1823	&& (Dis.aParams[1].fUse & DISUSE_PRE_INDEXED))
1824	{
1825	/* The fault address is already the final address. */
1826	uint8_t bVal = 0;
1827	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &bVal, 1, PGMACCESSORIGIN_HM);
1828	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1829	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, sizeof(bVal), sizeof(bVal),
1830	&bVal, VBOXSTRICTRC_VAL(rcStrict) ));
1831	if (rcStrict == VINF_SUCCESS)
1832	{
1833	nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, bVal);
1834	/* Update the indexed register. */
1835	pVCpu->cpum.GstCtx.aGRegs[Dis.aParams[1].armv8.Op.Reg.idReg].x += Dis.aParams[1].armv8.u.offBase;
1836	}
1837	}
1838	/*
1839	* Seeing the following with the Windows 11/ARM TPM driver:
1840	* %fffff800e5342888 48 25 45 29 ldp w8, w9, [x10, #+0x0028]
1841	*/
1842	else if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDP
1843	&& Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1844	&& Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1845	&& Dis.aParams[1].armv8.enmType == kDisArmv8OpParmReg
1846	&& Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1847	&& Dis.aParams[2].armv8.enmType == kDisArmv8OpParmAddrInGpr
1848	&& Dis.aParams[2].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit)
1849	{
1850	/** @todo This is tricky to handle if the first register read returns something else than VINF_SUCCESS... */
1851	/* The fault address is already the final address. */
1852	uint32_t u32Val1 = 0;
1853	uint32_t u32Val2 = 0;
1854	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u32Val1, sizeof(u32Val1), PGMACCESSORIGIN_HM);
1855	if (rcStrict == VINF_SUCCESS)
1856	rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt + sizeof(uint32_t), &u32Val2, sizeof(u32Val2), PGMACCESSORIGIN_HM);
1857	Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.Rhxs %.Rhxs rcStrict=%Rrc\n",
1858	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, 2 * sizeof(uint32_t), sizeof(u32Val1),
1859	&u32Val1, sizeof(u32Val2), &u32Val2, VBOXSTRICTRC_VAL(rcStrict) ));
1860	if (rcStrict == VINF_SUCCESS)
1861	{
1862	nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, u32Val1);
1863	nemR3DarwinSetGReg(pVCpu, Dis.aParams[1].armv8.Op.Reg.idReg, false /f64BitReg/, false /fSignExtend/, u32Val2);
1864	}
1865	}
1866	/* T O D O:
1867	* Recent W11:
1868	* x0=ffffb804ea3217d8 x1=ffffe28437802000 x2=0000000000000424 x3=fffff802e5716030
1869	* x4=ffffe28437802424 x5=ffffb804ea321bfc x6=000000000080009c x7=000000000080009c
1870	* x8=ffff87849fefc788 x9=ffff87849fefc788 x10=000000000000001c x11=ffffb804ea32909c
1871	* x12=000000000000001c x13=000000000000009c x14=ffffb804ea3290a8 x15=ffffd580b2b1f7d8
1872	* x16=0000f6999080cdbe x17=0000f6999080cdbe x18=ffffd08158fbf000 x19=ffffb804ea3217d0
1873	* x20=0000000000000001 x21=0000000000000004 x22=ffffb804ea321660 x23=000047fb15cdefd8
1874	* x24=0000000000000000 x25=ffffb804ea2f1080 x26=0000000000000000 x27=0000000000000380
1875	* x28=0000000000000000 x29=ffff87849fefc7e0 x30=fffff802e57120b0
1876	* pc=fffff802e5713c20 pstate=00000000a0001344
1877	* sp_el0=ffff87849fefc7e0 sp_el1=ffff87849e462400 elr_el1=fffff802e98889c8
1878	* pl061gpio!start_seg1_.text+0x2c20:
1879	* %fffff802e5713c20 23 00 c0 3d ldr q3, [x1]
1880	* VBoxDbg> format %%(%@x1)
1881	* Guest physical address: %%ffddd000
1882	* VBoxDbg> info mmio
1883	* MMIO registrations: 12 (186 allocated)
1884	* ## Ctx Size Mapping PCI Description
1885	* 0 R3 00000000000c0000 0000000004000000-00000000040bffff Flash Memory
1886	* [snip]
1887	* 11 R3 0000000000001000 00000000ffddd000-00000000ffdddfff PL061
1888	*/
1889	else
1890	AssertLogRelMsgFailedReturn(("pc=%#RX64: %#x opcode=%d\n",
1891	pVCpu->cpum.GstCtx.Pc.u64, Dis.Instr.au32[0], Dis.pCurInstr->uOpcode),
1892	VERR_NEM_IPE_2);
1893	}
1894	}
1895	}
1896
1897	if (rcStrict == VINF_SUCCESS)
1898	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1899
1900	return rcStrict;
1901	}
1902
1903
1904	/**
1905	* Works on the trapped MRS, MSR and system instruction exception.
1906	*
1907	* @returns VBox strict status code.
1908	* @param pVM The cross context VM structure.
1909	* @param pVCpu The cross context virtual CPU structure of the
1910	* calling EMT.
1911	* @param uIss The instruction specific syndrome value.
1912	* @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1913	*/
1914	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1915	{
1916	bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1917	uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1918	uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1919	uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1920	uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1921	uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1922	uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1923	uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1924	LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1925	fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1926
1927	/** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1928	EMHistoryAddExit(pVCpu,
1929	fRead
1930	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1931	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1932	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1933
1934	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1935	uint64_t u64Val = 0;
1936	if (fRead)
1937	{
1938	RT_NOREF(pVM);
1939	rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1940	Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1941	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1942	VBOXSTRICTRC_VAL(rcStrict) ));
1943	if (rcStrict == VINF_SUCCESS)
1944	nemR3DarwinSetGReg(pVCpu, uReg, true /f64BitReg/, false /fSignExtend/, u64Val);
1945	}
1946	else
1947	{
1948	u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1949	rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1950	Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1951	pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1952	VBOXSTRICTRC_VAL(rcStrict) ));
1953	}
1954
1955	if (rcStrict == VINF_SUCCESS)
1956	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1957
1958	return rcStrict;
1959	}
1960
1961
1962	/**
1963	* Works on the trapped HVC instruction exception.
1964	*
1965	* @returns VBox strict status code.
1966	* @param pVM The cross context VM structure.
1967	* @param pVCpu The cross context virtual CPU structure of the
1968	* calling EMT.
1969	* @param uIss The instruction specific syndrome value.
1970	* @param fAdvancePc Flag whether to advance the guest program counter.
1971	*/
1972	static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fAdvancePc = false)
1973	{
1974	uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1975	LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1976
1977	#if 0 /** @todo For later */
1978	EMHistoryAddExit(pVCpu,
1979	fRead
1980	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1981	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1982	pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1983	#endif
1984
1985	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1986	if (u16Imm == 0)
1987	{
1988	/** @todo Raise exception to EL1 if PSCI not configured. */
1989	/** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1990	uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_AARCH64_REG_X0].w;
1991	bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1992	uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1993	uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1994	if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1995	{
1996	switch (uFunNum)
1997	{
1998	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1999	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
2000	break;
2001	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
2002	rcStrict = VMR3PowerOff(pVM->pUVM);
2003	break;
2004	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
2005	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
2006	{
2007	bool fHaltOnReset;
2008	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
2009	if (RT_SUCCESS(rc) && fHaltOnReset)
2010	{
2011	Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
2012	rcStrict = VINF_EM_HALT;
2013	}
2014	else
2015	{
2016	/** @todo pVM->pdm.s.fResetFlags = fFlags; */
2017	VM_FF_SET(pVM, VM_FF_RESET);
2018	rcStrict = VINF_EM_RESET;
2019	}
2020	break;
2021	}
2022	case ARM_PSCI_FUNC_ID_CPU_ON:
2023	{
2024	uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
2025	RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X2);
2026	uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X3);
2027	VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
2028	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, true /f64BitReg/, false /fSignExtend/, ARM_PSCI_STS_SUCCESS);
2029	break;
2030	}
2031	case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
2032	{
2033	uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_AARCH64_REG_X1);
2034	switch (u32FunNum)
2035	{
2036	case ARM_PSCI_FUNC_ID_PSCI_VERSION:
2037	case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
2038	case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
2039	case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
2040	case ARM_PSCI_FUNC_ID_CPU_ON:
2041	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
2042	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
2043	false /f64BitReg/, false /fSignExtend/,
2044	(uint64_t)ARM_PSCI_STS_SUCCESS);
2045	break;
2046	default:
2047	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0,
2048	false /f64BitReg/, false /fSignExtend/,
2049	(uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
2050	}
2051	break;
2052	}
2053	case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
2054	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, ARM_PSCI_MIGRATE_INFO_TYPE_TOS_NOT_PRESENT);
2055	break;
2056	default:
2057	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
2058	}
2059	}
2060	else
2061	nemR3DarwinSetGReg(pVCpu, ARMV8_AARCH64_REG_X0, false /f64BitReg/, false /fSignExtend/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
2062	}
2063
2064	/** @todo What to do if immediate is != 0? */
2065
2066	if ( rcStrict == VINF_SUCCESS
2067	&& fAdvancePc)
2068	pVCpu->cpum.GstCtx.Pc.u64 += sizeof(uint32_t);
2069
2070	return rcStrict;
2071	}
2072
2073
2074	/**
2075	* Handles an exception VM exit.
2076	*
2077	* @returns VBox strict status code.
2078	* @param pVM The cross context VM structure.
2079	* @param pVCpu The cross context virtual CPU structure of the
2080	* calling EMT.
2081	* @param pExit Pointer to the exit information.
2082	*/
2083	static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
2084	{
2085	uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
2086	uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
2087	bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
2088
2089	LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2090	pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2091
2092	switch (uEc)
2093	{
2094	case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
2095	return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
2096	pExit->exception.physical_address);
2097	case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
2098	return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
2099	case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
2100	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
2101	case ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN:
2102	return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss, true);
2103	case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
2104	{
2105	/* No need to halt if there is an interrupt pending already. */
2106	if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ)))
2107	{
2108	LogFlowFunc(("IRQ \| FIQ set => VINF_SUCCESS\n"));
2109	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2110	return VINF_SUCCESS;
2111	}
2112
2113	/* Set the vTimer expiration in order to get out of the halt at the right point in time. */
2114	if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
2115	&& !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
2116	{
2117	uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
2118
2119	/* Check whether it expired and start executing guest code. */
2120	if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
2121	{
2122	LogFlowFunc(("Guest timer expired (cTicksVTimer=%RU64 CntvCValEl0=%RU64) => VINF_SUCCESS\n",
2123	cTicksVTimer, pVCpu->cpum.GstCtx.CntvCValEl0));
2124	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2125	return VINF_SUCCESS;
2126	}
2127
2128	uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
2129	uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
2130
2131	/*
2132	* Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
2133	* + scheduling overhead which would increase the wakeup latency.
2134	* So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
2135	* between CPU load when the guest is idle and performance).
2136	*/
2137	if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
2138	{
2139	LogFlowFunc(("Guest timer expiration < 2ms (cNanoSecsVTimerToExpire=%RU64) => VINF_SUCCESS\n",
2140	cNanoSecsVTimerToExpire));
2141	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2142	return VINF_SUCCESS;
2143	}
2144
2145	LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
2146	cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
2147	TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
2148	}
2149	else
2150	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2151
2152	pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2153	return VINF_EM_HALT;
2154	}
2155	case ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN:
2156	{
2157	VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx);
2158	/** @todo Forward genuine guest traps to the guest by either single stepping instruction with debug exception trapping turned off
2159	* or create instruction interpreter and inject exception ourselves. */
2160	Assert(rcStrict == VINF_EM_DBG_BREAKPOINT);
2161	return rcStrict;
2162	}
2163	case ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL:
2164	return VINF_EM_DBG_STEPPED;
2165	case ARMV8_ESR_EL2_EC_UNKNOWN:
2166	default:
2167	LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2168	uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2169	AssertReleaseFailed();
2170	return VERR_NOT_IMPLEMENTED;
2171	}
2172
2173	return VINF_SUCCESS;
2174	}
2175
2176
2177	/**
2178	* Handles an exit from hv_vcpu_run().
2179	*
2180	* @returns VBox strict status code.
2181	* @param pVM The cross context VM structure.
2182	* @param pVCpu The cross context virtual CPU structure of the
2183	* calling EMT.
2184	*/
2185	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
2186	{
2187	int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
2188	if (RT_FAILURE(rc))
2189	return rc;
2190
2191	#ifdef LOG_ENABLED
2192	if (LogIs3Enabled())
2193	nemR3DarwinLogState(pVM, pVCpu);
2194	#endif
2195
2196	hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
2197	switch (pExit->reason)
2198	{
2199	case HV_EXIT_REASON_CANCELED:
2200	return VINF_EM_RAW_INTERRUPT;
2201	case HV_EXIT_REASON_EXCEPTION:
2202	return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
2203	case HV_EXIT_REASON_VTIMER_ACTIVATED:
2204	{
2205	LogFlowFunc(("vTimer got activated\n"));
2206	TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2207	pVCpu->nem.s.fVTimerActivated = true;
2208	return PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /fAsserted/);
2209	}
2210	default:
2211	AssertReleaseFailed();
2212	break;
2213	}
2214
2215	return VERR_INVALID_STATE;
2216	}
2217
2218
2219	/**
2220	* Runs the guest once until an exit occurs.
2221	*
2222	* @returns HV status code.
2223	* @param pVM The cross context VM structure.
2224	* @param pVCpu The cross context virtual CPU structure.
2225	*/
2226	static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
2227	{
2228	TMNotifyStartOfExecution(pVM, pVCpu);
2229
2230	hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
2231
2232	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2233
2234	return hrc;
2235	}
2236
2237
2238	/**
2239	* Prepares the VM to run the guest.
2240	*
2241	* @returns Strict VBox status code.
2242	* @param pVM The cross context VM structure.
2243	* @param pVCpu The cross context virtual CPU structure.
2244	* @param fSingleStepping Flag whether we run in single stepping mode.
2245	*/
2246	static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
2247	{
2248	#ifdef LOG_ENABLED
2249	bool fIrq = false;
2250	bool fFiq = false;
2251
2252	if (LogIs3Enabled())
2253	nemR3DarwinLogState(pVM, pVCpu);
2254	#endif
2255
2256	int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
2257	AssertRCReturn(rc, rc);
2258
2259	/* In single stepping mode we will re-read SPSR and MDSCR and enable the software step bits. */
2260	if (fSingleStepping)
2261	{
2262	uint64_t u64Tmp;
2263	hv_return_t hrc = hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
2264	if (hrc == HV_SUCCESS)
2265	{
2266	u64Tmp \|= ARMV8_SPSR_EL2_AARCH64_SS;
2267	hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, u64Tmp);
2268	}
2269
2270	hrc \|= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, &u64Tmp);
2271	if (hrc == HV_SUCCESS)
2272	{
2273	u64Tmp \|= ARMV8_MDSCR_EL1_AARCH64_SS;
2274	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, u64Tmp);
2275	}
2276
2277	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2278	}
2279
2280	/* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
2281	if (pVCpu->nem.s.fVTimerActivated)
2282	{
2283	/* Read the CNTV_CTL_EL0 register. */
2284	uint64_t u64CntvCtl = 0;
2285
2286	hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
2287	AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2288
2289	if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_IMASK \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2290	!= (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE \| ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2291	{
2292	/* Clear the interrupt. */
2293	PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /fAsserted/);
2294
2295	pVCpu->nem.s.fVTimerActivated = false;
2296	hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /vtimer_is_masked/);
2297	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2298	}
2299	}
2300
2301	/* Set the pending interrupt state. */
2302	hv_return_t hrc = HV_SUCCESS;
2303	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
2304	{
2305	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
2306	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2307	#ifdef LOG_ENABLED
2308	fIrq = true;
2309	#endif
2310	}
2311	else
2312	{
2313	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
2314	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2315	}
2316
2317	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
2318	{
2319	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
2320	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2321	#ifdef LOG_ENABLED
2322	fFiq = true;
2323	#endif
2324	}
2325	else
2326	{
2327	hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
2328	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2329	}
2330
2331	LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
2332	pVCpu->nem.s.fEventPending = false;
2333	return VINF_SUCCESS;
2334	}
2335
2336
2337	/**
2338	* The normal runloop (no debugging features enabled).
2339	*
2340	* @returns Strict VBox status code.
2341	* @param pVM The cross context VM structure.
2342	* @param pVCpu The cross context virtual CPU structure.
2343	*/
2344	static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
2345	{
2346	/*
2347	* The run loop.
2348	*
2349	* Current approach to state updating to use the sledgehammer and sync
2350	* everything every time. This will be optimized later.
2351	*/
2352
2353	/* Update the vTimer offset after resuming if instructed. */
2354	if (pVCpu->nem.s.fVTimerOffUpdate)
2355	{
2356	hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2357	if (hrc != HV_SUCCESS)
2358	return nemR3DarwinHvSts2Rc(hrc);
2359
2360	pVCpu->nem.s.fVTimerOffUpdate = false;
2361
2362	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2363	if (hrc == HV_SUCCESS)
2364	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2365	if (hrc != HV_SUCCESS)
2366	return nemR3DarwinHvSts2Rc(hrc);
2367	}
2368
2369	/*
2370	* Poll timers and run for a bit.
2371	*/
2372	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2373	* the whole polling job when timers have changed... */
2374	uint64_t offDeltaIgnored;
2375	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2376	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2377	for (unsigned iLoop = 0;; iLoop++)
2378	{
2379	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
2380	if (rcStrict != VINF_SUCCESS)
2381	break;
2382
2383	hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2384	if (hrc == HV_SUCCESS)
2385	{
2386	/*
2387	* Deal with the message.
2388	*/
2389	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2390	if (rcStrict == VINF_SUCCESS)
2391	{ /* hopefully likely */ }
2392	else
2393	{
2394	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2395	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2396	break;
2397	}
2398	}
2399	else
2400	{
2401	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2402	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2403	}
2404	} /* the run loop */
2405
2406	return rcStrict;
2407	}
2408
2409
2410	/**
2411	* The debug runloop.
2412	*
2413	* @returns Strict VBox status code.
2414	* @param pVM The cross context VM structure.
2415	* @param pVCpu The cross context virtual CPU structure.
2416	*/
2417	static VBOXSTRICTRC nemR3DarwinRunGuestDebug(PVM pVM, PVMCPU pVCpu)
2418	{
2419	/*
2420	* The run loop.
2421	*
2422	* Current approach to state updating to use the sledgehammer and sync
2423	* everything every time. This will be optimized later.
2424	*/
2425
2426	bool const fSavedSingleInstruction = pVCpu->nem.s.fSingleInstruction;
2427	pVCpu->nem.s.fSingleInstruction = pVCpu->nem.s.fSingleInstruction \|\| DBGFIsStepping(pVCpu);
2428	pVCpu->nem.s.fUsingDebugLoop = true;
2429
2430	/* Trap any debug exceptions. */
2431	hv_return_t hrc = hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, true);
2432	if (hrc != HV_SUCCESS)
2433	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2434	"Trapping debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2435
2436	/* Update the vTimer offset after resuming if instructed. */
2437	if (pVCpu->nem.s.fVTimerOffUpdate)
2438	{
2439	hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2440	if (hrc != HV_SUCCESS)
2441	return nemR3DarwinHvSts2Rc(hrc);
2442
2443	pVCpu->nem.s.fVTimerOffUpdate = false;
2444
2445	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2446	if (hrc == HV_SUCCESS)
2447	hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2448	if (hrc != HV_SUCCESS)
2449	return nemR3DarwinHvSts2Rc(hrc);
2450	}
2451
2452	/* Save the guest MDSCR_EL1 */
2453	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG \| CPUMCTX_EXTRN_PSTATE);
2454	uint64_t u64RegMdscrEl1 = pVCpu->cpum.GstCtx.Mdscr.u64;
2455
2456	/*
2457	* Poll timers and run for a bit.
2458	*/
2459	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2460	* the whole polling job when timers have changed... */
2461	uint64_t offDeltaIgnored;
2462	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2463	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2464	for (unsigned iLoop = 0;; iLoop++)
2465	{
2466	bool const fStepping = pVCpu->nem.s.fSingleInstruction;
2467
2468	rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, fStepping);
2469	if (rcStrict != VINF_SUCCESS)
2470	break;
2471
2472	hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2473	if (hrc == HV_SUCCESS)
2474	{
2475	/*
2476	* Deal with the message.
2477	*/
2478	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2479	if (rcStrict == VINF_SUCCESS)
2480	{ /* hopefully likely */ }
2481	else
2482	{
2483	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2484	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2485	break;
2486	}
2487	}
2488	else
2489	{
2490	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2491	pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2492	}
2493	} /* the run loop */
2494
2495	/* Restore single stepping state. */
2496	if (pVCpu->nem.s.fSingleInstruction)
2497	{
2498	/** @todo This ASSUMES that guest code being single stepped is not modifying the MDSCR_EL1 register. */
2499	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG \| CPUMCTX_EXTRN_PSTATE);
2500	Assert(pVCpu->cpum.GstCtx.Mdscr.u64 & ARMV8_MDSCR_EL1_AARCH64_SS);
2501
2502	pVCpu->cpum.GstCtx.Mdscr.u64 = u64RegMdscrEl1;
2503	}
2504
2505	/* Restore debug exceptions trapping. */
2506	hrc \|= hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, false);
2507	if (hrc != HV_SUCCESS)
2508	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2509	"Clearing trapping of debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2510
2511	pVCpu->nem.s.fUsingDebugLoop = false;
2512	pVCpu->nem.s.fSingleInstruction = fSavedSingleInstruction;
2513
2514	return rcStrict;
2515
2516	}
2517
2518
2519	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2520	{
2521	#ifdef LOG_ENABLED
2522	if (LogIs3Enabled())
2523	nemR3DarwinLogState(pVM, pVCpu);
2524	#endif
2525
2526	AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
2527
2528	if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
2529	{
2530	/*
2531	* Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
2532	* Need to do it here and not during the init because loading a saved state might change the ID registers from what
2533	* done in the call to CPUMR3PopulateFeaturesByIdRegisters().
2534	*/
2535	static const struct
2536	{
2537	const char *pszIdReg;
2538	hv_sys_reg_t enmHvReg;
2539	uint32_t offIdStruct;
2540	} s_aSysIdRegs[] =
2541	{
2542	#define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMIDREGS, a_CpumIdReg) }
2543	ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
2544	ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
2545	ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
2546	ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
2547	ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
2548	ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
2549	ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
2550	ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
2551	ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
2552	#undef ID_SYS_REG_CREATE
2553	};
2554
2555	PCCPUMIDREGS pIdRegsGst = NULL;
2556	int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
2557	AssertRCReturn(rc, rc);
2558
2559	for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
2560	{
2561	uint64_t pu64 = (uint64_t )((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
2562	hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
2563	if (hrc != HV_SUCCESS)
2564	return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2565	"Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2566	}
2567
2568	pVCpu->nem.s.fIdRegsSynced = true;
2569	}
2570
2571	/*
2572	* Try switch to NEM runloop state.
2573	*/
2574	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2575	{ /* likely */ }
2576	else
2577	{
2578	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2579	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2580	return VINF_SUCCESS;
2581	}
2582
2583	VBOXSTRICTRC rcStrict;
2584	if ( !pVCpu->nem.s.fUseDebugLoop
2585	/&& !nemR3DarwinAnyExpensiveProbesEnabled()/
2586	&& !DBGFIsStepping(pVCpu)
2587	&& !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledSwBreakpoints)
2588	rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
2589	else
2590	rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
2591
2592	if (rcStrict == VINF_EM_RAW_TO_R3)
2593	rcStrict = VINF_SUCCESS;
2594
2595	/*
2596	* Convert any pending HM events back to TRPM due to premature exits.
2597	*
2598	* This is because execution may continue from IEM and we would need to inject
2599	* the event from there (hence place it back in TRPM).
2600	*/
2601	if (pVCpu->nem.s.fEventPending)
2602	{
2603	/** @todo */
2604	}
2605
2606
2607	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2608	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2609
2610	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2611	{
2612	/* Try anticipate what we might need. */
2613	uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2614	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2615	\|\| RT_FAILURE(rcStrict))
2616	fImport = CPUMCTX_EXTRN_ALL;
2617	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ \| VMCPU_FF_INTERRUPT_FIQ
2618	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2619	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2620
2621	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2622	{
2623	/* Only import what is external currently. */
2624	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2625	if (RT_SUCCESS(rc2))
2626	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2627	else if (RT_SUCCESS(rcStrict))
2628	rcStrict = rc2;
2629	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2630	pVCpu->cpum.GstCtx.fExtrn = 0;
2631	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2632	}
2633	else
2634	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2635	}
2636	else
2637	{
2638	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2639	pVCpu->cpum.GstCtx.fExtrn = 0;
2640	}
2641
2642	return rcStrict;
2643	}
2644
2645
2646	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2647	{
2648	RT_NOREF(pVM, pVCpu);
2649	return true; /** @todo Are there any cases where we have to emulate? */
2650	}
2651
2652
2653	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2654	{
2655	VMCPU_ASSERT_EMT(pVCpu);
2656	bool fOld = pVCpu->nem.s.fSingleInstruction;
2657	pVCpu->nem.s.fSingleInstruction = fEnable;
2658	pVCpu->nem.s.fUseDebugLoop = fEnable \|\| pVM->nem.s.fUseDebugLoop;
2659	return fOld;
2660	}
2661
2662
2663	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2664	{
2665	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2666
2667	RT_NOREF(pVM, fFlags);
2668
2669	hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
2670	if (hrc != HV_SUCCESS)
2671	LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
2672	}
2673
2674
2675	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
2676	{
2677	RT_NOREF(pVM, fUseDebugLoop);
2678	//AssertReleaseFailed();
2679	return false;
2680	}
2681
2682
2683	DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
2684	{
2685	RT_NOREF(pVM, pVCpu, fUseDebugLoop);
2686	return fUseDebugLoop;
2687	}
2688
2689
2690	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2691	uint8_t pu2State, uint32_t puNemRange)
2692	{
2693	RT_NOREF(pVM, puNemRange);
2694
2695	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2696	#if defined(VBOX_WITH_PGM_NEM_MODE)
2697	if (pvR3)
2698	{
2699	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2700	if (RT_FAILURE(rc))
2701	{
2702	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2703	return VERR_NEM_MAP_PAGES_FAILED;
2704	}
2705	}
2706	return VINF_SUCCESS;
2707	#else
2708	RT_NOREF(pVM, GCPhys, cb, pvR3);
2709	return VERR_NEM_MAP_PAGES_FAILED;
2710	#endif
2711	}
2712
2713
2714	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2715	{
2716	RT_NOREF(pVM);
2717	return true;
2718	}
2719
2720
2721	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2722	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
2723	{
2724	RT_NOREF(pvRam);
2725
2726	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2727	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2728
2729	#if defined(VBOX_WITH_PGM_NEM_MODE)
2730	/*
2731	* Unmap the RAM we're replacing.
2732	*/
2733	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2734	{
2735	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2736	if (RT_SUCCESS(rc))
2737	{ /* likely */ }
2738	else if (pvMmio2)
2739	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2740	GCPhys, cb, fFlags, rc));
2741	else
2742	{
2743	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2744	GCPhys, cb, fFlags, rc));
2745	return VERR_NEM_UNMAP_PAGES_FAILED;
2746	}
2747	}
2748
2749	/*
2750	* Map MMIO2 if any.
2751	*/
2752	if (pvMmio2)
2753	{
2754	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2755
2756	/* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
2757	uint32_t fProt = NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE;
2758	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2759	{
2760	/* Find a slot for dirty tracking. */
2761	PNEMHVMMIO2REGION pMmio2Region = NULL;
2762	uint32_t idSlot;
2763	for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
2764	{
2765	if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
2766	&& pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
2767	{
2768	pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
2769	break;
2770	}
2771	}
2772
2773	if (!pMmio2Region)
2774	{
2775	LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
2776	return VERR_NEM_MAP_PAGES_FAILED;
2777	}
2778
2779	pMmio2Region->GCPhysStart = GCPhys;
2780	pMmio2Region->GCPhysLast = GCPhys + cb - 1;
2781	pMmio2Region->fDirty = false;
2782	*puNemRange = idSlot;
2783	}
2784	else
2785	fProt \|= NEM_PAGE_PROT_WRITE;
2786
2787	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
2788	if (RT_FAILURE(rc))
2789	{
2790	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2791	GCPhys, cb, fFlags, pvMmio2, rc));
2792	return VERR_NEM_MAP_PAGES_FAILED;
2793	}
2794	}
2795	else
2796	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2797
2798	#else
2799	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2800	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2801	#endif
2802	return VINF_SUCCESS;
2803	}
2804
2805
2806	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2807	void pvRam, void pvMmio2, uint32_t *puNemRange)
2808	{
2809	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2810	return VINF_SUCCESS;
2811	}
2812
2813
2814	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2815	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
2816	{
2817	RT_NOREF(pVM, puNemRange);
2818
2819	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
2820	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
2821
2822	int rc = VINF_SUCCESS;
2823	#if defined(VBOX_WITH_PGM_NEM_MODE)
2824	/*
2825	* Unmap the MMIO2 pages.
2826	*/
2827	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2828	* we may have more stuff to unmap even in case of pure MMIO... */
2829	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2830	{
2831	rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2832	if (RT_FAILURE(rc))
2833	{
2834	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2835	GCPhys, cb, fFlags, rc));
2836	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2837	}
2838
2839	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2840	{
2841	/* Reset tracking structure. */
2842	uint32_t idSlot = *puNemRange;
2843	*puNemRange = UINT32_MAX;
2844
2845	Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2846	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
2847	pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
2848	pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
2849	}
2850	}
2851
2852	/* Ensure the page is masked as unmapped if relevant. */
2853	Assert(!pu2State \|\| *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
2854
2855	/*
2856	* Restore the RAM we replaced.
2857	*/
2858	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2859	{
2860	AssertPtr(pvRam);
2861	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2862	if (RT_SUCCESS(rc))
2863	{ /* likely */ }
2864	else
2865	{
2866	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2867	rc = VERR_NEM_MAP_PAGES_FAILED;
2868	}
2869	}
2870
2871	RT_NOREF(pvMmio2);
2872	#else
2873	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2874	if (pu2State)
2875	*pu2State = UINT8_MAX;
2876	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2877	#endif
2878	return rc;
2879	}
2880
2881
2882	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2883	void *pvBitmap, size_t cbBitmap)
2884	{
2885	LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
2886	Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2887
2888	/* Keep it simple for now and mark everything as dirty if it is. */
2889	int rc = VINF_SUCCESS;
2890	if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
2891	{
2892	ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
2893
2894	pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
2895	/* Restore as RX only. */
2896	uint8_t u2State;
2897	rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, &u2State);
2898	}
2899	else
2900	ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
2901
2902	return rc;
2903	}
2904
2905
2906	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2907	uint8_t pu2State, uint32_t puNemRange)
2908	{
2909	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2910
2911	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2912	*pu2State = UINT8_MAX;
2913	*puNemRange = 0;
2914	return VINF_SUCCESS;
2915	}
2916
2917
2918	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2919	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
2920	{
2921	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
2922	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
2923	*pu2State = UINT8_MAX;
2924
2925	#if defined(VBOX_WITH_PGM_NEM_MODE)
2926	/*
2927	* (Re-)map readonly.
2928	*/
2929	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2930
2931	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2932	AssertRC(rc);
2933
2934	rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE, pu2State);
2935	if (RT_FAILURE(rc))
2936	{
2937	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2938	GCPhys, cb, pvPages, fFlags, rc));
2939	return VERR_NEM_MAP_PAGES_FAILED;
2940	}
2941	RT_NOREF(fFlags, puNemRange);
2942	return VINF_SUCCESS;
2943	#else
2944	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2945	return VERR_NEM_MAP_PAGES_FAILED;
2946	#endif
2947	}
2948
2949
2950	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2951	RTR3PTR pvMemR3, uint8_t *pu2State)
2952	{
2953	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2954	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2955
2956	*pu2State = UINT8_MAX;
2957	#if defined(VBOX_WITH_PGM_NEM_MODE)
2958	if (pvMemR3)
2959	{
2960	/* Unregister what was there before. */
2961	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2962	AssertRC(rc);
2963
2964	rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE, pu2State);
2965	AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
2966	pvMemR3, GCPhys, cb, rc));
2967	}
2968	RT_NOREF(enmKind);
2969	#else
2970	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
2971	AssertFailed();
2972	#endif
2973	}
2974
2975
2976	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2977	{
2978	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2979	RT_NOREF(pVCpu, fEnabled);
2980	}
2981
2982
2983	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2984	{
2985	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2986	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2987	}
2988
2989
2990	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2991	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2992	{
2993	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2994	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2995	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2996	}
2997
2998
2999	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
3000	PGMPAGETYPE enmType, uint8_t *pu2State)
3001	{
3002	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3003	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3004	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
3005
3006	AssertFailed();
3007	return VINF_SUCCESS;
3008	}
3009
3010
3011	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
3012	PGMPAGETYPE enmType, uint8_t *pu2State)
3013	{
3014	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3015	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3016	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
3017	}
3018
3019
3020	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
3021	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
3022	{
3023	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3024	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
3025	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
3026
3027	AssertFailed();
3028	}
3029
3030
3031	/**
3032	* Interface for importing state on demand (used by IEM).
3033	*
3034	* @returns VBox status code.
3035	* @param pVCpu The cross context CPU structure.
3036	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
3037	*/
3038	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
3039	{
3040	LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
3041	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
3042
3043	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
3044	}
3045
3046
3047	/**
3048	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
3049	*
3050	* @returns VBox status code.
3051	* @param pVCpu The cross context CPU structure.
3052	* @param pcTicks Where to return the CPU tick count.
3053	* @param puAux Where to return the TSC_AUX register value.
3054	*/
3055	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
3056	{
3057	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
3058	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
3059
3060	if (puAux)
3061	*puAux = 0;
3062	pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; / This is the host timer minus the offset. */
3063	return VINF_SUCCESS;
3064	}
3065
3066
3067	/**
3068	* Resumes CPU clock (TSC) on all virtual CPUs.
3069	*
3070	* This is called by TM when the VM is started, restored, resumed or similar.
3071	*
3072	* @returns VBox status code.
3073	* @param pVM The cross context VM structure.
3074	* @param pVCpu The cross context CPU structure of the calling EMT.
3075	* @param uPausedTscValue The TSC value at the time of pausing.
3076	*/
3077	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
3078	{
3079	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
3080	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
3081	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
3082
3083	/*
3084	* Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
3085	* the new offset to let the guest not notice the pause.
3086	*/
3087	uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
3088	Assert(u64TscNew >= uPausedTscValue);
3089	LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
3090	pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
3091	pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
3092
3093	pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
3094
3095	/*
3096	* Set the flag to update the vTimer offset when the vCPU resumes for the first time
3097	* (needs to be done on the actual EMT).
3098	*/
3099	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3100	{
3101	PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
3102	pVCpuDst->nem.s.fVTimerOffUpdate = true;
3103	}
3104
3105	return VINF_SUCCESS;
3106	}
3107
3108
3109	/**
3110	* Returns features supported by the NEM backend.
3111	*
3112	* @returns Flags of features supported by the native NEM backend.
3113	* @param pVM The cross context VM structure.
3114	*/
3115	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
3116	{
3117	RT_NOREF(pVM);
3118	/*
3119	* Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
3120	* and unrestricted guest execution support so we can safely return these flags here always.
3121	*/
3122	return NEM_FEAT_F_NESTED_PAGING \| NEM_FEAT_F_FULL_GST_EXEC \| NEM_FEAT_F_XSAVE_XRSTOR;
3123	}
3124
3125
3126	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
3127	*
3128	* @todo Add notes as the implementation progresses...
3129	*/
3130

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 107316

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