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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp@ 108464

Last change on this file since 108464 was 108414, checked in by vboxsync, 2 months ago

VMM/NEMR3Native-darwin-armv8.cpp,VMM/GICR3Nem-darwin.cpp: Small cleanups after the GIC interface refactor [build fix]
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1/* $Id: NEMR3Native-darwin-armv8.cpp 108414 2025-02-28 09:29:04Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework, ARMv8 variant.
4 *
5 * Log group 2: Exit logging.
6 * Log group 3: Log context on exit.
7 * Log group 5: Ring-3 memory management
8 */
9
10/*
11 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
12 *
13 * This file is part of VirtualBox base platform packages, as
14 * available from https://www.virtualbox.org.
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License
18 * as published by the Free Software Foundation, in version 3 of the
19 * License.
20 *
21 * This program is distributed in the hope that it will be useful, but
22 * WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <https://www.gnu.org/licenses>.
28 *
29 * SPDX-License-Identifier: GPL-3.0-only
30 */
31
32
33/*********************************************************************************************************************************
34* Header Files *
35*********************************************************************************************************************************/
36#define LOG_GROUP LOG_GROUP_NEM
37#define VMCPU_INCL_CPUM_GST_CTX
38#include <VBox/vmm/nem.h>
39#include <VBox/vmm/iem.h>
40#include <VBox/vmm/em.h>
41#include <VBox/vmm/pdmgic.h>
42#include <VBox/vmm/pdm.h>
43#include <VBox/vmm/dbgftrace.h>
44#include <VBox/vmm/gcm.h>
45#include "NEMInternal.h"
46#include <VBox/vmm/vmcc.h>
47#include <VBox/vmm/vmm.h>
48#include <VBox/dis.h>
49#include <VBox/gic.h>
50#include "dtrace/VBoxVMM.h"
51
52#include <iprt/armv8.h>
53#include <iprt/asm.h>
54#include <iprt/asm-arm.h>
55#include <iprt/asm-math.h>
56#include <iprt/ldr.h>
57#include <iprt/mem.h>
58#include <iprt/path.h>
59#include <iprt/string.h>
60#include <iprt/system.h>
61#include <iprt/utf16.h>
62
63#include <iprt/formats/arm-psci.h>
64
65#include <mach/mach_time.h>
66#include <mach/kern_return.h>
67
68#include <Hypervisor/Hypervisor.h>
69
70
71/*********************************************************************************************************************************
72* Defined Constants And Macros *
73*********************************************************************************************************************************/
74
75
76/*********************************************************************************************************************************
77* Structures and Typedefs *
78*********************************************************************************************************************************/
79
80#if MAC_OS_X_VERSION_MIN_REQUIRED < 150000
81
82/* Since 15.0+ */
83typedef enum hv_gic_distributor_reg_t : uint16_t
84{
85 HV_GIC_DISTRIBUTOR_REG_GICD_CTLR,
86 HV_GIC_DISTRIBUTOR_REG_GICD_ICACTIVER0
87 /** @todo */
88} hv_gic_distributor_reg_t;
89
90
91typedef enum hv_gic_icc_reg_t : uint16_t
92{
93 HV_GIC_ICC_REG_PMR_EL1,
94 HV_GIC_ICC_REG_BPR0_EL1,
95 HV_GIC_ICC_REG_AP0R0_EL1,
96 HV_GIC_ICC_REG_AP1R0_EL1,
97 HV_GIC_ICC_REG_RPR_EL1,
98 HV_GIC_ICC_REG_BPR1_EL1,
99 HV_GIC_ICC_REG_CTLR_EL1,
100 HV_GIC_ICC_REG_SRE_EL1,
101 HV_GIC_ICC_REG_IGRPEN0_EL1,
102 HV_GIC_ICC_REG_IGRPEN1_EL1,
103 HV_GIC_ICC_REG_INVALID,
104 /** @todo */
105} hv_gic_icc_reg_t;
106
107
108typedef enum hv_gic_ich_reg_t : uint16_t
109{
110 HV_GIC_ICH_REG_AP0R0_EL2
111 /** @todo */
112} hv_gic_ich_reg_t;
113
114
115typedef enum hv_gic_icv_reg_t : uint16_t
116{
117 HV_GIC_ICV_REG_AP0R0_EL1
118 /** @todo */
119} hv_gic_icv_reg_t;
120
121
122typedef enum hv_gic_msi_reg_t : uint16_t
123{
124 HV_GIC_REG_GICM_SET_SPI_NSR
125 /** @todo */
126} hv_gic_msi_reg_t;
127
128
129typedef enum hv_gic_redistributor_reg_t : uint16_t
130{
131 HV_GIC_REDISTRIBUTOR_REG_GICR_ICACTIVER0
132 /** @todo */
133} hv_gic_redistributor_reg_t;
134
135
136typedef enum hv_gic_intid_t : uint16_t
137{
138 HV_GIC_INT_EL1_PHYSICAL_TIMER = 23,
139 HV_GIC_INT_EL1_VIRTUAL_TIMER = 25,
140 HV_GIC_INT_EL2_PHYSICAL_TIMER = 26,
141 HV_GIC_INT_MAINTENANCE = 27,
142 HV_GIC_INT_PERFORMANCE_MONITOR = 30
143} hv_gic_intid_t;
144
145#else
146# define HV_GIC_ICC_REG_INVALID (hv_gic_icc_reg_t)UINT16_MAX
147#endif
148
149typedef hv_vm_config_t FN_HV_VM_CONFIG_CREATE(void);
150typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_SUPPORTED(bool *el2_supported);
151typedef hv_return_t FN_HV_VM_CONFIG_GET_EL2_ENABLED(hv_vm_config_t config, bool *el2_enabled);
152typedef hv_return_t FN_HV_VM_CONFIG_SET_EL2_ENABLED(hv_vm_config_t config, bool el2_enabled);
153
154typedef struct hv_gic_config_s *hv_gic_config_t;
155typedef hv_return_t FN_HV_GIC_CREATE(hv_gic_config_t gic_config);
156typedef hv_return_t FN_HV_GIC_RESET(void);
157typedef hv_gic_config_t FN_HV_GIC_CONFIG_CREATE(void);
158typedef hv_return_t FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t distributor_base_address);
159typedef hv_return_t FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE(hv_gic_config_t config, hv_ipa_t redistributor_base_address);
160typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE(hv_gic_config_t config, hv_ipa_t msi_region_base_address);
161typedef hv_return_t FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE(hv_gic_config_t config, uint32_t msi_intid_base, uint32_t msi_intid_count);
162
163typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE(hv_vcpu_t vcpu, hv_ipa_t *redistributor_base_address);
164typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE(size_t *redistributor_region_size);
165typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_SIZE(size_t *redistributor_size);
166typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_SIZE(size_t *distributor_size);
167typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT(size_t *distributor_base_alignment);
168typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT(size_t *redistributor_base_alignment);
169typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT(size_t *msi_region_base_alignment);
170typedef hv_return_t FN_HV_GIC_GET_MSI_REGION_SIZE(size_t *msi_region_size);
171typedef hv_return_t FN_HV_GIC_GET_SPI_INTERRUPT_RANGE(uint32_t *spi_intid_base, uint32_t *spi_intid_count);
172
173typedef struct hv_gic_state_s *hv_gic_state_t;
174typedef hv_gic_state_t FN_HV_GIC_STATE_CREATE(void);
175typedef hv_return_t FN_HV_GIC_SET_STATE(const void *gic_state_data, size_t gic_state_size);
176typedef hv_return_t FN_HV_GIC_STATE_GET_SIZE(hv_gic_state_t state, size_t *gic_state_size);
177typedef hv_return_t FN_HV_GIC_STATE_GET_DATA(hv_gic_state_t state, void *gic_state_data);
178
179typedef hv_return_t FN_HV_GIC_SEND_MSI(hv_ipa_t address, uint32_t intid);
180typedef hv_return_t FN_HV_GIC_SET_SPI(uint32_t intid, bool level);
181
182typedef hv_return_t FN_HV_GIC_GET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t *value);
183typedef hv_return_t FN_HV_GIC_GET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t *value);
184typedef hv_return_t FN_HV_GIC_GET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t *value);
185typedef hv_return_t FN_HV_GIC_GET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t *value);
186typedef hv_return_t FN_HV_GIC_GET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t *value);
187typedef hv_return_t FN_HV_GIC_GET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t *value);
188
189typedef hv_return_t FN_HV_GIC_SET_DISTRIBUTOR_REG(hv_gic_distributor_reg_t reg, uint64_t value);
190typedef hv_return_t FN_HV_GIC_SET_MSI_REG(hv_gic_msi_reg_t reg, uint64_t value);
191typedef hv_return_t FN_HV_GIC_SET_ICC_REG(hv_vcpu_t vcpu, hv_gic_icc_reg_t reg, uint64_t value);
192typedef hv_return_t FN_HV_GIC_SET_ICH_REG(hv_vcpu_t vcpu, hv_gic_ich_reg_t reg, uint64_t value);
193typedef hv_return_t FN_HV_GIC_SET_ICV_REG(hv_vcpu_t vcpu, hv_gic_icv_reg_t reg, uint64_t value);
194typedef hv_return_t FN_HV_GIC_SET_REDISTRIBUTOR_REG(hv_vcpu_t vcpu, hv_gic_redistributor_reg_t reg, uint64_t value);
195
196typedef hv_return_t FN_HV_GIC_GET_INTID(hv_gic_intid_t interrupt, uint32_t *intid);
197
198
199/*********************************************************************************************************************************
200* Global Variables *
201*********************************************************************************************************************************/
202/** @name Optional APIs imported from Hypervisor.framework.
203 * @{ */
204static FN_HV_VM_CONFIG_CREATE *g_pfnHvVmConfigCreate = NULL; /* Since 13.0 */
205static FN_HV_VM_CONFIG_GET_EL2_SUPPORTED *g_pfnHvVmConfigGetEl2Supported = NULL; /* Since 15.0 */
206static FN_HV_VM_CONFIG_GET_EL2_ENABLED *g_pfnHvVmConfigGetEl2Enabled = NULL; /* Since 15.0 */
207static FN_HV_VM_CONFIG_SET_EL2_ENABLED *g_pfnHvVmConfigSetEl2Enabled = NULL; /* Since 15.0 */
208
209static FN_HV_GIC_CREATE *g_pfnHvGicCreate = NULL; /* Since 15.0 */
210static FN_HV_GIC_RESET *g_pfnHvGicReset = NULL; /* Since 15.0 */
211static FN_HV_GIC_CONFIG_CREATE *g_pfnHvGicConfigCreate = NULL; /* Since 15.0 */
212static FN_HV_GIC_CONFIG_SET_DISTRIBUTOR_BASE *g_pfnHvGicConfigSetDistributorBase = NULL; /* Since 15.0 */
213static FN_HV_GIC_CONFIG_SET_REDISTRIBUTOR_BASE *g_pfnHvGicConfigSetRedistributorBase = NULL; /* Since 15.0 */
214static FN_HV_GIC_CONFIG_SET_MSI_REGION_BASE *g_pfnHvGicConfigSetMsiRegionBase = NULL; /* Since 15.0 */
215static FN_HV_GIC_CONFIG_SET_MSI_INTERRUPT_RANGE *g_pfnHvGicConfigSetMsiInterruptRange = NULL; /* Since 15.0 */
216static FN_HV_GIC_GET_REDISTRIBUTOR_BASE *g_pfnHvGicGetRedistributorBase = NULL; /* Since 15.0 */
217static FN_HV_GIC_GET_REDISTRIBUTOR_REGION_SIZE *g_pfnHvGicGetRedistributorRegionSize = NULL; /* Since 15.0 */
218static FN_HV_GIC_GET_REDISTRIBUTOR_SIZE *g_pfnHvGicGetRedistributorSize = NULL; /* Since 15.0 */
219static FN_HV_GIC_GET_DISTRIBUTOR_SIZE *g_pfnHvGicGetDistributorSize = NULL; /* Since 15.0 */
220static FN_HV_GIC_GET_DISTRIBUTOR_BASE_ALIGNMENT *g_pfnHvGicGetDistributorBaseAlignment = NULL; /* Since 15.0 */
221static FN_HV_GIC_GET_REDISTRIBUTOR_BASE_ALIGNMENT *g_pfnHvGicGetRedistributorBaseAlignment = NULL; /* Since 15.0 */
222static FN_HV_GIC_GET_MSI_REGION_BASE_ALIGNMENT *g_pfnHvGicGetMsiRegionBaseAlignment = NULL; /* Since 15.0 */
223static FN_HV_GIC_GET_MSI_REGION_SIZE *g_pfnHvGicGetMsiRegionSize = NULL; /* Since 15.0 */
224static FN_HV_GIC_GET_SPI_INTERRUPT_RANGE *g_pfnHvGicGetSpiInterruptRange = NULL; /* Since 15.0 */
225static FN_HV_GIC_STATE_CREATE *g_pfnHvGicStateCreate = NULL; /* Since 15.0 */
226static FN_HV_GIC_SET_STATE *g_pfnHvGicSetState = NULL; /* Since 15.0 */
227static FN_HV_GIC_STATE_GET_SIZE *g_pfnHvGicStateGetSize = NULL; /* Since 15.0 */
228static FN_HV_GIC_STATE_GET_DATA *g_pfnHvGicStateGetData = NULL; /* Since 15.0 */
229static FN_HV_GIC_SEND_MSI *g_pfnHvGicSendMsi = NULL; /* Since 15.0 */
230 FN_HV_GIC_SET_SPI *g_pfnHvGicSetSpi = NULL; /* Since 15.0, exported for GICR3Nem-darwin.cpp */
231static FN_HV_GIC_GET_DISTRIBUTOR_REG *g_pfnHvGicGetDistributorReg = NULL; /* Since 15.0 */
232static FN_HV_GIC_GET_MSI_REG *g_pfnHvGicGetMsiReg = NULL; /* Since 15.0 */
233static FN_HV_GIC_GET_ICC_REG *g_pfnHvGicGetIccReg = NULL; /* Since 15.0 */
234static FN_HV_GIC_GET_ICH_REG *g_pfnHvGicGetIchReg = NULL; /* Since 15.0 */
235static FN_HV_GIC_GET_ICV_REG *g_pfnHvGicGetIcvReg = NULL; /* Since 15.0 */
236static FN_HV_GIC_GET_REDISTRIBUTOR_REG *g_pfnHvGicGetRedistributorReg = NULL; /* Since 15.0 */
237static FN_HV_GIC_SET_DISTRIBUTOR_REG *g_pfnHvGicSetDistributorReg = NULL; /* Since 15.0 */
238static FN_HV_GIC_SET_MSI_REG *g_pfnHvGicSetMsiReg = NULL; /* Since 15.0 */
239static FN_HV_GIC_SET_ICC_REG *g_pfnHvGicSetIccReg = NULL; /* Since 15.0 */
240static FN_HV_GIC_SET_ICH_REG *g_pfnHvGicSetIchReg = NULL; /* Since 15.0 */
241static FN_HV_GIC_SET_ICV_REG *g_pfnHvGicSetIcvReg = NULL; /* Since 15.0 */
242static FN_HV_GIC_SET_REDISTRIBUTOR_REG *g_pfnHvGicSetRedistributorReg = NULL; /* Since 15.0 */
243static FN_HV_GIC_GET_INTID *g_pfnHvGicGetIntid = NULL; /* Since 15.0 */
244/** @} */
245
246
247/**
248 * Import instructions.
249 */
250static const struct
251{
252 void **ppfn; /**< The function pointer variable. */
253 const char *pszName; /**< The function name. */
254} g_aImports[] =
255{
256#define NEM_DARWIN_IMPORT(a_Pfn, a_Name) { (void **)&(a_Pfn), #a_Name }
257 NEM_DARWIN_IMPORT(g_pfnHvVmConfigCreate, hv_vm_config_create),
258 NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Supported, hv_vm_config_get_el2_supported),
259 NEM_DARWIN_IMPORT(g_pfnHvVmConfigGetEl2Enabled, hv_vm_config_get_el2_enabled),
260 NEM_DARWIN_IMPORT(g_pfnHvVmConfigSetEl2Enabled, hv_vm_config_set_el2_enabled),
261
262 NEM_DARWIN_IMPORT(g_pfnHvGicCreate, hv_gic_create),
263 NEM_DARWIN_IMPORT(g_pfnHvGicReset, hv_gic_reset),
264 NEM_DARWIN_IMPORT(g_pfnHvGicConfigCreate, hv_gic_config_create),
265 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetDistributorBase, hv_gic_config_set_distributor_base),
266 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetRedistributorBase, hv_gic_config_set_redistributor_base),
267 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiRegionBase, hv_gic_config_set_msi_region_base),
268 NEM_DARWIN_IMPORT(g_pfnHvGicConfigSetMsiInterruptRange, hv_gic_config_set_msi_interrupt_range),
269 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBase, hv_gic_get_redistributor_base),
270 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorRegionSize, hv_gic_get_redistributor_region_size),
271 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorSize, hv_gic_get_redistributor_size),
272 NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorSize, hv_gic_get_distributor_size),
273 NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorBaseAlignment, hv_gic_get_distributor_base_alignment),
274 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorBaseAlignment, hv_gic_get_redistributor_base_alignment),
275 NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionBaseAlignment, hv_gic_get_msi_region_base_alignment),
276 NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiRegionSize, hv_gic_get_msi_region_size),
277 NEM_DARWIN_IMPORT(g_pfnHvGicGetSpiInterruptRange, hv_gic_get_spi_interrupt_range),
278 NEM_DARWIN_IMPORT(g_pfnHvGicStateCreate, hv_gic_state_create),
279 NEM_DARWIN_IMPORT(g_pfnHvGicSetState, hv_gic_set_state),
280 NEM_DARWIN_IMPORT(g_pfnHvGicStateGetSize, hv_gic_state_get_size),
281 NEM_DARWIN_IMPORT(g_pfnHvGicStateGetData, hv_gic_state_get_data),
282 NEM_DARWIN_IMPORT(g_pfnHvGicSendMsi, hv_gic_send_msi),
283 NEM_DARWIN_IMPORT(g_pfnHvGicSetSpi, hv_gic_set_spi),
284 NEM_DARWIN_IMPORT(g_pfnHvGicGetDistributorReg, hv_gic_get_distributor_reg),
285 NEM_DARWIN_IMPORT(g_pfnHvGicGetMsiReg, hv_gic_get_msi_reg),
286 NEM_DARWIN_IMPORT(g_pfnHvGicGetIccReg, hv_gic_get_icc_reg),
287 NEM_DARWIN_IMPORT(g_pfnHvGicGetIchReg, hv_gic_get_ich_reg),
288 NEM_DARWIN_IMPORT(g_pfnHvGicGetIcvReg, hv_gic_get_icv_reg),
289 NEM_DARWIN_IMPORT(g_pfnHvGicGetRedistributorReg, hv_gic_get_redistributor_reg),
290 NEM_DARWIN_IMPORT(g_pfnHvGicSetDistributorReg, hv_gic_set_distributor_reg),
291 NEM_DARWIN_IMPORT(g_pfnHvGicSetMsiReg, hv_gic_set_msi_reg),
292 NEM_DARWIN_IMPORT(g_pfnHvGicSetIccReg, hv_gic_set_icc_reg),
293 NEM_DARWIN_IMPORT(g_pfnHvGicSetIchReg, hv_gic_set_ich_reg),
294 NEM_DARWIN_IMPORT(g_pfnHvGicSetIcvReg, hv_gic_set_icv_reg),
295 NEM_DARWIN_IMPORT(g_pfnHvGicSetRedistributorReg, hv_gic_set_redistributor_reg),
296 NEM_DARWIN_IMPORT(g_pfnHvGicGetIntid, hv_gic_get_intid)
297#undef NEM_DARWIN_IMPORT
298};
299
300
301/*
302 * Let the preprocessor alias the APIs to import variables for better autocompletion.
303 */
304#ifndef IN_SLICKEDIT
305# define hv_vm_config_create g_pfnHvVmConfigCreate
306# define hv_vm_config_get_el2_supported g_pfnHvVmConfigGetEl2Supported
307# define hv_vm_config_get_el2_enabled g_pfnHvVmConfigGetEl2Enabled
308# define hv_vm_config_set_el2_enabled g_pfnHvVmConfigSetEl2Enabled
309
310# define hv_gic_create g_pfnHvGicCreate
311# define hv_gic_reset g_pfnHvGicReset
312# define hv_gic_config_create g_pfnHvGicConfigCreate
313# define hv_gic_config_set_distributor_base g_pfnHvGicConfigSetDistributorBase
314# define hv_gic_config_set_redistributor_base g_pfnHvGicConfigSetRedistributorBase
315# define hv_gic_config_set_msi_region_base g_pfnHvGicConfigSetMsiRegionBase
316# define hv_gic_config_set_msi_interrupt_range g_pfnHvGicConfigSetMsiInterruptRange
317# define hv_gic_get_redistributor_base g_pfnHvGicGetRedistributorBase
318# define hv_gic_get_redistributor_region_size g_pfnHvGicGetRedistributorRegionSize
319# define hv_gic_get_redistributor_size g_pfnHvGicGetRedistributorSize
320# define hv_gic_get_distributor_size g_pfnHvGicGetDistributorSize
321# define hv_gic_get_distributor_base_alignment g_pfnHvGicGetDistributorBaseAlignment
322# define hv_gic_get_redistributor_base_alignment g_pfnHvGicGetRedistributorBaseAlignment
323# define hv_gic_get_msi_region_base_alignment g_pfnHvGicGetMsiRegionBaseAlignment
324# define hv_gic_get_msi_region_size g_pfnHvGicGetMsiRegionSize
325# define hv_gic_get_spi_interrupt_range g_pfnHvGicGetSpiInterruptRange
326# define hv_gic_state_create g_pfnHvGicStateCreate
327# define hv_gic_set_state g_pfnHvGicSetState
328# define hv_gic_state_get_size g_pfnHvGicStateGetSize
329# define hv_gic_state_get_data g_pfnHvGicStateGetData
330# define hv_gic_send_msi g_pfnHvGicSendMsi
331# define hv_gic_set_spi g_pfnHvGicSetSpi
332# define hv_gic_get_distributor_reg g_pfnHvGicGetDistributorReg
333# define hv_gic_get_msi_reg g_pfnHvGicGetMsiReg
334# define hv_gic_get_icc_reg g_pfnHvGicGetIccReg
335# define hv_gic_get_ich_reg g_pfnHvGicGetIchReg
336# define hv_gic_get_icv_reg g_pfnHvGicGetIcvReg
337# define hv_gic_get_redistributor_reg g_pfnHvGicGetRedistributorReg
338# define hv_gic_set_distributor_reg g_pfnHvGicSetDistributorReg
339# define hv_gic_set_msi_reg g_pfnHvGicSetMsiReg
340# define hv_gic_set_icc_reg g_pfnHvGicSetIccReg
341# define hv_gic_set_ich_reg g_pfnHvGicSetIchReg
342# define hv_gic_set_icv_reg g_pfnHvGicSetIcvReg
343# define hv_gic_set_redistributor_reg g_pfnHvGicSetRedistributorReg
344# define hv_gic_get_intid g_pfnHvGicGetIntid
345#endif
346
347
348/** The general registers. */
349static const struct
350{
351 hv_reg_t enmHvReg;
352 uint32_t fCpumExtrn;
353 uint32_t offCpumCtx;
354} s_aCpumRegs[] =
355{
356#define CPUM_GREG_EMIT_X0_X3(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X ## a_Idx, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
357#define CPUM_GREG_EMIT_X4_X28(a_Idx) { HV_REG_X ## a_Idx, CPUMCTX_EXTRN_X4_X28, RT_UOFFSETOF(CPUMCTX, aGRegs[a_Idx].x) }
358 CPUM_GREG_EMIT_X0_X3(0),
359 CPUM_GREG_EMIT_X0_X3(1),
360 CPUM_GREG_EMIT_X0_X3(2),
361 CPUM_GREG_EMIT_X0_X3(3),
362 CPUM_GREG_EMIT_X4_X28(4),
363 CPUM_GREG_EMIT_X4_X28(5),
364 CPUM_GREG_EMIT_X4_X28(6),
365 CPUM_GREG_EMIT_X4_X28(7),
366 CPUM_GREG_EMIT_X4_X28(8),
367 CPUM_GREG_EMIT_X4_X28(9),
368 CPUM_GREG_EMIT_X4_X28(10),
369 CPUM_GREG_EMIT_X4_X28(11),
370 CPUM_GREG_EMIT_X4_X28(12),
371 CPUM_GREG_EMIT_X4_X28(13),
372 CPUM_GREG_EMIT_X4_X28(14),
373 CPUM_GREG_EMIT_X4_X28(15),
374 CPUM_GREG_EMIT_X4_X28(16),
375 CPUM_GREG_EMIT_X4_X28(17),
376 CPUM_GREG_EMIT_X4_X28(18),
377 CPUM_GREG_EMIT_X4_X28(19),
378 CPUM_GREG_EMIT_X4_X28(20),
379 CPUM_GREG_EMIT_X4_X28(21),
380 CPUM_GREG_EMIT_X4_X28(22),
381 CPUM_GREG_EMIT_X4_X28(23),
382 CPUM_GREG_EMIT_X4_X28(24),
383 CPUM_GREG_EMIT_X4_X28(25),
384 CPUM_GREG_EMIT_X4_X28(26),
385 CPUM_GREG_EMIT_X4_X28(27),
386 CPUM_GREG_EMIT_X4_X28(28),
387 { HV_REG_FP, CPUMCTX_EXTRN_FP, RT_UOFFSETOF(CPUMCTX, aGRegs[29].x) },
388 { HV_REG_LR, CPUMCTX_EXTRN_LR, RT_UOFFSETOF(CPUMCTX, aGRegs[30].x) },
389 { HV_REG_PC, CPUMCTX_EXTRN_PC, RT_UOFFSETOF(CPUMCTX, Pc.u64) },
390 { HV_REG_FPCR, CPUMCTX_EXTRN_FPCR, RT_UOFFSETOF(CPUMCTX, fpcr) },
391 { HV_REG_FPSR, CPUMCTX_EXTRN_FPSR, RT_UOFFSETOF(CPUMCTX, fpsr) }
392#undef CPUM_GREG_EMIT_X0_X3
393#undef CPUM_GREG_EMIT_X4_X28
394};
395/** SIMD/FP registers. */
396static const struct
397{
398 hv_simd_fp_reg_t enmHvReg;
399 uint32_t offCpumCtx;
400} s_aCpumFpRegs[] =
401{
402#define CPUM_VREG_EMIT(a_Idx) { HV_SIMD_FP_REG_Q ## a_Idx, RT_UOFFSETOF(CPUMCTX, aVRegs[a_Idx].v) }
403 CPUM_VREG_EMIT(0),
404 CPUM_VREG_EMIT(1),
405 CPUM_VREG_EMIT(2),
406 CPUM_VREG_EMIT(3),
407 CPUM_VREG_EMIT(4),
408 CPUM_VREG_EMIT(5),
409 CPUM_VREG_EMIT(6),
410 CPUM_VREG_EMIT(7),
411 CPUM_VREG_EMIT(8),
412 CPUM_VREG_EMIT(9),
413 CPUM_VREG_EMIT(10),
414 CPUM_VREG_EMIT(11),
415 CPUM_VREG_EMIT(12),
416 CPUM_VREG_EMIT(13),
417 CPUM_VREG_EMIT(14),
418 CPUM_VREG_EMIT(15),
419 CPUM_VREG_EMIT(16),
420 CPUM_VREG_EMIT(17),
421 CPUM_VREG_EMIT(18),
422 CPUM_VREG_EMIT(19),
423 CPUM_VREG_EMIT(20),
424 CPUM_VREG_EMIT(21),
425 CPUM_VREG_EMIT(22),
426 CPUM_VREG_EMIT(23),
427 CPUM_VREG_EMIT(24),
428 CPUM_VREG_EMIT(25),
429 CPUM_VREG_EMIT(26),
430 CPUM_VREG_EMIT(27),
431 CPUM_VREG_EMIT(28),
432 CPUM_VREG_EMIT(29),
433 CPUM_VREG_EMIT(30),
434 CPUM_VREG_EMIT(31)
435#undef CPUM_VREG_EMIT
436};
437/** Debug system registers. */
438static const struct
439{
440 hv_sys_reg_t enmHvReg;
441 uint32_t offCpumCtx;
442} s_aCpumDbgRegs[] =
443{
444#define CPUM_DBGREG_EMIT(a_BorW, a_Idx) \
445 { HV_SYS_REG_DBG ## a_BorW ## CR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Ctrl.u64) }, \
446 { HV_SYS_REG_DBG ## a_BorW ## VR ## a_Idx ## _EL1, RT_UOFFSETOF(CPUMCTX, a ## a_BorW ## p[a_Idx].Value.u64) }
447 /* Breakpoint registers. */
448 CPUM_DBGREG_EMIT(B, 0),
449 CPUM_DBGREG_EMIT(B, 1),
450 CPUM_DBGREG_EMIT(B, 2),
451 CPUM_DBGREG_EMIT(B, 3),
452 CPUM_DBGREG_EMIT(B, 4),
453 CPUM_DBGREG_EMIT(B, 5),
454 CPUM_DBGREG_EMIT(B, 6),
455 CPUM_DBGREG_EMIT(B, 7),
456 CPUM_DBGREG_EMIT(B, 8),
457 CPUM_DBGREG_EMIT(B, 9),
458 CPUM_DBGREG_EMIT(B, 10),
459 CPUM_DBGREG_EMIT(B, 11),
460 CPUM_DBGREG_EMIT(B, 12),
461 CPUM_DBGREG_EMIT(B, 13),
462 CPUM_DBGREG_EMIT(B, 14),
463 CPUM_DBGREG_EMIT(B, 15),
464 /* Watchpoint registers. */
465 CPUM_DBGREG_EMIT(W, 0),
466 CPUM_DBGREG_EMIT(W, 1),
467 CPUM_DBGREG_EMIT(W, 2),
468 CPUM_DBGREG_EMIT(W, 3),
469 CPUM_DBGREG_EMIT(W, 4),
470 CPUM_DBGREG_EMIT(W, 5),
471 CPUM_DBGREG_EMIT(W, 6),
472 CPUM_DBGREG_EMIT(W, 7),
473 CPUM_DBGREG_EMIT(W, 8),
474 CPUM_DBGREG_EMIT(W, 9),
475 CPUM_DBGREG_EMIT(W, 10),
476 CPUM_DBGREG_EMIT(W, 11),
477 CPUM_DBGREG_EMIT(W, 12),
478 CPUM_DBGREG_EMIT(W, 13),
479 CPUM_DBGREG_EMIT(W, 14),
480 CPUM_DBGREG_EMIT(W, 15),
481 { HV_SYS_REG_MDSCR_EL1, RT_UOFFSETOF(CPUMCTX, Mdscr.u64) }
482#undef CPUM_DBGREG_EMIT
483};
484/** PAuth key system registers. */
485static const struct
486{
487 hv_sys_reg_t enmHvReg;
488 uint32_t offCpumCtx;
489} s_aCpumPAuthKeyRegs[] =
490{
491 { HV_SYS_REG_APDAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apda.Low.u64) },
492 { HV_SYS_REG_APDAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apda.High.u64) },
493 { HV_SYS_REG_APDBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.Low.u64) },
494 { HV_SYS_REG_APDBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apdb.High.u64) },
495 { HV_SYS_REG_APGAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apga.Low.u64) },
496 { HV_SYS_REG_APGAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apga.High.u64) },
497 { HV_SYS_REG_APIAKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apia.Low.u64) },
498 { HV_SYS_REG_APIAKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apia.High.u64) },
499 { HV_SYS_REG_APIBKEYLO_EL1, RT_UOFFSETOF(CPUMCTX, Apib.Low.u64) },
500 { HV_SYS_REG_APIBKEYHI_EL1, RT_UOFFSETOF(CPUMCTX, Apib.High.u64) }
501};
502/** System registers. */
503static const struct
504{
505 hv_sys_reg_t enmHvReg;
506 uint32_t fCpumExtrn;
507 uint32_t offCpumCtx;
508} s_aCpumSysRegs[] =
509{
510 { HV_SYS_REG_SP_EL0, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64) },
511 { HV_SYS_REG_SP_EL1, CPUMCTX_EXTRN_SP, RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64) },
512 { HV_SYS_REG_SPSR_EL1, CPUMCTX_EXTRN_SPSR, RT_UOFFSETOF(CPUMCTX, Spsr.u64) },
513 { HV_SYS_REG_ELR_EL1, CPUMCTX_EXTRN_ELR, RT_UOFFSETOF(CPUMCTX, Elr.u64) },
514 { HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Sctlr.u64) },
515 { HV_SYS_REG_TCR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Tcr.u64) },
516 { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr0.u64) },
517 { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR, RT_UOFFSETOF(CPUMCTX, Ttbr1.u64) },
518 { HV_SYS_REG_VBAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, VBar.u64) },
519 { HV_SYS_REG_AFSR0_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr0.u64) },
520 { HV_SYS_REG_AFSR1_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Afsr1.u64) },
521 { HV_SYS_REG_AMAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Amair.u64) },
522 { HV_SYS_REG_CNTKCTL_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, CntKCtl.u64) },
523 { HV_SYS_REG_CONTEXTIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, ContextIdr.u64) },
524 { HV_SYS_REG_CPACR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Cpacr.u64) },
525 { HV_SYS_REG_CSSELR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Csselr.u64) },
526 { HV_SYS_REG_ESR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Esr.u64) },
527 { HV_SYS_REG_FAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Far.u64) },
528 { HV_SYS_REG_MAIR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Mair.u64) },
529 { HV_SYS_REG_PAR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, Par.u64) },
530 { HV_SYS_REG_TPIDRRO_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, TpIdrRoEl0.u64) },
531 { HV_SYS_REG_TPIDR_EL0, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[0].u64) },
532 { HV_SYS_REG_TPIDR_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, aTpIdr[1].u64) },
533 { HV_SYS_REG_MDCCINT_EL1, CPUMCTX_EXTRN_SYSREG_MISC, RT_UOFFSETOF(CPUMCTX, MDccInt.u64) }
534
535};
536/** EL2 support system registers. */
537static const struct
538{
539 uint16_t idSysReg;
540 uint32_t offCpumCtx;
541} s_aCpumEl2SysRegs[] =
542{
543 { ARMV8_AARCH64_SYSREG_CNTHCTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHCtlEl2.u64) },
544 { ARMV8_AARCH64_SYSREG_CNTHP_CTL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCtlEl2.u64) },
545 { ARMV8_AARCH64_SYSREG_CNTHP_CVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpCValEl2.u64) },
546 { ARMV8_AARCH64_SYSREG_CNTHP_TVAL_EL2, RT_UOFFSETOF(CPUMCTX, CntHpTValEl2.u64) },
547 { ARMV8_AARCH64_SYSREG_CNTVOFF_EL2, RT_UOFFSETOF(CPUMCTX, CntVOffEl2.u64) },
548 { ARMV8_AARCH64_SYSREG_CPTR_EL2, RT_UOFFSETOF(CPUMCTX, CptrEl2.u64) },
549 { ARMV8_AARCH64_SYSREG_ELR_EL2, RT_UOFFSETOF(CPUMCTX, ElrEl2.u64) },
550 { ARMV8_AARCH64_SYSREG_ESR_EL2, RT_UOFFSETOF(CPUMCTX, EsrEl2.u64) },
551 { ARMV8_AARCH64_SYSREG_FAR_EL2, RT_UOFFSETOF(CPUMCTX, FarEl2.u64) },
552 { ARMV8_AARCH64_SYSREG_HCR_EL2, RT_UOFFSETOF(CPUMCTX, HcrEl2.u64) },
553 { ARMV8_AARCH64_SYSREG_HPFAR_EL2, RT_UOFFSETOF(CPUMCTX, HpFarEl2.u64) },
554 { ARMV8_AARCH64_SYSREG_MAIR_EL2, RT_UOFFSETOF(CPUMCTX, MairEl2.u64) },
555 //{ ARMV8_AARCH64_SYSREG_MDCR_EL2, RT_UOFFSETOF(CPUMCTX, MdcrEl2.u64) },
556 { ARMV8_AARCH64_SYSREG_SCTLR_EL2, RT_UOFFSETOF(CPUMCTX, SctlrEl2.u64) },
557 { ARMV8_AARCH64_SYSREG_SPSR_EL2, RT_UOFFSETOF(CPUMCTX, SpsrEl2.u64) },
558 { ARMV8_AARCH64_SYSREG_SP_EL2, RT_UOFFSETOF(CPUMCTX, SpEl2.u64) },
559 { ARMV8_AARCH64_SYSREG_TCR_EL2, RT_UOFFSETOF(CPUMCTX, TcrEl2.u64) },
560 { ARMV8_AARCH64_SYSREG_TPIDR_EL2, RT_UOFFSETOF(CPUMCTX, TpidrEl2.u64) },
561 { ARMV8_AARCH64_SYSREG_TTBR0_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr0El2.u64) },
562 { ARMV8_AARCH64_SYSREG_TTBR1_EL2, RT_UOFFSETOF(CPUMCTX, Ttbr1El2.u64) },
563 { ARMV8_AARCH64_SYSREG_VBAR_EL2, RT_UOFFSETOF(CPUMCTX, VBarEl2.u64) },
564 { ARMV8_AARCH64_SYSREG_VMPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VMpidrEl2.u64) },
565 { ARMV8_AARCH64_SYSREG_VPIDR_EL2, RT_UOFFSETOF(CPUMCTX, VPidrEl2.u64) },
566 { ARMV8_AARCH64_SYSREG_VTCR_EL2, RT_UOFFSETOF(CPUMCTX, VTcrEl2.u64) },
567 { ARMV8_AARCH64_SYSREG_VTTBR_EL2, RT_UOFFSETOF(CPUMCTX, VTtbrEl2.u64) }
568};
569/** ID registers. */
570static const struct
571{
572 hv_feature_reg_t enmHvReg;
573 uint32_t offIdStruct;
574} s_aIdRegs[] =
575{
576 { HV_FEATURE_REG_ID_AA64DFR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Dfr0El1) },
577 { HV_FEATURE_REG_ID_AA64DFR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Dfr1El1) },
578 { HV_FEATURE_REG_ID_AA64ISAR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Isar0El1) },
579 { HV_FEATURE_REG_ID_AA64ISAR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Isar1El1) },
580 { HV_FEATURE_REG_ID_AA64MMFR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Mmfr0El1) },
581 { HV_FEATURE_REG_ID_AA64MMFR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Mmfr1El1) },
582 { HV_FEATURE_REG_ID_AA64MMFR2_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Mmfr2El1) },
583 { HV_FEATURE_REG_ID_AA64PFR0_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Pfr0El1) },
584 { HV_FEATURE_REG_ID_AA64PFR1_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegIdAa64Pfr1El1) },
585 { HV_FEATURE_REG_CLIDR_EL1, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegClidrEl1) },
586 { HV_FEATURE_REG_CTR_EL0, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegCtrEl0) },
587 { HV_FEATURE_REG_DCZID_EL0, RT_UOFFSETOF(CPUMARMV8IDREGS, u64RegDczidEl0) }
588};
589
590
591/*********************************************************************************************************************************
592* Internal Functions *
593*********************************************************************************************************************************/
594
595
596/**
597 * Converts a HV return code to a VBox status code.
598 *
599 * @returns VBox status code.
600 * @param hrc The HV return code to convert.
601 */
602DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
603{
604 if (hrc == HV_SUCCESS)
605 return VINF_SUCCESS;
606
607 switch (hrc)
608 {
609 case HV_ERROR: return VERR_INVALID_STATE;
610 case HV_BUSY: return VERR_RESOURCE_BUSY;
611 case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
612 case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
613 case HV_NO_DEVICE: return VERR_NOT_FOUND;
614 case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
615 }
616
617 return VERR_IPE_UNEXPECTED_STATUS;
618}
619
620
621/** Puts a name to a hypervisor framework status code. */
622static const char *nemR3DarwinHvStatusName(hv_return_t hrc)
623{
624 switch (hrc)
625 {
626 RT_CASE_RET_STR(HV_SUCCESS);
627 RT_CASE_RET_STR(HV_ERROR);
628 RT_CASE_RET_STR(HV_BUSY);
629 RT_CASE_RET_STR(HV_BAD_ARGUMENT);
630 RT_CASE_RET_STR(HV_ILLEGAL_GUEST_STATE);
631 RT_CASE_RET_STR(HV_NO_RESOURCES);
632 RT_CASE_RET_STR(HV_NO_DEVICE);
633 RT_CASE_RET_STR(HV_DENIED);
634 RT_CASE_RET_STR(HV_UNSUPPORTED);
635 }
636 return "";
637}
638
639
640#if 0 /* unused right now */
641/**
642 * Converts an ICC system register into Darwin's Hypervisor.Framework equivalent.
643 *
644 * @returns HvF's ICC system register.
645 * @param u32Reg The ARMv8 ICC system register.
646 */
647static hv_gic_icc_reg_t nemR3DarwinIccRegFromSysReg(uint32_t u32Reg)
648{
649 switch (u32Reg)
650 {
651 case ARMV8_AARCH64_SYSREG_ICC_PMR_EL1: return HV_GIC_ICC_REG_PMR_EL1;
652 case ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1: return HV_GIC_ICC_REG_INVALID;
653 case ARMV8_AARCH64_SYSREG_ICC_EOIR0_EL1: return HV_GIC_ICC_REG_INVALID;
654 case ARMV8_AARCH64_SYSREG_ICC_HPPIR0_EL1: return HV_GIC_ICC_REG_INVALID;
655 case ARMV8_AARCH64_SYSREG_ICC_BPR0_EL1: return HV_GIC_ICC_REG_BPR0_EL1;
656 case ARMV8_AARCH64_SYSREG_ICC_AP0R0_EL1: return HV_GIC_ICC_REG_AP0R0_EL1;
657 case ARMV8_AARCH64_SYSREG_ICC_AP0R1_EL1: return HV_GIC_ICC_REG_INVALID;
658 case ARMV8_AARCH64_SYSREG_ICC_AP0R2_EL1: return HV_GIC_ICC_REG_INVALID;
659 case ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1: return HV_GIC_ICC_REG_INVALID;
660 case ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1: return HV_GIC_ICC_REG_AP1R0_EL1;
661 case ARMV8_AARCH64_SYSREG_ICC_AP1R1_EL1: return HV_GIC_ICC_REG_INVALID;
662 case ARMV8_AARCH64_SYSREG_ICC_AP1R2_EL1: return HV_GIC_ICC_REG_INVALID;
663 case ARMV8_AARCH64_SYSREG_ICC_AP1R3_EL1: return HV_GIC_ICC_REG_INVALID;
664 case ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1: return HV_GIC_ICC_REG_INVALID;
665 case ARMV8_AARCH64_SYSREG_ICC_DIR_EL1: return HV_GIC_ICC_REG_INVALID;
666 case ARMV8_AARCH64_SYSREG_ICC_RPR_EL1: return HV_GIC_ICC_REG_RPR_EL1;
667 case ARMV8_AARCH64_SYSREG_ICC_SGI1R_EL1: return HV_GIC_ICC_REG_INVALID;
668 case ARMV8_AARCH64_SYSREG_ICC_ASGI1R_EL1: return HV_GIC_ICC_REG_INVALID;
669 case ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1: return HV_GIC_ICC_REG_INVALID;
670 case ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1: return HV_GIC_ICC_REG_INVALID;
671 case ARMV8_AARCH64_SYSREG_ICC_EOIR1_EL1: return HV_GIC_ICC_REG_INVALID;
672 case ARMV8_AARCH64_SYSREG_ICC_HPPIR1_EL1: return HV_GIC_ICC_REG_INVALID;
673 case ARMV8_AARCH64_SYSREG_ICC_BPR1_EL1: return HV_GIC_ICC_REG_BPR1_EL1;
674 case ARMV8_AARCH64_SYSREG_ICC_CTLR_EL1: return HV_GIC_ICC_REG_CTLR_EL1;
675 case ARMV8_AARCH64_SYSREG_ICC_SRE_EL1: return HV_GIC_ICC_REG_SRE_EL1;
676 case ARMV8_AARCH64_SYSREG_ICC_IGRPEN0_EL1: return HV_GIC_ICC_REG_IGRPEN0_EL1;
677 case ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1: return HV_GIC_ICC_REG_IGRPEN1_EL1;
678 }
679 AssertReleaseFailed();
680 return HV_GIC_ICC_REG_INVALID;
681}
682#endif
683
684
685/**
686 * Returns a human readable string of the given exception class.
687 *
688 * @returns Pointer to the string matching the given EC.
689 * @param u32Ec The exception class to return the string for.
690 */
691static const char *nemR3DarwinEsrEl2EcStringify(uint32_t u32Ec)
692{
693 switch (u32Ec)
694 {
695#define ARMV8_EC_CASE(a_Ec) case a_Ec: return #a_Ec
696 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_UNKNOWN);
697 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TRAPPED_WFX);
698 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_15);
699 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCRR_MRRC_COPROC15);
700 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MCR_MRC_COPROC_14);
701 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_LDC_STC);
702 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_SME_SVE_NEON);
703 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_VMRS);
704 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_PA_INSN);
705 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_LS64_EXCEPTION);
706 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_MRRC_COPROC14);
707 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_BTI_BRANCH_TARGET_EXCEPTION);
708 ARMV8_EC_CASE(ARMV8_ESR_EL2_ILLEGAL_EXECUTION_STATE);
709 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SVC_INSN);
710 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_HVC_INSN);
711 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_SMC_INSN);
712 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SVC_INSN);
713 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN);
714 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN);
715 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN);
716 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SVE_TRAPPED);
717 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_PAUTH_NV_TRAPPED_ERET_ERETAA_ERETAB);
718 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_TME_TSTART_INSN_EXCEPTION);
719 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_FPAC_PA_INSN_FAILURE_EXCEPTION);
720 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_SME_TRAPPED_SME_ACCESS);
721 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_RME_GRANULE_PROT_CHECK_EXCEPTION);
722 ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_LOWER_EL);
723 ARMV8_EC_CASE(ARMV8_ESR_EL2_INSN_ABORT_FROM_EL2);
724 ARMV8_EC_CASE(ARMV8_ESR_EL2_PC_ALIGNMENT_EXCEPTION);
725 ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL);
726 ARMV8_EC_CASE(ARMV8_ESR_EL2_DATA_ABORT_FROM_EL2);
727 ARMV8_EC_CASE(ARMV8_ESR_EL2_SP_ALIGNMENT_EXCEPTION);
728 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_MOPS_EXCEPTION);
729 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_TRAPPED_FP_EXCEPTION);
730 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_FP_EXCEPTION);
731 ARMV8_EC_CASE(ARMV8_ESR_EL2_SERROR_INTERRUPT);
732 ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_LOWER_EL);
733 ARMV8_EC_CASE(ARMV8_ESR_EL2_BKPT_EXCEPTION_FROM_EL2);
734 ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL);
735 ARMV8_EC_CASE(ARMV8_ESR_EL2_SS_EXCEPTION_FROM_EL2);
736 ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_LOWER_EL);
737 ARMV8_EC_CASE(ARMV8_ESR_EL2_WATCHPOINT_EXCEPTION_FROM_EL2);
738 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_BKPT_INSN);
739 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH32_VEC_CATCH_EXCEPTION);
740 ARMV8_EC_CASE(ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN);
741#undef ARMV8_EC_CASE
742 default:
743 break;
744 }
745
746 return "<INVALID>";
747}
748
749
750/**
751 * Resolves a NEM page state from the given protection flags.
752 *
753 * @returns NEM page state.
754 * @param fPageProt The page protection flags.
755 */
756DECLINLINE(uint8_t) nemR3DarwinPageStateFromProt(uint32_t fPageProt)
757{
758 switch (fPageProt)
759 {
760 case NEM_PAGE_PROT_NONE:
761 return NEM_DARWIN_PAGE_STATE_UNMAPPED;
762 case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE:
763 return NEM_DARWIN_PAGE_STATE_RX;
764 case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE:
765 return NEM_DARWIN_PAGE_STATE_RW;
766 case NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE:
767 return NEM_DARWIN_PAGE_STATE_RWX;
768 default:
769 break;
770 }
771
772 AssertLogRelMsgFailed(("Invalid combination of page protection flags %#x, can't map to page state!\n", fPageProt));
773 return NEM_DARWIN_PAGE_STATE_UNMAPPED;
774}
775
776
777/**
778 * Unmaps the given guest physical address range (page aligned).
779 *
780 * @returns VBox status code.
781 * @param pVM The cross context VM structure.
782 * @param GCPhys The guest physical address to start unmapping at.
783 * @param cb The size of the range to unmap in bytes.
784 * @param pu2State Where to store the new state of the unmappd page, optional.
785 */
786DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint8_t *pu2State)
787{
788 if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
789 {
790 Log5(("nemR3DarwinUnmap: %RGp == unmapped\n", GCPhys));
791 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
792 return VINF_SUCCESS;
793 }
794
795 LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
796 hv_return_t hrc = hv_vm_unmap(GCPhys, cb);
797 if (RT_LIKELY(hrc == HV_SUCCESS))
798 {
799 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
800 if (pu2State)
801 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
802 Log5(("nemR3DarwinUnmap: %RGp => unmapped\n", GCPhys));
803 return VINF_SUCCESS;
804 }
805
806 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
807 LogRel(("nemR3DarwinUnmap(%RGp): failed! hrc=%#x\n",
808 GCPhys, hrc));
809 return VERR_NEM_IPE_6;
810}
811
812
813/**
814 * Maps a given guest physical address range backed by the given memory with the given
815 * protection flags.
816 *
817 * @returns VBox status code.
818 * @param pVM The cross context VM structure.
819 * @param GCPhys The guest physical address to start mapping.
820 * @param pvRam The R3 pointer of the memory to back the range with.
821 * @param cb The size of the range, page aligned.
822 * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
823 * @param pu2State Where to store the state for the new page, optional.
824 */
825DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, const void *pvRam, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
826{
827 LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
828
829 Assert(fPageProt != NEM_PAGE_PROT_NONE);
830 RT_NOREF(pVM);
831
832 hv_memory_flags_t fHvMemProt = 0;
833 if (fPageProt & NEM_PAGE_PROT_READ)
834 fHvMemProt |= HV_MEMORY_READ;
835 if (fPageProt & NEM_PAGE_PROT_WRITE)
836 fHvMemProt |= HV_MEMORY_WRITE;
837 if (fPageProt & NEM_PAGE_PROT_EXECUTE)
838 fHvMemProt |= HV_MEMORY_EXEC;
839
840 hv_return_t hrc = hv_vm_map((void *)pvRam, GCPhys, cb, fHvMemProt);
841 if (hrc == HV_SUCCESS)
842 {
843 if (pu2State)
844 *pu2State = nemR3DarwinPageStateFromProt(fPageProt);
845 return VINF_SUCCESS;
846 }
847
848 return nemR3DarwinHvSts2Rc(hrc);
849}
850
851
852/**
853 * Changes the protection flags for the given guest physical address range.
854 *
855 * @returns VBox status code.
856 * @param GCPhys The guest physical address to start mapping.
857 * @param cb The size of the range, page aligned.
858 * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
859 * @param pu2State Where to store the state for the new page, optional.
860 */
861DECLINLINE(int) nemR3DarwinProtect(RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt, uint8_t *pu2State)
862{
863 hv_memory_flags_t fHvMemProt = 0;
864 if (fPageProt & NEM_PAGE_PROT_READ)
865 fHvMemProt |= HV_MEMORY_READ;
866 if (fPageProt & NEM_PAGE_PROT_WRITE)
867 fHvMemProt |= HV_MEMORY_WRITE;
868 if (fPageProt & NEM_PAGE_PROT_EXECUTE)
869 fHvMemProt |= HV_MEMORY_EXEC;
870
871 hv_return_t hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
872 if (hrc == HV_SUCCESS)
873 {
874 if (pu2State)
875 *pu2State = nemR3DarwinPageStateFromProt(fPageProt);
876 return VINF_SUCCESS;
877 }
878
879 LogRel(("nemR3DarwinProtect(%RGp,%zu,%#x): failed! hrc=%#x\n",
880 GCPhys, cb, fPageProt, hrc));
881 return nemR3DarwinHvSts2Rc(hrc);
882}
883
884
885#ifdef LOG_ENABLED
886/**
887 * Logs the current CPU state.
888 */
889static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
890{
891 if (LogIs3Enabled())
892 {
893 char szRegs[4096];
894 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
895 "x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n"
896 "x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n"
897 "x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n"
898 "x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n"
899 "x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n"
900 "x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n"
901 "x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n"
902 "x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n"
903 "pc=%016VR{pc} pstate=%016VR{pstate}\n"
904 "sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
905 "sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
906 "ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
907 "vbar_el1=%016VR{vbar_el1}\n"
908 );
909 if (pVM->nem.s.fEl2Enabled)
910 {
911 Log3(("%s\n", szRegs));
912 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
913 "sp_el2=%016VR{sp_el2} elr_el2=%016VR{elr_el2}\n"
914 "spsr_el2=%016VR{spsr_el2} tpidr_el2=%016VR{tpidr_el2}\n"
915 "sctlr_el2=%016VR{sctlr_el2} tcr_el2=%016VR{tcr_el2}\n"
916 "ttbr0_el2=%016VR{ttbr0_el2} ttbr1_el2=%016VR{ttbr1_el2}\n"
917 "esr_el2=%016VR{esr_el2} far_el2=%016VR{far_el2}\n"
918 "hcr_el2=%016VR{hcr_el2} tcr_el2=%016VR{tcr_el2}\n"
919 "vbar_el2=%016VR{vbar_el2} cptr_el2=%016VR{cptr_el2}\n"
920 );
921 }
922 char szInstr[256]; RT_ZERO(szInstr);
923 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
924 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
925 szInstr, sizeof(szInstr), NULL);
926 Log3(("%s%s\n", szRegs, szInstr));
927 }
928}
929#endif /* LOG_ENABLED */
930
931
932static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
933{
934 RT_NOREF(pVM);
935
936 hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &pVCpu->cpum.GstCtx.CntvCtlEl0);
937 if (hrc == HV_SUCCESS)
938 hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, &pVCpu->cpum.GstCtx.CntvCValEl0);
939
940 if ( hrc == HV_SUCCESS
941 && (fWhat & (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR)))
942 {
943 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
944 {
945 if (s_aCpumRegs[i].fCpumExtrn & fWhat)
946 {
947 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
948 hrc |= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, pu64);
949 }
950 }
951 }
952
953 if ( hrc == HV_SUCCESS
954 && (fWhat & CPUMCTX_EXTRN_V0_V31))
955 {
956 /* SIMD/FP registers. */
957 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
958 {
959 hv_simd_fp_uchar16_t *pu128 = (hv_simd_fp_uchar16_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
960 hrc |= hv_vcpu_get_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, pu128);
961 }
962 }
963
964 if ( hrc == HV_SUCCESS
965 && (fWhat & CPUMCTX_EXTRN_SYSREG_DEBUG))
966 {
967 /* Debug registers. */
968 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
969 {
970 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
971 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, pu64);
972 }
973 }
974
975 if ( hrc == HV_SUCCESS
976 && (fWhat & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
977 {
978 /* Debug registers. */
979 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
980 {
981 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
982 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, pu64);
983 }
984 }
985
986 if ( hrc == HV_SUCCESS
987 && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC)))
988 {
989 /* System registers. */
990 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
991 {
992 if (s_aCpumSysRegs[i].fCpumExtrn & fWhat)
993 {
994 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
995 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, pu64);
996 }
997 }
998 }
999
1000 if ( hrc == HV_SUCCESS
1001 && (fWhat & CPUMCTX_EXTRN_SYSREG_EL2)
1002 && pVM->nem.s.fEl2Enabled)
1003 {
1004 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1005 {
1006 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1007 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, pu64);
1008 }
1009 }
1010
1011 if ( hrc == HV_SUCCESS
1012 && (fWhat & CPUMCTX_EXTRN_PSTATE))
1013 {
1014 uint64_t u64Tmp;
1015 hrc |= hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
1016 if (hrc == HV_SUCCESS)
1017 pVCpu->cpum.GstCtx.fPState = (uint32_t)u64Tmp;
1018 }
1019
1020 /* Almost done, just update extern flags. */
1021 pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1022 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1023 pVCpu->cpum.GstCtx.fExtrn = 0;
1024
1025 return nemR3DarwinHvSts2Rc(hrc);
1026}
1027
1028
1029/**
1030 * Exports the guest state to HV for execution.
1031 *
1032 * @returns VBox status code.
1033 * @param pVM The cross context VM structure.
1034 * @param pVCpu The cross context virtual CPU structure of the
1035 * calling EMT.
1036 */
1037static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu)
1038{
1039 RT_NOREF(pVM);
1040 hv_return_t hrc = HV_SUCCESS;
1041
1042 if ( (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR))
1043 != (CPUMCTX_EXTRN_GPRS_MASK | CPUMCTX_EXTRN_PC | CPUMCTX_EXTRN_FPCR | CPUMCTX_EXTRN_FPSR))
1044 {
1045 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumRegs); i++)
1046 {
1047 if (!(s_aCpumRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1048 {
1049 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumRegs[i].offCpumCtx);
1050 hrc |= hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, s_aCpumRegs[i].enmHvReg, *pu64);
1051 }
1052 }
1053 }
1054
1055 if ( hrc == HV_SUCCESS
1056 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_V0_V31))
1057 {
1058 /* SIMD/FP registers. */
1059 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumFpRegs); i++)
1060 {
1061 hv_simd_fp_uchar16_t *pu128 = (hv_simd_fp_uchar16_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumFpRegs[i].offCpumCtx);
1062 hrc |= hv_vcpu_set_simd_fp_reg(pVCpu->nem.s.hVCpu, s_aCpumFpRegs[i].enmHvReg, *pu128);
1063 }
1064 }
1065
1066 if ( hrc == HV_SUCCESS
1067 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_DEBUG))
1068 {
1069 /* Debug registers. */
1070 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumDbgRegs); i++)
1071 {
1072 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumDbgRegs[i].offCpumCtx);
1073 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumDbgRegs[i].enmHvReg, *pu64);
1074 }
1075 }
1076
1077 if ( hrc == HV_SUCCESS
1078 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_PAUTH_KEYS))
1079 {
1080 /* Debug registers. */
1081 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumPAuthKeyRegs); i++)
1082 {
1083 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumPAuthKeyRegs[i].offCpumCtx);
1084 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumPAuthKeyRegs[i].enmHvReg, *pu64);
1085 }
1086 }
1087
1088 if ( hrc == HV_SUCCESS
1089 && (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
1090 != (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR | CPUMCTX_EXTRN_SYSREG_MISC))
1091 {
1092 /* System registers. */
1093 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumSysRegs); i++)
1094 {
1095 if (!(s_aCpumSysRegs[i].fCpumExtrn & pVCpu->cpum.GstCtx.fExtrn))
1096 {
1097 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumSysRegs[i].offCpumCtx);
1098 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aCpumSysRegs[i].enmHvReg, *pu64);
1099 }
1100 }
1101 }
1102
1103 if ( hrc == HV_SUCCESS
1104 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_SYSREG_EL2)
1105 && pVM->nem.s.fEl2Enabled)
1106 {
1107 for (uint32_t i = 0; i < RT_ELEMENTS(s_aCpumEl2SysRegs); i++)
1108 {
1109 uint64_t *pu64 = (uint64_t *)((uint8_t *)&pVCpu->cpum.GstCtx + s_aCpumEl2SysRegs[i].offCpumCtx);
1110 hrc |= hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, (hv_sys_reg_t)s_aCpumEl2SysRegs[i].idSysReg, *pu64);
1111 Assert(hrc == HV_SUCCESS);
1112 }
1113 }
1114
1115 if ( hrc == HV_SUCCESS
1116 && !(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_PSTATE))
1117 hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, pVCpu->cpum.GstCtx.fPState);
1118
1119 pVCpu->cpum.GstCtx.fExtrn |= CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_NEM;
1120 return nemR3DarwinHvSts2Rc(hrc);
1121}
1122
1123
1124/**
1125 * Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1126 *
1127 * @returns VBox status code.
1128 * @param pErrInfo Where to always return error info.
1129 */
1130static int nemR3DarwinLoadHv(PRTERRINFO pErrInfo)
1131{
1132 RTLDRMOD hMod = NIL_RTLDRMOD;
1133 static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1134
1135 int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD | RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1136 if (RT_SUCCESS(rc))
1137 {
1138 for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1139 {
1140 int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1141 if (RT_SUCCESS(rc2))
1142 LogRel(("NEM: info: Found optional import Hypervisor!%s.\n", g_aImports[i].pszName));
1143 else
1144 {
1145 *g_aImports[i].ppfn = NULL;
1146 LogRel(("NEM: info: Optional import Hypervisor!%s not found: %Rrc\n", g_aImports[i].pszName, rc2));
1147 }
1148 }
1149 Assert(RT_SUCCESS(rc) && !RTErrInfoIsSet(pErrInfo));
1150 RTLdrClose(hMod);
1151 }
1152 else
1153 {
1154 RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1155 rc = VERR_NEM_INIT_FAILED;
1156 }
1157
1158 return rc;
1159}
1160
1161
1162/**
1163 * Dumps some GIC information to the release log.
1164 */
1165static void nemR3DarwinDumpGicInfo(void)
1166{
1167 size_t val = 0;
1168 hv_return_t hrc = hv_gic_get_redistributor_size(&val);
1169 LogRel(("GICNem: hv_gic_get_redistributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1170 hrc = hv_gic_get_distributor_size(&val);
1171 LogRel(("GICNem: hv_gic_get_distributor_size() -> hrc=%#x / size=%zu\n", hrc, val));
1172 hrc = hv_gic_get_distributor_base_alignment(&val);
1173 LogRel(("GICNem: hv_gic_get_distributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1174 hrc = hv_gic_get_redistributor_base_alignment(&val);
1175 LogRel(("GICNem: hv_gic_get_redistributor_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1176 hrc = hv_gic_get_msi_region_base_alignment(&val);
1177 LogRel(("GICNem: hv_gic_get_msi_region_base_alignment() -> hrc=%#x / size=%zu\n", hrc, val));
1178 hrc = hv_gic_get_msi_region_size(&val);
1179 LogRel(("GICNem: hv_gic_get_msi_region_size() -> hrc=%#x / size=%zu\n", hrc, val));
1180 uint32_t u32SpiIntIdBase = 0;
1181 uint32_t cSpiIntIds = 0;
1182 hrc = hv_gic_get_spi_interrupt_range(&u32SpiIntIdBase, &cSpiIntIds);
1183 LogRel(("GICNem: hv_gic_get_spi_interrupt_range() -> hrc=%#x / SpiIntIdBase=%u, cSpiIntIds=%u\n", hrc, u32SpiIntIdBase, cSpiIntIds));
1184
1185 uint32_t u32IntId = 0;
1186 hrc = hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER, &u32IntId);
1187 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1188 hrc = hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER, &u32IntId);
1189 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL1_VIRTUAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1190 hrc = hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER, &u32IntId);
1191 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_EL2_PHYSICAL_TIMER) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1192 hrc = hv_gic_get_intid(HV_GIC_INT_MAINTENANCE, &u32IntId);
1193 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_MAINTENANCE) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1194 hrc = hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR, &u32IntId);
1195 LogRel(("GICNem: hv_gic_get_intid(HV_GIC_INT_PERFORMANCE_MONITOR) -> hrc=%#x / IntId=%u\n", hrc, u32IntId));
1196}
1197
1198
1199static int nemR3DarwinGicCreate(PVM pVM)
1200{
1201 nemR3DarwinDumpGicInfo();
1202
1203 //PCFGMNODE pGicDev = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic/0");
1204 PCFGMNODE pGicCfg = CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0/Config");
1205 AssertPtrReturn(pGicCfg, VERR_NEM_IPE_5);
1206
1207 hv_gic_config_t hGicCfg = hv_gic_config_create();
1208
1209 /*
1210 * Query the MMIO ranges.
1211 */
1212 RTGCPHYS GCPhysMmioBaseDist = 0;
1213 int rc = CFGMR3QueryU64(pGicCfg, "DistributorMmioBase", &GCPhysMmioBaseDist);
1214 if (RT_FAILURE(rc))
1215 return VMSetError(pVM, rc, RT_SRC_POS,
1216 "Configuration error: Failed to get the \"DistributorMmioBase\" value\n");
1217
1218 RTGCPHYS GCPhysMmioBaseReDist = 0;
1219 rc = CFGMR3QueryU64(pGicCfg, "RedistributorMmioBase", &GCPhysMmioBaseReDist);
1220 if (RT_FAILURE(rc))
1221 return VMSetError(pVM, rc, RT_SRC_POS,
1222 "Configuration error: Failed to get the \"RedistributorMmioBase\" value\n");
1223
1224 hv_return_t hrc = hv_gic_config_set_distributor_base(hGicCfg, GCPhysMmioBaseDist);
1225 if (hrc != HV_SUCCESS)
1226 return nemR3DarwinHvSts2Rc(hrc);
1227
1228 hrc = hv_gic_config_set_redistributor_base(hGicCfg, GCPhysMmioBaseReDist);
1229 if (hrc != HV_SUCCESS)
1230 return nemR3DarwinHvSts2Rc(hrc);
1231
1232 hrc = hv_gic_create(hGicCfg);
1233 os_release(hGicCfg);
1234 if (hrc != HV_SUCCESS)
1235 return nemR3DarwinHvSts2Rc(hrc);
1236
1237 return rc;
1238}
1239
1240
1241/**
1242 * Try initialize the native API.
1243 *
1244 * This may only do part of the job, more can be done in
1245 * nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
1246 *
1247 * @returns VBox status code.
1248 * @param pVM The cross context VM structure.
1249 * @param fFallback Whether we're in fallback mode or use-NEM mode. In
1250 * the latter we'll fail if we cannot initialize.
1251 * @param fForced Whether the HMForced flag is set and we should
1252 * fail if we cannot initialize.
1253 */
1254int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
1255{
1256 AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
1257
1258 /*
1259 * Some state init.
1260 */
1261 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
1262 RT_NOREF(pCfgNem);
1263
1264 /*
1265 * Error state.
1266 * The error message will be non-empty on failure and 'rc' will be set too.
1267 */
1268 RTERRINFOSTATIC ErrInfo;
1269 PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
1270
1271 /* Resolve optional imports */
1272 int rc = nemR3DarwinLoadHv(pErrInfo);
1273 if (RT_FAILURE(rc))
1274 {
1275 if ((fForced || !fFallback) && RTErrInfoIsSet(pErrInfo))
1276 return VMSetError(pVM, rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1277 return rc;
1278 }
1279
1280 /*
1281 * Need to enable nested virt here if supported and reset the CFGM value to false
1282 * if not supported. This ASSUMES that NEM is initialized before CPUM.
1283 */
1284 PCFGMNODE pCfgCpum = CFGMR3GetChild(CFGMR3GetRoot(pVM), "CPUM/");
1285
1286 hv_vm_config_t hVmCfg = NULL;
1287 if ( hv_vm_config_create
1288 && hv_vm_config_get_el2_supported)
1289 {
1290 hVmCfg = hv_vm_config_create();
1291
1292 bool fHvEl2Supported = false;
1293 hv_return_t hrc = hv_vm_config_get_el2_supported(&fHvEl2Supported);
1294 if ( hrc == HV_SUCCESS
1295 && fHvEl2Supported)
1296 {
1297 /** @cfgm{/CPUM/NestedHWVirt, bool, false}
1298 * Whether to expose the hardware virtualization (EL2/VHE) feature to the guest.
1299 * The default is false. Only supported on M3 and later and macOS 15.0+ (Sonoma).
1300 */
1301 bool fNestedHWVirt = false;
1302 rc = CFGMR3QueryBoolDef(pCfgCpum, "NestedHWVirt", &fNestedHWVirt, false);
1303 AssertLogRelRCReturn(rc, rc);
1304 if (fNestedHWVirt)
1305 {
1306 hrc = hv_vm_config_set_el2_enabled(hVmCfg, fNestedHWVirt);
1307 if (hrc != HV_SUCCESS)
1308 return VMSetError(pVM, VERR_CPUM_INVALID_HWVIRT_CONFIG, RT_SRC_POS,
1309 "Cannot enable nested virtualization: hrc=%#x %s!\n", hrc, nemR3DarwinHvStatusName(hrc));
1310 pVM->nem.s.fEl2Enabled = true;
1311 LogRel(("NEM: Enabled nested virtualization (EL2) support\n"));
1312 }
1313 }
1314 else
1315 {
1316 /* Ensure nested virt is not set. */
1317 rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1318 AssertLogRelRC(rc);
1319
1320 LogRel(("NEM: The host doesn't supported nested virtualization! (hrc=%#x fHvEl2Supported=%RTbool)\n",
1321 hrc, fHvEl2Supported));
1322 }
1323 }
1324 else
1325 {
1326 /* Ensure nested virt is not set. */
1327 rc = CFGMR3RemoveValue(pCfgCpum, "NestedHWVirt");
1328 AssertLogRelRC(rc);
1329
1330 LogRel(("NEM: Hypervisor.framework doesn't supported nested virtualization!\n"));
1331 }
1332
1333 hv_return_t hrc = hv_vm_create(hVmCfg);
1334 os_release(hVmCfg);
1335 if (hrc == HV_SUCCESS)
1336 {
1337 pVM->nem.s.fCreatedVm = true;
1338 pVM->nem.s.u64CntFrqHz = ASMReadCntFrqEl0();
1339
1340 /* Will be initialized in NEMHCResumeCpuTickOnAll() before executing guest code. */
1341 pVM->nem.s.u64VTimerOff = 0;
1342
1343 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
1344 Log(("NEM: Marked active!\n"));
1345 PGMR3EnableNemMode(pVM);
1346 return VINF_SUCCESS;
1347 }
1348
1349 rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED, "hv_vm_create() failed: %#x %s", hrc, nemR3DarwinHvStatusName(hrc));
1350
1351 /*
1352 * We only fail if in forced mode, otherwise just log the complaint and return.
1353 */
1354 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API || RTErrInfoIsSet(pErrInfo));
1355 if ( (fForced || !fFallback)
1356 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
1357 return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
1358
1359 if (RTErrInfoIsSet(pErrInfo))
1360 LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
1361 return VINF_SUCCESS;
1362}
1363
1364
1365/**
1366 * Worker to create the vCPU handle on the EMT running it later on (as required by HV).
1367 *
1368 * @returns VBox status code
1369 * @param pVM The VM handle.
1370 * @param pVCpu The vCPU handle.
1371 * @param idCpu ID of the CPU to create.
1372 */
1373static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
1374{
1375 if (idCpu == 0)
1376 {
1377 Assert(pVM->nem.s.hVCpuCfg == NULL);
1378
1379 /* Create a new vCPU config and query the ID registers. */
1380 pVM->nem.s.hVCpuCfg = hv_vcpu_config_create();
1381 if (!pVM->nem.s.hVCpuCfg)
1382 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1383 "Call to hv_vcpu_config_create failed on vCPU %u", idCpu);
1384
1385 /* Query ID registers and hand them to CPUM. */
1386 CPUMARMV8IDREGS IdRegs; RT_ZERO(IdRegs);
1387 for (uint32_t i = 0; i < RT_ELEMENTS(s_aIdRegs); i++)
1388 {
1389 uint64_t *pu64 = (uint64_t *)((uint8_t *)&IdRegs + s_aIdRegs[i].offIdStruct);
1390 hv_return_t hrc = hv_vcpu_config_get_feature_reg(pVM->nem.s.hVCpuCfg, s_aIdRegs[i].enmHvReg, pu64);
1391 if (hrc != HV_SUCCESS)
1392 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1393 "Call to hv_vcpu_get_feature_reg(, %#x, ) failed: %#x (%Rrc)", hrc, nemR3DarwinHvSts2Rc(hrc));
1394 }
1395
1396 int rc = CPUMR3PopulateFeaturesByIdRegisters(pVM, &IdRegs);
1397 if (RT_FAILURE(rc))
1398 return rc;
1399 }
1400
1401 hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpu, &pVCpu->nem.s.pHvExit, pVM->nem.s.hVCpuCfg);
1402 if (hrc != HV_SUCCESS)
1403 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1404 "Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1405
1406 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MPIDR_EL1, idCpu);
1407 if (hrc != HV_SUCCESS)
1408 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
1409 "Setting MPIDR_EL1 failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
1410
1411 return VINF_SUCCESS;
1412}
1413
1414
1415/**
1416 * Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
1417 *
1418 * @returns VBox status code.
1419 * @param pVM The VM handle.
1420 * @param pVCpu The vCPU handle.
1421 */
1422static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVM pVM, PVMCPU pVCpu)
1423{
1424 hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1425 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1426
1427 if (pVCpu->idCpu == 0)
1428 {
1429 os_release(pVM->nem.s.hVCpuCfg);
1430 pVM->nem.s.hVCpuCfg = NULL;
1431 }
1432 return VINF_SUCCESS;
1433}
1434
1435
1436/**
1437 * This is called after CPUMR3Init is done.
1438 *
1439 * @returns VBox status code.
1440 * @param pVM The VM handle..
1441 */
1442int nemR3NativeInitAfterCPUM(PVM pVM)
1443{
1444 /*
1445 * Validate sanity.
1446 */
1447 AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
1448 AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
1449
1450 /*
1451 * Need to create the GIC here if the NEM variant is configured
1452 * before any vCPU is created according to the Apple docs.
1453 */
1454 if ( hv_gic_create
1455 && CFGMR3GetChild(CFGMR3GetRoot(pVM), "Devices/gic-nem/0"))
1456 {
1457 int rc = nemR3DarwinGicCreate(pVM);
1458 if (RT_FAILURE(rc))
1459 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Creating the GIC failed: %Rrc", rc);
1460 }
1461
1462 /*
1463 * Setup the EMTs.
1464 */
1465 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1466 {
1467 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1468
1469 int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
1470 if (RT_FAILURE(rc))
1471 {
1472 /* Rollback. */
1473 while (idCpu--)
1474 VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 2, pVM, pVCpu);
1475
1476 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
1477 }
1478 }
1479
1480 pVM->nem.s.fCreatedEmts = true;
1481 return VINF_SUCCESS;
1482}
1483
1484
1485int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1486{
1487 RT_NOREF(pVM, enmWhat);
1488 return VINF_SUCCESS;
1489}
1490
1491
1492int nemR3NativeTerm(PVM pVM)
1493{
1494 /*
1495 * Delete the VM.
1496 */
1497
1498 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
1499 {
1500 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1501
1502 /*
1503 * Apple's documentation states that the vCPU should be destroyed
1504 * on the thread running the vCPU but as all the other EMTs are gone
1505 * at this point, destroying the VM would hang.
1506 *
1507 * We seem to be at luck here though as destroying apparently works
1508 * from EMT(0) as well.
1509 */
1510 hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpu);
1511 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
1512 }
1513
1514 pVM->nem.s.fCreatedEmts = false;
1515 if (pVM->nem.s.fCreatedVm)
1516 {
1517 hv_return_t hrc = hv_vm_destroy();
1518 if (hrc != HV_SUCCESS)
1519 LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
1520
1521 pVM->nem.s.fCreatedVm = false;
1522 }
1523 return VINF_SUCCESS;
1524}
1525
1526
1527/**
1528 * VM reset notification.
1529 *
1530 * @param pVM The cross context VM structure.
1531 */
1532void nemR3NativeReset(PVM pVM)
1533{
1534 RT_NOREF(pVM);
1535}
1536
1537
1538/**
1539 * Reset CPU due to INIT IPI or hot (un)plugging.
1540 *
1541 * @param pVCpu The cross context virtual CPU structure of the CPU being
1542 * reset.
1543 * @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
1544 */
1545void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
1546{
1547 RT_NOREF(pVCpu, fInitIpi);
1548}
1549
1550
1551/**
1552 * Returns the byte size from the given access SAS value.
1553 *
1554 * @returns Number of bytes to transfer.
1555 * @param uSas The SAS value to convert.
1556 */
1557DECLINLINE(size_t) nemR3DarwinGetByteCountFromSas(uint8_t uSas)
1558{
1559 switch (uSas)
1560 {
1561 case ARMV8_EC_ISS_DATA_ABRT_SAS_BYTE: return sizeof(uint8_t);
1562 case ARMV8_EC_ISS_DATA_ABRT_SAS_HALFWORD: return sizeof(uint16_t);
1563 case ARMV8_EC_ISS_DATA_ABRT_SAS_WORD: return sizeof(uint32_t);
1564 case ARMV8_EC_ISS_DATA_ABRT_SAS_DWORD: return sizeof(uint64_t);
1565 default:
1566 AssertReleaseFailed();
1567 }
1568
1569 return 0;
1570}
1571
1572
1573/**
1574 * Sets the given general purpose register to the given value.
1575 *
1576 * @param pVCpu The cross context virtual CPU structure of the
1577 * calling EMT.
1578 * @param uReg The register index.
1579 * @param f64BitReg Flag whether to operate on a 64-bit or 32-bit register.
1580 * @param fSignExtend Flag whether to sign extend the value.
1581 * @param u64Val The value.
1582 */
1583DECLINLINE(void) nemR3DarwinSetGReg(PVMCPU pVCpu, uint8_t uReg, bool f64BitReg, bool fSignExtend, uint64_t u64Val)
1584{
1585 AssertReturnVoid(uReg < 31);
1586
1587 if (f64BitReg)
1588 pVCpu->cpum.GstCtx.aGRegs[uReg].x = fSignExtend ? (int64_t)u64Val : u64Val;
1589 else
1590 pVCpu->cpum.GstCtx.aGRegs[uReg].x = (uint64_t)(fSignExtend ? (int32_t)u64Val : (uint32_t)u64Val);
1591
1592 /* Mark the register as not extern anymore. */
1593 switch (uReg)
1594 {
1595 case 0:
1596 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X0;
1597 break;
1598 case 1:
1599 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X1;
1600 break;
1601 case 2:
1602 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X2;
1603 break;
1604 case 3:
1605 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_X3;
1606 break;
1607 default:
1608 AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_X4_X28));
1609 /** @todo We need to import all missing registers in order to clear this flag (or just set it in HV from here). */
1610 }
1611}
1612
1613
1614/**
1615 * Gets the given general purpose register and returns the value.
1616 *
1617 * @returns Value from the given register.
1618 * @param pVCpu The cross context virtual CPU structure of the
1619 * calling EMT.
1620 * @param uReg The register index.
1621 */
1622DECLINLINE(uint64_t) nemR3DarwinGetGReg(PVMCPU pVCpu, uint8_t uReg)
1623{
1624 AssertReturn(uReg <= ARMV8_A64_REG_XZR, 0);
1625
1626 if (uReg == ARMV8_A64_REG_XZR)
1627 return 0;
1628
1629 /** @todo Import the register if extern. */
1630 AssertRelease(!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_GPRS_MASK));
1631
1632 return pVCpu->cpum.GstCtx.aGRegs[uReg].x;
1633}
1634
1635
1636/**
1637 * Works on the data abort exception (which will be a MMIO access most of the time).
1638 *
1639 * @returns VBox strict status code.
1640 * @param pVM The cross context VM structure.
1641 * @param pVCpu The cross context virtual CPU structure of the
1642 * calling EMT.
1643 * @param uIss The instruction specific syndrome value.
1644 * @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1645 * @param GCPtrDataAbrt The virtual GC address causing the data abort.
1646 * @param GCPhysDataAbrt The physical GC address which caused the data abort.
1647 */
1648static VBOXSTRICTRC nemR3DarwinHandleExitExceptionDataAbort(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit,
1649 RTGCPTR GCPtrDataAbrt, RTGCPHYS GCPhysDataAbrt)
1650{
1651 bool fIsv = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_ISV);
1652 bool fL2Fault = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_S1PTW);
1653 bool fWrite = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_WNR);
1654 bool f64BitReg = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SF);
1655 bool fSignExtend = RT_BOOL(uIss & ARMV8_EC_ISS_DATA_ABRT_SSE);
1656 uint8_t uReg = ARMV8_EC_ISS_DATA_ABRT_SRT_GET(uIss);
1657 uint8_t uAcc = ARMV8_EC_ISS_DATA_ABRT_SAS_GET(uIss);
1658 size_t cbAcc = nemR3DarwinGetByteCountFromSas(uAcc);
1659 LogFlowFunc(("fIsv=%RTbool fL2Fault=%RTbool fWrite=%RTbool f64BitReg=%RTbool fSignExtend=%RTbool uReg=%u uAcc=%u GCPtrDataAbrt=%RGv GCPhysDataAbrt=%RGp\n",
1660 fIsv, fL2Fault, fWrite, f64BitReg, fSignExtend, uReg, uAcc, GCPtrDataAbrt, GCPhysDataAbrt));
1661
1662 RT_NOREF(fL2Fault, GCPtrDataAbrt);
1663
1664 if (fWrite)
1665 {
1666 /*
1667 * Check whether this is one of the dirty tracked regions, mark it as dirty
1668 * and enable write support for this region again.
1669 *
1670 * This is required for proper VRAM tracking or the display might not get updated
1671 * and it is impossible to use the PGM generic facility as it operates on guest page sizes
1672 * but setting protection flags with Hypervisor.framework works only host page sized regions, so
1673 * we have to cook our own. Additionally the VRAM region is marked as prefetchable (write-back)
1674 * which doesn't produce a valid instruction syndrome requiring restarting the instruction after enabling
1675 * write access again (due to a missing interpreter right now).
1676 */
1677 for (uint32_t idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
1678 {
1679 PNEMHVMMIO2REGION pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
1680
1681 if ( GCPhysDataAbrt >= pMmio2Region->GCPhysStart
1682 && GCPhysDataAbrt <= pMmio2Region->GCPhysLast)
1683 {
1684 pMmio2Region->fDirty = true;
1685
1686 uint8_t u2State;
1687 int rc = nemR3DarwinProtect(pMmio2Region->GCPhysStart, pMmio2Region->GCPhysLast - pMmio2Region->GCPhysStart + 1,
1688 NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE | NEM_PAGE_PROT_WRITE, &u2State);
1689
1690 /* Restart the instruction if there is no instruction syndrome available. */
1691 if (RT_FAILURE(rc) || !fIsv)
1692 return rc;
1693 }
1694 }
1695 }
1696
1697 VBOXSTRICTRC rcStrict;
1698 if (fIsv)
1699 {
1700 EMHistoryAddExit(pVCpu,
1701 fWrite
1702 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
1703 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
1704 pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1705
1706 uint64_t u64Val = 0;
1707 if (fWrite)
1708 {
1709 u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1710 rcStrict = PGMPhysWrite(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1711 Log4(("MmioExit/%u: %08RX64: WRITE %#RGp LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
1712 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1713 &u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1714 }
1715 else
1716 {
1717 rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u64Val, cbAcc, PGMACCESSORIGIN_HM);
1718 Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1719 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, cbAcc, cbAcc,
1720 &u64Val, VBOXSTRICTRC_VAL(rcStrict) ));
1721 if (rcStrict == VINF_SUCCESS)
1722 nemR3DarwinSetGReg(pVCpu, uReg, f64BitReg, fSignExtend, u64Val);
1723 }
1724 }
1725 else
1726 {
1727 /** @todo Our UEFI firmware accesses the flash region with the following instruction
1728 * when the NVRAM actually contains data:
1729 * ldrb w9, [x6, #-0x0001]!
1730 * This is too complicated for the hardware so the ISV bit is not set. Until there
1731 * is a proper IEM implementation we just handle this here for now to avoid annoying
1732 * users too much.
1733 */
1734 /* The following ASSUMES that the vCPU state is completely synced. */
1735
1736 /* Read instruction. */
1737 RTGCPTR GCPtrPage = pVCpu->cpum.GstCtx.Pc.u64 & ~(RTGCPTR)GUEST_PAGE_OFFSET_MASK;
1738 const void *pvPageR3 = NULL;
1739 PGMPAGEMAPLOCK PageMapLock;
1740
1741 rcStrict = PGMPhysGCPtr2CCPtrReadOnly(pVCpu, GCPtrPage, &pvPageR3, &PageMapLock);
1742 if (rcStrict == VINF_SUCCESS)
1743 {
1744 uint32_t u32Instr = *(uint32_t *)((uint8_t *)pvPageR3 + (pVCpu->cpum.GstCtx.Pc.u64 - GCPtrPage));
1745 PGMPhysReleasePageMappingLock(pVCpu->pVMR3, &PageMapLock);
1746
1747 DISSTATE Dis;
1748 rcStrict = DISInstrWithPrefetchedBytes((uintptr_t)pVCpu->cpum.GstCtx.Pc.u64, DISCPUMODE_ARMV8_A64, 0 /*fFilter - none */,
1749 &u32Instr, sizeof(u32Instr), NULL, NULL, &Dis, NULL);
1750 if (rcStrict == VINF_SUCCESS)
1751 {
1752 if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDRB
1753 && Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1754 && Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1755 && Dis.aParams[1].armv8.enmType == kDisArmv8OpParmAddrInGpr
1756 && Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit
1757 && (Dis.aParams[1].fUse & DISUSE_PRE_INDEXED))
1758 {
1759 /* The fault address is already the final address. */
1760 uint8_t bVal = 0;
1761 rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &bVal, 1, PGMACCESSORIGIN_HM);
1762 Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs rcStrict=%Rrc\n",
1763 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, sizeof(bVal), sizeof(bVal),
1764 &bVal, VBOXSTRICTRC_VAL(rcStrict) ));
1765 if (rcStrict == VINF_SUCCESS)
1766 {
1767 nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /*f64BitReg*/, false /*fSignExtend*/, bVal);
1768 /* Update the indexed register. */
1769 pVCpu->cpum.GstCtx.aGRegs[Dis.aParams[1].armv8.Op.Reg.idReg].x += Dis.aParams[1].armv8.u.offBase;
1770 }
1771 }
1772 /*
1773 * Seeing the following with the Windows 11/ARM TPM driver:
1774 * %fffff800e5342888 48 25 45 29 ldp w8, w9, [x10, #+0x0028]
1775 */
1776 else if ( Dis.pCurInstr->uOpcode == OP_ARMV8_A64_LDP
1777 && Dis.aParams[0].armv8.enmType == kDisArmv8OpParmReg
1778 && Dis.aParams[0].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1779 && Dis.aParams[1].armv8.enmType == kDisArmv8OpParmReg
1780 && Dis.aParams[1].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_32Bit
1781 && Dis.aParams[2].armv8.enmType == kDisArmv8OpParmAddrInGpr
1782 && Dis.aParams[2].armv8.Op.Reg.enmRegType == kDisOpParamArmV8RegType_Gpr_64Bit)
1783 {
1784 /** @todo This is tricky to handle if the first register read returns something else than VINF_SUCCESS... */
1785 /* The fault address is already the final address. */
1786 uint32_t u32Val1 = 0;
1787 uint32_t u32Val2 = 0;
1788 rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt, &u32Val1, sizeof(u32Val1), PGMACCESSORIGIN_HM);
1789 if (rcStrict == VINF_SUCCESS)
1790 rcStrict = PGMPhysRead(pVM, GCPhysDataAbrt + sizeof(uint32_t), &u32Val2, sizeof(u32Val2), PGMACCESSORIGIN_HM);
1791 Log4(("MmioExit/%u: %08RX64: READ %#RGp LB %u -> %.*Rhxs %.*Rhxs rcStrict=%Rrc\n",
1792 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, GCPhysDataAbrt, 2 * sizeof(uint32_t), sizeof(u32Val1),
1793 &u32Val1, sizeof(u32Val2), &u32Val2, VBOXSTRICTRC_VAL(rcStrict) ));
1794 if (rcStrict == VINF_SUCCESS)
1795 {
1796 nemR3DarwinSetGReg(pVCpu, Dis.aParams[0].armv8.Op.Reg.idReg, false /*f64BitReg*/, false /*fSignExtend*/, u32Val1);
1797 nemR3DarwinSetGReg(pVCpu, Dis.aParams[1].armv8.Op.Reg.idReg, false /*f64BitReg*/, false /*fSignExtend*/, u32Val2);
1798 }
1799 }
1800 /* T O D O:
1801 * Recent W11:
1802 * x0=ffffb804ea3217d8 x1=ffffe28437802000 x2=0000000000000424 x3=fffff802e5716030
1803 * x4=ffffe28437802424 x5=ffffb804ea321bfc x6=000000000080009c x7=000000000080009c
1804 * x8=ffff87849fefc788 x9=ffff87849fefc788 x10=000000000000001c x11=ffffb804ea32909c
1805 * x12=000000000000001c x13=000000000000009c x14=ffffb804ea3290a8 x15=ffffd580b2b1f7d8
1806 * x16=0000f6999080cdbe x17=0000f6999080cdbe x18=ffffd08158fbf000 x19=ffffb804ea3217d0
1807 * x20=0000000000000001 x21=0000000000000004 x22=ffffb804ea321660 x23=000047fb15cdefd8
1808 * x24=0000000000000000 x25=ffffb804ea2f1080 x26=0000000000000000 x27=0000000000000380
1809 * x28=0000000000000000 x29=ffff87849fefc7e0 x30=fffff802e57120b0
1810 * pc=fffff802e5713c20 pstate=00000000a0001344
1811 * sp_el0=ffff87849fefc7e0 sp_el1=ffff87849e462400 elr_el1=fffff802e98889c8
1812 * pl061gpio!start_seg1_.text+0x2c20:
1813 * %fffff802e5713c20 23 00 c0 3d ldr q3, [x1]
1814 * VBoxDbg> format %%(%@x1)
1815 * Guest physical address: %%ffddd000
1816 * VBoxDbg> info mmio
1817 * MMIO registrations: 12 (186 allocated)
1818 * ## Ctx Size Mapping PCI Description
1819 * 0 R3 00000000000c0000 0000000004000000-00000000040bffff Flash Memory
1820 * [snip]
1821 * 11 R3 0000000000001000 00000000ffddd000-00000000ffdddfff PL061
1822 */
1823 else
1824 AssertLogRelMsgFailedReturn(("pc=%#RX64: %#x opcode=%d\n",
1825 pVCpu->cpum.GstCtx.Pc.u64, Dis.Instr.au32[0], Dis.pCurInstr->uOpcode),
1826 VERR_NEM_IPE_2);
1827 }
1828 }
1829 }
1830
1831 if (rcStrict == VINF_SUCCESS)
1832 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1833
1834 return rcStrict;
1835}
1836
1837
1838/**
1839 * Works on the trapped MRS, MSR and system instruction exception.
1840 *
1841 * @returns VBox strict status code.
1842 * @param pVM The cross context VM structure.
1843 * @param pVCpu The cross context virtual CPU structure of the
1844 * calling EMT.
1845 * @param uIss The instruction specific syndrome value.
1846 * @param fInsn32Bit Flag whether the exception was caused by a 32-bit or 16-bit instruction.
1847 */
1848static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedSysInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fInsn32Bit)
1849{
1850 bool fRead = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_DIRECTION_IS_READ(uIss);
1851 uint8_t uCRm = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRM_GET(uIss);
1852 uint8_t uReg = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_RT_GET(uIss);
1853 uint8_t uCRn = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_CRN_GET(uIss);
1854 uint8_t uOp1 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP1_GET(uIss);
1855 uint8_t uOp2 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP2_GET(uIss);
1856 uint8_t uOp0 = ARMV8_EC_ISS_AARCH64_TRAPPED_SYS_INSN_OP0_GET(uIss);
1857 uint16_t idSysReg = ARMV8_AARCH64_SYSREG_ID_CREATE(uOp0, uOp1, uCRn, uCRm, uOp2);
1858 LogFlowFunc(("fRead=%RTbool uCRm=%u uReg=%u uCRn=%u uOp1=%u uOp2=%u uOp0=%u idSysReg=%#x\n",
1859 fRead, uCRm, uReg, uCRn, uOp1, uOp2, uOp0, idSysReg));
1860
1861 /** @todo EMEXITTYPE_MSR_READ/EMEXITTYPE_MSR_WRITE are misnomers. */
1862 EMHistoryAddExit(pVCpu,
1863 fRead
1864 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1865 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1866 pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1867
1868 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1869 uint64_t u64Val = 0;
1870 if (fRead)
1871 {
1872 RT_NOREF(pVM);
1873 rcStrict = CPUMQueryGuestSysReg(pVCpu, idSysReg, &u64Val);
1874 Log4(("SysInsnExit/%u: %08RX64: READ %u:%u:%u:%u:%u -> %#RX64 rcStrict=%Rrc\n",
1875 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1876 VBOXSTRICTRC_VAL(rcStrict) ));
1877 if (rcStrict == VINF_SUCCESS)
1878 nemR3DarwinSetGReg(pVCpu, uReg, true /*f64BitReg*/, false /*fSignExtend*/, u64Val);
1879 }
1880 else
1881 {
1882 u64Val = nemR3DarwinGetGReg(pVCpu, uReg);
1883 rcStrict = CPUMSetGuestSysReg(pVCpu, idSysReg, u64Val);
1884 Log4(("SysInsnExit/%u: %08RX64: WRITE %u:%u:%u:%u:%u %#RX64 -> rcStrict=%Rrc\n",
1885 pVCpu->idCpu, pVCpu->cpum.GstCtx.Pc.u64, uOp0, uOp1, uCRn, uCRm, uOp2, u64Val,
1886 VBOXSTRICTRC_VAL(rcStrict) ));
1887 }
1888
1889 if (rcStrict == VINF_SUCCESS)
1890 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
1891
1892 return rcStrict;
1893}
1894
1895
1896/**
1897 * Works on the trapped HVC instruction exception.
1898 *
1899 * @returns VBox strict status code.
1900 * @param pVM The cross context VM structure.
1901 * @param pVCpu The cross context virtual CPU structure of the
1902 * calling EMT.
1903 * @param uIss The instruction specific syndrome value.
1904 * @param fAdvancePc Flag whether to advance the guest program counter.
1905 */
1906static VBOXSTRICTRC nemR3DarwinHandleExitExceptionTrappedHvcInsn(PVM pVM, PVMCPU pVCpu, uint32_t uIss, bool fAdvancePc = false)
1907{
1908 uint16_t u16Imm = ARMV8_EC_ISS_AARCH64_TRAPPED_HVC_INSN_IMM_GET(uIss);
1909 LogFlowFunc(("u16Imm=%#RX16\n", u16Imm));
1910
1911#if 0 /** @todo For later */
1912 EMHistoryAddExit(pVCpu,
1913 fRead
1914 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ)
1915 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
1916 pVCpu->cpum.GstCtx.Pc.u64, ASMReadTSC());
1917#endif
1918
1919 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
1920 if (u16Imm == 0)
1921 {
1922 /** @todo Raise exception to EL1 if PSCI not configured. */
1923 /** @todo Need a generic mechanism here to pass this to, GIM maybe?. */
1924 uint32_t uFunId = pVCpu->cpum.GstCtx.aGRegs[ARMV8_A64_REG_X0].w;
1925 bool fHvc64 = RT_BOOL(uFunId & ARM_SMCCC_FUNC_ID_64BIT); RT_NOREF(fHvc64);
1926 uint32_t uEntity = ARM_SMCCC_FUNC_ID_ENTITY_GET(uFunId);
1927 uint32_t uFunNum = ARM_SMCCC_FUNC_ID_NUM_GET(uFunId);
1928 if (uEntity == ARM_SMCCC_FUNC_ID_ENTITY_STD_SEC_SERVICE)
1929 {
1930 switch (uFunNum)
1931 {
1932 case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1933 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_FUNC_ID_PSCI_VERSION_SET(1, 2));
1934 break;
1935 case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1936 rcStrict = VMR3PowerOff(pVM->pUVM);
1937 break;
1938 case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1939 case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1940 {
1941 bool fHaltOnReset;
1942 int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
1943 if (RT_SUCCESS(rc) && fHaltOnReset)
1944 {
1945 Log(("nemR3DarwinHandleExitExceptionTrappedHvcInsn: Halt On Reset!\n"));
1946 rcStrict = VINF_EM_HALT;
1947 }
1948 else
1949 {
1950 /** @todo pVM->pdm.s.fResetFlags = fFlags; */
1951 VM_FF_SET(pVM, VM_FF_RESET);
1952 rcStrict = VINF_EM_RESET;
1953 }
1954 break;
1955 }
1956 case ARM_PSCI_FUNC_ID_CPU_ON:
1957 {
1958 uint64_t u64TgtCpu = nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X1);
1959 RTGCPHYS GCPhysExecAddr = nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X2);
1960 uint64_t u64CtxId = nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X3);
1961 VMMR3CpuOn(pVM, u64TgtCpu & 0xff, GCPhysExecAddr, u64CtxId);
1962 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, true /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_STS_SUCCESS);
1963 break;
1964 }
1965 case ARM_PSCI_FUNC_ID_PSCI_FEATURES:
1966 {
1967 uint32_t u32FunNum = (uint32_t)nemR3DarwinGetGReg(pVCpu, ARMV8_A64_REG_X1);
1968 switch (u32FunNum)
1969 {
1970 case ARM_PSCI_FUNC_ID_PSCI_VERSION:
1971 case ARM_PSCI_FUNC_ID_SYSTEM_OFF:
1972 case ARM_PSCI_FUNC_ID_SYSTEM_RESET:
1973 case ARM_PSCI_FUNC_ID_SYSTEM_RESET2:
1974 case ARM_PSCI_FUNC_ID_CPU_ON:
1975 case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1976 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0,
1977 false /*f64BitReg*/, false /*fSignExtend*/,
1978 (uint64_t)ARM_PSCI_STS_SUCCESS);
1979 break;
1980 default:
1981 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0,
1982 false /*f64BitReg*/, false /*fSignExtend*/,
1983 (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1984 }
1985 break;
1986 }
1987 case ARM_PSCI_FUNC_ID_MIGRATE_INFO_TYPE:
1988 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, ARM_PSCI_MIGRATE_INFO_TYPE_TOS_NOT_PRESENT);
1989 break;
1990 default:
1991 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1992 }
1993 }
1994 else
1995 nemR3DarwinSetGReg(pVCpu, ARMV8_A64_REG_X0, false /*f64BitReg*/, false /*fSignExtend*/, (uint64_t)ARM_PSCI_STS_NOT_SUPPORTED);
1996 }
1997
1998 /** @todo What to do if immediate is != 0? */
1999
2000 if ( rcStrict == VINF_SUCCESS
2001 && fAdvancePc)
2002 pVCpu->cpum.GstCtx.Pc.u64 += sizeof(uint32_t);
2003
2004 return rcStrict;
2005}
2006
2007
2008/**
2009 * Handles an exception VM exit.
2010 *
2011 * @returns VBox strict status code.
2012 * @param pVM The cross context VM structure.
2013 * @param pVCpu The cross context virtual CPU structure of the
2014 * calling EMT.
2015 * @param pExit Pointer to the exit information.
2016 */
2017static VBOXSTRICTRC nemR3DarwinHandleExitException(PVM pVM, PVMCPU pVCpu, const hv_vcpu_exit_t *pExit)
2018{
2019 uint32_t uEc = ARMV8_ESR_EL2_EC_GET(pExit->exception.syndrome);
2020 uint32_t uIss = ARMV8_ESR_EL2_ISS_GET(pExit->exception.syndrome);
2021 bool fInsn32Bit = ARMV8_ESR_EL2_IL_IS_32BIT(pExit->exception.syndrome);
2022
2023 LogFlowFunc(("pVM=%p pVCpu=%p{.idCpu=%u} uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2024 pVM, pVCpu, pVCpu->idCpu, uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2025
2026 switch (uEc)
2027 {
2028 case ARMV8_ESR_EL2_DATA_ABORT_FROM_LOWER_EL:
2029 return nemR3DarwinHandleExitExceptionDataAbort(pVM, pVCpu, uIss, fInsn32Bit, pExit->exception.virtual_address,
2030 pExit->exception.physical_address);
2031 case ARMV8_ESR_EL2_EC_AARCH64_TRAPPED_SYS_INSN:
2032 return nemR3DarwinHandleExitExceptionTrappedSysInsn(pVM, pVCpu, uIss, fInsn32Bit);
2033 case ARMV8_ESR_EL2_EC_AARCH64_HVC_INSN:
2034 return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss);
2035 case ARMV8_ESR_EL2_EC_AARCH64_SMC_INSN:
2036 return nemR3DarwinHandleExitExceptionTrappedHvcInsn(pVM, pVCpu, uIss, true);
2037 case ARMV8_ESR_EL2_EC_TRAPPED_WFX:
2038 {
2039 /* No need to halt if there is an interrupt pending already. */
2040 if (VMCPU_FF_IS_ANY_SET(pVCpu, (VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ)))
2041 {
2042 LogFlowFunc(("IRQ | FIQ set => VINF_SUCCESS\n"));
2043 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2044 return VINF_SUCCESS;
2045 }
2046
2047 /* Set the vTimer expiration in order to get out of the halt at the right point in time. */
2048 if ( (pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE)
2049 && !(pVCpu->cpum.GstCtx.CntvCtlEl0 & ARMV8_CNTV_CTL_EL0_AARCH64_IMASK))
2050 {
2051 uint64_t cTicksVTimer = mach_absolute_time() - pVM->nem.s.u64VTimerOff;
2052
2053 /* Check whether it expired and start executing guest code. */
2054 if (cTicksVTimer >= pVCpu->cpum.GstCtx.CntvCValEl0)
2055 {
2056 LogFlowFunc(("Guest timer expired (cTicksVTimer=%RU64 CntvCValEl0=%RU64) => VINF_SUCCESS\n",
2057 cTicksVTimer, pVCpu->cpum.GstCtx.CntvCValEl0));
2058 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2059 return VINF_SUCCESS;
2060 }
2061
2062 uint64_t cTicksVTimerToExpire = pVCpu->cpum.GstCtx.CntvCValEl0 - cTicksVTimer;
2063 uint64_t cNanoSecsVTimerToExpire = ASMMultU64ByU32DivByU32(cTicksVTimerToExpire, RT_NS_1SEC, (uint32_t)pVM->nem.s.u64CntFrqHz);
2064
2065 /*
2066 * Our halt method doesn't work with sub millisecond granularity at the moment causing a huge slowdown
2067 * + scheduling overhead which would increase the wakeup latency.
2068 * So only halt when the threshold is exceeded (needs more experimentation but 5ms turned out to be a good compromise
2069 * between CPU load when the guest is idle and performance).
2070 */
2071 if (cNanoSecsVTimerToExpire < 2 * RT_NS_1MS)
2072 {
2073 LogFlowFunc(("Guest timer expiration < 2ms (cNanoSecsVTimerToExpire=%RU64) => VINF_SUCCESS\n",
2074 cNanoSecsVTimerToExpire));
2075 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2076 return VINF_SUCCESS;
2077 }
2078
2079 LogFlowFunc(("Set vTimer activation to cNanoSecsVTimerToExpire=%#RX64 (CntvCValEl0=%#RX64, u64VTimerOff=%#RX64 cTicksVTimer=%#RX64 u64CntFrqHz=%#RX64)\n",
2080 cNanoSecsVTimerToExpire, pVCpu->cpum.GstCtx.CntvCValEl0, pVM->nem.s.u64VTimerOff, cTicksVTimer, pVM->nem.s.u64CntFrqHz));
2081 TMCpuSetVTimerNextActivation(pVCpu, cNanoSecsVTimerToExpire);
2082 }
2083 else
2084 TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2085
2086 pVCpu->cpum.GstCtx.Pc.u64 += fInsn32Bit ? sizeof(uint32_t) : sizeof(uint16_t);
2087 return VINF_EM_HALT;
2088 }
2089 case ARMV8_ESR_EL2_EC_AARCH64_BRK_INSN:
2090 {
2091 VBOXSTRICTRC rcStrict = DBGFTrap03Handler(pVCpu->CTX_SUFF(pVM), pVCpu, &pVCpu->cpum.GstCtx);
2092 /** @todo Forward genuine guest traps to the guest by either single stepping instruction with debug exception trapping turned off
2093 * or create instruction interpreter and inject exception ourselves. */
2094 Assert(rcStrict == VINF_EM_DBG_BREAKPOINT);
2095 return rcStrict;
2096 }
2097 case ARMV8_ESR_EL2_SS_EXCEPTION_FROM_LOWER_EL:
2098 return VINF_EM_DBG_STEPPED;
2099 case ARMV8_ESR_EL2_EC_UNKNOWN:
2100 default:
2101 LogRel(("NEM/Darwin: Unknown Exception Class in syndrome: uEc=%u{%s} uIss=%#RX32 fInsn32Bit=%RTbool\n",
2102 uEc, nemR3DarwinEsrEl2EcStringify(uEc), uIss, fInsn32Bit));
2103 AssertReleaseFailed();
2104 return VERR_NOT_IMPLEMENTED;
2105 }
2106
2107 return VINF_SUCCESS;
2108}
2109
2110
2111/**
2112 * Handles an exit from hv_vcpu_run().
2113 *
2114 * @returns VBox strict status code.
2115 * @param pVM The cross context VM structure.
2116 * @param pVCpu The cross context virtual CPU structure of the
2117 * calling EMT.
2118 */
2119static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu)
2120{
2121 int rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
2122 if (RT_FAILURE(rc))
2123 return rc;
2124
2125#ifdef LOG_ENABLED
2126 if (LogIs3Enabled())
2127 nemR3DarwinLogState(pVM, pVCpu);
2128#endif
2129
2130 hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit;
2131 switch (pExit->reason)
2132 {
2133 case HV_EXIT_REASON_CANCELED:
2134 return VINF_EM_RAW_INTERRUPT;
2135 case HV_EXIT_REASON_EXCEPTION:
2136 return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
2137 case HV_EXIT_REASON_VTIMER_ACTIVATED:
2138 {
2139 LogFlowFunc(("vTimer got activated\n"));
2140 TMCpuSetVTimerNextActivation(pVCpu, UINT64_MAX);
2141 pVCpu->nem.s.fVTimerActivated = true;
2142 return PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, true /*fAsserted*/);
2143 }
2144 default:
2145 AssertReleaseFailed();
2146 break;
2147 }
2148
2149 return VERR_INVALID_STATE;
2150}
2151
2152
2153/**
2154 * Runs the guest once until an exit occurs.
2155 *
2156 * @returns HV status code.
2157 * @param pVM The cross context VM structure.
2158 * @param pVCpu The cross context virtual CPU structure.
2159 */
2160static hv_return_t nemR3DarwinRunGuest(PVM pVM, PVMCPU pVCpu)
2161{
2162 TMNotifyStartOfExecution(pVM, pVCpu);
2163
2164 hv_return_t hrc = hv_vcpu_run(pVCpu->nem.s.hVCpu);
2165
2166 TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2167
2168 return hrc;
2169}
2170
2171
2172/**
2173 * Prepares the VM to run the guest.
2174 *
2175 * @returns Strict VBox status code.
2176 * @param pVM The cross context VM structure.
2177 * @param pVCpu The cross context virtual CPU structure.
2178 * @param fSingleStepping Flag whether we run in single stepping mode.
2179 */
2180static VBOXSTRICTRC nemR3DarwinPreRunGuest(PVM pVM, PVMCPU pVCpu, bool fSingleStepping)
2181{
2182#ifdef LOG_ENABLED
2183 bool fIrq = false;
2184 bool fFiq = false;
2185
2186 if (LogIs3Enabled())
2187 nemR3DarwinLogState(pVM, pVCpu);
2188#endif
2189
2190 int rc = nemR3DarwinExportGuestState(pVM, pVCpu);
2191 AssertRCReturn(rc, rc);
2192
2193 /* In single stepping mode we will re-read SPSR and MDSCR and enable the software step bits. */
2194 if (fSingleStepping)
2195 {
2196 uint64_t u64Tmp;
2197 hv_return_t hrc = hv_vcpu_get_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, &u64Tmp);
2198 if (hrc == HV_SUCCESS)
2199 {
2200 u64Tmp |= ARMV8_SPSR_EL2_AARCH64_SS;
2201 hrc = hv_vcpu_set_reg(pVCpu->nem.s.hVCpu, HV_REG_CPSR, u64Tmp);
2202 }
2203
2204 hrc |= hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, &u64Tmp);
2205 if (hrc == HV_SUCCESS)
2206 {
2207 u64Tmp |= ARMV8_MDSCR_EL1_AARCH64_SS;
2208 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_MDSCR_EL1, u64Tmp);
2209 }
2210
2211 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2212 }
2213
2214 /* Check whether the vTimer interrupt was handled by the guest and we can unmask the vTimer. */
2215 if (pVCpu->nem.s.fVTimerActivated)
2216 {
2217 /* Read the CNTV_CTL_EL0 register. */
2218 uint64_t u64CntvCtl = 0;
2219
2220 hv_return_t hrc = hv_vcpu_get_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, &u64CntvCtl);
2221 AssertRCReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2222
2223 if ( (u64CntvCtl & (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE | ARMV8_CNTV_CTL_EL0_AARCH64_IMASK | ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2224 != (ARMV8_CNTV_CTL_EL0_AARCH64_ENABLE | ARMV8_CNTV_CTL_EL0_AARCH64_ISTATUS))
2225 {
2226 /* Clear the interrupt. */
2227 PDMGicSetPpi(pVCpu, pVM->nem.s.u32GicPpiVTimer, false /*fAsserted*/);
2228
2229 pVCpu->nem.s.fVTimerActivated = false;
2230 hrc = hv_vcpu_set_vtimer_mask(pVCpu->nem.s.hVCpu, false /*vtimer_is_masked*/);
2231 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2232 }
2233 }
2234
2235 /* Set the pending interrupt state. */
2236 hv_return_t hrc = HV_SUCCESS;
2237 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
2238 {
2239 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
2240 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2241#ifdef LOG_ENABLED
2242 fIrq = true;
2243#endif
2244 }
2245 else
2246 {
2247 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
2248 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2249 }
2250
2251 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
2252 {
2253 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
2254 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2255#ifdef LOG_ENABLED
2256 fFiq = true;
2257#endif
2258 }
2259 else
2260 {
2261 hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
2262 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
2263 }
2264
2265 LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
2266 pVCpu->nem.s.fEventPending = false;
2267 return VINF_SUCCESS;
2268}
2269
2270
2271/**
2272 * The normal runloop (no debugging features enabled).
2273 *
2274 * @returns Strict VBox status code.
2275 * @param pVM The cross context VM structure.
2276 * @param pVCpu The cross context virtual CPU structure.
2277 */
2278static VBOXSTRICTRC nemR3DarwinRunGuestNormal(PVM pVM, PVMCPU pVCpu)
2279{
2280 /*
2281 * The run loop.
2282 *
2283 * Current approach to state updating to use the sledgehammer and sync
2284 * everything every time. This will be optimized later.
2285 */
2286
2287 /* Update the vTimer offset after resuming if instructed. */
2288 if (pVCpu->nem.s.fVTimerOffUpdate)
2289 {
2290 hv_return_t hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2291 if (hrc != HV_SUCCESS)
2292 return nemR3DarwinHvSts2Rc(hrc);
2293
2294 pVCpu->nem.s.fVTimerOffUpdate = false;
2295
2296 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2297 if (hrc == HV_SUCCESS)
2298 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2299 if (hrc != HV_SUCCESS)
2300 return nemR3DarwinHvSts2Rc(hrc);
2301 }
2302
2303 /*
2304 * Poll timers and run for a bit.
2305 */
2306 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2307 * the whole polling job when timers have changed... */
2308 uint64_t offDeltaIgnored;
2309 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2310 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2311 for (unsigned iLoop = 0;; iLoop++)
2312 {
2313 rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, false /* fSingleStepping */);
2314 if (rcStrict != VINF_SUCCESS)
2315 break;
2316
2317 hv_return_t hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2318 if (hrc == HV_SUCCESS)
2319 {
2320 /*
2321 * Deal with the message.
2322 */
2323 rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2324 if (rcStrict == VINF_SUCCESS)
2325 { /* hopefully likely */ }
2326 else
2327 {
2328 LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2329 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2330 break;
2331 }
2332 }
2333 else
2334 {
2335 AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2336 pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2337 }
2338 } /* the run loop */
2339
2340 return rcStrict;
2341}
2342
2343
2344/**
2345 * The debug runloop.
2346 *
2347 * @returns Strict VBox status code.
2348 * @param pVM The cross context VM structure.
2349 * @param pVCpu The cross context virtual CPU structure.
2350 */
2351static VBOXSTRICTRC nemR3DarwinRunGuestDebug(PVM pVM, PVMCPU pVCpu)
2352{
2353 /*
2354 * The run loop.
2355 *
2356 * Current approach to state updating to use the sledgehammer and sync
2357 * everything every time. This will be optimized later.
2358 */
2359
2360 bool const fSavedSingleInstruction = pVCpu->nem.s.fSingleInstruction;
2361 pVCpu->nem.s.fSingleInstruction = pVCpu->nem.s.fSingleInstruction || DBGFIsStepping(pVCpu);
2362 pVCpu->nem.s.fUsingDebugLoop = true;
2363
2364 /* Trap any debug exceptions. */
2365 hv_return_t hrc = hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, true);
2366 if (hrc != HV_SUCCESS)
2367 return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2368 "Trapping debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2369
2370 /* Update the vTimer offset after resuming if instructed. */
2371 if (pVCpu->nem.s.fVTimerOffUpdate)
2372 {
2373 hrc = hv_vcpu_set_vtimer_offset(pVCpu->nem.s.hVCpu, pVM->nem.s.u64VTimerOff);
2374 if (hrc != HV_SUCCESS)
2375 return nemR3DarwinHvSts2Rc(hrc);
2376
2377 pVCpu->nem.s.fVTimerOffUpdate = false;
2378
2379 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CTL_EL0, pVCpu->cpum.GstCtx.CntvCtlEl0);
2380 if (hrc == HV_SUCCESS)
2381 hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, HV_SYS_REG_CNTV_CVAL_EL0, pVCpu->cpum.GstCtx.CntvCValEl0);
2382 if (hrc != HV_SUCCESS)
2383 return nemR3DarwinHvSts2Rc(hrc);
2384 }
2385
2386 /* Save the guest MDSCR_EL1 */
2387 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG | CPUMCTX_EXTRN_PSTATE);
2388 uint64_t u64RegMdscrEl1 = pVCpu->cpum.GstCtx.Mdscr.u64;
2389
2390 /*
2391 * Poll timers and run for a bit.
2392 */
2393 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2394 * the whole polling job when timers have changed... */
2395 uint64_t offDeltaIgnored;
2396 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2397 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2398 for (unsigned iLoop = 0;; iLoop++)
2399 {
2400 bool const fStepping = pVCpu->nem.s.fSingleInstruction;
2401
2402 rcStrict = nemR3DarwinPreRunGuest(pVM, pVCpu, fStepping);
2403 if (rcStrict != VINF_SUCCESS)
2404 break;
2405
2406 hrc = nemR3DarwinRunGuest(pVM, pVCpu);
2407 if (hrc == HV_SUCCESS)
2408 {
2409 /*
2410 * Deal with the message.
2411 */
2412 rcStrict = nemR3DarwinHandleExit(pVM, pVCpu);
2413 if (rcStrict == VINF_SUCCESS)
2414 { /* hopefully likely */ }
2415 else
2416 {
2417 LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2418 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2419 break;
2420 }
2421 }
2422 else
2423 {
2424 AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x \n",
2425 pVCpu->idCpu, hrc), VERR_NEM_IPE_0);
2426 }
2427 } /* the run loop */
2428
2429 /* Restore single stepping state. */
2430 if (pVCpu->nem.s.fSingleInstruction)
2431 {
2432 /** @todo This ASSUMES that guest code being single stepped is not modifying the MDSCR_EL1 register. */
2433 CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_SYSREG_DEBUG | CPUMCTX_EXTRN_PSTATE);
2434 Assert(pVCpu->cpum.GstCtx.Mdscr.u64 & ARMV8_MDSCR_EL1_AARCH64_SS);
2435
2436 pVCpu->cpum.GstCtx.Mdscr.u64 = u64RegMdscrEl1;
2437 }
2438
2439 /* Restore debug exceptions trapping. */
2440 hrc |= hv_vcpu_set_trap_debug_exceptions(pVCpu->nem.s.hVCpu, false);
2441 if (hrc != HV_SUCCESS)
2442 return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2443 "Clearing trapping of debug exceptions on vCPU %u failed: %#x (%Rrc)", pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2444
2445 pVCpu->nem.s.fUsingDebugLoop = false;
2446 pVCpu->nem.s.fSingleInstruction = fSavedSingleInstruction;
2447
2448 return rcStrict;
2449
2450}
2451
2452
2453VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2454{
2455#ifdef LOG_ENABLED
2456 if (LogIs3Enabled())
2457 nemR3DarwinLogState(pVM, pVCpu);
2458#endif
2459
2460 AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
2461
2462 if (RT_UNLIKELY(!pVCpu->nem.s.fIdRegsSynced))
2463 {
2464 /*
2465 * Sync the guest ID registers which are per VM once (they are readonly and stay constant during VM lifetime).
2466 * Need to do it here and not during the init because loading a saved state might change the ID registers from what
2467 * done in the call to CPUMR3PopulateFeaturesByIdRegisters().
2468 */
2469 static const struct
2470 {
2471 const char *pszIdReg;
2472 hv_sys_reg_t enmHvReg;
2473 uint32_t offIdStruct;
2474 } s_aSysIdRegs[] =
2475 {
2476#define ID_SYS_REG_CREATE(a_IdReg, a_CpumIdReg) { #a_IdReg, HV_SYS_REG_##a_IdReg, RT_UOFFSETOF(CPUMARMV8IDREGS, a_CpumIdReg) }
2477 ID_SYS_REG_CREATE(ID_AA64DFR0_EL1, u64RegIdAa64Dfr0El1),
2478 ID_SYS_REG_CREATE(ID_AA64DFR1_EL1, u64RegIdAa64Dfr1El1),
2479 ID_SYS_REG_CREATE(ID_AA64ISAR0_EL1, u64RegIdAa64Isar0El1),
2480 ID_SYS_REG_CREATE(ID_AA64ISAR1_EL1, u64RegIdAa64Isar1El1),
2481 ID_SYS_REG_CREATE(ID_AA64MMFR0_EL1, u64RegIdAa64Mmfr0El1),
2482 ID_SYS_REG_CREATE(ID_AA64MMFR1_EL1, u64RegIdAa64Mmfr1El1),
2483 ID_SYS_REG_CREATE(ID_AA64MMFR2_EL1, u64RegIdAa64Mmfr2El1),
2484 ID_SYS_REG_CREATE(ID_AA64PFR0_EL1, u64RegIdAa64Pfr0El1),
2485 ID_SYS_REG_CREATE(ID_AA64PFR1_EL1, u64RegIdAa64Pfr1El1),
2486#undef ID_SYS_REG_CREATE
2487 };
2488
2489 PCCPUMARMV8IDREGS pIdRegsGst = NULL;
2490 int rc = CPUMR3QueryGuestIdRegs(pVM, &pIdRegsGst);
2491 AssertRCReturn(rc, rc);
2492
2493 for (uint32_t i = 0; i < RT_ELEMENTS(s_aSysIdRegs); i++)
2494 {
2495 uint64_t *pu64 = (uint64_t *)((uint8_t *)pIdRegsGst + s_aSysIdRegs[i].offIdStruct);
2496 hv_return_t hrc = hv_vcpu_set_sys_reg(pVCpu->nem.s.hVCpu, s_aSysIdRegs[i].enmHvReg, *pu64);
2497 if (hrc != HV_SUCCESS)
2498 return VMSetError(pVM, VERR_NEM_SET_REGISTERS_FAILED, RT_SRC_POS,
2499 "Setting %s failed on vCPU %u: %#x (%Rrc)", s_aSysIdRegs[i].pszIdReg, pVCpu->idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2500 }
2501
2502 pVCpu->nem.s.fIdRegsSynced = true;
2503 }
2504
2505 /*
2506 * Try switch to NEM runloop state.
2507 */
2508 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2509 { /* likely */ }
2510 else
2511 {
2512 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2513 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2514 return VINF_SUCCESS;
2515 }
2516
2517 VBOXSTRICTRC rcStrict;
2518 if ( !pVCpu->nem.s.fUseDebugLoop
2519 /*&& !nemR3DarwinAnyExpensiveProbesEnabled()*/
2520 && !DBGFIsStepping(pVCpu)
2521 && !pVCpu->CTX_SUFF(pVM)->dbgf.ro.cEnabledSwBreakpoints)
2522 rcStrict = nemR3DarwinRunGuestNormal(pVM, pVCpu);
2523 else
2524 rcStrict = nemR3DarwinRunGuestDebug(pVM, pVCpu);
2525
2526 if (rcStrict == VINF_EM_RAW_TO_R3)
2527 rcStrict = VINF_SUCCESS;
2528
2529 /*
2530 * Convert any pending HM events back to TRPM due to premature exits.
2531 *
2532 * This is because execution may continue from IEM and we would need to inject
2533 * the event from there (hence place it back in TRPM).
2534 */
2535 if (pVCpu->nem.s.fEventPending)
2536 {
2537 /** @todo */
2538 }
2539
2540
2541 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2542 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2543
2544 if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2545 {
2546 /* Try anticipate what we might need. */
2547 uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
2548 if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2549 || RT_FAILURE(rcStrict))
2550 fImport = CPUMCTX_EXTRN_ALL;
2551 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ
2552 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2553 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2554
2555 if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2556 {
2557 /* Only import what is external currently. */
2558 int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2559 if (RT_SUCCESS(rc2))
2560 pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2561 else if (RT_SUCCESS(rcStrict))
2562 rcStrict = rc2;
2563 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2564 pVCpu->cpum.GstCtx.fExtrn = 0;
2565 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2566 }
2567 else
2568 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2569 }
2570 else
2571 {
2572 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2573 pVCpu->cpum.GstCtx.fExtrn = 0;
2574 }
2575
2576 return rcStrict;
2577}
2578
2579
2580VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2581{
2582 RT_NOREF(pVM, pVCpu);
2583 return true; /** @todo Are there any cases where we have to emulate? */
2584}
2585
2586
2587bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2588{
2589 VMCPU_ASSERT_EMT(pVCpu);
2590 bool fOld = pVCpu->nem.s.fSingleInstruction;
2591 pVCpu->nem.s.fSingleInstruction = fEnable;
2592 pVCpu->nem.s.fUseDebugLoop = fEnable || pVM->nem.s.fUseDebugLoop;
2593 return fOld;
2594}
2595
2596
2597void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2598{
2599 LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2600
2601 RT_NOREF(pVM, fFlags);
2602
2603 hv_return_t hrc = hv_vcpus_exit(&pVCpu->nem.s.hVCpu, 1);
2604 if (hrc != HV_SUCCESS)
2605 LogRel(("NEM: hv_vcpus_exit(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpu, hrc));
2606}
2607
2608
2609DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChanged(PVM pVM, bool fUseDebugLoop)
2610{
2611 RT_NOREF(pVM, fUseDebugLoop);
2612 //AssertReleaseFailed();
2613 return false;
2614}
2615
2616
2617DECLHIDDEN(bool) nemR3NativeNotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu, bool fUseDebugLoop)
2618{
2619 RT_NOREF(pVM, pVCpu, fUseDebugLoop);
2620 return fUseDebugLoop;
2621}
2622
2623
2624VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2625 uint8_t *pu2State, uint32_t *puNemRange)
2626{
2627 RT_NOREF(pVM, puNemRange);
2628
2629 Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2630#if defined(VBOX_WITH_PGM_NEM_MODE)
2631 if (pvR3)
2632 {
2633 int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
2634 if (RT_FAILURE(rc))
2635 {
2636 LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2637 return VERR_NEM_MAP_PAGES_FAILED;
2638 }
2639 }
2640 return VINF_SUCCESS;
2641#else
2642 RT_NOREF(pVM, GCPhys, cb, pvR3);
2643 return VERR_NEM_MAP_PAGES_FAILED;
2644#endif
2645}
2646
2647
2648VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2649{
2650 RT_NOREF(pVM);
2651 return true;
2652}
2653
2654
2655VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2656 void *pvRam, void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
2657{
2658 RT_NOREF(pvRam);
2659
2660 Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2661 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2662
2663#if defined(VBOX_WITH_PGM_NEM_MODE)
2664 /*
2665 * Unmap the RAM we're replacing.
2666 */
2667 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2668 {
2669 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2670 if (RT_SUCCESS(rc))
2671 { /* likely */ }
2672 else if (pvMmio2)
2673 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2674 GCPhys, cb, fFlags, rc));
2675 else
2676 {
2677 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2678 GCPhys, cb, fFlags, rc));
2679 return VERR_NEM_UNMAP_PAGES_FAILED;
2680 }
2681 }
2682
2683 /*
2684 * Map MMIO2 if any.
2685 */
2686 if (pvMmio2)
2687 {
2688 Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2689
2690 /* We need to set up our own dirty tracking due to Hypervisor.framework only working on host page sized aligned regions. */
2691 uint32_t fProt = NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE;
2692 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2693 {
2694 /* Find a slot for dirty tracking. */
2695 PNEMHVMMIO2REGION pMmio2Region = NULL;
2696 uint32_t idSlot;
2697 for (idSlot = 0; idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking); idSlot++)
2698 {
2699 if ( pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart == 0
2700 && pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast == 0)
2701 {
2702 pMmio2Region = &pVM->nem.s.aMmio2DirtyTracking[idSlot];
2703 break;
2704 }
2705 }
2706
2707 if (!pMmio2Region)
2708 {
2709 LogRel(("NEMR3NotifyPhysMmioExMapEarly: Out of dirty tracking structures -> VERR_NEM_MAP_PAGES_FAILED\n"));
2710 return VERR_NEM_MAP_PAGES_FAILED;
2711 }
2712
2713 pMmio2Region->GCPhysStart = GCPhys;
2714 pMmio2Region->GCPhysLast = GCPhys + cb - 1;
2715 pMmio2Region->fDirty = false;
2716 *puNemRange = idSlot;
2717 }
2718 else
2719 fProt |= NEM_PAGE_PROT_WRITE;
2720
2721 int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, fProt, pu2State);
2722 if (RT_FAILURE(rc))
2723 {
2724 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2725 GCPhys, cb, fFlags, pvMmio2, rc));
2726 return VERR_NEM_MAP_PAGES_FAILED;
2727 }
2728 }
2729 else
2730 Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2731
2732#else
2733 RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2734 *pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2735#endif
2736 return VINF_SUCCESS;
2737}
2738
2739
2740VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2741 void *pvRam, void *pvMmio2, uint32_t *puNemRange)
2742{
2743 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2744 return VINF_SUCCESS;
2745}
2746
2747
2748VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2749 void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
2750{
2751 RT_NOREF(pVM, puNemRange);
2752
2753 Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
2754 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
2755
2756 int rc = VINF_SUCCESS;
2757#if defined(VBOX_WITH_PGM_NEM_MODE)
2758 /*
2759 * Unmap the MMIO2 pages.
2760 */
2761 /** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2762 * we may have more stuff to unmap even in case of pure MMIO... */
2763 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2764 {
2765 rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2766 if (RT_FAILURE(rc))
2767 {
2768 LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2769 GCPhys, cb, fFlags, rc));
2770 rc = VERR_NEM_UNMAP_PAGES_FAILED;
2771 }
2772
2773 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES)
2774 {
2775 /* Reset tracking structure. */
2776 uint32_t idSlot = *puNemRange;
2777 *puNemRange = UINT32_MAX;
2778
2779 Assert(idSlot < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2780 pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysStart = 0;
2781 pVM->nem.s.aMmio2DirtyTracking[idSlot].GCPhysLast = 0;
2782 pVM->nem.s.aMmio2DirtyTracking[idSlot].fDirty = false;
2783 }
2784 }
2785
2786 /* Ensure the page is masked as unmapped if relevant. */
2787 Assert(!pu2State || *pu2State == NEM_DARWIN_PAGE_STATE_UNMAPPED);
2788
2789 /*
2790 * Restore the RAM we replaced.
2791 */
2792 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2793 {
2794 AssertPtr(pvRam);
2795 rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
2796 if (RT_SUCCESS(rc))
2797 { /* likely */ }
2798 else
2799 {
2800 LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2801 rc = VERR_NEM_MAP_PAGES_FAILED;
2802 }
2803 }
2804
2805 RT_NOREF(pvMmio2);
2806#else
2807 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2808 if (pu2State)
2809 *pu2State = UINT8_MAX;
2810 rc = VERR_NEM_UNMAP_PAGES_FAILED;
2811#endif
2812 return rc;
2813}
2814
2815
2816VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2817 void *pvBitmap, size_t cbBitmap)
2818{
2819 LogFlowFunc(("NEMR3PhysMmio2QueryAndResetDirtyBitmap: %RGp LB %RGp UnemRange=%u\n", GCPhys, cb, uNemRange));
2820 Assert(uNemRange < RT_ELEMENTS(pVM->nem.s.aMmio2DirtyTracking));
2821
2822 /* Keep it simple for now and mark everything as dirty if it is. */
2823 int rc = VINF_SUCCESS;
2824 if (pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty)
2825 {
2826 ASMBitSetRange(pvBitmap, 0, cbBitmap * 8);
2827
2828 pVM->nem.s.aMmio2DirtyTracking[uNemRange].fDirty = false;
2829 /* Restore as RX only. */
2830 uint8_t u2State;
2831 rc = nemR3DarwinProtect(GCPhys, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE, &u2State);
2832 }
2833 else
2834 ASMBitClearRange(pvBitmap, 0, cbBitmap * 8);
2835
2836 return rc;
2837}
2838
2839
2840VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2841 uint8_t *pu2State, uint32_t *puNemRange)
2842{
2843 RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2844
2845 Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2846 *pu2State = UINT8_MAX;
2847 *puNemRange = 0;
2848 return VINF_SUCCESS;
2849}
2850
2851
2852VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2853 uint32_t fFlags, uint8_t *pu2State, uint32_t *puNemRange)
2854{
2855 Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
2856 GCPhys, cb, pvPages, fFlags, pu2State, *pu2State, puNemRange, *puNemRange));
2857 *pu2State = UINT8_MAX;
2858
2859#if defined(VBOX_WITH_PGM_NEM_MODE)
2860 /*
2861 * (Re-)map readonly.
2862 */
2863 AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2864
2865 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2866 AssertRC(rc);
2867
2868 rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE, pu2State);
2869 if (RT_FAILURE(rc))
2870 {
2871 LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2872 GCPhys, cb, pvPages, fFlags, rc));
2873 return VERR_NEM_MAP_PAGES_FAILED;
2874 }
2875 RT_NOREF(fFlags, puNemRange);
2876 return VINF_SUCCESS;
2877#else
2878 RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
2879 return VERR_NEM_MAP_PAGES_FAILED;
2880#endif
2881}
2882
2883
2884VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2885 RTR3PTR pvMemR3, uint8_t *pu2State)
2886{
2887 Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2888 GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2889
2890 *pu2State = UINT8_MAX;
2891#if defined(VBOX_WITH_PGM_NEM_MODE)
2892 if (pvMemR3)
2893 {
2894 /* Unregister what was there before. */
2895 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb, pu2State);
2896 AssertRC(rc);
2897
2898 rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE, pu2State);
2899 AssertLogRelMsgRC(rc, ("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
2900 pvMemR3, GCPhys, cb, rc));
2901 }
2902 RT_NOREF(enmKind);
2903#else
2904 RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
2905 AssertFailed();
2906#endif
2907}
2908
2909
2910VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
2911{
2912 Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
2913 RT_NOREF(pVCpu, fEnabled);
2914}
2915
2916
2917void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
2918{
2919 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
2920 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
2921}
2922
2923
2924void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
2925 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
2926{
2927 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
2928 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
2929 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
2930}
2931
2932
2933int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
2934 PGMPAGETYPE enmType, uint8_t *pu2State)
2935{
2936 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2937 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2938 RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
2939
2940 AssertFailed();
2941 return VINF_SUCCESS;
2942}
2943
2944
2945VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
2946 PGMPAGETYPE enmType, uint8_t *pu2State)
2947{
2948 Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2949 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
2950 RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
2951}
2952
2953
2954VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
2955 RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
2956{
2957 Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
2958 GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
2959 RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
2960
2961 AssertFailed();
2962}
2963
2964
2965/**
2966 * Interface for importing state on demand (used by IEM).
2967 *
2968 * @returns VBox status code.
2969 * @param pVCpu The cross context CPU structure.
2970 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
2971 */
2972VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
2973{
2974 LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
2975 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
2976
2977 return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
2978}
2979
2980
2981/**
2982 * Query the CPU tick counter and optionally the TSC_AUX MSR value.
2983 *
2984 * @returns VBox status code.
2985 * @param pVCpu The cross context CPU structure.
2986 * @param pcTicks Where to return the CPU tick count.
2987 * @param puAux Where to return the TSC_AUX register value.
2988 */
2989VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)
2990{
2991 LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
2992 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
2993
2994 if (puAux)
2995 *puAux = 0;
2996 *pcTicks = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff; /* This is the host timer minus the offset. */
2997 return VINF_SUCCESS;
2998}
2999
3000
3001/**
3002 * Resumes CPU clock (TSC) on all virtual CPUs.
3003 *
3004 * This is called by TM when the VM is started, restored, resumed or similar.
3005 *
3006 * @returns VBox status code.
3007 * @param pVM The cross context VM structure.
3008 * @param pVCpu The cross context CPU structure of the calling EMT.
3009 * @param uPausedTscValue The TSC value at the time of pausing.
3010 */
3011VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
3012{
3013 LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVM, pVCpu, uPausedTscValue));
3014 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
3015 AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
3016
3017 /*
3018 * Calculate the new offset, first get the new TSC value with the old vTimer offset and then adjust the
3019 * the new offset to let the guest not notice the pause.
3020 */
3021 uint64_t u64TscNew = mach_absolute_time() - pVCpu->pVMR3->nem.s.u64VTimerOff;
3022 Assert(u64TscNew >= uPausedTscValue);
3023 LogFlowFunc(("u64VTimerOffOld=%#RX64 u64TscNew=%#RX64 u64VTimerValuePaused=%#RX64 -> u64VTimerOff=%#RX64\n",
3024 pVM->nem.s.u64VTimerOff, u64TscNew, uPausedTscValue,
3025 pVM->nem.s.u64VTimerOff + (u64TscNew - uPausedTscValue)));
3026
3027 pVM->nem.s.u64VTimerOff += u64TscNew - uPausedTscValue;
3028
3029 /*
3030 * Set the flag to update the vTimer offset when the vCPU resumes for the first time
3031 * (needs to be done on the actual EMT).
3032 */
3033 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3034 {
3035 PVMCPUCC pVCpuDst = pVM->apCpusR3[idCpu];
3036 pVCpuDst->nem.s.fVTimerOffUpdate = true;
3037 }
3038
3039 return VINF_SUCCESS;
3040}
3041
3042
3043/**
3044 * Returns features supported by the NEM backend.
3045 *
3046 * @returns Flags of features supported by the native NEM backend.
3047 * @param pVM The cross context VM structure.
3048 */
3049VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
3050{
3051 RT_NOREF(pVM);
3052 /*
3053 * Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
3054 * and unrestricted guest execution support so we can safely return these flags here always.
3055 */
3056 return NEM_FEAT_F_NESTED_PAGING | NEM_FEAT_F_FULL_GST_EXEC | NEM_FEAT_F_XSAVE_XRSTOR;
3057}
3058
3059
3060/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
3061 *
3062 * @todo Add notes as the implementation progresses...
3063 */
3064
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