NEMR3Native-darwin.cpp@ 92424

Last change on this file since 92424 was 92376, checked in by vboxsync, 3 years ago
VMM/NEMR3Native-darwin: Make use of the ASID feature if available on the platform, some smaller cleanups, bugref:9044
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 121.2 KB

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1	/* $Id: NEMR3Native-darwin.cpp 92376 2021-11-11 15:09:59Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework.
4	*
5	* Log group 2: Exit logging.
6	* Log group 3: Log context on exit.
7	* Log group 5: Ring-3 memory management
8	*/
9
10	/*
11	* Copyright (C) 2020 Oracle Corporation
12	*
13	* This file is part of VirtualBox Open Source Edition (OSE), as
14	* available from http://www.virtualbox.org. This file is free software;
15	* you can redistribute it and/or modify it under the terms of the GNU
16	* General Public License (GPL) as published by the Free Software
17	* Foundation, in version 2 as it comes in the "COPYING" file of the
18	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20	*/
21
22
23	/*********************************************************************************************************************************
24	* Header Files *
25	*********************************************************************************************************************************/
26	#define LOG_GROUP LOG_GROUP_NEM
27	#define VMCPU_INCL_CPUM_GST_CTX
28	#include <VBox/vmm/nem.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/em.h>
31	#include <VBox/vmm/apic.h>
32	#include <VBox/vmm/pdm.h>
33	#include <VBox/vmm/hm.h>
34	#include <VBox/vmm/hm_vmx.h>
35	#include <VBox/vmm/dbgftrace.h>
36	#include "VMXInternal.h"
37	#include "NEMInternal.h"
38	#include <VBox/vmm/vmcc.h>
39	#include "dtrace/VBoxVMM.h"
40
41	#include <iprt/asm.h>
42	#include <iprt/ldr.h>
43	#include <iprt/mem.h>
44	#include <iprt/path.h>
45	#include <iprt/string.h>
46	#include <iprt/system.h>
47	#include <iprt/utf16.h>
48
49
50	/*********************************************************************************************************************************
51	* Defined Constants And Macros *
52	*********************************************************************************************************************************/
53	/* No nested hwvirt (for now). */
54	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
55	# undef VBOX_WITH_NESTED_HWVIRT_VMX
56	#endif
57
58
59	/** @name HV return codes.
60	* @{ */
61	/** Operation was successful. */
62	#define HV_SUCCESS 0
63	/** An error occurred during operation. */
64	#define HV_ERROR 0xfae94001
65	/** The operation could not be completed right now, try again. */
66	#define HV_BUSY 0xfae94002
67	/** One of the parameters passed wis invalid. */
68	#define HV_BAD_ARGUMENT 0xfae94003
69	/** Not enough resources left to fulfill the operation. */
70	#define HV_NO_RESOURCES 0xfae94005
71	/** The device could not be found. */
72	#define HV_NO_DEVICE 0xfae94006
73	/** The operation is not supportd on this platform with this configuration. */
74	#define HV_UNSUPPORTED 0xfae94007
75	/** @} */
76
77
78	/** @name HV memory protection flags.
79	* @{ */
80	/** Memory is readable. */
81	#define HV_MEMORY_READ RT_BIT_64(0)
82	/** Memory is writeable. */
83	#define HV_MEMORY_WRITE RT_BIT_64(1)
84	/** Memory is executable. */
85	#define HV_MEMORY_EXEC RT_BIT_64(2)
86	/** @} */
87
88
89	/** @name HV shadow VMCS protection flags.
90	* @{ */
91	/** Shadow VMCS field is not accessible. */
92	#define HV_SHADOW_VMCS_NONE 0
93	/** Shadow VMCS fild is readable. */
94	#define HV_SHADOW_VMCS_READ RT_BIT_64(0)
95	/** Shadow VMCS field is writeable. */
96	#define HV_SHADOW_VMCS_WRITE RT_BIT_64(1)
97	/** @} */
98
99
100	/** Default VM creation flags. */
101	#define HV_VM_DEFAULT 0
102	/** Default guest address space creation flags. */
103	#define HV_VM_SPACE_DEFAULT 0
104	/** Default vCPU creation flags. */
105	#define HV_VCPU_DEFAULT 0
106
107	#define HV_DEADLINE_FOREVER UINT64_MAX
108
109
110	/*********************************************************************************************************************************
111	* Structures and Typedefs *
112	*********************************************************************************************************************************/
113
114	/** HV return code type. */
115	typedef uint32_t hv_return_t;
116	/** HV capability bitmask. */
117	typedef uint64_t hv_capability_t;
118	/** Option bitmask type when creating a VM. */
119	typedef uint64_t hv_vm_options_t;
120	/** Option bitmask when creating a vCPU. */
121	typedef uint64_t hv_vcpu_options_t;
122	/** HV memory protection flags type. */
123	typedef uint64_t hv_memory_flags_t;
124	/** Shadow VMCS protection flags. */
125	typedef uint64_t hv_shadow_flags_t;
126	/** Guest physical address type. */
127	typedef uint64_t hv_gpaddr_t;
128
129
130	/**
131	* VMX Capability enumeration.
132	*/
133	typedef enum
134	{
135	HV_VMX_CAP_PINBASED = 0,
136	HV_VMX_CAP_PROCBASED,
137	HV_VMX_CAP_PROCBASED2,
138	HV_VMX_CAP_ENTRY,
139	HV_VMX_CAP_EXIT,
140	HV_VMX_CAP_BASIC, /* Since 11.0 */
141	HV_VMX_CAP_TRUE_PINBASED, /* Since 11.0 */
142	HV_VMX_CAP_TRUE_PROCBASED, /* Since 11.0 */
143	HV_VMX_CAP_TRUE_ENTRY, /* Since 11.0 */
144	HV_VMX_CAP_TRUE_EXIT, /* Since 11.0 */
145	HV_VMX_CAP_MISC, /* Since 11.0 */
146	HV_VMX_CAP_CR0_FIXED0, /* Since 11.0 */
147	HV_VMX_CAP_CR0_FIXED1, /* Since 11.0 */
148	HV_VMX_CAP_CR4_FIXED0, /* Since 11.0 */
149	HV_VMX_CAP_CR4_FIXED1, /* Since 11.0 */
150	HV_VMX_CAP_VMCS_ENUM, /* Since 11.0 */
151	HV_VMX_CAP_EPT_VPID_CAP, /* Since 11.0 */
152	HV_VMX_CAP_PREEMPTION_TIMER = 32
153	} hv_vmx_capability_t;
154
155
156	/**
157	* HV x86 register enumeration.
158	*/
159	typedef enum
160	{
161	HV_X86_RIP = 0,
162	HV_X86_RFLAGS,
163	HV_X86_RAX,
164	HV_X86_RCX,
165	HV_X86_RDX,
166	HV_X86_RBX,
167	HV_X86_RSI,
168	HV_X86_RDI,
169	HV_X86_RSP,
170	HV_X86_RBP,
171	HV_X86_R8,
172	HV_X86_R9,
173	HV_X86_R10,
174	HV_X86_R11,
175	HV_X86_R12,
176	HV_X86_R13,
177	HV_X86_R14,
178	HV_X86_R15,
179	HV_X86_CS,
180	HV_X86_SS,
181	HV_X86_DS,
182	HV_X86_ES,
183	HV_X86_FS,
184	HV_X86_GS,
185	HV_X86_IDT_BASE,
186	HV_X86_IDT_LIMIT,
187	HV_X86_GDT_BASE,
188	HV_X86_GDT_LIMIT,
189	HV_X86_LDTR,
190	HV_X86_LDT_BASE,
191	HV_X86_LDT_LIMIT,
192	HV_X86_LDT_AR,
193	HV_X86_TR,
194	HV_X86_TSS_BASE,
195	HV_X86_TSS_LIMIT,
196	HV_X86_TSS_AR,
197	HV_X86_CR0,
198	HV_X86_CR1,
199	HV_X86_CR2,
200	HV_X86_CR3,
201	HV_X86_CR4,
202	HV_X86_DR0,
203	HV_X86_DR1,
204	HV_X86_DR2,
205	HV_X86_DR3,
206	HV_X86_DR4,
207	HV_X86_DR5,
208	HV_X86_DR6,
209	HV_X86_DR7,
210	HV_X86_TPR,
211	HV_X86_XCR0,
212	HV_X86_REGISTERS_MAX
213	} hv_x86_reg_t;
214
215
216	typedef hv_return_t FN_HV_CAPABILITY(hv_capability_t capability, uint64_t *valu);
217	typedef hv_return_t FN_HV_VM_CREATE(hv_vm_options_t flags);
218	typedef hv_return_t FN_HV_VM_DESTROY(void);
219	typedef hv_return_t FN_HV_VM_SPACE_CREATE(hv_vm_space_t *asid);
220	typedef hv_return_t FN_HV_VM_SPACE_DESTROY(hv_vm_space_t asid);
221	typedef hv_return_t FN_HV_VM_MAP(const void *uva, hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
222	typedef hv_return_t FN_HV_VM_UNMAP(hv_gpaddr_t gpa, size_t size);
223	typedef hv_return_t FN_HV_VM_PROTECT(hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
224	typedef hv_return_t FN_HV_VM_MAP_SPACE(hv_vm_space_t asid, const void *uva, hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
225	typedef hv_return_t FN_HV_VM_UNMAP_SPACE(hv_vm_space_t asid, hv_gpaddr_t gpa, size_t size);
226	typedef hv_return_t FN_HV_VM_PROTECT_SPACE(hv_vm_space_t asid, hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
227	typedef hv_return_t FN_HV_VM_SYNC_TSC(uint64_t tsc);
228
229	typedef hv_return_t FN_HV_VCPU_CREATE(hv_vcpuid_t *vcpu, hv_vcpu_options_t flags);
230	typedef hv_return_t FN_HV_VCPU_DESTROY(hv_vcpuid_t vcpu);
231	typedef hv_return_t FN_HV_VCPU_SET_SPACE(hv_vcpuid_t vcpu, hv_vm_space_t asid);
232	typedef hv_return_t FN_HV_VCPU_READ_REGISTER(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t *value);
233	typedef hv_return_t FN_HV_VCPU_WRITE_REGISTER(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t value);
234	typedef hv_return_t FN_HV_VCPU_READ_FPSTATE(hv_vcpuid_t vcpu, void *buffer, size_t size);
235	typedef hv_return_t FN_HV_VCPU_WRITE_FPSTATE(hv_vcpuid_t vcpu, const void *buffer, size_t size);
236	typedef hv_return_t FN_HV_VCPU_ENABLE_NATIVE_MSR(hv_vcpuid_t vcpu, uint32_t msr, bool enable);
237	typedef hv_return_t FN_HV_VCPU_READ_MSR(hv_vcpuid_t vcpu, uint32_t msr, uint64_t *value);
238	typedef hv_return_t FN_HV_VCPU_WRITE_MSR(hv_vcpuid_t vcpu, uint32_t msr, uint64_t value);
239	typedef hv_return_t FN_HV_VCPU_FLUSH(hv_vcpuid_t vcpu);
240	typedef hv_return_t FN_HV_VCPU_INVALIDATE_TLB(hv_vcpuid_t vcpu);
241	typedef hv_return_t FN_HV_VCPU_RUN(hv_vcpuid_t vcpu);
242	typedef hv_return_t FN_HV_VCPU_RUN_UNTIL(hv_vcpuid_t vcpu, uint64_t deadline);
243	typedef hv_return_t FN_HV_VCPU_INTERRUPT(hv_vcpuid_t *vcpus, unsigned int vcpu_count);
244	typedef hv_return_t FN_HV_VCPU_GET_EXEC_TIME(hv_vcpuid_t vcpus, uint64_t time);
245
246	typedef hv_return_t FN_HV_VMX_VCPU_READ_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t *value);
247	typedef hv_return_t FN_HV_VMX_VCPU_WRITE_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t value);
248
249	typedef hv_return_t FN_HV_VMX_VCPU_READ_SHADOW_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t *value);
250	typedef hv_return_t FN_HV_VMX_VCPU_WRITE_SHADOW_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t value);
251	typedef hv_return_t FN_HV_VMX_VCPU_SET_SHADOW_ACCESS(hv_vcpuid_t vcpu, uint32_t field, hv_shadow_flags_t flags);
252
253	typedef hv_return_t FN_HV_VMX_READ_CAPABILITY(hv_vmx_capability_t field, uint64_t *value);
254	typedef hv_return_t FN_HV_VMX_VCPU_SET_APIC_ADDRESS(hv_vcpuid_t vcpu, hv_gpaddr_t gpa);
255
256
257	/*********************************************************************************************************************************
258	* Global Variables *
259	*********************************************************************************************************************************/
260	/** NEM_DARWIN_PAGE_STATE_XXX names. */
261	NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
262	/** MSRs. */
263	static SUPHWVIRTMSRS g_HmMsrs;
264	/** VMX: Set if swapping EFER is supported. */
265	static bool g_fHmVmxSupportsVmcsEfer = false;
266	/** @name APIs imported from Hypervisor.framework.
267	* @{ */
268	static FN_HV_CAPABILITY g_pfnHvCapability = NULL; / Since 10.15 */
269	static FN_HV_VM_CREATE g_pfnHvVmCreate = NULL; / Since 10.10 */
270	static FN_HV_VM_DESTROY g_pfnHvVmDestroy = NULL; / Since 10.10 */
271	static FN_HV_VM_SPACE_CREATE g_pfnHvVmSpaceCreate = NULL; / Since 10.15 */
272	static FN_HV_VM_SPACE_DESTROY g_pfnHvVmSpaceDestroy = NULL; / Since 10.15 */
273	static FN_HV_VM_MAP g_pfnHvVmMap = NULL; / Since 10.10 */
274	static FN_HV_VM_UNMAP g_pfnHvVmUnmap = NULL; / Since 10.10 */
275	static FN_HV_VM_PROTECT g_pfnHvVmProtect = NULL; / Since 10.10 */
276	static FN_HV_VM_MAP_SPACE g_pfnHvVmMapSpace = NULL; / Since 10.15 */
277	static FN_HV_VM_UNMAP_SPACE g_pfnHvVmUnmapSpace = NULL; / Since 10.15 */
278	static FN_HV_VM_PROTECT_SPACE g_pfnHvVmProtectSpace = NULL; / Since 10.15 */
279	static FN_HV_VM_SYNC_TSC g_pfnHvVmSyncTsc = NULL; / Since 10.10 */
280
281	static FN_HV_VCPU_CREATE g_pfnHvVCpuCreate = NULL; / Since 10.10 */
282	static FN_HV_VCPU_DESTROY g_pfnHvVCpuDestroy = NULL; / Since 10.10 */
283	static FN_HV_VCPU_SET_SPACE g_pfnHvVCpuSetSpace = NULL; / Since 10.15 */
284	static FN_HV_VCPU_READ_REGISTER g_pfnHvVCpuReadRegister = NULL; / Since 10.10 */
285	static FN_HV_VCPU_WRITE_REGISTER g_pfnHvVCpuWriteRegister = NULL; / Since 10.10 */
286	static FN_HV_VCPU_READ_FPSTATE g_pfnHvVCpuReadFpState = NULL; / Since 10.10 */
287	static FN_HV_VCPU_WRITE_FPSTATE g_pfnHvVCpuWriteFpState = NULL; / Since 10.10 */
288	static FN_HV_VCPU_ENABLE_NATIVE_MSR g_pfnHvVCpuEnableNativeMsr = NULL; / Since 10.10 */
289	static FN_HV_VCPU_READ_MSR g_pfnHvVCpuReadMsr = NULL; / Since 10.10 */
290	static FN_HV_VCPU_WRITE_MSR g_pfnHvVCpuWriteMsr = NULL; / Since 10.10 */
291	static FN_HV_VCPU_FLUSH g_pfnHvVCpuFlush = NULL; / Since 10.10 */
292	static FN_HV_VCPU_INVALIDATE_TLB g_pfnHvVCpuInvalidateTlb = NULL; / Since 10.10 */
293	static FN_HV_VCPU_RUN g_pfnHvVCpuRun = NULL; / Since 10.10 */
294	static FN_HV_VCPU_RUN_UNTIL g_pfnHvVCpuRunUntil = NULL; / Since 10.15 */
295	static FN_HV_VCPU_INTERRUPT g_pfnHvVCpuInterrupt = NULL; / Since 10.10 */
296	static FN_HV_VCPU_GET_EXEC_TIME g_pfnHvVCpuGetExecTime = NULL; / Since 10.10 */
297
298	static FN_HV_VMX_READ_CAPABILITY g_pfnHvVmxReadCapability = NULL; / Since 10.10 */
299	static FN_HV_VMX_VCPU_READ_VMCS g_pfnHvVmxVCpuReadVmcs = NULL; / Since 10.10 */
300	static FN_HV_VMX_VCPU_WRITE_VMCS g_pfnHvVmxVCpuWriteVmcs = NULL; / Since 10.10 */
301	static FN_HV_VMX_VCPU_READ_SHADOW_VMCS g_pfnHvVmxVCpuReadShadowVmcs = NULL; / Since 10.15 */
302	static FN_HV_VMX_VCPU_WRITE_SHADOW_VMCS g_pfnHvVmxVCpuWriteShadowVmcs = NULL; / Since 10.15 */
303	static FN_HV_VMX_VCPU_SET_SHADOW_ACCESS g_pfnHvVmxVCpuSetShadowAccess = NULL; / Since 10.15 */
304	static FN_HV_VMX_VCPU_SET_APIC_ADDRESS g_pfnHvVmxVCpuSetApicAddress = NULL; / Since 10.10 */
305	/** @} */
306
307
308	/**
309	* Import instructions.
310	*/
311	static const struct
312	{
313	bool fOptional; /*< Set if import is optional. /
314	void ppfn; /< The function pointer variable. */
315	const char pszName; /< The function name. /
316	} g_aImports[] =
317	{
318	#define NEM_DARWIN_IMPORT(a_fOptional, a_Pfn, a_Name) { (a_fOptional), (void **)&(a_Pfn), #a_Name }
319	NEM_DARWIN_IMPORT(true, g_pfnHvCapability, hv_capability),
320	NEM_DARWIN_IMPORT(false, g_pfnHvVmCreate, hv_vm_create),
321	NEM_DARWIN_IMPORT(false, g_pfnHvVmDestroy, hv_vm_destroy),
322	NEM_DARWIN_IMPORT(true, g_pfnHvVmSpaceCreate, hv_vm_space_create),
323	NEM_DARWIN_IMPORT(true, g_pfnHvVmSpaceDestroy, hv_vm_space_destroy),
324	NEM_DARWIN_IMPORT(false, g_pfnHvVmMap, hv_vm_map),
325	NEM_DARWIN_IMPORT(false, g_pfnHvVmUnmap, hv_vm_unmap),
326	NEM_DARWIN_IMPORT(false, g_pfnHvVmProtect, hv_vm_protect),
327	NEM_DARWIN_IMPORT(true, g_pfnHvVmMapSpace, hv_vm_map_space),
328	NEM_DARWIN_IMPORT(true, g_pfnHvVmUnmapSpace, hv_vm_unmap_space),
329	NEM_DARWIN_IMPORT(true, g_pfnHvVmProtectSpace, hv_vm_protect_space),
330	NEM_DARWIN_IMPORT(false, g_pfnHvVmSyncTsc, hv_vm_sync_tsc),
331
332	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuCreate, hv_vcpu_create),
333	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuDestroy, hv_vcpu_destroy),
334	NEM_DARWIN_IMPORT(true, g_pfnHvVCpuSetSpace, hv_vcpu_set_space),
335	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuReadRegister, hv_vcpu_read_register),
336	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuWriteRegister, hv_vcpu_write_register),
337	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuReadFpState, hv_vcpu_read_fpstate),
338	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuWriteFpState, hv_vcpu_write_fpstate),
339	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuEnableNativeMsr, hv_vcpu_enable_native_msr),
340	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuReadMsr, hv_vcpu_read_msr),
341	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuWriteMsr, hv_vcpu_write_msr),
342	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuFlush, hv_vcpu_flush),
343	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuInvalidateTlb, hv_vcpu_invalidate_tlb),
344	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuRun, hv_vcpu_run),
345	NEM_DARWIN_IMPORT(true, g_pfnHvVCpuRunUntil, hv_vcpu_run_until),
346	NEM_DARWIN_IMPORT(false, g_pfnHvVCpuInterrupt, hv_vcpu_interrupt),
347	NEM_DARWIN_IMPORT(true, g_pfnHvVCpuGetExecTime, hv_vcpu_get_exec_time),
348	NEM_DARWIN_IMPORT(false, g_pfnHvVmxReadCapability, hv_vmx_read_capability),
349	NEM_DARWIN_IMPORT(false, g_pfnHvVmxVCpuReadVmcs, hv_vmx_vcpu_read_vmcs),
350	NEM_DARWIN_IMPORT(false, g_pfnHvVmxVCpuWriteVmcs, hv_vmx_vcpu_write_vmcs),
351	NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuReadShadowVmcs, hv_vmx_vcpu_read_shadow_vmcs),
352	NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuWriteShadowVmcs, hv_vmx_vcpu_write_shadow_vmcs),
353	NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuSetShadowAccess, hv_vmx_vcpu_set_shadow_access),
354	NEM_DARWIN_IMPORT(false, g_pfnHvVmxVCpuSetApicAddress, hv_vmx_vcpu_set_apic_address),
355	#undef NEM_DARWIN_IMPORT
356	};
357
358
359	/*
360	* Let the preprocessor alias the APIs to import variables for better autocompletion.
361	*/
362	#ifndef IN_SLICKEDIT
363	# define hv_capability g_pfnHvCapability
364	# define hv_vm_create g_pfnHvVmCreate
365	# define hv_vm_destroy g_pfnHvVmDestroy
366	# define hv_vm_space_create g_pfnHvVmSpaceCreate
367	# define hv_vm_space_destroy g_pfnHvVmSpaceDestroy
368	# define hv_vm_map g_pfnHvVmMap
369	# define hv_vm_unmap g_pfnHvVmUnmap
370	# define hv_vm_protect g_pfnHvVmProtect
371	# define hv_vm_map_space g_pfnHvVmMapSpace
372	# define hv_vm_unmap_space g_pfnHvVmUnmapSpace
373	# define hv_vm_protect_space g_pfnHvVmProtectSpace
374	# define hv_vm_sync_tsc g_pfnHvVmSyncTsc
375
376	# define hv_vcpu_create g_pfnHvVCpuCreate
377	# define hv_vcpu_destroy g_pfnHvVCpuDestroy
378	# define hv_vcpu_set_space g_pfnHvVCpuSetSpace
379	# define hv_vcpu_read_register g_pfnHvVCpuReadRegister
380	# define hv_vcpu_write_register g_pfnHvVCpuWriteRegister
381	# define hv_vcpu_read_fpstate g_pfnHvVCpuReadFpState
382	# define hv_vcpu_write_fpstate g_pfnHvVCpuWriteFpState
383	# define hv_vcpu_enable_native_msr g_pfnHvVCpuEnableNativeMsr
384	# define hv_vcpu_read_msr g_pfnHvVCpuReadMsr
385	# define hv_vcpu_write_msr g_pfnHvVCpuWriteMsr
386	# define hv_vcpu_flush g_pfnHvVCpuFlush
387	# define hv_vcpu_invalidate_tlb g_pfnHvVCpuInvalidateTlb
388	# define hv_vcpu_run g_pfnHvVCpuRun
389	# define hv_vcpu_run_until g_pfnHvVCpuRunUntil
390	# define hv_vcpu_interrupt g_pfnHvVCpuInterrupt
391	# define hv_vcpu_get_exec_time g_pfnHvVCpuGetExecTime
392
393	# define hv_vmx_read_capability g_pfnHvVmxReadCapability
394	# define hv_vmx_vcpu_read_vmcs g_pfnHvVmxVCpuReadVmcs
395	# define hv_vmx_vcpu_write_vmcs g_pfnHvVmxVCpuWriteVmcs
396	# define hv_vmx_vcpu_read_shadow_vmcs g_pfnHvVmxVCpuReadShadowVmcs
397	# define hv_vmx_vcpu_write_shadow_vmcs g_pfnHvVmxVCpuWriteShadowVmcs
398	# define hv_vmx_vcpu_set_shadow_access g_pfnHvVmxVCpuSetShadowAccess
399	# define hv_vmx_vcpu_set_apic_address g_pfnHvVmxVCpuSetApicAddress
400	#endif
401
402
403	/*********************************************************************************************************************************
404	* Internal Functions *
405	*********************************************************************************************************************************/
406
407	/**
408	* Converts a HV return code to a VBox status code.
409	*
410	* @returns VBox status code.
411	* @param hrc The HV return code to convert.
412	*/
413	DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
414	{
415	if (hrc == HV_SUCCESS)
416	return VINF_SUCCESS;
417
418	switch (hrc)
419	{
420	case HV_ERROR: return VERR_INVALID_STATE;
421	case HV_BUSY: return VERR_RESOURCE_BUSY;
422	case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
423	case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
424	case HV_NO_DEVICE: return VERR_NOT_FOUND;
425	case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
426	}
427
428	return VERR_IPE_UNEXPECTED_STATUS;
429	}
430
431
432	/**
433	* Unmaps the given guest physical address range (page aligned).
434	*
435	* @returns VBox status code.
436	* @param pVM The cross context VM structure.
437	* @param GCPhys The guest physical address to start unmapping at.
438	* @param cb The size of the range to unmap in bytes.
439	*/
440	DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb)
441	{
442	LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
443	hv_return_t hrc;
444	if (pVM->nem.s.fCreatedAsid)
445	hrc = hv_vm_unmap_space(pVM->nem.s.uVmAsid, GCPhys, cb);
446	else
447	hrc = hv_vm_unmap(GCPhys, cb);
448	return nemR3DarwinHvSts2Rc(hrc);
449	}
450
451
452	/**
453	* Maps a given guest physical address range backed by the given memory with the given
454	* protection flags.
455	*
456	* @returns VBox status code.
457	* @param pVM The cross context VM structure.
458	* @param GCPhys The guest physical address to start mapping.
459	* @param pvRam The R3 pointer of the memory to back the range with.
460	* @param cb The size of the range, page aligned.
461	* @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
462	*/
463	DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, void *pvRam, size_t cb, uint32_t fPageProt)
464	{
465	LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
466
467	hv_memory_flags_t fHvMemProt = 0;
468	if (fPageProt & NEM_PAGE_PROT_READ)
469	fHvMemProt \|= HV_MEMORY_READ;
470	if (fPageProt & NEM_PAGE_PROT_WRITE)
471	fHvMemProt \|= HV_MEMORY_WRITE;
472	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
473	fHvMemProt \|= HV_MEMORY_EXEC;
474
475	hv_return_t hrc;
476	if (pVM->nem.s.fCreatedAsid)
477	hrc = hv_vm_map_space(pVM->nem.s.uVmAsid, pvRam, GCPhys, cb, fHvMemProt);
478	else
479	hrc = hv_vm_map(pvRam, GCPhys, cb, fHvMemProt);
480	return nemR3DarwinHvSts2Rc(hrc);
481	}
482
483
484	#if 0 /* unused */
485	DECLINLINE(int) nemR3DarwinProtectPage(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt)
486	{
487	hv_memory_flags_t fHvMemProt = 0;
488	if (fPageProt & NEM_PAGE_PROT_READ)
489	fHvMemProt \|= HV_MEMORY_READ;
490	if (fPageProt & NEM_PAGE_PROT_WRITE)
491	fHvMemProt \|= HV_MEMORY_WRITE;
492	if (fPageProt & NEM_PAGE_PROT_EXECUTE)
493	fHvMemProt \|= HV_MEMORY_EXEC;
494
495	if (pVM->nem.s.fCreatedAsid)
496	hrc = hv_vm_protect_space(pVM->nem.s.uVmAsid, GCPhys, cb, fHvMemProt);
497	else
498	hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
499
500	return nemR3DarwinHvSts2Rc(hrc);
501	}
502	#endif
503
504
505	DECLINLINE(int) nemR3NativeGCPhys2R3PtrReadOnly(PVM pVM, RTGCPHYS GCPhys, const void **ppv)
506	{
507	PGMPAGEMAPLOCK Lock;
508	int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, ppv, &Lock);
509	if (RT_SUCCESS(rc))
510	PGMPhysReleasePageMappingLock(pVM, &Lock);
511	return rc;
512	}
513
514
515	DECLINLINE(int) nemR3NativeGCPhys2R3PtrWriteable(PVM pVM, RTGCPHYS GCPhys, void **ppv)
516	{
517	PGMPAGEMAPLOCK Lock;
518	int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys, ppv, &Lock);
519	if (RT_SUCCESS(rc))
520	PGMPhysReleasePageMappingLock(pVM, &Lock);
521	return rc;
522	}
523
524
525	/**
526	* Worker that maps pages into Hyper-V.
527	*
528	* This is used by the PGM physical page notifications as well as the memory
529	* access VMEXIT handlers.
530	*
531	* @returns VBox status code.
532	* @param pVM The cross context VM structure.
533	* @param pVCpu The cross context virtual CPU structure of the
534	* calling EMT.
535	* @param GCPhysSrc The source page address.
536	* @param GCPhysDst The hyper-V destination page. This may differ from
537	* GCPhysSrc when A20 is disabled.
538	* @param fPageProt NEM_PAGE_PROT_XXX.
539	* @param pu2State Our page state (input/output).
540	* @param fBackingChanged Set if the page backing is being changed.
541	* @thread EMT(pVCpu)
542	*/
543	NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
544	uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
545	{
546	/*
547	* Looks like we need to unmap a page before we can change the backing
548	* or even modify the protection. This is going to be REALLY efficient.
549	* PGM lends us two bits to keep track of the state here.
550	*/
551	RT_NOREF(pVCpu);
552	uint8_t const u2OldState = *pu2State;
553	uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_DARWIN_PAGE_STATE_WRITABLE
554	: fPageProt & NEM_PAGE_PROT_READ ? NEM_DARWIN_PAGE_STATE_READABLE : NEM_DARWIN_PAGE_STATE_UNMAPPED;
555	if ( fBackingChanged
556	\|\| u2NewState != u2OldState)
557	{
558	if (u2OldState > NEM_DARWIN_PAGE_STATE_UNMAPPED)
559	{
560	int rc = nemR3DarwinUnmap(pVM, GCPhysDst, X86_PAGE_SIZE);
561	if (RT_SUCCESS(rc))
562	{
563	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
564	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
565	if (u2NewState == NEM_DARWIN_PAGE_STATE_UNMAPPED)
566	{
567	Log5(("NEM GPA unmapped/set: %RGp (was %s)\n", GCPhysDst, g_apszPageStates[u2OldState]));
568	return VINF_SUCCESS;
569	}
570	}
571	else
572	{
573	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
574	LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
575	return VERR_NEM_INIT_FAILED;
576	}
577	}
578	}
579
580	/*
581	* Writeable mapping?
582	*/
583	if (fPageProt & NEM_PAGE_PROT_WRITE)
584	{
585	void *pvPage;
586	int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
587	if (RT_SUCCESS(rc))
588	{
589	rc = nemR3DarwinMap(pVM, GCPhysDst, pvPage, X86_PAGE_SIZE, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE);
590	if (RT_SUCCESS(rc))
591	{
592	*pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
593	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
594	Log5(("NEM GPA mapped/set: %RGp %s (was %s)\n", GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState]));
595	return VINF_SUCCESS;
596	}
597	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
598	LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst));
599	return VERR_NEM_INIT_FAILED;
600	}
601	LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
602	return rc;
603	}
604
605	if (fPageProt & NEM_PAGE_PROT_READ)
606	{
607	const void *pvPage;
608	int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
609	if (RT_SUCCESS(rc))
610	{
611	rc = nemR3DarwinMap(pVM, GCPhysDst, (void *)pvPage, X86_PAGE_SIZE, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE);
612	if (RT_SUCCESS(rc))
613	{
614	*pu2State = NEM_DARWIN_PAGE_STATE_READABLE;
615	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
616	Log5(("NEM GPA mapped/set: %RGp %s (was %s)\n", GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState]));
617	return VINF_SUCCESS;
618	}
619	STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
620	LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
621	return VERR_NEM_INIT_FAILED;
622	}
623	LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
624	return rc;
625	}
626
627	/* We already unmapped it above. */
628	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
629	return VINF_SUCCESS;
630	}
631
632
633	#ifdef LOG_ENABLED
634	/**
635	* Logs the current CPU state.
636	*/
637	static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
638	{
639	if (LogIs3Enabled())
640	{
641	#if 0
642	char szRegs[4096];
643	DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
644	"rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
645	"rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
646	"r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
647	"r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
648	"rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
649	"cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
650	"ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
651	"es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
652	"fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
653	"gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
654	"ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
655	"dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
656	"dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
657	"gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
658	"ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
659	"tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
660	" sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
661	" efer=%016VR{efer}\n"
662	" pat=%016VR{pat}\n"
663	" sf_mask=%016VR{sf_mask}\n"
664	"krnl_gs_base=%016VR{krnl_gs_base}\n"
665	" lstar=%016VR{lstar}\n"
666	" star=%016VR{star} cstar=%016VR{cstar}\n"
667	"fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
668	);
669
670	char szInstr[256];
671	DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
672	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
673	szInstr, sizeof(szInstr), NULL);
674	Log3(("%s%s\n", szRegs, szInstr));
675	#else
676	RT_NOREF(pVM, pVCpu);
677	#endif
678	}
679	}
680	#endif /* LOG_ENABLED */
681
682
683	DECLINLINE(int) nemR3DarwinReadVmcs16(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint16_t *pData)
684	{
685	uint64_t u64Data;
686	hv_return_t hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, &u64Data);
687	if (RT_LIKELY(hrc == HV_SUCCESS))
688	{
689	*pData = (uint16_t)u64Data;
690	return VINF_SUCCESS;
691	}
692
693	return nemR3DarwinHvSts2Rc(hrc);
694	}
695
696
697	DECLINLINE(int) nemR3DarwinReadVmcs32(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint32_t *pData)
698	{
699	uint64_t u64Data;
700	hv_return_t hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, &u64Data);
701	if (RT_LIKELY(hrc == HV_SUCCESS))
702	{
703	*pData = (uint32_t)u64Data;
704	return VINF_SUCCESS;
705	}
706
707	return nemR3DarwinHvSts2Rc(hrc);
708	}
709
710
711	DECLINLINE(int) nemR3DarwinReadVmcs64(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint64_t *pData)
712	{
713	hv_return_t hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, pData);
714	if (RT_LIKELY(hrc == HV_SUCCESS))
715	return VINF_SUCCESS;
716
717	return nemR3DarwinHvSts2Rc(hrc);
718	}
719
720
721	DECLINLINE(int) nemR3DarwinWriteVmcs16(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint16_t u16Val)
722	{
723	hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, u16Val);
724	if (RT_LIKELY(hrc == HV_SUCCESS))
725	return VINF_SUCCESS;
726
727	return nemR3DarwinHvSts2Rc(hrc);
728	}
729
730
731	DECLINLINE(int) nemR3DarwinWriteVmcs32(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint32_t u32Val)
732	{
733	hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, u32Val);
734	if (RT_LIKELY(hrc == HV_SUCCESS))
735	return VINF_SUCCESS;
736
737	return nemR3DarwinHvSts2Rc(hrc);
738	}
739
740
741	DECLINLINE(int) nemR3DarwinWriteVmcs64(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint64_t u64Val)
742	{
743	hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, u64Val);
744	if (RT_LIKELY(hrc == HV_SUCCESS))
745	return VINF_SUCCESS;
746
747	return nemR3DarwinHvSts2Rc(hrc);
748	}
749
750	DECLINLINE(int) nemR3DarwinMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Val)
751	{
752	hv_return_t hrc = hv_vcpu_read_msr(pVCpu->nem.s.hVCpuId, idMsr, pu64Val);
753	if (RT_LIKELY(hrc == HV_SUCCESS))
754	return VINF_SUCCESS;
755
756	return nemR3DarwinHvSts2Rc(hrc);
757	}
758
759	#if 0 /unused/
760	DECLINLINE(int) nemR3DarwinMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Val)
761	{
762	hv_return_t hrc = hv_vcpu_write_msr(pVCpu->nem.s.hVCpuId, idMsr, u64Val);
763	if (RT_LIKELY(hrc == HV_SUCCESS))
764	return VINF_SUCCESS;
765
766	return nemR3DarwinHvSts2Rc(hrc);
767	}
768	#endif
769
770	static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
771	{
772	#define READ_GREG(a_GReg, a_Value) \
773	do \
774	{ \
775	hrc = hv_vcpu_read_register(pVCpu->nem.s.hVCpuId, (a_GReg), &(a_Value)); \
776	if (RT_LIKELY(hrc == HV_SUCCESS)) \
777	{ /* likely */ } \
778	else \
779	return VERR_INTERNAL_ERROR; \
780	} while(0)
781	#define READ_VMCS_FIELD(a_Field, a_Value) \
782	do \
783	{ \
784	hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), &(a_Value)); \
785	if (RT_LIKELY(hrc == HV_SUCCESS)) \
786	{ /* likely */ } \
787	else \
788	return VERR_INTERNAL_ERROR; \
789	} while(0)
790	#define READ_VMCS16_FIELD(a_Field, a_Value) \
791	do \
792	{ \
793	uint64_t u64Data; \
794	hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), &u64Data); \
795	if (RT_LIKELY(hrc == HV_SUCCESS)) \
796	{ (a_Value) = (uint16_t)u64Data; } \
797	else \
798	return VERR_INTERNAL_ERROR; \
799	} while(0)
800	#define READ_VMCS32_FIELD(a_Field, a_Value) \
801	do \
802	{ \
803	uint64_t u64Data; \
804	hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), &u64Data); \
805	if (RT_LIKELY(hrc == HV_SUCCESS)) \
806	{ (a_Value) = (uint32_t)u64Data; } \
807	else \
808	return VERR_INTERNAL_ERROR; \
809	} while(0)
810	#define READ_MSR(a_Msr, a_Value) \
811	do \
812	{ \
813	hrc = hv_vcpu_read_msr(pVCpu->nem.s.hVCpuId, (a_Msr), &(a_Value)); \
814	if (RT_LIKELY(hrc == HV_SUCCESS)) \
815	{ /* likely */ } \
816	else \
817	AssertFailedReturn(VERR_INTERNAL_ERROR); \
818	} while(0)
819
820	RT_NOREF(pVM);
821	fWhat &= pVCpu->cpum.GstCtx.fExtrn;
822
823	/* GPRs */
824	hv_return_t hrc;
825	if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
826	{
827	if (fWhat & CPUMCTX_EXTRN_RAX)
828	READ_GREG(HV_X86_RAX, pVCpu->cpum.GstCtx.rax);
829	if (fWhat & CPUMCTX_EXTRN_RCX)
830	READ_GREG(HV_X86_RCX, pVCpu->cpum.GstCtx.rcx);
831	if (fWhat & CPUMCTX_EXTRN_RDX)
832	READ_GREG(HV_X86_RDX, pVCpu->cpum.GstCtx.rdx);
833	if (fWhat & CPUMCTX_EXTRN_RBX)
834	READ_GREG(HV_X86_RBX, pVCpu->cpum.GstCtx.rbx);
835	if (fWhat & CPUMCTX_EXTRN_RSP)
836	READ_GREG(HV_X86_RSP, pVCpu->cpum.GstCtx.rsp);
837	if (fWhat & CPUMCTX_EXTRN_RBP)
838	READ_GREG(HV_X86_RBP, pVCpu->cpum.GstCtx.rbp);
839	if (fWhat & CPUMCTX_EXTRN_RSI)
840	READ_GREG(HV_X86_RSI, pVCpu->cpum.GstCtx.rsi);
841	if (fWhat & CPUMCTX_EXTRN_RDI)
842	READ_GREG(HV_X86_RDI, pVCpu->cpum.GstCtx.rdi);
843	if (fWhat & CPUMCTX_EXTRN_R8_R15)
844	{
845	READ_GREG(HV_X86_R8, pVCpu->cpum.GstCtx.r8);
846	READ_GREG(HV_X86_R9, pVCpu->cpum.GstCtx.r9);
847	READ_GREG(HV_X86_R10, pVCpu->cpum.GstCtx.r10);
848	READ_GREG(HV_X86_R11, pVCpu->cpum.GstCtx.r11);
849	READ_GREG(HV_X86_R12, pVCpu->cpum.GstCtx.r12);
850	READ_GREG(HV_X86_R13, pVCpu->cpum.GstCtx.r13);
851	READ_GREG(HV_X86_R14, pVCpu->cpum.GstCtx.r14);
852	READ_GREG(HV_X86_R15, pVCpu->cpum.GstCtx.r15);
853	}
854	}
855
856	/* RIP & Flags */
857	if (fWhat & CPUMCTX_EXTRN_RIP)
858	READ_GREG(HV_X86_RIP, pVCpu->cpum.GstCtx.rip);
859	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
860	READ_GREG(HV_X86_RFLAGS, pVCpu->cpum.GstCtx.rflags.u);
861
862	/* Segments */
863	#define READ_SEG(a_SReg, a_enmName) \
864	do { \
865	READ_VMCS16_FIELD(VMX_VMCS16_GUEST_ ## a_enmName ## _SEL, (a_SReg).Sel); \
866	READ_VMCS32_FIELD(VMX_VMCS32_GUEST_ ## a_enmName ## _LIMIT, (a_SReg).u32Limit); \
867	READ_VMCS32_FIELD(VMX_VMCS32_GUEST_ ## a_enmName ## _ACCESS_RIGHTS, (a_SReg).Attr.u); \
868	READ_VMCS_FIELD(VMX_VMCS_GUEST_ ## a_enmName ## _BASE, (a_SReg).u64Base); \
869	(a_SReg).ValidSel = (a_SReg).Sel; \
870	} while (0)
871	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
872	{
873	if (fWhat & CPUMCTX_EXTRN_ES)
874	READ_SEG(pVCpu->cpum.GstCtx.es, ES);
875	if (fWhat & CPUMCTX_EXTRN_CS)
876	READ_SEG(pVCpu->cpum.GstCtx.cs, CS);
877	if (fWhat & CPUMCTX_EXTRN_SS)
878	READ_SEG(pVCpu->cpum.GstCtx.ss, SS);
879	if (fWhat & CPUMCTX_EXTRN_DS)
880	READ_SEG(pVCpu->cpum.GstCtx.ds, DS);
881	if (fWhat & CPUMCTX_EXTRN_FS)
882	READ_SEG(pVCpu->cpum.GstCtx.fs, FS);
883	if (fWhat & CPUMCTX_EXTRN_GS)
884	READ_SEG(pVCpu->cpum.GstCtx.gs, GS);
885	}
886
887	/* Descriptor tables and the task segment. */
888	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
889	{
890	if (fWhat & CPUMCTX_EXTRN_LDTR)
891	READ_SEG(pVCpu->cpum.GstCtx.ldtr, LDTR);
892
893	if (fWhat & CPUMCTX_EXTRN_TR)
894	{
895	/* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
896	avoid to trigger sanity assertions around the code, always fix this. */
897	READ_SEG(pVCpu->cpum.GstCtx.tr, TR);
898	switch (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type)
899	{
900	case X86_SEL_TYPE_SYS_386_TSS_BUSY:
901	case X86_SEL_TYPE_SYS_286_TSS_BUSY:
902	break;
903	case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
904	pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
905	break;
906	case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
907	pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
908	break;
909	}
910	}
911	if (fWhat & CPUMCTX_EXTRN_IDTR)
912	{
913	READ_VMCS32_FIELD(VMX_VMCS32_GUEST_IDTR_LIMIT, pVCpu->cpum.GstCtx.idtr.cbIdt);
914	READ_VMCS_FIELD(VMX_VMCS_GUEST_IDTR_BASE, pVCpu->cpum.GstCtx.idtr.pIdt);
915	}
916	if (fWhat & CPUMCTX_EXTRN_GDTR)
917	{
918	READ_VMCS32_FIELD(VMX_VMCS32_GUEST_GDTR_LIMIT, pVCpu->cpum.GstCtx.gdtr.cbGdt);
919	READ_VMCS_FIELD(VMX_VMCS_GUEST_GDTR_BASE, pVCpu->cpum.GstCtx.gdtr.pGdt);
920	}
921	}
922
923	/* Control registers. */
924	bool fMaybeChangedMode = false;
925	bool fUpdateCr3 = false;
926	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
927	{
928	uint64_t u64CrTmp = 0;
929
930	if (fWhat & CPUMCTX_EXTRN_CR0)
931	{
932	READ_GREG(HV_X86_CR0, u64CrTmp);
933	if (pVCpu->cpum.GstCtx.cr0 != u64CrTmp)
934	{
935	CPUMSetGuestCR0(pVCpu, u64CrTmp);
936	fMaybeChangedMode = true;
937	}
938	}
939	if (fWhat & CPUMCTX_EXTRN_CR2)
940	READ_GREG(HV_X86_CR2, pVCpu->cpum.GstCtx.cr2);
941	if (fWhat & CPUMCTX_EXTRN_CR3)
942	{
943	READ_GREG(HV_X86_CR3, u64CrTmp);
944	if (pVCpu->cpum.GstCtx.cr3 != u64CrTmp)
945	{
946	CPUMSetGuestCR3(pVCpu, u64CrTmp);
947	fUpdateCr3 = true;
948	}
949	}
950	if (fWhat & CPUMCTX_EXTRN_CR4)
951	{
952	READ_GREG(HV_X86_CR4, u64CrTmp);
953	u64CrTmp &= ~VMX_V_CR4_FIXED0;
954
955	if (pVCpu->cpum.GstCtx.cr4 != u64CrTmp)
956	{
957	CPUMSetGuestCR4(pVCpu, u64CrTmp);
958	fMaybeChangedMode = true;
959	}
960	}
961	}
962	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
963	{
964	uint64_t u64Cr8 = 0;
965
966	READ_GREG(HV_X86_TPR, u64Cr8);
967	APICSetTpr(pVCpu, u64Cr8);
968	}
969
970	/* Debug registers. */
971	if (fWhat & CPUMCTX_EXTRN_DR7)
972	{
973	uint64_t u64Dr7;
974	READ_GREG(HV_X86_DR7, u64Dr7);
975	if (pVCpu->cpum.GstCtx.dr[7] != u64Dr7)
976	CPUMSetGuestDR7(pVCpu, u64Dr7);
977	pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_DR7; /* Hack alert! Avoids asserting when processing CPUMCTX_EXTRN_DR0_DR3. */
978	}
979	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
980	{
981	uint64_t u64DrTmp;
982
983	READ_GREG(HV_X86_DR0, u64DrTmp);
984	if (pVCpu->cpum.GstCtx.dr[0] != u64DrTmp)
985	CPUMSetGuestDR0(pVCpu, u64DrTmp);
986	READ_GREG(HV_X86_DR1, u64DrTmp);
987	if (pVCpu->cpum.GstCtx.dr[1] != u64DrTmp)
988	CPUMSetGuestDR1(pVCpu, u64DrTmp);
989	READ_GREG(HV_X86_DR3, u64DrTmp);
990	if (pVCpu->cpum.GstCtx.dr[2] != u64DrTmp)
991	CPUMSetGuestDR2(pVCpu, u64DrTmp);
992	READ_GREG(HV_X86_DR3, u64DrTmp);
993	if (pVCpu->cpum.GstCtx.dr[3] != u64DrTmp)
994	CPUMSetGuestDR3(pVCpu, u64DrTmp);
995	}
996	if (fWhat & CPUMCTX_EXTRN_DR6)
997	{
998	uint64_t u64Dr6;
999	READ_GREG(HV_X86_DR7, u64Dr6);
1000	if (pVCpu->cpum.GstCtx.dr[6] != u64Dr6)
1001	CPUMSetGuestDR6(pVCpu, u64Dr6);
1002	}
1003
1004	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
1005	{
1006	hrc = hv_vcpu_read_fpstate(pVCpu->nem.s.hVCpuId, &pVCpu->cpum.GstCtx.XState, sizeof(pVCpu->cpum.GstCtx.XState));
1007	if (hrc == HV_SUCCESS)
1008	{ /* likely */ }
1009	else
1010	return nemR3DarwinHvSts2Rc(hrc);
1011	}
1012
1013	/* MSRs */
1014	if (fWhat & CPUMCTX_EXTRN_EFER)
1015	{
1016	uint64_t u64Efer;
1017
1018	READ_VMCS_FIELD(VMX_VMCS64_GUEST_EFER_FULL, u64Efer);
1019	if (u64Efer != pVCpu->cpum.GstCtx.msrEFER)
1020	{
1021	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, u64Efer));
1022	if ((u64Efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1023	PGMNotifyNxeChanged(pVCpu, RT_BOOL(u64Efer & MSR_K6_EFER_NXE));
1024	pVCpu->cpum.GstCtx.msrEFER = u64Efer;
1025	fMaybeChangedMode = true;
1026	}
1027	}
1028
1029	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1030	READ_MSR(MSR_K8_KERNEL_GS_BASE, pVCpu->cpum.GstCtx.msrKERNELGSBASE);
1031	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1032	{
1033	uint64_t u64Tmp;
1034	READ_MSR(MSR_IA32_SYSENTER_EIP, u64Tmp);
1035	pVCpu->cpum.GstCtx.SysEnter.eip = u64Tmp;
1036	READ_MSR(MSR_IA32_SYSENTER_ESP, u64Tmp);
1037	pVCpu->cpum.GstCtx.SysEnter.esp = u64Tmp;
1038	READ_MSR(MSR_IA32_SYSENTER_CS, u64Tmp);
1039	pVCpu->cpum.GstCtx.SysEnter.cs = u64Tmp;
1040	}
1041	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1042	{
1043	READ_MSR(MSR_K6_STAR, pVCpu->cpum.GstCtx.msrSTAR);
1044	READ_MSR(MSR_K8_LSTAR, pVCpu->cpum.GstCtx.msrLSTAR);
1045	READ_MSR(MSR_K8_CSTAR, pVCpu->cpum.GstCtx.msrCSTAR);
1046	READ_MSR(MSR_K8_SF_MASK, pVCpu->cpum.GstCtx.msrSFMASK);
1047	}
1048	#if 0
1049	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1050	{
1051	Assert(aenmNames[iReg] == WHvX64RegisterApicBase);
1052	const uint64_t uOldBase = APICGetBaseMsrNoCheck(pVCpu);
1053	if (aValues[iReg].Reg64 != uOldBase)
1054	{
1055	Log7(("NEM/%u: MSR APICBase changed %RX64 -> %RX64 (%RX64)\n",
1056	pVCpu->idCpu, uOldBase, aValues[iReg].Reg64, aValues[iReg].Reg64 ^ uOldBase));
1057	int rc2 = APICSetBaseMsr(pVCpu, aValues[iReg].Reg64);
1058	AssertLogRelMsg(rc2 == VINF_SUCCESS, ("%Rrc %RX64\n", rc2, aValues[iReg].Reg64));
1059	}
1060	iReg++;
1061
1062	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrPAT, WHvX64RegisterPat, "MSR PAT");
1063	#if 0 /def LOG_ENABLED/ /** @todo something's wrong with HvX64RegisterMtrrCap? (AMD) */
1064	GET_REG64_LOG7(pVCpu->cpum.GstCtx.msrPAT, WHvX64RegisterMsrMtrrCap);
1065	#endif
1066	PCPUMCTXMSRS pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1067	GET_REG64_LOG7(pCtxMsrs->msr.MtrrDefType, WHvX64RegisterMsrMtrrDefType, "MSR MTRR_DEF_TYPE");
1068	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix64K_00000, WHvX64RegisterMsrMtrrFix64k00000, "MSR MTRR_FIX_64K_00000");
1069	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix16K_80000, WHvX64RegisterMsrMtrrFix16k80000, "MSR MTRR_FIX_16K_80000");
1070	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix16K_A0000, WHvX64RegisterMsrMtrrFix16kA0000, "MSR MTRR_FIX_16K_A0000");
1071	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_C0000, WHvX64RegisterMsrMtrrFix4kC0000, "MSR MTRR_FIX_4K_C0000");
1072	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_C8000, WHvX64RegisterMsrMtrrFix4kC8000, "MSR MTRR_FIX_4K_C8000");
1073	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_D0000, WHvX64RegisterMsrMtrrFix4kD0000, "MSR MTRR_FIX_4K_D0000");
1074	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_D8000, WHvX64RegisterMsrMtrrFix4kD8000, "MSR MTRR_FIX_4K_D8000");
1075	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_E0000, WHvX64RegisterMsrMtrrFix4kE0000, "MSR MTRR_FIX_4K_E0000");
1076	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_E8000, WHvX64RegisterMsrMtrrFix4kE8000, "MSR MTRR_FIX_4K_E8000");
1077	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_F0000, WHvX64RegisterMsrMtrrFix4kF0000, "MSR MTRR_FIX_4K_F0000");
1078	GET_REG64_LOG7(pCtxMsrs->msr.MtrrFix4K_F8000, WHvX64RegisterMsrMtrrFix4kF8000, "MSR MTRR_FIX_4K_F8000");
1079	GET_REG64_LOG7(pCtxMsrs->msr.TscAux, WHvX64RegisterTscAux, "MSR TSC_AUX");
1080	/** @todo look for HvX64RegisterIa32MiscEnable and HvX64RegisterIa32FeatureControl? */
1081	}
1082	#endif
1083
1084	/* Almost done, just update extrn flags and maybe change PGM mode. */
1085	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1086	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1087	pVCpu->cpum.GstCtx.fExtrn = 0;
1088
1089	/* Typical. */
1090	if (!fMaybeChangedMode && !fUpdateCr3)
1091	return VINF_SUCCESS;
1092
1093	/*
1094	* Slow.
1095	*/
1096	if (fMaybeChangedMode)
1097	{
1098	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1099	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1100	}
1101
1102	if (fUpdateCr3)
1103	{
1104	int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3, false /fPdpesMapped/);
1105	if (rc == VINF_SUCCESS)
1106	{ /* likely */ }
1107	else
1108	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1109	}
1110
1111	return VINF_SUCCESS;
1112	#undef READ_GREG
1113	#undef READ_VMCS_FIELD
1114	#undef READ_VMCS32_FIELD
1115	#undef READ_SEG
1116	#undef READ_MSR
1117	}
1118
1119
1120	/**
1121	* State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
1122	* and nemHCWinHandleMemoryAccessPageCheckerCallback.
1123	*/
1124	typedef struct NEMHCDARWINHMACPCCSTATE
1125	{
1126	/** Input: Write access. */
1127	bool fWriteAccess;
1128	/** Output: Set if we did something. */
1129	bool fDidSomething;
1130	/** Output: Set it we should resume. */
1131	bool fCanResume;
1132	} NEMHCDARWINHMACPCCSTATE;
1133
1134	/**
1135	* @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1136	* Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1137	* NEMHCDARWINHMACPCCSTATE structure. }
1138	*/
1139	static DECLCALLBACK(int)
1140	nemR3DarwinHandleMemoryAccessPageCheckerCallback(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1141	{
1142	NEMHCDARWINHMACPCCSTATE pState = (NEMHCDARWINHMACPCCSTATE )pvUser;
1143	pState->fDidSomething = false;
1144	pState->fCanResume = false;
1145
1146	uint8_t u2State = pInfo->u2NemState;
1147
1148	/*
1149	* Consolidate current page state with actual page protection and access type.
1150	* We don't really consider downgrades here, as they shouldn't happen.
1151	*/
1152	int rc;
1153	switch (u2State)
1154	{
1155	case NEM_DARWIN_PAGE_STATE_UNMAPPED:
1156	case NEM_DARWIN_PAGE_STATE_NOT_SET:
1157	if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1158	{
1159	Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1160	return VINF_SUCCESS;
1161	}
1162
1163	/* Don't bother remapping it if it's a write request to a non-writable page. */
1164	if ( pState->fWriteAccess
1165	&& !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1166	{
1167	Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1168	return VINF_SUCCESS;
1169	}
1170
1171	/* Map the page. */
1172	rc = nemHCNativeSetPhysPage(pVM,
1173	pVCpu,
1174	GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1175	GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1176	pInfo->fNemProt,
1177	&u2State,
1178	true /fBackingState/);
1179	pInfo->u2NemState = u2State;
1180	Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1181	GCPhys, g_apszPageStates[u2State], rc));
1182	pState->fDidSomething = true;
1183	pState->fCanResume = true;
1184	return rc;
1185
1186	case NEM_DARWIN_PAGE_STATE_READABLE:
1187	if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1188	&& (pInfo->fNemProt & (NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE)))
1189	{
1190	pState->fCanResume = true;
1191	Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1192	return VINF_SUCCESS;
1193	}
1194	break;
1195
1196	case NEM_DARWIN_PAGE_STATE_WRITABLE:
1197	if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1198	{
1199	/* We get spurious EPT exit violations when everything is fine (#3a case) but can resume without issues here... */
1200	pState->fCanResume = true;
1201	if (pInfo->u2OldNemState == NEM_DARWIN_PAGE_STATE_WRITABLE)
1202	Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #3a\n", GCPhys));
1203	else
1204	Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #3b (%s -> %s)\n",
1205	GCPhys, g_apszPageStates[pInfo->u2OldNemState], g_apszPageStates[u2State]));
1206	return VINF_SUCCESS;
1207	}
1208
1209	break;
1210
1211	default:
1212	AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_NEM_IPE_4);
1213	}
1214
1215	/*
1216	* Unmap and restart the instruction.
1217	* If this fails, which it does every so often, just unmap everything for now.
1218	*/
1219	rc = nemR3DarwinUnmap(pVM, GCPhys, X86_PAGE_SIZE);
1220	if (RT_SUCCESS(rc))
1221	{
1222	pState->fDidSomething = true;
1223	pState->fCanResume = true;
1224	pInfo->u2NemState = NEM_DARWIN_PAGE_STATE_UNMAPPED;
1225	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
1226	Log5(("NEM GPA unmapped/exit: %RGp (was %s)\n", GCPhys, g_apszPageStates[u2State]));
1227	return VINF_SUCCESS;
1228	}
1229	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
1230	LogRel(("nemR3DarwinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s rc=%Rrc\n",
1231	GCPhys, g_apszPageStates[u2State], rc));
1232	return VERR_NEM_UNMAP_PAGES_FAILED;
1233	}
1234
1235
1236	DECL_FORCE_INLINE(bool) vmxHCShouldSwapEferMsr(PCVMCPUCC pVCpu, PCVMXTRANSIENT pVmxTransient)
1237	{
1238	RT_NOREF(pVCpu, pVmxTransient);
1239	return true;
1240	}
1241
1242
1243	DECL_FORCE_INLINE(bool) nemR3DarwinIsUnrestrictedGuest(PCVMCC pVM)
1244	{
1245	RT_NOREF(pVM);
1246	return true;
1247	}
1248
1249
1250	DECL_FORCE_INLINE(bool) nemR3DarwinIsNestedPaging(PCVMCC pVM)
1251	{
1252	RT_NOREF(pVM);
1253	return true;
1254	}
1255
1256
1257	DECL_FORCE_INLINE(bool) nemR3DarwinIsPreemptTimerUsed(PCVMCC pVM)
1258	{
1259	RT_NOREF(pVM);
1260	return false;
1261	}
1262
1263
1264	DECL_FORCE_INLINE(bool) nemR3DarwinIsVmxLbr(PCVMCC pVM)
1265	{
1266	RT_NOREF(pVM);
1267	return false;
1268	}
1269
1270
1271	/*
1272	* Instantiate the code we share with ring-0.
1273	*/
1274	#define IN_NEM_DARWIN
1275	//#define HMVMX_ALWAYS_TRAP_ALL_XCPTS
1276	#define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
1277	#define VCPU_2_VMXSTATE(a_pVCpu) (a_pVCpu)->nem.s
1278	#define VCPU_2_VMXSTATS(a_pVCpu) (*(a_pVCpu)->nem.s.pVmxStats)
1279
1280	#define VM_IS_VMX_UNRESTRICTED_GUEST(a_pVM) nemR3DarwinIsUnrestrictedGuest((a_pVM))
1281	#define VM_IS_VMX_NESTED_PAGING(a_pVM) nemR3DarwinIsNestedPaging((a_pVM))
1282	#define VM_IS_VMX_PREEMPT_TIMER_USED(a_pVM) nemR3DarwinIsPreemptTimerUsed((a_pVM))
1283	#define VM_IS_VMX_LBR(a_pVM) nemR3DarwinIsVmxLbr((a_pVM))
1284
1285	#define VMX_VMCS_WRITE_16(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs16((a_pVCpu), (a_FieldEnc), (a_Val))
1286	#define VMX_VMCS_WRITE_32(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs32((a_pVCpu), (a_FieldEnc), (a_Val))
1287	#define VMX_VMCS_WRITE_64(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs64((a_pVCpu), (a_FieldEnc), (a_Val))
1288	#define VMX_VMCS_WRITE_NW(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs64((a_pVCpu), (a_FieldEnc), (a_Val))
1289
1290	#define VMX_VMCS_READ_16(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs16((a_pVCpu), (a_FieldEnc), (a_pVal))
1291	#define VMX_VMCS_READ_32(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs32((a_pVCpu), (a_FieldEnc), (a_pVal))
1292	#define VMX_VMCS_READ_64(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs64((a_pVCpu), (a_FieldEnc), (a_pVal))
1293	#define VMX_VMCS_READ_NW(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs64((a_pVCpu), (a_FieldEnc), (a_pVal))
1294
1295	#include "../VMMAll/VMXAllTemplate.cpp.h"
1296
1297	#undef VMX_VMCS_WRITE_16
1298	#undef VMX_VMCS_WRITE_32
1299	#undef VMX_VMCS_WRITE_64
1300	#undef VMX_VMCS_WRITE_NW
1301
1302	#undef VMX_VMCS_READ_16
1303	#undef VMX_VMCS_READ_32
1304	#undef VMX_VMCS_READ_64
1305	#undef VMX_VMCS_READ_NW
1306
1307	#undef VM_IS_VMX_PREEMPT_TIMER_USED
1308	#undef VM_IS_VMX_NESTED_PAGING
1309	#undef VM_IS_VMX_UNRESTRICTED_GUEST
1310	#undef VCPU_2_VMXSTATS
1311	#undef VCPU_2_VMXSTATE
1312
1313
1314	/**
1315	* Exports the guest GP registers to HV for execution.
1316	*
1317	* @returns VBox status code.
1318	* @param pVCpu The cross context virtual CPU structure of the
1319	* calling EMT.
1320	*/
1321	static int nemR3DarwinExportGuestGprs(PVMCPUCC pVCpu)
1322	{
1323	#define WRITE_GREG(a_GReg, a_Value) \
1324	do \
1325	{ \
1326	hv_return_t hrc = hv_vcpu_write_register(pVCpu->nem.s.hVCpuId, (a_GReg), (a_Value)); \
1327	if (RT_LIKELY(hrc == HV_SUCCESS)) \
1328	{ /* likely */ } \
1329	else \
1330	return VERR_INTERNAL_ERROR; \
1331	} while(0)
1332
1333	uint64_t fCtxChanged = ASMAtomicUoReadU64(&pVCpu->nem.s.fCtxChanged);
1334	if (fCtxChanged & HM_CHANGED_GUEST_GPRS_MASK)
1335	{
1336	if (fCtxChanged & HM_CHANGED_GUEST_RAX)
1337	WRITE_GREG(HV_X86_RAX, pVCpu->cpum.GstCtx.rax);
1338	if (fCtxChanged & HM_CHANGED_GUEST_RCX)
1339	WRITE_GREG(HV_X86_RCX, pVCpu->cpum.GstCtx.rcx);
1340	if (fCtxChanged & HM_CHANGED_GUEST_RDX)
1341	WRITE_GREG(HV_X86_RDX, pVCpu->cpum.GstCtx.rdx);
1342	if (fCtxChanged & HM_CHANGED_GUEST_RBX)
1343	WRITE_GREG(HV_X86_RBX, pVCpu->cpum.GstCtx.rbx);
1344	if (fCtxChanged & HM_CHANGED_GUEST_RSP)
1345	WRITE_GREG(HV_X86_RSP, pVCpu->cpum.GstCtx.rsp);
1346	if (fCtxChanged & HM_CHANGED_GUEST_RBP)
1347	WRITE_GREG(HV_X86_RBP, pVCpu->cpum.GstCtx.rbp);
1348	if (fCtxChanged & HM_CHANGED_GUEST_RSI)
1349	WRITE_GREG(HV_X86_RSI, pVCpu->cpum.GstCtx.rsi);
1350	if (fCtxChanged & HM_CHANGED_GUEST_RDI)
1351	WRITE_GREG(HV_X86_RDI, pVCpu->cpum.GstCtx.rdi);
1352	if (fCtxChanged & HM_CHANGED_GUEST_R8_R15)
1353	{
1354	WRITE_GREG(HV_X86_R8, pVCpu->cpum.GstCtx.r8);
1355	WRITE_GREG(HV_X86_R9, pVCpu->cpum.GstCtx.r9);
1356	WRITE_GREG(HV_X86_R10, pVCpu->cpum.GstCtx.r10);
1357	WRITE_GREG(HV_X86_R11, pVCpu->cpum.GstCtx.r11);
1358	WRITE_GREG(HV_X86_R12, pVCpu->cpum.GstCtx.r12);
1359	WRITE_GREG(HV_X86_R13, pVCpu->cpum.GstCtx.r13);
1360	WRITE_GREG(HV_X86_R14, pVCpu->cpum.GstCtx.r14);
1361	WRITE_GREG(HV_X86_R15, pVCpu->cpum.GstCtx.r15);
1362	}
1363
1364	ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_GPRS_MASK);
1365	}
1366
1367	if (fCtxChanged & HM_CHANGED_GUEST_CR2)
1368	{
1369	WRITE_GREG(HV_X86_CR2, pVCpu->cpum.GstCtx.cr2);
1370	ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_CR2);
1371	}
1372
1373	return VINF_SUCCESS;
1374	#undef WRITE_GREG
1375	}
1376
1377
1378	/**
1379	* Converts the given CPUM externalized bitmask to the appropriate HM changed bitmask.
1380	*
1381	* @returns Bitmask of HM changed flags.
1382	* @param fCpumExtrn The CPUM extern bitmask.
1383	*/
1384	static uint64_t nemR3DarwinCpumExtrnToHmChanged(uint64_t fCpumExtrn)
1385	{
1386	uint64_t fHmChanged = 0;
1387
1388	/* Invert to gt a mask of things which are kept in CPUM. */
1389	uint64_t fCpumIntern = ~fCpumExtrn;
1390
1391	if (fCpumIntern & CPUMCTX_EXTRN_GPRS_MASK)
1392	{
1393	if (fCpumIntern & CPUMCTX_EXTRN_RAX)
1394	fHmChanged \|= HM_CHANGED_GUEST_RAX;
1395	if (fCpumIntern & CPUMCTX_EXTRN_RCX)
1396	fHmChanged \|= HM_CHANGED_GUEST_RCX;
1397	if (fCpumIntern & CPUMCTX_EXTRN_RDX)
1398	fHmChanged \|= HM_CHANGED_GUEST_RDX;
1399	if (fCpumIntern & CPUMCTX_EXTRN_RBX)
1400	fHmChanged \|= HM_CHANGED_GUEST_RBX;
1401	if (fCpumIntern & CPUMCTX_EXTRN_RSP)
1402	fHmChanged \|= HM_CHANGED_GUEST_RSP;
1403	if (fCpumIntern & CPUMCTX_EXTRN_RBP)
1404	fHmChanged \|= HM_CHANGED_GUEST_RBP;
1405	if (fCpumIntern & CPUMCTX_EXTRN_RSI)
1406	fHmChanged \|= HM_CHANGED_GUEST_RSI;
1407	if (fCpumIntern & CPUMCTX_EXTRN_RDI)
1408	fHmChanged \|= HM_CHANGED_GUEST_RDI;
1409	if (fCpumIntern & CPUMCTX_EXTRN_R8_R15)
1410	fHmChanged \|= HM_CHANGED_GUEST_R8_R15;
1411	}
1412
1413	/* RIP & Flags */
1414	if (fCpumIntern & CPUMCTX_EXTRN_RIP)
1415	fHmChanged \|= HM_CHANGED_GUEST_RIP;
1416	if (fCpumIntern & CPUMCTX_EXTRN_RFLAGS)
1417	fHmChanged \|= HM_CHANGED_GUEST_RFLAGS;
1418
1419	/* Segments */
1420	if (fCpumIntern & CPUMCTX_EXTRN_SREG_MASK)
1421	{
1422	if (fCpumIntern & CPUMCTX_EXTRN_ES)
1423	fHmChanged \|= HM_CHANGED_GUEST_ES;
1424	if (fCpumIntern & CPUMCTX_EXTRN_CS)
1425	fHmChanged \|= HM_CHANGED_GUEST_CS;
1426	if (fCpumIntern & CPUMCTX_EXTRN_SS)
1427	fHmChanged \|= HM_CHANGED_GUEST_SS;
1428	if (fCpumIntern & CPUMCTX_EXTRN_DS)
1429	fHmChanged \|= HM_CHANGED_GUEST_DS;
1430	if (fCpumIntern & CPUMCTX_EXTRN_FS)
1431	fHmChanged \|= HM_CHANGED_GUEST_FS;
1432	if (fCpumIntern & CPUMCTX_EXTRN_GS)
1433	fHmChanged \|= HM_CHANGED_GUEST_GS;
1434	}
1435
1436	/* Descriptor tables & task segment. */
1437	if (fCpumIntern & CPUMCTX_EXTRN_TABLE_MASK)
1438	{
1439	if (fCpumIntern & CPUMCTX_EXTRN_LDTR)
1440	fHmChanged \|= HM_CHANGED_GUEST_LDTR;
1441	if (fCpumIntern & CPUMCTX_EXTRN_TR)
1442	fHmChanged \|= HM_CHANGED_GUEST_TR;
1443	if (fCpumIntern & CPUMCTX_EXTRN_IDTR)
1444	fHmChanged \|= HM_CHANGED_GUEST_IDTR;
1445	if (fCpumIntern & CPUMCTX_EXTRN_GDTR)
1446	fHmChanged \|= HM_CHANGED_GUEST_GDTR;
1447	}
1448
1449	/* Control registers. */
1450	if (fCpumIntern & CPUMCTX_EXTRN_CR_MASK)
1451	{
1452	if (fCpumIntern & CPUMCTX_EXTRN_CR0)
1453	fHmChanged \|= HM_CHANGED_GUEST_CR0;
1454	if (fCpumIntern & CPUMCTX_EXTRN_CR2)
1455	fHmChanged \|= HM_CHANGED_GUEST_CR2;
1456	if (fCpumIntern & CPUMCTX_EXTRN_CR3)
1457	fHmChanged \|= HM_CHANGED_GUEST_CR3;
1458	if (fCpumIntern & CPUMCTX_EXTRN_CR4)
1459	fHmChanged \|= HM_CHANGED_GUEST_CR4;
1460	}
1461	if (fCpumIntern & CPUMCTX_EXTRN_APIC_TPR)
1462	fHmChanged \|= HM_CHANGED_GUEST_APIC_TPR;
1463
1464	/* Debug registers. */
1465	if (fCpumIntern & CPUMCTX_EXTRN_DR0_DR3)
1466	fHmChanged \|= HM_CHANGED_GUEST_DR0_DR3;
1467	if (fCpumIntern & CPUMCTX_EXTRN_DR6)
1468	fHmChanged \|= HM_CHANGED_GUEST_DR6;
1469	if (fCpumIntern & CPUMCTX_EXTRN_DR7)
1470	fHmChanged \|= HM_CHANGED_GUEST_DR7;
1471
1472	/* Floating point state. */
1473	if (fCpumIntern & CPUMCTX_EXTRN_X87)
1474	fHmChanged \|= HM_CHANGED_GUEST_X87;
1475	if (fCpumIntern & CPUMCTX_EXTRN_SSE_AVX)
1476	fHmChanged \|= HM_CHANGED_GUEST_SSE_AVX;
1477	if (fCpumIntern & CPUMCTX_EXTRN_OTHER_XSAVE)
1478	fHmChanged \|= HM_CHANGED_GUEST_OTHER_XSAVE;
1479	if (fCpumIntern & CPUMCTX_EXTRN_XCRx)
1480	fHmChanged \|= HM_CHANGED_GUEST_XCRx;
1481
1482	/* MSRs */
1483	if (fCpumIntern & CPUMCTX_EXTRN_EFER)
1484	fHmChanged \|= HM_CHANGED_GUEST_EFER_MSR;
1485	if (fCpumIntern & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1486	fHmChanged \|= HM_CHANGED_GUEST_KERNEL_GS_BASE;
1487	if (fCpumIntern & CPUMCTX_EXTRN_SYSENTER_MSRS)
1488	fHmChanged \|= HM_CHANGED_GUEST_SYSENTER_MSR_MASK;
1489	if (fCpumIntern & CPUMCTX_EXTRN_SYSCALL_MSRS)
1490	fHmChanged \|= HM_CHANGED_GUEST_SYSCALL_MSRS;
1491	if (fCpumIntern & CPUMCTX_EXTRN_TSC_AUX)
1492	fHmChanged \|= HM_CHANGED_GUEST_TSC_AUX;
1493	if (fCpumIntern & CPUMCTX_EXTRN_OTHER_MSRS)
1494	fHmChanged \|= HM_CHANGED_GUEST_OTHER_MSRS;
1495
1496	return fHmChanged;
1497	}
1498
1499
1500	/**
1501	* Exports the guest state to HV for execution.
1502	*
1503	* @returns VBox status code.
1504	* @param pVM The cross context VM structure.
1505	* @param pVCpu The cross context virtual CPU structure of the
1506	* calling EMT.
1507	* @param pVmxTransient The transient VMX structure.
1508	*/
1509	static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
1510	{
1511	#define WRITE_GREG(a_GReg, a_Value) \
1512	do \
1513	{ \
1514	hv_return_t hrc = hv_vcpu_write_register(pVCpu->nem.s.hVCpuId, (a_GReg), (a_Value)); \
1515	if (RT_LIKELY(hrc == HV_SUCCESS)) \
1516	{ /* likely */ } \
1517	else \
1518	return VERR_INTERNAL_ERROR; \
1519	} while(0)
1520	#define WRITE_VMCS_FIELD(a_Field, a_Value) \
1521	do \
1522	{ \
1523	hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), (a_Value)); \
1524	if (RT_LIKELY(hrc == HV_SUCCESS)) \
1525	{ /* likely */ } \
1526	else \
1527	return VERR_INTERNAL_ERROR; \
1528	} while(0)
1529	#define WRITE_MSR(a_Msr, a_Value) \
1530	do \
1531	{ \
1532	hv_return_t hrc = hv_vcpu_write_msr(pVCpu->nem.s.hVCpuId, (a_Msr), (a_Value)); \
1533	if (RT_LIKELY(hrc == HV_SUCCESS)) \
1534	{ /* likely */ } \
1535	else \
1536	AssertFailedReturn(VERR_INTERNAL_ERROR); \
1537	} while(0)
1538
1539	RT_NOREF(pVM);
1540
1541	uint64_t const fWhat = ~pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL;
1542	if (!fWhat)
1543	return VINF_SUCCESS;
1544
1545	pVCpu->nem.s.fCtxChanged \|= nemR3DarwinCpumExtrnToHmChanged(pVCpu->cpum.GstCtx.fExtrn);
1546
1547	int rc = vmxHCExportGuestEntryExitCtls(pVCpu, pVmxTransient);
1548	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1549
1550	rc = nemR3DarwinExportGuestGprs(pVCpu);
1551	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1552
1553	rc = vmxHCExportGuestCR0(pVCpu, pVmxTransient);
1554	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1555
1556	VBOXSTRICTRC rcStrict = vmxHCExportGuestCR3AndCR4(pVCpu, pVmxTransient);
1557	if (rcStrict == VINF_SUCCESS)
1558	{ /* likely */ }
1559	else
1560	{
1561	Assert(rcStrict == VINF_EM_RESCHEDULE_REM \|\| RT_FAILURE_NP(rcStrict));
1562	return VBOXSTRICTRC_VAL(rcStrict);
1563	}
1564
1565	vmxHCExportGuestXcptIntercepts(pVCpu, pVmxTransient);
1566	vmxHCExportGuestRip(pVCpu);
1567	//vmxHCExportGuestRsp(pVCpu);
1568	vmxHCExportGuestRflags(pVCpu, pVmxTransient);
1569
1570	rc = vmxHCExportGuestSegRegsXdtr(pVCpu, pVmxTransient);
1571	AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1572
1573	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1574	WRITE_GREG(HV_X86_TPR, CPUMGetGuestCR8(pVCpu));
1575
1576	/* Debug registers. */
1577	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1578	{
1579	WRITE_GREG(HV_X86_DR0, pVCpu->cpum.GstCtx.dr[0]); // CPUMGetHyperDR0(pVCpu));
1580	WRITE_GREG(HV_X86_DR1, pVCpu->cpum.GstCtx.dr[1]); // CPUMGetHyperDR1(pVCpu));
1581	WRITE_GREG(HV_X86_DR2, pVCpu->cpum.GstCtx.dr[2]); // CPUMGetHyperDR2(pVCpu));
1582	WRITE_GREG(HV_X86_DR3, pVCpu->cpum.GstCtx.dr[3]); // CPUMGetHyperDR3(pVCpu));
1583	}
1584	if (fWhat & CPUMCTX_EXTRN_DR6)
1585	WRITE_GREG(HV_X86_DR6, pVCpu->cpum.GstCtx.dr[6]); // CPUMGetHyperDR6(pVCpu));
1586	if (fWhat & CPUMCTX_EXTRN_DR7)
1587	WRITE_GREG(HV_X86_DR7, pVCpu->cpum.GstCtx.dr[7]); // CPUMGetHyperDR7(pVCpu));
1588
1589	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX))
1590	{
1591	hv_return_t hrc = hv_vcpu_write_fpstate(pVCpu->nem.s.hVCpuId, &pVCpu->cpum.GstCtx.XState, sizeof(pVCpu->cpum.GstCtx.XState));
1592	if (hrc == HV_SUCCESS)
1593	{ /* likely */ }
1594	else
1595	return nemR3DarwinHvSts2Rc(hrc);
1596	}
1597
1598	/* MSRs */
1599	if (fWhat & CPUMCTX_EXTRN_EFER)
1600	WRITE_VMCS_FIELD(VMX_VMCS64_GUEST_EFER_FULL, pVCpu->cpum.GstCtx.msrEFER);
1601	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1602	WRITE_MSR(MSR_K8_KERNEL_GS_BASE, pVCpu->cpum.GstCtx.msrKERNELGSBASE);
1603	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1604	{
1605	WRITE_MSR(MSR_IA32_SYSENTER_CS, pVCpu->cpum.GstCtx.SysEnter.cs);
1606	WRITE_MSR(MSR_IA32_SYSENTER_EIP, pVCpu->cpum.GstCtx.SysEnter.eip);
1607	WRITE_MSR(MSR_IA32_SYSENTER_ESP, pVCpu->cpum.GstCtx.SysEnter.esp);
1608	}
1609	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1610	{
1611	WRITE_MSR(MSR_K6_STAR, pVCpu->cpum.GstCtx.msrSTAR);
1612	WRITE_MSR(MSR_K8_LSTAR, pVCpu->cpum.GstCtx.msrLSTAR);
1613	WRITE_MSR(MSR_K8_CSTAR, pVCpu->cpum.GstCtx.msrCSTAR);
1614	WRITE_MSR(MSR_K8_SF_MASK, pVCpu->cpum.GstCtx.msrSFMASK);
1615	}
1616	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1617	{
1618	hv_return_t hrc = hv_vmx_vcpu_set_apic_address(pVCpu->nem.s.hVCpuId, APICGetBaseMsrNoCheck(pVCpu) & PAGE_BASE_GC_MASK);
1619	if (RT_UNLIKELY(hrc != HV_SUCCESS))
1620	return nemR3DarwinHvSts2Rc(hrc);
1621
1622	#if 0
1623	ADD_REG64(WHvX64RegisterPat, pVCpu->cpum.GstCtx.msrPAT);
1624	#if 0 /** @todo check if WHvX64RegisterMsrMtrrCap works here... */
1625	ADD_REG64(WHvX64RegisterMsrMtrrCap, CPUMGetGuestIa32MtrrCap(pVCpu));
1626	#endif
1627	PCPUMCTXMSRS pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1628	ADD_REG64(WHvX64RegisterMsrMtrrDefType, pCtxMsrs->msr.MtrrDefType);
1629	ADD_REG64(WHvX64RegisterMsrMtrrFix64k00000, pCtxMsrs->msr.MtrrFix64K_00000);
1630	ADD_REG64(WHvX64RegisterMsrMtrrFix16k80000, pCtxMsrs->msr.MtrrFix16K_80000);
1631	ADD_REG64(WHvX64RegisterMsrMtrrFix16kA0000, pCtxMsrs->msr.MtrrFix16K_A0000);
1632	ADD_REG64(WHvX64RegisterMsrMtrrFix4kC0000, pCtxMsrs->msr.MtrrFix4K_C0000);
1633	ADD_REG64(WHvX64RegisterMsrMtrrFix4kC8000, pCtxMsrs->msr.MtrrFix4K_C8000);
1634	ADD_REG64(WHvX64RegisterMsrMtrrFix4kD0000, pCtxMsrs->msr.MtrrFix4K_D0000);
1635	ADD_REG64(WHvX64RegisterMsrMtrrFix4kD8000, pCtxMsrs->msr.MtrrFix4K_D8000);
1636	ADD_REG64(WHvX64RegisterMsrMtrrFix4kE0000, pCtxMsrs->msr.MtrrFix4K_E0000);
1637	ADD_REG64(WHvX64RegisterMsrMtrrFix4kE8000, pCtxMsrs->msr.MtrrFix4K_E8000);
1638	ADD_REG64(WHvX64RegisterMsrMtrrFix4kF0000, pCtxMsrs->msr.MtrrFix4K_F0000);
1639	ADD_REG64(WHvX64RegisterMsrMtrrFix4kF8000, pCtxMsrs->msr.MtrrFix4K_F8000);
1640	ADD_REG64(WHvX64RegisterTscAux, pCtxMsrs->msr.TscAux);
1641	#if 0 /** @todo these registers aren't available? Might explain something.. .*/
1642	const CPUMCPUVENDOR enmCpuVendor = CPUMGetHostCpuVendor(pVM);
1643	if (enmCpuVendor != CPUMCPUVENDOR_AMD)
1644	{
1645	ADD_REG64(HvX64RegisterIa32MiscEnable, pCtxMsrs->msr.MiscEnable);
1646	ADD_REG64(HvX64RegisterIa32FeatureControl, CPUMGetGuestIa32FeatureControl(pVCpu));
1647	}
1648	#endif
1649	#endif
1650	}
1651
1652	WRITE_VMCS_FIELD(VMX_VMCS64_GUEST_DEBUGCTL_FULL, 0 /MSR_IA32_DEBUGCTL_LBR/);
1653
1654	#if 0 /** @todo */
1655	WRITE_GREG(HV_X86_TSS_BASE, );
1656	WRITE_GREG(HV_X86_TSS_LIMIT, );
1657	WRITE_GREG(HV_X86_TSS_AR, );
1658	WRITE_GREG(HV_X86_XCR0, );
1659	#endif
1660
1661	hv_vcpu_invalidate_tlb(pVCpu->nem.s.hVCpuId);
1662	hv_vcpu_flush(pVCpu->nem.s.hVCpuId);
1663
1664	pVCpu->cpum.GstCtx.fExtrn \|= CPUMCTX_EXTRN_ALL \| CPUMCTX_EXTRN_KEEPER_NEM;
1665
1666	/* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
1667	ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~( (HM_CHANGED_GUEST_GPRS_MASK & ~HM_CHANGED_GUEST_RSP)
1668	\| HM_CHANGED_GUEST_CR2
1669	\| (HM_CHANGED_GUEST_DR_MASK & ~HM_CHANGED_GUEST_DR7)
1670	\| HM_CHANGED_GUEST_X87
1671	\| HM_CHANGED_GUEST_SSE_AVX
1672	\| HM_CHANGED_GUEST_OTHER_XSAVE
1673	\| HM_CHANGED_GUEST_XCRx
1674	\| HM_CHANGED_GUEST_KERNEL_GS_BASE /* Part of lazy or auto load-store MSRs. */
1675	\| HM_CHANGED_GUEST_SYSCALL_MSRS /* Part of lazy or auto load-store MSRs. */
1676	\| HM_CHANGED_GUEST_TSC_AUX
1677	\| HM_CHANGED_GUEST_OTHER_MSRS
1678	\| (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK)));
1679
1680	return VINF_SUCCESS;
1681	#undef WRITE_GREG
1682	#undef WRITE_VMCS_FIELD
1683	}
1684
1685
1686	/**
1687	* Handles an exit from hv_vcpu_run().
1688	*
1689	* @returns VBox strict status code.
1690	* @param pVM The cross context VM structure.
1691	* @param pVCpu The cross context virtual CPU structure of the
1692	* calling EMT.
1693	* @param pVmxTransient The transient VMX structure.
1694	*/
1695	static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
1696	{
1697	uint32_t uExitReason;
1698	int rc = nemR3DarwinReadVmcs32(pVCpu, VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
1699	AssertRC(rc);
1700	pVmxTransient->fVmcsFieldsRead = 0;
1701	pVmxTransient->fIsNestedGuest = false;
1702	pVmxTransient->uExitReason = VMX_EXIT_REASON_BASIC(uExitReason);
1703	pVmxTransient->fVMEntryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
1704
1705	if (RT_UNLIKELY(pVmxTransient->fVMEntryFailed))
1706	AssertLogRelMsgFailedReturn(("Running guest failed for CPU #%u: %#x %u\n",
1707	pVCpu->idCpu, pVmxTransient->uExitReason, vmxHCCheckGuestState(pVCpu, &pVCpu->nem.s.VmcsInfo)),
1708	VERR_NEM_IPE_0);
1709
1710	/** @todo Only copy the state on demand (requires changing to adhere to fCtxChanged from th VMX code
1711	* flags instead of the fExtrn one living in CPUM.
1712	*/
1713	rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, UINT64_MAX);
1714	AssertRCReturn(rc, rc);
1715
1716	#ifndef HMVMX_USE_FUNCTION_TABLE
1717	return vmxHCHandleExit(pVCpu, pVmxTransient);
1718	#else
1719	return g_aVMExitHandlers[pVmxTransient->uExitReason].pfn(pVCpu, pVmxTransient);
1720	#endif
1721	}
1722
1723
1724	/**
1725	* Worker for nemR3NativeInit that loads the Hypervisor.framwork shared library.
1726	*
1727	* @returns VBox status code.
1728	* @param fForced Whether the HMForced flag is set and we should
1729	* fail if we cannot initialize.
1730	* @param pErrInfo Where to always return error info.
1731	*/
1732	static int nemR3DarwinLoadHv(bool fForced, PRTERRINFO pErrInfo)
1733	{
1734	RTLDRMOD hMod = NIL_RTLDRMOD;
1735	static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1736
1737	int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD \| RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1738	if (RT_SUCCESS(rc))
1739	{
1740	for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1741	{
1742	int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1743	if (RT_SUCCESS(rc2))
1744	{
1745	if (g_aImports[i].fOptional)
1746	LogRel(("NEM: info: Found optional import Hypervisor!%s.\n",
1747	g_aImports[i].pszName));
1748	}
1749	else
1750	{
1751	*g_aImports[i].ppfn = NULL;
1752
1753	LogRel(("NEM: %s: Failed to import Hypervisor!%s: %Rrc\n",
1754	g_aImports[i].fOptional ? "info" : fForced ? "fatal" : "error",
1755	g_aImports[i].pszName, rc2));
1756	if (!g_aImports[i].fOptional)
1757	{
1758	if (RTErrInfoIsSet(pErrInfo))
1759	RTErrInfoAddF(pErrInfo, rc2, ", Hypervisor!%s", g_aImports[i].pszName);
1760	else
1761	rc = RTErrInfoSetF(pErrInfo, rc2, "Failed to import: Hypervisor!%s", g_aImports[i].pszName);
1762	Assert(RT_FAILURE(rc));
1763	}
1764	}
1765	}
1766	if (RT_SUCCESS(rc))
1767	{
1768	Assert(!RTErrInfoIsSet(pErrInfo));
1769	}
1770
1771	RTLdrClose(hMod);
1772	}
1773	else
1774	{
1775	RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1776	rc = VERR_NEM_INIT_FAILED;
1777	}
1778
1779	return rc;
1780	}
1781
1782
1783	/**
1784	* Read and initialize the global capabilities supported by this CPU.
1785	*
1786	* @returns VBox status code.
1787	*/
1788	static int nemR3DarwinCapsInit(void)
1789	{
1790	RT_ZERO(g_HmMsrs);
1791
1792	hv_return_t hrc = hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &g_HmMsrs.u.vmx.PinCtls.u);
1793	if (hrc == HV_SUCCESS)
1794	hrc = hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &g_HmMsrs.u.vmx.ProcCtls.u);
1795	if (hrc == HV_SUCCESS)
1796	hrc = hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &g_HmMsrs.u.vmx.EntryCtls.u);
1797	if (hrc == HV_SUCCESS)
1798	hrc = hv_vmx_read_capability(HV_VMX_CAP_EXIT, &g_HmMsrs.u.vmx.ExitCtls.u);
1799	if (hrc == HV_SUCCESS)
1800	{
1801	hrc = hv_vmx_read_capability(HV_VMX_CAP_BASIC, &g_HmMsrs.u.vmx.u64Basic);
1802	if (hrc == HV_SUCCESS)
1803	{
1804	if (hrc == HV_SUCCESS)
1805	hrc = hv_vmx_read_capability(HV_VMX_CAP_MISC, &g_HmMsrs.u.vmx.u64Misc);
1806	if (hrc == HV_SUCCESS)
1807	hrc = hv_vmx_read_capability(HV_VMX_CAP_CR0_FIXED0, &g_HmMsrs.u.vmx.u64Cr0Fixed0);
1808	if (hrc == HV_SUCCESS)
1809	hrc = hv_vmx_read_capability(HV_VMX_CAP_CR0_FIXED1, &g_HmMsrs.u.vmx.u64Cr0Fixed1);
1810	if (hrc == HV_SUCCESS)
1811	hrc = hv_vmx_read_capability(HV_VMX_CAP_CR4_FIXED0, &g_HmMsrs.u.vmx.u64Cr4Fixed0);
1812	if (hrc == HV_SUCCESS)
1813	hrc = hv_vmx_read_capability(HV_VMX_CAP_CR4_FIXED1, &g_HmMsrs.u.vmx.u64Cr4Fixed1);
1814	if (hrc == HV_SUCCESS)
1815	hrc = hv_vmx_read_capability(HV_VMX_CAP_VMCS_ENUM, &g_HmMsrs.u.vmx.u64VmcsEnum);
1816	if ( hrc == HV_SUCCESS
1817	&& RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1818	{
1819	hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_PINBASED, &g_HmMsrs.u.vmx.TruePinCtls.u);
1820	if (hrc == HV_SUCCESS)
1821	hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_PROCBASED, &g_HmMsrs.u.vmx.TrueProcCtls.u);
1822	if (hrc == HV_SUCCESS)
1823	hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_ENTRY, &g_HmMsrs.u.vmx.TrueEntryCtls.u);
1824	if (hrc == HV_SUCCESS)
1825	hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_EXIT, &g_HmMsrs.u.vmx.TrueExitCtls.u);
1826	}
1827	}
1828	else
1829	{
1830	/* Likely running on anything < 11.0 (BigSur) so provide some sensible defaults. */
1831	g_HmMsrs.u.vmx.u64Cr0Fixed0 = 0x80000021;
1832	g_HmMsrs.u.vmx.u64Cr0Fixed1 = 0xffffffff;
1833	g_HmMsrs.u.vmx.u64Cr4Fixed0 = 0x2000;
1834	g_HmMsrs.u.vmx.u64Cr4Fixed1 = 0x1767ff;
1835	hrc = HV_SUCCESS;
1836	}
1837	}
1838
1839	if ( hrc == HV_SUCCESS
1840	&& g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1841	{
1842	hrc = hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &g_HmMsrs.u.vmx.ProcCtls2.u);
1843
1844	if ( hrc == HV_SUCCESS
1845	&& g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & (VMX_PROC_CTLS2_EPT \| VMX_PROC_CTLS2_VPID))
1846	{
1847	hrc = hv_vmx_read_capability(HV_VMX_CAP_EPT_VPID_CAP, &g_HmMsrs.u.vmx.u64EptVpidCaps);
1848	if (hrc != HV_SUCCESS)
1849	hrc = HV_SUCCESS; /* Probably just outdated OS. */
1850	}
1851
1852	g_HmMsrs.u.vmx.u64VmFunc = 0; /* No way to read that on macOS. */
1853	}
1854
1855	if (hrc == HV_SUCCESS)
1856	{
1857	/*
1858	* Check for EFER swapping support.
1859	*/
1860	g_fHmVmxSupportsVmcsEfer = true; //(g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1861	//&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1862	//&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1863	}
1864
1865	return nemR3DarwinHvSts2Rc(hrc);
1866	}
1867
1868
1869	/**
1870	* Sets up pin-based VM-execution controls in the VMCS.
1871	*
1872	* @returns VBox status code.
1873	* @param pVCpu The cross context virtual CPU structure.
1874	* @param pVmcsInfo The VMCS info. object.
1875	*/
1876	static int nemR3DarwinVmxSetupVmcsPinCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
1877	{
1878	//PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1879	uint32_t fVal = g_HmMsrs.u.vmx.PinCtls.n.allowed0; /* Bits set here must always be set. */
1880	uint32_t const fZap = g_HmMsrs.u.vmx.PinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
1881
1882	if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
1883	fVal \|= VMX_PIN_CTLS_VIRT_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
1884
1885	#if 0 /** @todo Use preemption timer */
1886	/* Enable the VMX-preemption timer. */
1887	if (pVM->hmr0.s.vmx.fUsePreemptTimer)
1888	{
1889	Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
1890	fVal \|= VMX_PIN_CTLS_PREEMPT_TIMER;
1891	}
1892
1893	/* Enable posted-interrupt processing. */
1894	if (pVM->hm.s.fPostedIntrs)
1895	{
1896	Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT);
1897	Assert(g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
1898	fVal \|= VMX_PIN_CTLS_POSTED_INT;
1899	}
1900	#endif
1901
1902	if ((fVal & fZap) != fVal)
1903	{
1904	LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
1905	g_HmMsrs.u.vmx.PinCtls.n.allowed0, fVal, fZap));
1906	pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
1907	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1908	}
1909
1910	/* Commit it to the VMCS and update our cache. */
1911	int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PIN_EXEC, fVal);
1912	AssertRC(rc);
1913	pVmcsInfo->u32PinCtls = fVal;
1914
1915	return VINF_SUCCESS;
1916	}
1917
1918
1919	/**
1920	* Sets up secondary processor-based VM-execution controls in the VMCS.
1921	*
1922	* @returns VBox status code.
1923	* @param pVCpu The cross context virtual CPU structure.
1924	* @param pVmcsInfo The VMCS info. object.
1925	*/
1926	static int nemR3DarwinVmxSetupVmcsProcCtls2(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
1927	{
1928	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
1929	uint32_t fVal = g_HmMsrs.u.vmx.ProcCtls2.n.allowed0; /* Bits set here must be set in the VMCS. */
1930	uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
1931
1932	/* WBINVD causes a VM-exit. */
1933	if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
1934	fVal \|= VMX_PROC_CTLS2_WBINVD_EXIT;
1935
1936	/* Enable the INVPCID instruction if we expose it to the guest and is supported
1937	by the hardware. Without this, guest executing INVPCID would cause a #UD. */
1938	if ( pVM->cpum.ro.GuestFeatures.fInvpcid
1939	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID))
1940	fVal \|= VMX_PROC_CTLS2_INVPCID;
1941
1942	#if 0 /** @todo */
1943	/* Enable VPID. */
1944	if (pVM->hmr0.s.vmx.fVpid)
1945	fVal \|= VMX_PROC_CTLS2_VPID;
1946
1947	if (pVM->hm.s.fVirtApicRegs)
1948	{
1949	/* Enable APIC-register virtualization. */
1950	Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
1951	fVal \|= VMX_PROC_CTLS2_APIC_REG_VIRT;
1952
1953	/* Enable virtual-interrupt delivery. */
1954	Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
1955	fVal \|= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
1956	}
1957
1958	/* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is
1959	where the TPR shadow resides. */
1960	/** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
1961	* done dynamically. */
1962	if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
1963	{
1964	fVal \|= VMX_PROC_CTLS2_VIRT_APIC_ACCESS;
1965	hmR0VmxSetupVmcsApicAccessAddr(pVCpu);
1966	}
1967	#endif
1968
1969	/* Enable the RDTSCP instruction if we expose it to the guest and is supported
1970	by the hardware. Without this, guest executing RDTSCP would cause a #UD. */
1971	if ( pVM->cpum.ro.GuestFeatures.fRdTscP
1972	&& (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP))
1973	fVal \|= VMX_PROC_CTLS2_RDTSCP;
1974
1975	#if 0
1976	/* Enable Pause-Loop exiting. */
1977	if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
1978	&& pVM->hm.s.vmx.cPleGapTicks
1979	&& pVM->hm.s.vmx.cPleWindowTicks)
1980	{
1981	fVal \|= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
1982
1983	int rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_GAP, pVM->hm.s.vmx.cPleGapTicks); AssertRC(rc);
1984	rc = VMXWriteVmcs32(VMX_VMCS32_CTRL_PLE_WINDOW, pVM->hm.s.vmx.cPleWindowTicks); AssertRC(rc);
1985	}
1986	#endif
1987
1988	if ((fVal & fZap) != fVal)
1989	{
1990	LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
1991	g_HmMsrs.u.vmx.ProcCtls2.n.allowed0, fVal, fZap));
1992	pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
1993	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
1994	}
1995
1996	/* Commit it to the VMCS and update our cache. */
1997	int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, fVal);
1998	AssertRC(rc);
1999	pVmcsInfo->u32ProcCtls2 = fVal;
2000
2001	return VINF_SUCCESS;
2002	}
2003
2004
2005	/**
2006	* Enables native access for the given MSR.
2007	*
2008	* @returns VBox status code.
2009	* @param pVCpu The cross context virtual CPU structure.
2010	* @param idMsr The MSR to enable native access for.
2011	*/
2012	static int nemR3DarwinMsrSetNative(PVMCPUCC pVCpu, uint32_t idMsr)
2013	{
2014	hv_return_t hrc = hv_vcpu_enable_native_msr(pVCpu->nem.s.hVCpuId, idMsr, true /enable/);
2015	if (hrc == HV_SUCCESS)
2016	return VINF_SUCCESS;
2017
2018	return nemR3DarwinHvSts2Rc(hrc);
2019	}
2020
2021
2022	/**
2023	* Sets up the MSR permissions which don't change through the lifetime of the VM.
2024	*
2025	* @returns VBox status code.
2026	* @param pVCpu The cross context virtual CPU structure.
2027	* @param pVmcsInfo The VMCS info. object.
2028	*/
2029	static int nemR3DarwinSetupVmcsMsrPermissions(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2030	{
2031	RT_NOREF(pVmcsInfo);
2032
2033	/*
2034	* The guest can access the following MSRs (read, write) without causing
2035	* VM-exits; they are loaded/stored automatically using fields in the VMCS.
2036	*/
2037	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2038	int rc;
2039	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SYSENTER_CS); AssertRCReturn(rc, rc);
2040	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SYSENTER_ESP); AssertRCReturn(rc, rc);
2041	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SYSENTER_EIP); AssertRCReturn(rc, rc);
2042	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_GS_BASE); AssertRCReturn(rc, rc);
2043	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_FS_BASE); AssertRCReturn(rc, rc);
2044
2045	/*
2046	* The IA32_PRED_CMD and IA32_FLUSH_CMD MSRs are write-only and has no state
2047	* associated with then. We never need to intercept access (writes need to be
2048	* executed without causing a VM-exit, reads will #GP fault anyway).
2049	*
2050	* The IA32_SPEC_CTRL MSR is read/write and has state. We allow the guest to
2051	* read/write them. We swap the guest/host MSR value using the
2052	* auto-load/store MSR area.
2053	*/
2054	if (pVM->cpum.ro.GuestFeatures.fIbpb)
2055	{
2056	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_PRED_CMD);
2057	AssertRCReturn(rc, rc);
2058	}
2059	#if 0 /* Doesn't work. */
2060	if (pVM->cpum.ro.GuestFeatures.fFlushCmd)
2061	{
2062	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_FLUSH_CMD);
2063	AssertRCReturn(rc, rc);
2064	}
2065	#endif
2066	if (pVM->cpum.ro.GuestFeatures.fIbrs)
2067	{
2068	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SPEC_CTRL);
2069	AssertRCReturn(rc, rc);
2070	}
2071
2072	/*
2073	* Allow full read/write access for the following MSRs (mandatory for VT-x)
2074	* required for 64-bit guests.
2075	*/
2076	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_LSTAR); AssertRCReturn(rc, rc);
2077	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K6_STAR); AssertRCReturn(rc, rc);
2078	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_SF_MASK); AssertRCReturn(rc, rc);
2079	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_KERNEL_GS_BASE); AssertRCReturn(rc, rc);
2080
2081	/* Required for enabling the RDTSCP instruction. */
2082	rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_TSC_AUX); AssertRCReturn(rc, rc);
2083
2084	return VINF_SUCCESS;
2085	}
2086
2087
2088	/**
2089	* Sets up processor-based VM-execution controls in the VMCS.
2090	*
2091	* @returns VBox status code.
2092	* @param pVCpu The cross context virtual CPU structure.
2093	* @param pVmcsInfo The VMCS info. object.
2094	*/
2095	static int nemR3DarwinVmxSetupVmcsProcCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2096	{
2097	PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2098	uint32_t fVal = g_HmMsrs.u.vmx.ProcCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
2099	uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2100
2101	fVal \|= VMX_PROC_CTLS_HLT_EXIT /* HLT causes a VM-exit. */
2102	// \| VMX_PROC_CTLS_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2103	\| VMX_PROC_CTLS_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2104	\| VMX_PROC_CTLS_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2105	\| VMX_PROC_CTLS_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2106	\| VMX_PROC_CTLS_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2107	\| VMX_PROC_CTLS_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2108
2109	/* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2110	if ( !(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
2111	\|\| (g_HmMsrs.u.vmx.ProcCtls.n.allowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
2112	{
2113	pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2114	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2115	}
2116
2117	/* Use TPR shadowing if supported by the CPU. */
2118	if ( PDMHasApic(pVM)
2119	&& (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
2120	{
2121	fVal \|= VMX_PROC_CTLS_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2122	/* CR8 writes cause a VM-exit based on TPR threshold. */
2123	Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
2124	Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
2125	}
2126	else
2127	{
2128	fVal \|= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2129	\| VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2130	}
2131
2132	/* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2133	if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2134	fVal \|= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
2135
2136	if ((fVal & fZap) != fVal)
2137	{
2138	LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2139	g_HmMsrs.u.vmx.ProcCtls.n.allowed0, fVal, fZap));
2140	pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2141	return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2142	}
2143
2144	/* Commit it to the VMCS and update our cache. */
2145	int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, fVal);
2146	AssertRC(rc);
2147	pVmcsInfo->u32ProcCtls = fVal;
2148
2149	/* Set up MSR permissions that don't change through the lifetime of the VM. */
2150	rc = nemR3DarwinSetupVmcsMsrPermissions(pVCpu, pVmcsInfo);
2151	AssertRCReturn(rc, rc);
2152
2153	/*
2154	* Set up secondary processor-based VM-execution controls
2155	* (we assume the CPU to always support it as we rely on unrestricted guest execution support).
2156	*/
2157	Assert(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2158	return nemR3DarwinVmxSetupVmcsProcCtls2(pVCpu, pVmcsInfo);
2159	}
2160
2161
2162	/**
2163	* Sets up miscellaneous (everything other than Pin, Processor and secondary
2164	* Processor-based VM-execution) control fields in the VMCS.
2165	*
2166	* @returns VBox status code.
2167	* @param pVCpu The cross context virtual CPU structure.
2168	* @param pVmcsInfo The VMCS info. object.
2169	*/
2170	static int nemR3DarwinVmxSetupVmcsMiscCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2171	{
2172	int rc = VINF_SUCCESS;
2173	//rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVmcsInfo); TODO
2174	if (RT_SUCCESS(rc))
2175	{
2176	uint64_t const u64Cr0Mask = vmxHCGetFixedCr0Mask(pVCpu);
2177	uint64_t const u64Cr4Mask = vmxHCGetFixedCr4Mask(pVCpu);
2178
2179	rc = nemR3DarwinWriteVmcs64(pVCpu, VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask); AssertRC(rc);
2180	rc = nemR3DarwinWriteVmcs64(pVCpu, VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask); AssertRC(rc);
2181
2182	pVmcsInfo->u64Cr0Mask = u64Cr0Mask;
2183	pVmcsInfo->u64Cr4Mask = u64Cr4Mask;
2184
2185	#if 0 /** @todo */
2186	if (pVCpu->CTX_SUFF(pVM)->hmr0.s.vmx.fLbr)
2187	{
2188	rc = VMXWriteVmcsNw(VMX_VMCS64_GUEST_DEBUGCTL_FULL, MSR_IA32_DEBUGCTL_LBR);
2189	AssertRC(rc);
2190	}
2191	#endif
2192	return VINF_SUCCESS;
2193	}
2194	else
2195	LogRelFunc(("Failed to initialize VMCS auto-load/store MSR addresses. rc=%Rrc\n", rc));
2196	return rc;
2197	}
2198
2199
2200	/**
2201	* Sets up the initial exception bitmap in the VMCS based on static conditions.
2202	*
2203	* We shall setup those exception intercepts that don't change during the
2204	* lifetime of the VM here. The rest are done dynamically while loading the
2205	* guest state.
2206	*
2207	* @param pVCpu The cross context virtual CPU structure.
2208	* @param pVmcsInfo The VMCS info. object.
2209	*/
2210	static void nemR3DarwinVmxSetupVmcsXcptBitmap(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2211	{
2212	/*
2213	* The following exceptions are always intercepted:
2214	*
2215	* #AC - To prevent the guest from hanging the CPU and for dealing with
2216	* split-lock detecting host configs.
2217	* #DB - To maintain the DR6 state even when intercepting DRx reads/writes and
2218	* recursive #DBs can cause a CPU hang.
2219	*/
2220	uint32_t const uXcptBitmap = RT_BIT(X86_XCPT_AC)
2221	\| RT_BIT(X86_XCPT_DB);
2222
2223	/* Commit it to the VMCS. */
2224	int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
2225	AssertRC(rc);
2226
2227	/* Update our cache of the exception bitmap. */
2228	pVmcsInfo->u32XcptBitmap = uXcptBitmap;
2229	}
2230
2231
2232	/**
2233	* Initialize the VMCS information field for the given vCPU.
2234	*
2235	* @returns VBox status code.
2236	* @param pVCpu The cross context virtual CPU structure of the
2237	* calling EMT.
2238	*/
2239	static int nemR3DarwinInitVmcs(PVMCPU pVCpu)
2240	{
2241	int rc = nemR3DarwinVmxSetupVmcsPinCtls(pVCpu, &pVCpu->nem.s.VmcsInfo);
2242	if (RT_SUCCESS(rc))
2243	{
2244	rc = nemR3DarwinVmxSetupVmcsProcCtls(pVCpu, &pVCpu->nem.s.VmcsInfo);
2245	if (RT_SUCCESS(rc))
2246	{
2247	rc = nemR3DarwinVmxSetupVmcsMiscCtls(pVCpu, &pVCpu->nem.s.VmcsInfo);
2248	if (RT_SUCCESS(rc))
2249	{
2250	rc = nemR3DarwinReadVmcs32(pVCpu, VMX_VMCS32_CTRL_ENTRY, &pVCpu->nem.s.VmcsInfo.u32EntryCtls);
2251	if (RT_SUCCESS(rc))
2252	{
2253	rc = nemR3DarwinReadVmcs32(pVCpu, VMX_VMCS32_CTRL_EXIT, &pVCpu->nem.s.VmcsInfo.u32ExitCtls);
2254	if (RT_SUCCESS(rc))
2255	{
2256	nemR3DarwinVmxSetupVmcsXcptBitmap(pVCpu, &pVCpu->nem.s.VmcsInfo);
2257	return VINF_SUCCESS;
2258	}
2259	else
2260	LogRelFunc(("Failed to read the exit controls. rc=%Rrc\n", rc));
2261	}
2262	else
2263	LogRelFunc(("Failed to read the entry controls. rc=%Rrc\n", rc));
2264	}
2265	else
2266	LogRelFunc(("Failed to setup miscellaneous controls. rc=%Rrc\n", rc));
2267	}
2268	else
2269	LogRelFunc(("Failed to setup processor-based VM-execution controls. rc=%Rrc\n", rc));
2270	}
2271	else
2272	LogRelFunc(("Failed to setup pin-based controls. rc=%Rrc\n", rc));
2273
2274	return rc;
2275	}
2276
2277
2278	/**
2279	* Try initialize the native API.
2280	*
2281	* This may only do part of the job, more can be done in
2282	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
2283	*
2284	* @returns VBox status code.
2285	* @param pVM The cross context VM structure.
2286	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
2287	* the latter we'll fail if we cannot initialize.
2288	* @param fForced Whether the HMForced flag is set and we should
2289	* fail if we cannot initialize.
2290	*/
2291	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
2292	{
2293	AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
2294
2295	/*
2296	* Some state init.
2297	*/
2298
2299	/*
2300	* Error state.
2301	* The error message will be non-empty on failure and 'rc' will be set too.
2302	*/
2303	RTERRINFOSTATIC ErrInfo;
2304	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
2305	int rc = nemR3DarwinLoadHv(fForced, pErrInfo);
2306	if (RT_SUCCESS(rc))
2307	{
2308	hv_return_t hrc = hv_vm_create(HV_VM_DEFAULT);
2309	if (hrc == HV_SUCCESS)
2310	{
2311	if (hv_vm_space_create)
2312	{
2313	hrc = hv_vm_space_create(&pVM->nem.s.uVmAsid);
2314	if (hrc == HV_SUCCESS)
2315	{
2316	LogRel(("NEM: Successfully created ASID: %u\n", pVM->nem.s.uVmAsid));
2317	pVM->nem.s.fCreatedAsid = true;
2318	}
2319	else
2320	LogRel(("NEM: Failed to create ASID for VM (hrc=%#x), continuing...\n", pVM->nem.s.uVmAsid));
2321	}
2322	pVM->nem.s.fCreatedVm = true;
2323
2324	/* Register release statistics */
2325	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2326	{
2327	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
2328	PVMXSTATISTICS pVmxStats = (PVMXSTATISTICS)RTMemAllocZ(sizeof(*pVmxStats));
2329	if (RT_LIKELY(pVmxStats))
2330	pNemCpu->pVmxStats = pVmxStats;
2331	else
2332	{
2333	rc = VERR_NO_MEMORY;
2334	break;
2335	}
2336	}
2337
2338	if (RT_SUCCESS(rc))
2339	{
2340	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
2341	Log(("NEM: Marked active!\n"));
2342	PGMR3EnableNemMode(pVM);
2343	}
2344	}
2345	else
2346	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
2347	"hv_vm_create() failed: %#x", hrc);
2348	}
2349
2350	/*
2351	* We only fail if in forced mode, otherwise just log the complaint and return.
2352	*/
2353	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API \|\| RTErrInfoIsSet(pErrInfo));
2354	if ( (fForced \|\| !fFallback)
2355	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
2356	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
2357
2358	if (RTErrInfoIsSet(pErrInfo))
2359	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
2360	return VINF_SUCCESS;
2361	}
2362
2363
2364	/**
2365	* Worker to create the vCPU handle on the EMT running it later on (as required by HV).
2366	*
2367	* @returns VBox status code
2368	* @param pVM The VM handle.
2369	* @param pVCpu The vCPU handle.
2370	* @param idCpu ID of the CPU to create.
2371	*/
2372	static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
2373	{
2374	hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpuId, HV_VCPU_DEFAULT);
2375	if (hrc != HV_SUCCESS)
2376	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
2377	"Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2378
2379	if (idCpu == 0)
2380	{
2381	/* First call initializs the MSR structure holding the capabilities of the host CPU. */
2382	int rc = nemR3DarwinCapsInit();
2383	AssertRCReturn(rc, rc);
2384	}
2385
2386	int rc = nemR3DarwinInitVmcs(pVCpu);
2387	AssertRCReturn(rc, rc);
2388
2389	if (pVM->nem.s.fCreatedAsid)
2390	{
2391	hv_return_t hrc = hv_vcpu_set_space(pVCpu->nem.s.hVCpuId, pVM->nem.s.uVmAsid);
2392	AssertReturn(hrc == HV_SUCCESS, VERR_NEM_VM_CREATE_FAILED);
2393	}
2394
2395	ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
2396
2397	return VINF_SUCCESS;
2398	}
2399
2400
2401	/**
2402	* Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
2403	*
2404	* @returns VBox status code
2405	* @param pVCpu The vCPU handle.
2406	*/
2407	static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVMCPU pVCpu)
2408	{
2409	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpuId);
2410	Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
2411	return VINF_SUCCESS;
2412	}
2413
2414
2415	/**
2416	* This is called after CPUMR3Init is done.
2417	*
2418	* @returns VBox status code.
2419	* @param pVM The VM handle..
2420	*/
2421	int nemR3NativeInitAfterCPUM(PVM pVM)
2422	{
2423	/*
2424	* Validate sanity.
2425	*/
2426	AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
2427	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
2428
2429	/*
2430	* Setup the EMTs.
2431	*/
2432	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2433	{
2434	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2435
2436	int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
2437	if (RT_FAILURE(rc))
2438	{
2439	/* Rollback. */
2440	while (idCpu--)
2441	VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 1, pVCpu);
2442
2443	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
2444	}
2445	}
2446
2447	pVM->nem.s.fCreatedEmts = true;
2448	return VINF_SUCCESS;
2449	}
2450
2451
2452	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2453	{
2454	NOREF(pVM); NOREF(enmWhat);
2455	return VINF_SUCCESS;
2456	}
2457
2458
2459	int nemR3NativeTerm(PVM pVM)
2460	{
2461	/*
2462	* Delete the VM.
2463	*/
2464
2465	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
2466	{
2467	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2468
2469	/*
2470	* Apple's documentation states that the vCPU should be destroyed
2471	* on the thread running the vCPU but as all the other EMTs are gone
2472	* at this point, destroying the VM would hang.
2473	*
2474	* We seem to be at luck here though as destroying apparently works
2475	* from EMT(0) as well.
2476	*/
2477	hv_return_t hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpuId);
2478	Assert(hrc == HV_SUCCESS);
2479
2480	if (pVCpu->nem.s.pVmxStats)
2481	{
2482	RTMemFree(pVCpu->nem.s.pVmxStats);
2483	pVCpu->nem.s.pVmxStats = NULL;
2484	}
2485	}
2486
2487	pVM->nem.s.fCreatedEmts = false;
2488
2489	if (pVM->nem.s.fCreatedAsid)
2490	{
2491	hv_return_t hrc = hv_vm_space_destroy(pVM->nem.s.uVmAsid);
2492	Assert(hrc == HV_SUCCESS);
2493	pVM->nem.s.fCreatedAsid = false;
2494	}
2495
2496	if (pVM->nem.s.fCreatedVm)
2497	{
2498	hv_return_t hrc = hv_vm_destroy();
2499	if (hrc != HV_SUCCESS)
2500	LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
2501
2502	pVM->nem.s.fCreatedVm = false;
2503	}
2504	return VINF_SUCCESS;
2505	}
2506
2507
2508	/**
2509	* VM reset notification.
2510	*
2511	* @param pVM The cross context VM structure.
2512	*/
2513	void nemR3NativeReset(PVM pVM)
2514	{
2515	RT_NOREF(pVM);
2516	}
2517
2518
2519	/**
2520	* Reset CPU due to INIT IPI or hot (un)plugging.
2521	*
2522	* @param pVCpu The cross context virtual CPU structure of the CPU being
2523	* reset.
2524	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
2525	*/
2526	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
2527	{
2528	RT_NOREF(fInitIpi);
2529	ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
2530	}
2531
2532
2533	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2534	{
2535	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags));
2536	#ifdef LOG_ENABLED
2537	if (LogIs3Enabled())
2538	nemR3DarwinLogState(pVM, pVCpu);
2539	#endif
2540
2541	/*
2542	* Try switch to NEM runloop state.
2543	*/
2544	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2545	{ /* likely */ }
2546	else
2547	{
2548	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2549	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2550	return VINF_SUCCESS;
2551	}
2552
2553	/*
2554	* The run loop.
2555	*
2556	* Current approach to state updating to use the sledgehammer and sync
2557	* everything every time. This will be optimized later.
2558	*/
2559
2560	VMXTRANSIENT VmxTransient;
2561	RT_ZERO(VmxTransient);
2562	VmxTransient.pVmcsInfo = &pVCpu->nem.s.VmcsInfo;
2563
2564	const bool fSingleStepping = DBGFIsStepping(pVCpu);
2565	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2566	for (unsigned iLoop = 0;; iLoop++)
2567	{
2568	/*
2569	* Check and process force flag actions, some of which might require us to go back to ring-3.
2570	*/
2571	rcStrict = vmxHCCheckForceFlags(pVCpu, false /fIsNestedGuest/, fSingleStepping);
2572	if (rcStrict == VINF_SUCCESS)
2573	{ /likely / }
2574	else
2575	break;
2576
2577	/*
2578	* Evaluate events to be injected into the guest.
2579	*
2580	* Events in TRPM can be injected without inspecting the guest state.
2581	* If any new events (interrupts/NMI) are pending currently, we try to set up the
2582	* guest to cause a VM-exit the next time they are ready to receive the event.
2583	*/
2584	if (TRPMHasTrap(pVCpu))
2585	vmxHCTrpmTrapToPendingEvent(pVCpu);
2586
2587	uint32_t fIntrState;
2588	rcStrict = vmxHCEvaluatePendingEvent(pVCpu, &pVCpu->nem.s.VmcsInfo, false /fIsNestedGuest/, &fIntrState);
2589
2590	/*
2591	* Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
2592	* needs to be done with longjmps or interrupts + preemption enabled. Event injection might
2593	* also result in triple-faulting the VM.
2594	*
2595	* With nested-guests, the above does not apply since unrestricted guest execution is a
2596	* requirement. Regardless, we do this here to avoid duplicating code elsewhere.
2597	*/
2598	rcStrict = vmxHCInjectPendingEvent(pVCpu, &pVCpu->nem.s.VmcsInfo, false /fIsNestedGuest/, fIntrState, fSingleStepping);
2599	if (RT_LIKELY(rcStrict == VINF_SUCCESS))
2600	{ /* likely */ }
2601	else
2602	{
2603	AssertMsg(rcStrict == VINF_EM_RESET \|\| (rcStrict == VINF_EM_DBG_STEPPED && fSingleStepping),
2604	("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
2605	break;
2606	}
2607
2608	int rc = nemR3DarwinExportGuestState(pVM, pVCpu, &VmxTransient);
2609	AssertRCReturn(rc, rc);
2610
2611	/*
2612	* Poll timers and run for a bit.
2613	*/
2614	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2615	* the whole polling job when timers have changed... */
2616	uint64_t offDeltaIgnored;
2617	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2618	if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2619	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2620	{
2621	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2622	{
2623	LogFlowFunc(("Running vCPU\n"));
2624	pVCpu->nem.s.Event.fPending = false;
2625
2626	hv_return_t hrc;
2627	if (hv_vcpu_run_until)
2628	hrc = hv_vcpu_run_until(pVCpu->nem.s.hVCpuId, HV_DEADLINE_FOREVER);
2629	else
2630	hrc = hv_vcpu_run(pVCpu->nem.s.hVCpuId);
2631
2632	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2633	if (hrc == HV_SUCCESS)
2634	{
2635	/*
2636	* Deal with the message.
2637	*/
2638	rcStrict = nemR3DarwinHandleExit(pVM, pVCpu, &VmxTransient);
2639	if (rcStrict == VINF_SUCCESS)
2640	{ /* hopefully likely */ }
2641	else
2642	{
2643	LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2644	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2645	break;
2646	}
2647	}
2648	else
2649	{
2650	AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x %u\n",
2651	pVCpu->idCpu, hrc, vmxHCCheckGuestState(pVCpu, &pVCpu->nem.s.VmcsInfo)),
2652	VERR_NEM_IPE_0);
2653	}
2654
2655	/*
2656	* If no relevant FFs are pending, loop.
2657	*/
2658	if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2659	&& !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2660	continue;
2661
2662	/** @todo Try handle pending flags, not just return to EM loops. Take care
2663	* not to set important RCs here unless we've handled a message. */
2664	LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2665	pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2666	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2667	}
2668	else
2669	{
2670	LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2671	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2672	}
2673	}
2674	else
2675	{
2676	LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2677	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2678	}
2679	break;
2680	} /* the run loop */
2681
2682
2683	/*
2684	* Convert any pending HM events back to TRPM due to premature exits.
2685	*
2686	* This is because execution may continue from IEM and we would need to inject
2687	* the event from there (hence place it back in TRPM).
2688	*/
2689	if (pVCpu->nem.s.Event.fPending)
2690	{
2691	vmxHCPendingEventToTrpmTrap(pVCpu);
2692	Assert(!pVCpu->nem.s.Event.fPending);
2693
2694	/* Clear the events from the VMCS. */
2695	int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);
2696	rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0); AssertRC(rc);
2697	}
2698
2699
2700	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2701	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2702
2703	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
2704	{
2705	/* Try anticipate what we might need. */
2706	uint64_t fImport = IEM_CPUMCTX_EXTRN_MUST_MASK;
2707	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2708	\|\| RT_FAILURE(rcStrict))
2709	fImport = CPUMCTX_EXTRN_ALL;
2710	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_INTERRUPT_APIC
2711	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2712	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2713
2714	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2715	{
2716	/* Only import what is external currently. */
2717	int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
2718	if (RT_SUCCESS(rc2))
2719	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2720	else if (RT_SUCCESS(rcStrict))
2721	rcStrict = rc2;
2722	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2723	{
2724	pVCpu->cpum.GstCtx.fExtrn = 0;
2725	ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
2726	}
2727	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2728	}
2729	else
2730	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2731	}
2732	else
2733	{
2734	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2735	pVCpu->cpum.GstCtx.fExtrn = 0;
2736	ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
2737	}
2738
2739	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n",
2740	pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2741	return rcStrict;
2742	}
2743
2744
2745	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
2746	{
2747	NOREF(pVM);
2748	return PGMPhysIsA20Enabled(pVCpu);
2749	}
2750
2751
2752	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
2753	{
2754	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
2755	return false;
2756	}
2757
2758
2759	/**
2760	* Forced flag notification call from VMEmt.h.
2761	*
2762	* This is only called when pVCpu is in the VMCPUSTATE_STARTED_EXEC_NEM state.
2763	*
2764	* @param pVM The cross context VM structure.
2765	* @param pVCpu The cross context virtual CPU structure of the CPU
2766	* to be notified.
2767	* @param fFlags Notification flags, VMNOTIFYFF_FLAGS_XXX.
2768	*/
2769	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
2770	{
2771	LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
2772
2773	hv_return_t hrc = hv_vcpu_interrupt(&pVCpu->nem.s.hVCpuId, 1);
2774	if (hrc != HV_SUCCESS)
2775	LogRel(("NEM: hv_vcpu_interrupt(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpuId, hrc));
2776	}
2777
2778
2779	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
2780	uint8_t pu2State, uint32_t puNemRange)
2781	{
2782	RT_NOREF(pVM, puNemRange);
2783
2784	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
2785	#if defined(VBOX_WITH_PGM_NEM_MODE)
2786	if (pvR3)
2787	{
2788	int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE);
2789	if (RT_SUCCESS(rc))
2790	*pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
2791	else
2792	{
2793	LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
2794	return VERR_NEM_MAP_PAGES_FAILED;
2795	}
2796	}
2797	return VINF_SUCCESS;
2798	#else
2799	RT_NOREF(pVM, GCPhys, cb, pvR3);
2800	return VERR_NEM_MAP_PAGES_FAILED;
2801	#endif
2802	}
2803
2804
2805	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
2806	{
2807	RT_NOREF(pVM);
2808	return false;
2809	}
2810
2811
2812	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2813	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
2814	{
2815	RT_NOREF(pVM, puNemRange);
2816
2817	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
2818	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
2819
2820	#if defined(VBOX_WITH_PGM_NEM_MODE)
2821	/*
2822	* Unmap the RAM we're replacing.
2823	*/
2824	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2825	{
2826	int rc = nemR3DarwinUnmap(pVM, GCPhys, cb);
2827	if (RT_SUCCESS(rc))
2828	{ /* likely */ }
2829	else if (pvMmio2)
2830	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
2831	GCPhys, cb, fFlags, rc));
2832	else
2833	{
2834	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2835	GCPhys, cb, fFlags, rc));
2836	return VERR_NEM_UNMAP_PAGES_FAILED;
2837	}
2838	}
2839
2840	/*
2841	* Map MMIO2 if any.
2842	*/
2843	if (pvMmio2)
2844	{
2845	Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
2846	int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE);
2847	if (RT_SUCCESS(rc))
2848	*pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
2849	else
2850	{
2851	LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
2852	GCPhys, cb, fFlags, pvMmio2, rc));
2853	return VERR_NEM_MAP_PAGES_FAILED;
2854	}
2855	}
2856	else
2857	{
2858	Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
2859	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
2860	}
2861
2862	#else
2863	RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
2864	*pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
2865	#endif
2866	return VINF_SUCCESS;
2867	}
2868
2869
2870	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
2871	void pvRam, void pvMmio2, uint32_t *puNemRange)
2872	{
2873	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
2874	return VINF_SUCCESS;
2875	}
2876
2877
2878	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
2879	void pvMmio2, uint8_t pu2State)
2880	{
2881	RT_NOREF(pVM);
2882
2883	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p\n",
2884	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State));
2885
2886	int rc = VINF_SUCCESS;
2887	#if defined(VBOX_WITH_PGM_NEM_MODE)
2888	/*
2889	* Unmap the MMIO2 pages.
2890	*/
2891	/** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
2892	* we may have more stuff to unmap even in case of pure MMIO... */
2893	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
2894	{
2895	rc = nemR3DarwinUnmap(pVM, GCPhys, cb);
2896	if (RT_FAILURE(rc))
2897	{
2898	LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
2899	GCPhys, cb, fFlags, rc));
2900	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2901	}
2902	}
2903
2904	/*
2905	* Restore the RAM we replaced.
2906	*/
2907	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
2908	{
2909	AssertPtr(pvRam);
2910	rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE);
2911	if (RT_SUCCESS(rc))
2912	{ /* likely */ }
2913	else
2914	{
2915	LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
2916	rc = VERR_NEM_MAP_PAGES_FAILED;
2917	}
2918	if (pu2State)
2919	*pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
2920	}
2921	/* Mark the pages as unmapped if relevant. */
2922	else if (pu2State)
2923	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
2924
2925	RT_NOREF(pvMmio2);
2926	#else
2927	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
2928	if (pu2State)
2929	*pu2State = UINT8_MAX;
2930	rc = VERR_NEM_UNMAP_PAGES_FAILED;
2931	#endif
2932	return rc;
2933	}
2934
2935
2936	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
2937	void *pvBitmap, size_t cbBitmap)
2938	{
2939	RT_NOREF(pVM, GCPhys, cb, uNemRange, pvBitmap, cbBitmap);
2940	AssertFailed();
2941	return VERR_NOT_IMPLEMENTED;
2942	}
2943
2944
2945	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
2946	uint8_t *pu2State)
2947	{
2948	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags);
2949
2950	Log5(("nemR3NativeNotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
2951	*pu2State = UINT8_MAX;
2952	return VINF_SUCCESS;
2953	}
2954
2955
2956	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
2957	uint32_t fFlags, uint8_t *pu2State)
2958	{
2959	Log5(("nemR3NativeNotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p\n",
2960	GCPhys, cb, pvPages, fFlags, pu2State));
2961	*pu2State = UINT8_MAX;
2962
2963	#if defined(VBOX_WITH_PGM_NEM_MODE)
2964	/*
2965	* (Re-)map readonly.
2966	*/
2967	AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
2968	int rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_EXECUTE);
2969	if (RT_SUCCESS(rc))
2970	*pu2State = NEM_DARWIN_PAGE_STATE_READABLE;
2971	else
2972	{
2973	LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
2974	GCPhys, cb, pvPages, fFlags, rc));
2975	return VERR_NEM_MAP_PAGES_FAILED;
2976	}
2977	RT_NOREF(pVM, fFlags);
2978	return VINF_SUCCESS;
2979	#else
2980	RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags);
2981	return VERR_NEM_MAP_PAGES_FAILED;
2982	#endif
2983	}
2984
2985
2986	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
2987	RTR3PTR pvMemR3, uint8_t *pu2State)
2988	{
2989	RT_NOREF(pVM);
2990
2991	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
2992	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
2993
2994	*pu2State = UINT8_MAX;
2995	#if defined(VBOX_WITH_PGM_NEM_MODE)
2996	if (pvMemR3)
2997	{
2998	int rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ \| NEM_PAGE_PROT_WRITE \| NEM_PAGE_PROT_EXECUTE);
2999	if (RT_SUCCESS(rc))
3000	*pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
3001	else
3002	AssertLogRelMsgFailed(("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
3003	pvMemR3, GCPhys, cb, rc));
3004	}
3005	RT_NOREF(enmKind);
3006	#else
3007	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
3008	AssertFailed();
3009	#endif
3010	}
3011
3012
3013	static int nemHCJustUnmapPage(PVMCC pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
3014	{
3015	if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
3016	{
3017	Log5(("nemHCJustUnmapPage: %RGp == unmapped\n", GCPhysDst));
3018	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
3019	return VINF_SUCCESS;
3020	}
3021
3022	int rc = nemR3DarwinUnmap(pVM, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
3023	if (RT_SUCCESS(rc))
3024	{
3025	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
3026	*pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
3027	Log5(("nemHCJustUnmapPage: %RGp => unmapped\n", GCPhysDst));
3028	return VINF_SUCCESS;
3029	}
3030	STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
3031	LogRel(("nemHCJustUnmapPage(%RGp): failed! rc=%Rrc\n",
3032	GCPhysDst, rc));
3033	return VERR_NEM_IPE_6;
3034	}
3035
3036
3037	/**
3038	* Called when the A20 state changes.
3039	*
3040	* @param pVCpu The CPU the A20 state changed on.
3041	* @param fEnabled Whether it was enabled (true) or disabled.
3042	*/
3043	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
3044	{
3045	Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
3046	RT_NOREF(pVCpu, fEnabled);
3047	}
3048
3049
3050	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
3051	{
3052	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
3053	NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
3054	}
3055
3056
3057	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
3058	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
3059	{
3060	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
3061	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
3062	NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
3063	}
3064
3065
3066	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
3067	PGMPAGETYPE enmType, uint8_t *pu2State)
3068	{
3069	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3070	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3071	RT_NOREF_PV(HCPhys); RT_NOREF_PV(enmType);
3072
3073	return nemHCJustUnmapPage(pVM, GCPhys, pu2State);
3074	}
3075
3076
3077	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
3078	PGMPAGETYPE enmType, uint8_t *pu2State)
3079	{
3080	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3081	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3082	RT_NOREF(HCPhys, pvR3, fPageProt, enmType)
3083
3084	nemHCJustUnmapPage(pVM, GCPhys, pu2State);
3085	}
3086
3087
3088	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
3089	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
3090	{
3091	Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3092	GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
3093	RT_NOREF(HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType);
3094
3095	nemHCJustUnmapPage(pVM, GCPhys, pu2State);
3096	}
3097
3098
3099	/**
3100	* Interface for importing state on demand (used by IEM).
3101	*
3102	* @returns VBox status code.
3103	* @param pVCpu The cross context CPU structure.
3104	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
3105	*/
3106	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
3107	{
3108	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
3109
3110	return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
3111	}
3112
3113
3114	/**
3115	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
3116	*
3117	* @returns VBox status code.
3118	* @param pVCpu The cross context CPU structure.
3119	* @param pcTicks Where to return the CPU tick count.
3120	* @param puAux Where to return the TSC_AUX register value.
3121	*/
3122	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
3123	{
3124	LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
3125	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
3126
3127	int rc = nemR3DarwinMsrRead(pVCpu, MSR_IA32_TSC, pcTicks);
3128	if ( RT_SUCCESS(rc)
3129	&& puAux)
3130	{
3131	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_TSC_AUX)
3132	{
3133	/** @todo Why the heck is puAux a uint32_t?. */
3134	uint64_t u64Aux;
3135	rc = nemR3DarwinMsrRead(pVCpu, MSR_K8_TSC_AUX, &u64Aux);
3136	if (RT_SUCCESS(rc))
3137	*puAux = (uint32_t)u64Aux;
3138	}
3139	else
3140	*puAux = CPUMGetGuestTscAux(pVCpu);
3141	}
3142
3143	return rc;
3144	}
3145
3146
3147	/**
3148	* Resumes CPU clock (TSC) on all virtual CPUs.
3149	*
3150	* This is called by TM when the VM is started, restored, resumed or similar.
3151	*
3152	* @returns VBox status code.
3153	* @param pVM The cross context VM structure.
3154	* @param pVCpu The cross context CPU structure of the calling EMT.
3155	* @param uPausedTscValue The TSC value at the time of pausing.
3156	*/
3157	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
3158	{
3159	LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVCpu, uPausedTscValue));
3160	VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
3161	AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
3162
3163	hv_return_t hrc = hv_vm_sync_tsc(uPausedTscValue);
3164	if (RT_LIKELY(hrc == HV_SUCCESS))
3165	return VINF_SUCCESS;
3166
3167	return nemR3DarwinHvSts2Rc(hrc);
3168	}
3169
3170
3171	/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
3172	*
3173	* @todo Add notes as the implementation progresses...
3174	*/
3175

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin.cpp@ 92424

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