VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin.cpp@ 93725

Last change on this file since 93725 was 93723, checked in by vboxsync, 3 years ago

VMM/NEMR3Native-darwin: Fix clearing context changed flag for TSC AUX which caused an debug assertion, bugref:9044
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1/* $Id: NEMR3Native-darwin.cpp 93723 2022-02-14 13:13:54Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, native ring-3 macOS backend using Hypervisor.framework.
4 *
5 * Log group 2: Exit logging.
6 * Log group 3: Log context on exit.
7 * Log group 5: Ring-3 memory management
8 */
9
10/*
11 * Copyright (C) 2020-2022 Oracle Corporation
12 *
13 * This file is part of VirtualBox Open Source Edition (OSE), as
14 * available from http://www.virtualbox.org. This file is free software;
15 * you can redistribute it and/or modify it under the terms of the GNU
16 * General Public License (GPL) as published by the Free Software
17 * Foundation, in version 2 as it comes in the "COPYING" file of the
18 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
19 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
20 */
21
22
23/*********************************************************************************************************************************
24* Header Files *
25*********************************************************************************************************************************/
26#define LOG_GROUP LOG_GROUP_NEM
27#define VMCPU_INCL_CPUM_GST_CTX
28#include <VBox/vmm/nem.h>
29#include <VBox/vmm/iem.h>
30#include <VBox/vmm/em.h>
31#include <VBox/vmm/apic.h>
32#include <VBox/vmm/pdm.h>
33#include <VBox/vmm/hm.h>
34#include <VBox/vmm/hm_vmx.h>
35#include <VBox/vmm/dbgftrace.h>
36#include "VMXInternal.h"
37#include "NEMInternal.h"
38#include <VBox/vmm/vmcc.h>
39#include "dtrace/VBoxVMM.h"
40
41#include <iprt/asm.h>
42#include <iprt/ldr.h>
43#include <iprt/mem.h>
44#include <iprt/path.h>
45#include <iprt/string.h>
46#include <iprt/system.h>
47#include <iprt/utf16.h>
48
49#include <mach/mach_time.h>
50#include <mach/kern_return.h>
51
52
53/*********************************************************************************************************************************
54* Defined Constants And Macros *
55*********************************************************************************************************************************/
56/* No nested hwvirt (for now). */
57#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
58# undef VBOX_WITH_NESTED_HWVIRT_VMX
59#endif
60
61
62/** @name HV return codes.
63 * @{ */
64/** Operation was successful. */
65#define HV_SUCCESS 0
66/** An error occurred during operation. */
67#define HV_ERROR 0xfae94001
68/** The operation could not be completed right now, try again. */
69#define HV_BUSY 0xfae94002
70/** One of the parameters passed wis invalid. */
71#define HV_BAD_ARGUMENT 0xfae94003
72/** Not enough resources left to fulfill the operation. */
73#define HV_NO_RESOURCES 0xfae94005
74/** The device could not be found. */
75#define HV_NO_DEVICE 0xfae94006
76/** The operation is not supportd on this platform with this configuration. */
77#define HV_UNSUPPORTED 0xfae94007
78/** @} */
79
80
81/** @name HV memory protection flags.
82 * @{ */
83/** Memory is readable. */
84#define HV_MEMORY_READ RT_BIT_64(0)
85/** Memory is writeable. */
86#define HV_MEMORY_WRITE RT_BIT_64(1)
87/** Memory is executable. */
88#define HV_MEMORY_EXEC RT_BIT_64(2)
89/** @} */
90
91
92/** @name HV shadow VMCS protection flags.
93 * @{ */
94/** Shadow VMCS field is not accessible. */
95#define HV_SHADOW_VMCS_NONE 0
96/** Shadow VMCS fild is readable. */
97#define HV_SHADOW_VMCS_READ RT_BIT_64(0)
98/** Shadow VMCS field is writeable. */
99#define HV_SHADOW_VMCS_WRITE RT_BIT_64(1)
100/** @} */
101
102
103/** Default VM creation flags. */
104#define HV_VM_DEFAULT 0
105/** Default guest address space creation flags. */
106#define HV_VM_SPACE_DEFAULT 0
107/** Default vCPU creation flags. */
108#define HV_VCPU_DEFAULT 0
109
110#define HV_DEADLINE_FOREVER UINT64_MAX
111
112
113/*********************************************************************************************************************************
114* Structures and Typedefs *
115*********************************************************************************************************************************/
116
117/** HV return code type. */
118typedef uint32_t hv_return_t;
119/** HV capability bitmask. */
120typedef uint64_t hv_capability_t;
121/** Option bitmask type when creating a VM. */
122typedef uint64_t hv_vm_options_t;
123/** Option bitmask when creating a vCPU. */
124typedef uint64_t hv_vcpu_options_t;
125/** HV memory protection flags type. */
126typedef uint64_t hv_memory_flags_t;
127/** Shadow VMCS protection flags. */
128typedef uint64_t hv_shadow_flags_t;
129/** Guest physical address type. */
130typedef uint64_t hv_gpaddr_t;
131
132
133/**
134 * VMX Capability enumeration.
135 */
136typedef enum
137{
138 HV_VMX_CAP_PINBASED = 0,
139 HV_VMX_CAP_PROCBASED,
140 HV_VMX_CAP_PROCBASED2,
141 HV_VMX_CAP_ENTRY,
142 HV_VMX_CAP_EXIT,
143 HV_VMX_CAP_BASIC, /* Since 11.0 */
144 HV_VMX_CAP_TRUE_PINBASED, /* Since 11.0 */
145 HV_VMX_CAP_TRUE_PROCBASED, /* Since 11.0 */
146 HV_VMX_CAP_TRUE_ENTRY, /* Since 11.0 */
147 HV_VMX_CAP_TRUE_EXIT, /* Since 11.0 */
148 HV_VMX_CAP_MISC, /* Since 11.0 */
149 HV_VMX_CAP_CR0_FIXED0, /* Since 11.0 */
150 HV_VMX_CAP_CR0_FIXED1, /* Since 11.0 */
151 HV_VMX_CAP_CR4_FIXED0, /* Since 11.0 */
152 HV_VMX_CAP_CR4_FIXED1, /* Since 11.0 */
153 HV_VMX_CAP_VMCS_ENUM, /* Since 11.0 */
154 HV_VMX_CAP_EPT_VPID_CAP, /* Since 11.0 */
155 HV_VMX_CAP_PREEMPTION_TIMER = 32
156} hv_vmx_capability_t;
157
158
159/**
160 * HV x86 register enumeration.
161 */
162typedef enum
163{
164 HV_X86_RIP = 0,
165 HV_X86_RFLAGS,
166 HV_X86_RAX,
167 HV_X86_RCX,
168 HV_X86_RDX,
169 HV_X86_RBX,
170 HV_X86_RSI,
171 HV_X86_RDI,
172 HV_X86_RSP,
173 HV_X86_RBP,
174 HV_X86_R8,
175 HV_X86_R9,
176 HV_X86_R10,
177 HV_X86_R11,
178 HV_X86_R12,
179 HV_X86_R13,
180 HV_X86_R14,
181 HV_X86_R15,
182 HV_X86_CS,
183 HV_X86_SS,
184 HV_X86_DS,
185 HV_X86_ES,
186 HV_X86_FS,
187 HV_X86_GS,
188 HV_X86_IDT_BASE,
189 HV_X86_IDT_LIMIT,
190 HV_X86_GDT_BASE,
191 HV_X86_GDT_LIMIT,
192 HV_X86_LDTR,
193 HV_X86_LDT_BASE,
194 HV_X86_LDT_LIMIT,
195 HV_X86_LDT_AR,
196 HV_X86_TR,
197 HV_X86_TSS_BASE,
198 HV_X86_TSS_LIMIT,
199 HV_X86_TSS_AR,
200 HV_X86_CR0,
201 HV_X86_CR1,
202 HV_X86_CR2,
203 HV_X86_CR3,
204 HV_X86_CR4,
205 HV_X86_DR0,
206 HV_X86_DR1,
207 HV_X86_DR2,
208 HV_X86_DR3,
209 HV_X86_DR4,
210 HV_X86_DR5,
211 HV_X86_DR6,
212 HV_X86_DR7,
213 HV_X86_TPR,
214 HV_X86_XCR0,
215 HV_X86_REGISTERS_MAX
216} hv_x86_reg_t;
217
218
219/** MSR permission flags type. */
220typedef uint32_t hv_msr_flags_t;
221/** MSR can't be accessed. */
222#define HV_MSR_NONE 0
223/** MSR is readable by the guest. */
224#define HV_MSR_READ RT_BIT(0)
225/** MSR is writeable by the guest. */
226#define HV_MSR_WRITE RT_BIT(1)
227
228
229typedef hv_return_t FN_HV_CAPABILITY(hv_capability_t capability, uint64_t *valu);
230typedef hv_return_t FN_HV_VM_CREATE(hv_vm_options_t flags);
231typedef hv_return_t FN_HV_VM_DESTROY(void);
232typedef hv_return_t FN_HV_VM_SPACE_CREATE(hv_vm_space_t *asid);
233typedef hv_return_t FN_HV_VM_SPACE_DESTROY(hv_vm_space_t asid);
234typedef hv_return_t FN_HV_VM_MAP(const void *uva, hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
235typedef hv_return_t FN_HV_VM_UNMAP(hv_gpaddr_t gpa, size_t size);
236typedef hv_return_t FN_HV_VM_PROTECT(hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
237typedef hv_return_t FN_HV_VM_MAP_SPACE(hv_vm_space_t asid, const void *uva, hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
238typedef hv_return_t FN_HV_VM_UNMAP_SPACE(hv_vm_space_t asid, hv_gpaddr_t gpa, size_t size);
239typedef hv_return_t FN_HV_VM_PROTECT_SPACE(hv_vm_space_t asid, hv_gpaddr_t gpa, size_t size, hv_memory_flags_t flags);
240typedef hv_return_t FN_HV_VM_SYNC_TSC(uint64_t tsc);
241
242typedef hv_return_t FN_HV_VCPU_CREATE(hv_vcpuid_t *vcpu, hv_vcpu_options_t flags);
243typedef hv_return_t FN_HV_VCPU_DESTROY(hv_vcpuid_t vcpu);
244typedef hv_return_t FN_HV_VCPU_SET_SPACE(hv_vcpuid_t vcpu, hv_vm_space_t asid);
245typedef hv_return_t FN_HV_VCPU_READ_REGISTER(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t *value);
246typedef hv_return_t FN_HV_VCPU_WRITE_REGISTER(hv_vcpuid_t vcpu, hv_x86_reg_t reg, uint64_t value);
247typedef hv_return_t FN_HV_VCPU_READ_FPSTATE(hv_vcpuid_t vcpu, void *buffer, size_t size);
248typedef hv_return_t FN_HV_VCPU_WRITE_FPSTATE(hv_vcpuid_t vcpu, const void *buffer, size_t size);
249typedef hv_return_t FN_HV_VCPU_ENABLE_NATIVE_MSR(hv_vcpuid_t vcpu, uint32_t msr, bool enable);
250typedef hv_return_t FN_HV_VCPU_READ_MSR(hv_vcpuid_t vcpu, uint32_t msr, uint64_t *value);
251typedef hv_return_t FN_HV_VCPU_WRITE_MSR(hv_vcpuid_t vcpu, uint32_t msr, uint64_t value);
252typedef hv_return_t FN_HV_VCPU_FLUSH(hv_vcpuid_t vcpu);
253typedef hv_return_t FN_HV_VCPU_INVALIDATE_TLB(hv_vcpuid_t vcpu);
254typedef hv_return_t FN_HV_VCPU_RUN(hv_vcpuid_t vcpu);
255typedef hv_return_t FN_HV_VCPU_RUN_UNTIL(hv_vcpuid_t vcpu, uint64_t deadline);
256typedef hv_return_t FN_HV_VCPU_INTERRUPT(hv_vcpuid_t *vcpus, unsigned int vcpu_count);
257typedef hv_return_t FN_HV_VCPU_GET_EXEC_TIME(hv_vcpuid_t *vcpus, uint64_t *time);
258
259typedef hv_return_t FN_HV_VMX_VCPU_READ_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t *value);
260typedef hv_return_t FN_HV_VMX_VCPU_WRITE_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t value);
261
262typedef hv_return_t FN_HV_VMX_VCPU_READ_SHADOW_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t *value);
263typedef hv_return_t FN_HV_VMX_VCPU_WRITE_SHADOW_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t value);
264typedef hv_return_t FN_HV_VMX_VCPU_SET_SHADOW_ACCESS(hv_vcpuid_t vcpu, uint32_t field, hv_shadow_flags_t flags);
265
266typedef hv_return_t FN_HV_VMX_READ_CAPABILITY(hv_vmx_capability_t field, uint64_t *value);
267typedef hv_return_t FN_HV_VMX_VCPU_SET_APIC_ADDRESS(hv_vcpuid_t vcpu, hv_gpaddr_t gpa);
268
269/* Since 11.0 */
270typedef hv_return_t FN_HV_VMX_VCPU_GET_CAP_WRITE_VMCS(hv_vcpuid_t vcpu, uint32_t field, uint64_t *allowed_0, uint64_t *allowed_1);
271typedef hv_return_t FN_HV_VCPU_ENABLE_MANAGED_MSR(hv_vcpuid_t vcpu, uint32_t msr, bool enable);
272typedef hv_return_t FN_HV_VCPU_SET_MSR_ACCESS(hv_vcpuid_t vcpu, uint32_t msr, hv_msr_flags_t flags);
273
274
275/*********************************************************************************************************************************
276* Global Variables *
277*********************************************************************************************************************************/
278/** NEM_DARWIN_PAGE_STATE_XXX names. */
279NEM_TMPL_STATIC const char * const g_apszPageStates[4] = { "not-set", "unmapped", "readable", "writable" };
280/** MSRs. */
281static SUPHWVIRTMSRS g_HmMsrs;
282/** VMX: Set if swapping EFER is supported. */
283static bool g_fHmVmxSupportsVmcsEfer = false;
284/** @name APIs imported from Hypervisor.framework.
285 * @{ */
286static FN_HV_CAPABILITY *g_pfnHvCapability = NULL; /* Since 10.15 */
287static FN_HV_VM_CREATE *g_pfnHvVmCreate = NULL; /* Since 10.10 */
288static FN_HV_VM_DESTROY *g_pfnHvVmDestroy = NULL; /* Since 10.10 */
289static FN_HV_VM_SPACE_CREATE *g_pfnHvVmSpaceCreate = NULL; /* Since 10.15 */
290static FN_HV_VM_SPACE_DESTROY *g_pfnHvVmSpaceDestroy = NULL; /* Since 10.15 */
291static FN_HV_VM_MAP *g_pfnHvVmMap = NULL; /* Since 10.10 */
292static FN_HV_VM_UNMAP *g_pfnHvVmUnmap = NULL; /* Since 10.10 */
293static FN_HV_VM_PROTECT *g_pfnHvVmProtect = NULL; /* Since 10.10 */
294static FN_HV_VM_MAP_SPACE *g_pfnHvVmMapSpace = NULL; /* Since 10.15 */
295static FN_HV_VM_UNMAP_SPACE *g_pfnHvVmUnmapSpace = NULL; /* Since 10.15 */
296static FN_HV_VM_PROTECT_SPACE *g_pfnHvVmProtectSpace = NULL; /* Since 10.15 */
297static FN_HV_VM_SYNC_TSC *g_pfnHvVmSyncTsc = NULL; /* Since 10.10 */
298
299static FN_HV_VCPU_CREATE *g_pfnHvVCpuCreate = NULL; /* Since 10.10 */
300static FN_HV_VCPU_DESTROY *g_pfnHvVCpuDestroy = NULL; /* Since 10.10 */
301static FN_HV_VCPU_SET_SPACE *g_pfnHvVCpuSetSpace = NULL; /* Since 10.15 */
302static FN_HV_VCPU_READ_REGISTER *g_pfnHvVCpuReadRegister = NULL; /* Since 10.10 */
303static FN_HV_VCPU_WRITE_REGISTER *g_pfnHvVCpuWriteRegister = NULL; /* Since 10.10 */
304static FN_HV_VCPU_READ_FPSTATE *g_pfnHvVCpuReadFpState = NULL; /* Since 10.10 */
305static FN_HV_VCPU_WRITE_FPSTATE *g_pfnHvVCpuWriteFpState = NULL; /* Since 10.10 */
306static FN_HV_VCPU_ENABLE_NATIVE_MSR *g_pfnHvVCpuEnableNativeMsr = NULL; /* Since 10.10 */
307static FN_HV_VCPU_READ_MSR *g_pfnHvVCpuReadMsr = NULL; /* Since 10.10 */
308static FN_HV_VCPU_WRITE_MSR *g_pfnHvVCpuWriteMsr = NULL; /* Since 10.10 */
309static FN_HV_VCPU_FLUSH *g_pfnHvVCpuFlush = NULL; /* Since 10.10 */
310static FN_HV_VCPU_INVALIDATE_TLB *g_pfnHvVCpuInvalidateTlb = NULL; /* Since 10.10 */
311static FN_HV_VCPU_RUN *g_pfnHvVCpuRun = NULL; /* Since 10.10 */
312static FN_HV_VCPU_RUN_UNTIL *g_pfnHvVCpuRunUntil = NULL; /* Since 10.15 */
313static FN_HV_VCPU_INTERRUPT *g_pfnHvVCpuInterrupt = NULL; /* Since 10.10 */
314static FN_HV_VCPU_GET_EXEC_TIME *g_pfnHvVCpuGetExecTime = NULL; /* Since 10.10 */
315
316static FN_HV_VMX_READ_CAPABILITY *g_pfnHvVmxReadCapability = NULL; /* Since 10.10 */
317static FN_HV_VMX_VCPU_READ_VMCS *g_pfnHvVmxVCpuReadVmcs = NULL; /* Since 10.10 */
318static FN_HV_VMX_VCPU_WRITE_VMCS *g_pfnHvVmxVCpuWriteVmcs = NULL; /* Since 10.10 */
319static FN_HV_VMX_VCPU_READ_SHADOW_VMCS *g_pfnHvVmxVCpuReadShadowVmcs = NULL; /* Since 10.15 */
320static FN_HV_VMX_VCPU_WRITE_SHADOW_VMCS *g_pfnHvVmxVCpuWriteShadowVmcs = NULL; /* Since 10.15 */
321static FN_HV_VMX_VCPU_SET_SHADOW_ACCESS *g_pfnHvVmxVCpuSetShadowAccess = NULL; /* Since 10.15 */
322static FN_HV_VMX_VCPU_SET_APIC_ADDRESS *g_pfnHvVmxVCpuSetApicAddress = NULL; /* Since 10.10 */
323
324static FN_HV_VMX_VCPU_GET_CAP_WRITE_VMCS *g_pfnHvVmxVCpuGetCapWriteVmcs = NULL; /* Since 11.0 */
325static FN_HV_VCPU_ENABLE_MANAGED_MSR *g_pfnHvVCpuEnableManagedMsr = NULL; /* Since 11.0 */
326static FN_HV_VCPU_SET_MSR_ACCESS *g_pfnHvVCpuSetMsrAccess = NULL; /* Since 11.0 */
327/** @} */
328
329
330/**
331 * Import instructions.
332 */
333static const struct
334{
335 bool fOptional; /**< Set if import is optional. */
336 void **ppfn; /**< The function pointer variable. */
337 const char *pszName; /**< The function name. */
338} g_aImports[] =
339{
340#define NEM_DARWIN_IMPORT(a_fOptional, a_Pfn, a_Name) { (a_fOptional), (void **)&(a_Pfn), #a_Name }
341 NEM_DARWIN_IMPORT(true, g_pfnHvCapability, hv_capability),
342 NEM_DARWIN_IMPORT(false, g_pfnHvVmCreate, hv_vm_create),
343 NEM_DARWIN_IMPORT(false, g_pfnHvVmDestroy, hv_vm_destroy),
344 NEM_DARWIN_IMPORT(true, g_pfnHvVmSpaceCreate, hv_vm_space_create),
345 NEM_DARWIN_IMPORT(true, g_pfnHvVmSpaceDestroy, hv_vm_space_destroy),
346 NEM_DARWIN_IMPORT(false, g_pfnHvVmMap, hv_vm_map),
347 NEM_DARWIN_IMPORT(false, g_pfnHvVmUnmap, hv_vm_unmap),
348 NEM_DARWIN_IMPORT(false, g_pfnHvVmProtect, hv_vm_protect),
349 NEM_DARWIN_IMPORT(true, g_pfnHvVmMapSpace, hv_vm_map_space),
350 NEM_DARWIN_IMPORT(true, g_pfnHvVmUnmapSpace, hv_vm_unmap_space),
351 NEM_DARWIN_IMPORT(true, g_pfnHvVmProtectSpace, hv_vm_protect_space),
352 NEM_DARWIN_IMPORT(false, g_pfnHvVmSyncTsc, hv_vm_sync_tsc),
353
354 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuCreate, hv_vcpu_create),
355 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuDestroy, hv_vcpu_destroy),
356 NEM_DARWIN_IMPORT(true, g_pfnHvVCpuSetSpace, hv_vcpu_set_space),
357 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuReadRegister, hv_vcpu_read_register),
358 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuWriteRegister, hv_vcpu_write_register),
359 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuReadFpState, hv_vcpu_read_fpstate),
360 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuWriteFpState, hv_vcpu_write_fpstate),
361 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuEnableNativeMsr, hv_vcpu_enable_native_msr),
362 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuReadMsr, hv_vcpu_read_msr),
363 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuWriteMsr, hv_vcpu_write_msr),
364 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuFlush, hv_vcpu_flush),
365 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuInvalidateTlb, hv_vcpu_invalidate_tlb),
366 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuRun, hv_vcpu_run),
367 NEM_DARWIN_IMPORT(true, g_pfnHvVCpuRunUntil, hv_vcpu_run_until),
368 NEM_DARWIN_IMPORT(false, g_pfnHvVCpuInterrupt, hv_vcpu_interrupt),
369 NEM_DARWIN_IMPORT(true, g_pfnHvVCpuGetExecTime, hv_vcpu_get_exec_time),
370 NEM_DARWIN_IMPORT(false, g_pfnHvVmxReadCapability, hv_vmx_read_capability),
371 NEM_DARWIN_IMPORT(false, g_pfnHvVmxVCpuReadVmcs, hv_vmx_vcpu_read_vmcs),
372 NEM_DARWIN_IMPORT(false, g_pfnHvVmxVCpuWriteVmcs, hv_vmx_vcpu_write_vmcs),
373 NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuReadShadowVmcs, hv_vmx_vcpu_read_shadow_vmcs),
374 NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuWriteShadowVmcs, hv_vmx_vcpu_write_shadow_vmcs),
375 NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuSetShadowAccess, hv_vmx_vcpu_set_shadow_access),
376 NEM_DARWIN_IMPORT(false, g_pfnHvVmxVCpuSetApicAddress, hv_vmx_vcpu_set_apic_address),
377 NEM_DARWIN_IMPORT(true, g_pfnHvVmxVCpuGetCapWriteVmcs, hv_vmx_vcpu_get_cap_write_vmcs),
378 NEM_DARWIN_IMPORT(true, g_pfnHvVCpuEnableManagedMsr, hv_vcpu_enable_managed_msr),
379 NEM_DARWIN_IMPORT(true, g_pfnHvVCpuSetMsrAccess, hv_vcpu_set_msr_access)
380#undef NEM_DARWIN_IMPORT
381};
382
383
384/*
385 * Let the preprocessor alias the APIs to import variables for better autocompletion.
386 */
387#ifndef IN_SLICKEDIT
388# define hv_capability g_pfnHvCapability
389# define hv_vm_create g_pfnHvVmCreate
390# define hv_vm_destroy g_pfnHvVmDestroy
391# define hv_vm_space_create g_pfnHvVmSpaceCreate
392# define hv_vm_space_destroy g_pfnHvVmSpaceDestroy
393# define hv_vm_map g_pfnHvVmMap
394# define hv_vm_unmap g_pfnHvVmUnmap
395# define hv_vm_protect g_pfnHvVmProtect
396# define hv_vm_map_space g_pfnHvVmMapSpace
397# define hv_vm_unmap_space g_pfnHvVmUnmapSpace
398# define hv_vm_protect_space g_pfnHvVmProtectSpace
399# define hv_vm_sync_tsc g_pfnHvVmSyncTsc
400
401# define hv_vcpu_create g_pfnHvVCpuCreate
402# define hv_vcpu_destroy g_pfnHvVCpuDestroy
403# define hv_vcpu_set_space g_pfnHvVCpuSetSpace
404# define hv_vcpu_read_register g_pfnHvVCpuReadRegister
405# define hv_vcpu_write_register g_pfnHvVCpuWriteRegister
406# define hv_vcpu_read_fpstate g_pfnHvVCpuReadFpState
407# define hv_vcpu_write_fpstate g_pfnHvVCpuWriteFpState
408# define hv_vcpu_enable_native_msr g_pfnHvVCpuEnableNativeMsr
409# define hv_vcpu_read_msr g_pfnHvVCpuReadMsr
410# define hv_vcpu_write_msr g_pfnHvVCpuWriteMsr
411# define hv_vcpu_flush g_pfnHvVCpuFlush
412# define hv_vcpu_invalidate_tlb g_pfnHvVCpuInvalidateTlb
413# define hv_vcpu_run g_pfnHvVCpuRun
414# define hv_vcpu_run_until g_pfnHvVCpuRunUntil
415# define hv_vcpu_interrupt g_pfnHvVCpuInterrupt
416# define hv_vcpu_get_exec_time g_pfnHvVCpuGetExecTime
417
418# define hv_vmx_read_capability g_pfnHvVmxReadCapability
419# define hv_vmx_vcpu_read_vmcs g_pfnHvVmxVCpuReadVmcs
420# define hv_vmx_vcpu_write_vmcs g_pfnHvVmxVCpuWriteVmcs
421# define hv_vmx_vcpu_read_shadow_vmcs g_pfnHvVmxVCpuReadShadowVmcs
422# define hv_vmx_vcpu_write_shadow_vmcs g_pfnHvVmxVCpuWriteShadowVmcs
423# define hv_vmx_vcpu_set_shadow_access g_pfnHvVmxVCpuSetShadowAccess
424# define hv_vmx_vcpu_set_apic_address g_pfnHvVmxVCpuSetApicAddress
425
426# define hv_vmx_vcpu_get_cap_write_vmcs g_pfnHvVmxVCpuGetCapWriteVmcs
427# define hv_vcpu_enable_managed_msr g_pfnHvVCpuEnableManagedMsr
428# define hv_vcpu_set_msr_access g_pfnHvVCpuSetMsrAccess
429#endif
430
431static const struct
432{
433 uint32_t u32VmcsFieldId; /**< The VMCS field identifier. */
434 const char *pszVmcsField; /**< The VMCS field name. */
435 bool f64Bit;
436} g_aVmcsFieldsCap[] =
437{
438#define NEM_DARWIN_VMCS64_FIELD_CAP(a_u32VmcsFieldId) { (a_u32VmcsFieldId), #a_u32VmcsFieldId, true }
439#define NEM_DARWIN_VMCS32_FIELD_CAP(a_u32VmcsFieldId) { (a_u32VmcsFieldId), #a_u32VmcsFieldId, false }
440
441 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_PIN_EXEC),
442 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_PROC_EXEC),
443 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_EXCEPTION_BITMAP),
444 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_EXIT),
445 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_ENTRY),
446 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_PROC_EXEC2),
447 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_PLE_GAP),
448 NEM_DARWIN_VMCS32_FIELD_CAP(VMX_VMCS32_CTRL_PLE_WINDOW),
449 NEM_DARWIN_VMCS64_FIELD_CAP(VMX_VMCS64_CTRL_TSC_OFFSET_FULL),
450 NEM_DARWIN_VMCS64_FIELD_CAP(VMX_VMCS64_GUEST_DEBUGCTL_FULL)
451#undef NEM_DARWIN_VMCS64_FIELD_CAP
452#undef NEM_DARWIN_VMCS32_FIELD_CAP
453};
454
455
456/*********************************************************************************************************************************
457* Internal Functions *
458*********************************************************************************************************************************/
459static void vmxHCImportGuestIntrState(PVMCPUCC pVCpu, PCVMXVMCSINFO pVmcsInfo);
460
461/**
462 * Converts a HV return code to a VBox status code.
463 *
464 * @returns VBox status code.
465 * @param hrc The HV return code to convert.
466 */
467DECLINLINE(int) nemR3DarwinHvSts2Rc(hv_return_t hrc)
468{
469 if (hrc == HV_SUCCESS)
470 return VINF_SUCCESS;
471
472 switch (hrc)
473 {
474 case HV_ERROR: return VERR_INVALID_STATE;
475 case HV_BUSY: return VERR_RESOURCE_BUSY;
476 case HV_BAD_ARGUMENT: return VERR_INVALID_PARAMETER;
477 case HV_NO_RESOURCES: return VERR_OUT_OF_RESOURCES;
478 case HV_NO_DEVICE: return VERR_NOT_FOUND;
479 case HV_UNSUPPORTED: return VERR_NOT_SUPPORTED;
480 }
481
482 return VERR_IPE_UNEXPECTED_STATUS;
483}
484
485
486/**
487 * Unmaps the given guest physical address range (page aligned).
488 *
489 * @returns VBox status code.
490 * @param pVM The cross context VM structure.
491 * @param GCPhys The guest physical address to start unmapping at.
492 * @param cb The size of the range to unmap in bytes.
493 */
494DECLINLINE(int) nemR3DarwinUnmap(PVM pVM, RTGCPHYS GCPhys, size_t cb)
495{
496 LogFlowFunc(("Unmapping %RGp LB %zu\n", GCPhys, cb));
497 hv_return_t hrc;
498 if (pVM->nem.s.fCreatedAsid)
499 hrc = hv_vm_unmap_space(pVM->nem.s.uVmAsid, GCPhys, cb);
500 else
501 hrc = hv_vm_unmap(GCPhys, cb);
502 return nemR3DarwinHvSts2Rc(hrc);
503}
504
505
506/**
507 * Maps a given guest physical address range backed by the given memory with the given
508 * protection flags.
509 *
510 * @returns VBox status code.
511 * @param pVM The cross context VM structure.
512 * @param GCPhys The guest physical address to start mapping.
513 * @param pvRam The R3 pointer of the memory to back the range with.
514 * @param cb The size of the range, page aligned.
515 * @param fPageProt The page protection flags to use for this range, combination of NEM_PAGE_PROT_XXX
516 */
517DECLINLINE(int) nemR3DarwinMap(PVM pVM, RTGCPHYS GCPhys, void *pvRam, size_t cb, uint32_t fPageProt)
518{
519 LogFlowFunc(("Mapping %RGp LB %zu fProt=%#x\n", GCPhys, cb, fPageProt));
520
521 hv_memory_flags_t fHvMemProt = 0;
522 if (fPageProt & NEM_PAGE_PROT_READ)
523 fHvMemProt |= HV_MEMORY_READ;
524 if (fPageProt & NEM_PAGE_PROT_WRITE)
525 fHvMemProt |= HV_MEMORY_WRITE;
526 if (fPageProt & NEM_PAGE_PROT_EXECUTE)
527 fHvMemProt |= HV_MEMORY_EXEC;
528
529 hv_return_t hrc;
530 if (pVM->nem.s.fCreatedAsid)
531 hrc = hv_vm_map_space(pVM->nem.s.uVmAsid, pvRam, GCPhys, cb, fHvMemProt);
532 else
533 hrc = hv_vm_map(pvRam, GCPhys, cb, fHvMemProt);
534 return nemR3DarwinHvSts2Rc(hrc);
535}
536
537
538#if 0 /* unused */
539DECLINLINE(int) nemR3DarwinProtectPage(PVM pVM, RTGCPHYS GCPhys, size_t cb, uint32_t fPageProt)
540{
541 hv_memory_flags_t fHvMemProt = 0;
542 if (fPageProt & NEM_PAGE_PROT_READ)
543 fHvMemProt |= HV_MEMORY_READ;
544 if (fPageProt & NEM_PAGE_PROT_WRITE)
545 fHvMemProt |= HV_MEMORY_WRITE;
546 if (fPageProt & NEM_PAGE_PROT_EXECUTE)
547 fHvMemProt |= HV_MEMORY_EXEC;
548
549 if (pVM->nem.s.fCreatedAsid)
550 hrc = hv_vm_protect_space(pVM->nem.s.uVmAsid, GCPhys, cb, fHvMemProt);
551 else
552 hrc = hv_vm_protect(GCPhys, cb, fHvMemProt);
553
554 return nemR3DarwinHvSts2Rc(hrc);
555}
556#endif
557
558
559DECLINLINE(int) nemR3NativeGCPhys2R3PtrReadOnly(PVM pVM, RTGCPHYS GCPhys, const void **ppv)
560{
561 PGMPAGEMAPLOCK Lock;
562 int rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, ppv, &Lock);
563 if (RT_SUCCESS(rc))
564 PGMPhysReleasePageMappingLock(pVM, &Lock);
565 return rc;
566}
567
568
569DECLINLINE(int) nemR3NativeGCPhys2R3PtrWriteable(PVM pVM, RTGCPHYS GCPhys, void **ppv)
570{
571 PGMPAGEMAPLOCK Lock;
572 int rc = PGMPhysGCPhys2CCPtr(pVM, GCPhys, ppv, &Lock);
573 if (RT_SUCCESS(rc))
574 PGMPhysReleasePageMappingLock(pVM, &Lock);
575 return rc;
576}
577
578
579/**
580 * Worker that maps pages into Hyper-V.
581 *
582 * This is used by the PGM physical page notifications as well as the memory
583 * access VMEXIT handlers.
584 *
585 * @returns VBox status code.
586 * @param pVM The cross context VM structure.
587 * @param pVCpu The cross context virtual CPU structure of the
588 * calling EMT.
589 * @param GCPhysSrc The source page address.
590 * @param GCPhysDst The hyper-V destination page. This may differ from
591 * GCPhysSrc when A20 is disabled.
592 * @param fPageProt NEM_PAGE_PROT_XXX.
593 * @param pu2State Our page state (input/output).
594 * @param fBackingChanged Set if the page backing is being changed.
595 * @thread EMT(pVCpu)
596 */
597NEM_TMPL_STATIC int nemHCNativeSetPhysPage(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhysSrc, RTGCPHYS GCPhysDst,
598 uint32_t fPageProt, uint8_t *pu2State, bool fBackingChanged)
599{
600 /*
601 * Looks like we need to unmap a page before we can change the backing
602 * or even modify the protection. This is going to be *REALLY* efficient.
603 * PGM lends us two bits to keep track of the state here.
604 */
605 RT_NOREF(pVCpu);
606 uint8_t const u2OldState = *pu2State;
607 uint8_t const u2NewState = fPageProt & NEM_PAGE_PROT_WRITE ? NEM_DARWIN_PAGE_STATE_WRITABLE
608 : fPageProt & NEM_PAGE_PROT_READ ? NEM_DARWIN_PAGE_STATE_READABLE : NEM_DARWIN_PAGE_STATE_UNMAPPED;
609 if ( fBackingChanged
610 || u2NewState != u2OldState)
611 {
612 if (u2OldState > NEM_DARWIN_PAGE_STATE_UNMAPPED)
613 {
614 int rc = nemR3DarwinUnmap(pVM, GCPhysDst, X86_PAGE_SIZE);
615 if (RT_SUCCESS(rc))
616 {
617 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
618 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
619 if (u2NewState == NEM_DARWIN_PAGE_STATE_UNMAPPED)
620 {
621 Log5(("NEM GPA unmapped/set: %RGp (was %s)\n", GCPhysDst, g_apszPageStates[u2OldState]));
622 return VINF_SUCCESS;
623 }
624 }
625 else
626 {
627 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
628 LogRel(("nemHCNativeSetPhysPage/unmap: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
629 return VERR_NEM_INIT_FAILED;
630 }
631 }
632 }
633
634 /*
635 * Writeable mapping?
636 */
637 if (fPageProt & NEM_PAGE_PROT_WRITE)
638 {
639 void *pvPage;
640 int rc = nemR3NativeGCPhys2R3PtrWriteable(pVM, GCPhysSrc, &pvPage);
641 if (RT_SUCCESS(rc))
642 {
643 rc = nemR3DarwinMap(pVM, GCPhysDst, pvPage, X86_PAGE_SIZE, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE);
644 if (RT_SUCCESS(rc))
645 {
646 *pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
647 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
648 Log5(("NEM GPA mapped/set: %RGp %s (was %s)\n", GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState]));
649 return VINF_SUCCESS;
650 }
651 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
652 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst));
653 return VERR_NEM_INIT_FAILED;
654 }
655 LogRel(("nemHCNativeSetPhysPage/writable: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
656 return rc;
657 }
658
659 if (fPageProt & NEM_PAGE_PROT_READ)
660 {
661 const void *pvPage;
662 int rc = nemR3NativeGCPhys2R3PtrReadOnly(pVM, GCPhysSrc, &pvPage);
663 if (RT_SUCCESS(rc))
664 {
665 rc = nemR3DarwinMap(pVM, GCPhysDst, (void *)pvPage, X86_PAGE_SIZE, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE);
666 if (RT_SUCCESS(rc))
667 {
668 *pu2State = NEM_DARWIN_PAGE_STATE_READABLE;
669 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPage);
670 Log5(("NEM GPA mapped/set: %RGp %s (was %s)\n", GCPhysDst, g_apszPageStates[u2NewState], g_apszPageStates[u2OldState]));
671 return VINF_SUCCESS;
672 }
673 STAM_REL_COUNTER_INC(&pVM->nem.s.StatMapPageFailed);
674 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysDst=%RGp rc=%Rrc\n", GCPhysDst, rc));
675 return VERR_NEM_INIT_FAILED;
676 }
677 LogRel(("nemHCNativeSetPhysPage/readonly: GCPhysSrc=%RGp rc=%Rrc\n", GCPhysSrc, rc));
678 return rc;
679 }
680
681 /* We already unmapped it above. */
682 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
683 return VINF_SUCCESS;
684}
685
686
687#ifdef LOG_ENABLED
688/**
689 * Logs the current CPU state.
690 */
691static void nemR3DarwinLogState(PVMCC pVM, PVMCPUCC pVCpu)
692{
693 if (LogIs3Enabled())
694 {
695#if 0
696 char szRegs[4096];
697 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs),
698 "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n"
699 "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n"
700 "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n"
701 "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n"
702 "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n"
703 "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n"
704 "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n"
705 "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n"
706 "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n"
707 "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n"
708 "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n"
709 "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n"
710 "dr6=%016VR{dr6} dr7=%016VR{dr7}\n"
711 "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n"
712 "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n"
713 "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n"
714 " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n"
715 " efer=%016VR{efer}\n"
716 " pat=%016VR{pat}\n"
717 " sf_mask=%016VR{sf_mask}\n"
718 "krnl_gs_base=%016VR{krnl_gs_base}\n"
719 " lstar=%016VR{lstar}\n"
720 " star=%016VR{star} cstar=%016VR{cstar}\n"
721 "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n"
722 );
723
724 char szInstr[256];
725 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0,
726 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE,
727 szInstr, sizeof(szInstr), NULL);
728 Log3(("%s%s\n", szRegs, szInstr));
729#else
730 RT_NOREF(pVM, pVCpu);
731#endif
732 }
733}
734#endif /* LOG_ENABLED */
735
736
737DECLINLINE(int) nemR3DarwinReadVmcs16(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint16_t *pData)
738{
739 uint64_t u64Data;
740 hv_return_t hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, &u64Data);
741 if (RT_LIKELY(hrc == HV_SUCCESS))
742 {
743 *pData = (uint16_t)u64Data;
744 return VINF_SUCCESS;
745 }
746
747 return nemR3DarwinHvSts2Rc(hrc);
748}
749
750
751DECLINLINE(int) nemR3DarwinReadVmcs32(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint32_t *pData)
752{
753 uint64_t u64Data;
754 hv_return_t hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, &u64Data);
755 if (RT_LIKELY(hrc == HV_SUCCESS))
756 {
757 *pData = (uint32_t)u64Data;
758 return VINF_SUCCESS;
759 }
760
761 return nemR3DarwinHvSts2Rc(hrc);
762}
763
764
765DECLINLINE(int) nemR3DarwinReadVmcs64(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint64_t *pData)
766{
767 hv_return_t hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, pData);
768 if (RT_LIKELY(hrc == HV_SUCCESS))
769 return VINF_SUCCESS;
770
771 return nemR3DarwinHvSts2Rc(hrc);
772}
773
774
775DECLINLINE(int) nemR3DarwinWriteVmcs16(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint16_t u16Val)
776{
777 hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, u16Val);
778 if (RT_LIKELY(hrc == HV_SUCCESS))
779 return VINF_SUCCESS;
780
781 return nemR3DarwinHvSts2Rc(hrc);
782}
783
784
785DECLINLINE(int) nemR3DarwinWriteVmcs32(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint32_t u32Val)
786{
787 hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, u32Val);
788 if (RT_LIKELY(hrc == HV_SUCCESS))
789 return VINF_SUCCESS;
790
791 return nemR3DarwinHvSts2Rc(hrc);
792}
793
794
795DECLINLINE(int) nemR3DarwinWriteVmcs64(PVMCPUCC pVCpu, uint32_t uFieldEnc, uint64_t u64Val)
796{
797 hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, uFieldEnc, u64Val);
798 if (RT_LIKELY(hrc == HV_SUCCESS))
799 return VINF_SUCCESS;
800
801 return nemR3DarwinHvSts2Rc(hrc);
802}
803
804DECLINLINE(int) nemR3DarwinMsrRead(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Val)
805{
806 hv_return_t hrc = hv_vcpu_read_msr(pVCpu->nem.s.hVCpuId, idMsr, pu64Val);
807 if (RT_LIKELY(hrc == HV_SUCCESS))
808 return VINF_SUCCESS;
809
810 return nemR3DarwinHvSts2Rc(hrc);
811}
812
813#if 0 /*unused*/
814DECLINLINE(int) nemR3DarwinMsrWrite(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t u64Val)
815{
816 hv_return_t hrc = hv_vcpu_write_msr(pVCpu->nem.s.hVCpuId, idMsr, u64Val);
817 if (RT_LIKELY(hrc == HV_SUCCESS))
818 return VINF_SUCCESS;
819
820 return nemR3DarwinHvSts2Rc(hrc);
821}
822#endif
823
824static int nemR3DarwinCopyStateFromHv(PVMCC pVM, PVMCPUCC pVCpu, uint64_t fWhat)
825{
826#define READ_GREG(a_GReg, a_Value) \
827 do \
828 { \
829 hrc = hv_vcpu_read_register(pVCpu->nem.s.hVCpuId, (a_GReg), &(a_Value)); \
830 if (RT_LIKELY(hrc == HV_SUCCESS)) \
831 { /* likely */ } \
832 else \
833 return VERR_INTERNAL_ERROR; \
834 } while(0)
835#define READ_VMCS_FIELD(a_Field, a_Value) \
836 do \
837 { \
838 hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), &(a_Value)); \
839 if (RT_LIKELY(hrc == HV_SUCCESS)) \
840 { /* likely */ } \
841 else \
842 return VERR_INTERNAL_ERROR; \
843 } while(0)
844#define READ_VMCS16_FIELD(a_Field, a_Value) \
845 do \
846 { \
847 uint64_t u64Data; \
848 hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), &u64Data); \
849 if (RT_LIKELY(hrc == HV_SUCCESS)) \
850 { (a_Value) = (uint16_t)u64Data; } \
851 else \
852 return VERR_INTERNAL_ERROR; \
853 } while(0)
854#define READ_VMCS32_FIELD(a_Field, a_Value) \
855 do \
856 { \
857 uint64_t u64Data; \
858 hrc = hv_vmx_vcpu_read_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), &u64Data); \
859 if (RT_LIKELY(hrc == HV_SUCCESS)) \
860 { (a_Value) = (uint32_t)u64Data; } \
861 else \
862 return VERR_INTERNAL_ERROR; \
863 } while(0)
864#define READ_MSR(a_Msr, a_Value) \
865 do \
866 { \
867 hrc = hv_vcpu_read_msr(pVCpu->nem.s.hVCpuId, (a_Msr), &(a_Value)); \
868 if (RT_LIKELY(hrc == HV_SUCCESS)) \
869 { /* likely */ } \
870 else \
871 AssertFailedReturn(VERR_INTERNAL_ERROR); \
872 } while(0)
873
874 STAM_PROFILE_ADV_START(&pVCpu->nem.s.StatProfGstStateImport, x);
875
876 RT_NOREF(pVM);
877 fWhat &= pVCpu->cpum.GstCtx.fExtrn;
878
879 if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
880 vmxHCImportGuestIntrState(pVCpu, &pVCpu->nem.s.VmcsInfo);
881
882 /* GPRs */
883 hv_return_t hrc;
884 if (fWhat & CPUMCTX_EXTRN_GPRS_MASK)
885 {
886 if (fWhat & CPUMCTX_EXTRN_RAX)
887 READ_GREG(HV_X86_RAX, pVCpu->cpum.GstCtx.rax);
888 if (fWhat & CPUMCTX_EXTRN_RCX)
889 READ_GREG(HV_X86_RCX, pVCpu->cpum.GstCtx.rcx);
890 if (fWhat & CPUMCTX_EXTRN_RDX)
891 READ_GREG(HV_X86_RDX, pVCpu->cpum.GstCtx.rdx);
892 if (fWhat & CPUMCTX_EXTRN_RBX)
893 READ_GREG(HV_X86_RBX, pVCpu->cpum.GstCtx.rbx);
894 if (fWhat & CPUMCTX_EXTRN_RSP)
895 READ_GREG(HV_X86_RSP, pVCpu->cpum.GstCtx.rsp);
896 if (fWhat & CPUMCTX_EXTRN_RBP)
897 READ_GREG(HV_X86_RBP, pVCpu->cpum.GstCtx.rbp);
898 if (fWhat & CPUMCTX_EXTRN_RSI)
899 READ_GREG(HV_X86_RSI, pVCpu->cpum.GstCtx.rsi);
900 if (fWhat & CPUMCTX_EXTRN_RDI)
901 READ_GREG(HV_X86_RDI, pVCpu->cpum.GstCtx.rdi);
902 if (fWhat & CPUMCTX_EXTRN_R8_R15)
903 {
904 READ_GREG(HV_X86_R8, pVCpu->cpum.GstCtx.r8);
905 READ_GREG(HV_X86_R9, pVCpu->cpum.GstCtx.r9);
906 READ_GREG(HV_X86_R10, pVCpu->cpum.GstCtx.r10);
907 READ_GREG(HV_X86_R11, pVCpu->cpum.GstCtx.r11);
908 READ_GREG(HV_X86_R12, pVCpu->cpum.GstCtx.r12);
909 READ_GREG(HV_X86_R13, pVCpu->cpum.GstCtx.r13);
910 READ_GREG(HV_X86_R14, pVCpu->cpum.GstCtx.r14);
911 READ_GREG(HV_X86_R15, pVCpu->cpum.GstCtx.r15);
912 }
913 }
914
915 /* RIP & Flags */
916 if (fWhat & CPUMCTX_EXTRN_RIP)
917 READ_GREG(HV_X86_RIP, pVCpu->cpum.GstCtx.rip);
918 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
919 READ_GREG(HV_X86_RFLAGS, pVCpu->cpum.GstCtx.rflags.u);
920
921 /* Segments */
922#define READ_SEG(a_SReg, a_enmName) \
923 do { \
924 READ_VMCS16_FIELD(VMX_VMCS16_GUEST_ ## a_enmName ## _SEL, (a_SReg).Sel); \
925 READ_VMCS32_FIELD(VMX_VMCS32_GUEST_ ## a_enmName ## _LIMIT, (a_SReg).u32Limit); \
926 READ_VMCS32_FIELD(VMX_VMCS32_GUEST_ ## a_enmName ## _ACCESS_RIGHTS, (a_SReg).Attr.u); \
927 READ_VMCS_FIELD(VMX_VMCS_GUEST_ ## a_enmName ## _BASE, (a_SReg).u64Base); \
928 (a_SReg).ValidSel = (a_SReg).Sel; \
929 } while (0)
930 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
931 {
932 if (fWhat & CPUMCTX_EXTRN_ES)
933 READ_SEG(pVCpu->cpum.GstCtx.es, ES);
934 if (fWhat & CPUMCTX_EXTRN_CS)
935 READ_SEG(pVCpu->cpum.GstCtx.cs, CS);
936 if (fWhat & CPUMCTX_EXTRN_SS)
937 READ_SEG(pVCpu->cpum.GstCtx.ss, SS);
938 if (fWhat & CPUMCTX_EXTRN_DS)
939 READ_SEG(pVCpu->cpum.GstCtx.ds, DS);
940 if (fWhat & CPUMCTX_EXTRN_FS)
941 READ_SEG(pVCpu->cpum.GstCtx.fs, FS);
942 if (fWhat & CPUMCTX_EXTRN_GS)
943 READ_SEG(pVCpu->cpum.GstCtx.gs, GS);
944 }
945
946 /* Descriptor tables and the task segment. */
947 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
948 {
949 if (fWhat & CPUMCTX_EXTRN_LDTR)
950 READ_SEG(pVCpu->cpum.GstCtx.ldtr, LDTR);
951
952 if (fWhat & CPUMCTX_EXTRN_TR)
953 {
954 /* AMD-V likes loading TR with in AVAIL state, whereas intel insists on BUSY. So,
955 avoid to trigger sanity assertions around the code, always fix this. */
956 READ_SEG(pVCpu->cpum.GstCtx.tr, TR);
957 switch (pVCpu->cpum.GstCtx.tr.Attr.n.u4Type)
958 {
959 case X86_SEL_TYPE_SYS_386_TSS_BUSY:
960 case X86_SEL_TYPE_SYS_286_TSS_BUSY:
961 break;
962 case X86_SEL_TYPE_SYS_386_TSS_AVAIL:
963 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_386_TSS_BUSY;
964 break;
965 case X86_SEL_TYPE_SYS_286_TSS_AVAIL:
966 pVCpu->cpum.GstCtx.tr.Attr.n.u4Type = X86_SEL_TYPE_SYS_286_TSS_BUSY;
967 break;
968 }
969 }
970 if (fWhat & CPUMCTX_EXTRN_IDTR)
971 {
972 READ_VMCS32_FIELD(VMX_VMCS32_GUEST_IDTR_LIMIT, pVCpu->cpum.GstCtx.idtr.cbIdt);
973 READ_VMCS_FIELD(VMX_VMCS_GUEST_IDTR_BASE, pVCpu->cpum.GstCtx.idtr.pIdt);
974 }
975 if (fWhat & CPUMCTX_EXTRN_GDTR)
976 {
977 READ_VMCS32_FIELD(VMX_VMCS32_GUEST_GDTR_LIMIT, pVCpu->cpum.GstCtx.gdtr.cbGdt);
978 READ_VMCS_FIELD(VMX_VMCS_GUEST_GDTR_BASE, pVCpu->cpum.GstCtx.gdtr.pGdt);
979 }
980 }
981
982 /* Control registers. */
983 bool fMaybeChangedMode = false;
984 bool fUpdateCr3 = false;
985 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
986 {
987 uint64_t u64CrTmp = 0;
988
989 if (fWhat & CPUMCTX_EXTRN_CR0)
990 {
991 READ_GREG(HV_X86_CR0, u64CrTmp);
992 if (pVCpu->cpum.GstCtx.cr0 != u64CrTmp)
993 {
994 CPUMSetGuestCR0(pVCpu, u64CrTmp);
995 fMaybeChangedMode = true;
996 }
997 }
998 if (fWhat & CPUMCTX_EXTRN_CR2)
999 READ_GREG(HV_X86_CR2, pVCpu->cpum.GstCtx.cr2);
1000 if (fWhat & CPUMCTX_EXTRN_CR3)
1001 {
1002 READ_GREG(HV_X86_CR3, u64CrTmp);
1003 if (pVCpu->cpum.GstCtx.cr3 != u64CrTmp)
1004 {
1005 CPUMSetGuestCR3(pVCpu, u64CrTmp);
1006 fUpdateCr3 = true;
1007 }
1008
1009 /*
1010 * If the guest is in PAE mode, sync back the PDPE's into the guest state.
1011 * CR4.PAE, CR0.PG, EFER MSR changes are always intercepted, so they're up to date.
1012 */
1013 if (CPUMIsGuestInPAEModeEx(&pVCpu->cpum.GstCtx))
1014 {
1015 X86PDPE aPaePdpes[4];
1016 READ_VMCS_FIELD(VMX_VMCS64_GUEST_PDPTE0_FULL, aPaePdpes[0].u);
1017 READ_VMCS_FIELD(VMX_VMCS64_GUEST_PDPTE1_FULL, aPaePdpes[1].u);
1018 READ_VMCS_FIELD(VMX_VMCS64_GUEST_PDPTE2_FULL, aPaePdpes[2].u);
1019 READ_VMCS_FIELD(VMX_VMCS64_GUEST_PDPTE3_FULL, aPaePdpes[3].u);
1020 if (memcmp(&aPaePdpes[0], &pVCpu->cpum.GstCtx.aPaePdpes[0], sizeof(aPaePdpes)))
1021 {
1022 memcpy(&pVCpu->cpum.GstCtx.aPaePdpes[0], &aPaePdpes[0], sizeof(aPaePdpes));
1023 fUpdateCr3 = true;
1024 }
1025 }
1026 }
1027 if (fWhat & CPUMCTX_EXTRN_CR4)
1028 {
1029 READ_GREG(HV_X86_CR4, u64CrTmp);
1030 u64CrTmp &= ~VMX_V_CR4_FIXED0;
1031
1032 if (pVCpu->cpum.GstCtx.cr4 != u64CrTmp)
1033 {
1034 CPUMSetGuestCR4(pVCpu, u64CrTmp);
1035 fMaybeChangedMode = true;
1036 }
1037 }
1038 }
1039
1040#if 0 /* Always done. */
1041 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1042 {
1043 uint64_t u64Cr8 = 0;
1044
1045 READ_GREG(HV_X86_TPR, u64Cr8);
1046 APICSetTpr(pVCpu, u64Cr8 << 4);
1047 }
1048#endif
1049
1050 if (fWhat & CPUMCTX_EXTRN_XCRx)
1051 READ_GREG(HV_X86_XCR0, pVCpu->cpum.GstCtx.aXcr[0]);
1052
1053 /* Debug registers. */
1054 if (fWhat & CPUMCTX_EXTRN_DR7)
1055 {
1056 uint64_t u64Dr7;
1057 READ_GREG(HV_X86_DR7, u64Dr7);
1058 if (pVCpu->cpum.GstCtx.dr[7] != u64Dr7)
1059 CPUMSetGuestDR7(pVCpu, u64Dr7);
1060 pVCpu->cpum.GstCtx.fExtrn &= ~CPUMCTX_EXTRN_DR7; /* Hack alert! Avoids asserting when processing CPUMCTX_EXTRN_DR0_DR3. */
1061 }
1062 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1063 {
1064 uint64_t u64DrTmp;
1065
1066 READ_GREG(HV_X86_DR0, u64DrTmp);
1067 if (pVCpu->cpum.GstCtx.dr[0] != u64DrTmp)
1068 CPUMSetGuestDR0(pVCpu, u64DrTmp);
1069 READ_GREG(HV_X86_DR1, u64DrTmp);
1070 if (pVCpu->cpum.GstCtx.dr[1] != u64DrTmp)
1071 CPUMSetGuestDR1(pVCpu, u64DrTmp);
1072 READ_GREG(HV_X86_DR2, u64DrTmp);
1073 if (pVCpu->cpum.GstCtx.dr[2] != u64DrTmp)
1074 CPUMSetGuestDR2(pVCpu, u64DrTmp);
1075 READ_GREG(HV_X86_DR3, u64DrTmp);
1076 if (pVCpu->cpum.GstCtx.dr[3] != u64DrTmp)
1077 CPUMSetGuestDR3(pVCpu, u64DrTmp);
1078 }
1079 if (fWhat & CPUMCTX_EXTRN_DR6)
1080 {
1081 uint64_t u64Dr6;
1082 READ_GREG(HV_X86_DR6, u64Dr6);
1083 if (pVCpu->cpum.GstCtx.dr[6] != u64Dr6)
1084 CPUMSetGuestDR6(pVCpu, u64Dr6);
1085 }
1086
1087 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX))
1088 {
1089 hrc = hv_vcpu_read_fpstate(pVCpu->nem.s.hVCpuId, &pVCpu->cpum.GstCtx.XState, sizeof(pVCpu->cpum.GstCtx.XState));
1090 if (hrc == HV_SUCCESS)
1091 { /* likely */ }
1092 else
1093 {
1094 STAM_PROFILE_ADV_STOP(&pVCpu->nem.s.StatProfGstStateImport, x);
1095 return nemR3DarwinHvSts2Rc(hrc);
1096 }
1097 }
1098
1099 /* MSRs */
1100 if (fWhat & CPUMCTX_EXTRN_EFER)
1101 {
1102 uint64_t u64Efer;
1103
1104 READ_VMCS_FIELD(VMX_VMCS64_GUEST_EFER_FULL, u64Efer);
1105 if (u64Efer != pVCpu->cpum.GstCtx.msrEFER)
1106 {
1107 Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, u64Efer));
1108 if ((u64Efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1109 PGMNotifyNxeChanged(pVCpu, RT_BOOL(u64Efer & MSR_K6_EFER_NXE));
1110 pVCpu->cpum.GstCtx.msrEFER = u64Efer;
1111 fMaybeChangedMode = true;
1112 }
1113 }
1114
1115 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1116 READ_MSR(MSR_K8_KERNEL_GS_BASE, pVCpu->cpum.GstCtx.msrKERNELGSBASE);
1117 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1118 {
1119 uint64_t u64Tmp;
1120 READ_MSR(MSR_IA32_SYSENTER_EIP, u64Tmp);
1121 pVCpu->cpum.GstCtx.SysEnter.eip = u64Tmp;
1122 READ_MSR(MSR_IA32_SYSENTER_ESP, u64Tmp);
1123 pVCpu->cpum.GstCtx.SysEnter.esp = u64Tmp;
1124 READ_MSR(MSR_IA32_SYSENTER_CS, u64Tmp);
1125 pVCpu->cpum.GstCtx.SysEnter.cs = u64Tmp;
1126 }
1127 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1128 {
1129 READ_MSR(MSR_K6_STAR, pVCpu->cpum.GstCtx.msrSTAR);
1130 READ_MSR(MSR_K8_LSTAR, pVCpu->cpum.GstCtx.msrLSTAR);
1131 READ_MSR(MSR_K8_CSTAR, pVCpu->cpum.GstCtx.msrCSTAR);
1132 READ_MSR(MSR_K8_SF_MASK, pVCpu->cpum.GstCtx.msrSFMASK);
1133 }
1134 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1135 {
1136 PCPUMCTXMSRS pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1137 READ_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1138
1139 /* Last Branch Record. */
1140 if (pVM->nem.s.fLbr)
1141 {
1142 PVMXVMCSINFOSHARED const pVmcsInfoShared = &pVCpu->nem.s.vmx.VmcsInfo;
1143 uint32_t const idFromIpMsrStart = pVM->nem.s.idLbrFromIpMsrFirst;
1144 uint32_t const idToIpMsrStart = pVM->nem.s.idLbrToIpMsrFirst;
1145 uint32_t const cLbrStack = pVM->nem.s.idLbrFromIpMsrLast - pVM->nem.s.idLbrFromIpMsrFirst + 1;
1146 Assert(cLbrStack <= 32);
1147 for (uint32_t i = 0; i < cLbrStack; i++)
1148 {
1149 READ_MSR(idFromIpMsrStart + i, pVmcsInfoShared->au64LbrFromIpMsr[i]);
1150
1151 /* Some CPUs don't have a Branch-To-IP MSR (P4 and related Xeons). */
1152 if (idToIpMsrStart != 0)
1153 READ_MSR(idToIpMsrStart + i, pVmcsInfoShared->au64LbrToIpMsr[i]);
1154 }
1155
1156 READ_MSR(pVM->nem.s.idLbrTosMsr, pVmcsInfoShared->u64LbrTosMsr);
1157 }
1158 }
1159
1160 /* Almost done, just update extrn flags and maybe change PGM mode. */
1161 pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1162 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1163 pVCpu->cpum.GstCtx.fExtrn = 0;
1164
1165#ifdef LOG_ENABLED
1166 nemR3DarwinLogState(pVM, pVCpu);
1167#endif
1168
1169 /* Typical. */
1170 if (!fMaybeChangedMode && !fUpdateCr3)
1171 {
1172 STAM_PROFILE_ADV_STOP(&pVCpu->nem.s.StatProfGstStateImport, x);
1173 return VINF_SUCCESS;
1174 }
1175
1176 /*
1177 * Slow.
1178 */
1179 if (fMaybeChangedMode)
1180 {
1181 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER,
1182 false /* fForce */);
1183 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1184 }
1185
1186 if (fUpdateCr3)
1187 {
1188 int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3);
1189 if (rc == VINF_SUCCESS)
1190 { /* likely */ }
1191 else
1192 AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1193 }
1194
1195 STAM_PROFILE_ADV_STOP(&pVCpu->nem.s.StatProfGstStateImport, x);
1196
1197 return VINF_SUCCESS;
1198#undef READ_GREG
1199#undef READ_VMCS_FIELD
1200#undef READ_VMCS32_FIELD
1201#undef READ_SEG
1202#undef READ_MSR
1203}
1204
1205
1206/**
1207 * State to pass between nemHCWinHandleMemoryAccess / nemR3WinWHvHandleMemoryAccess
1208 * and nemHCWinHandleMemoryAccessPageCheckerCallback.
1209 */
1210typedef struct NEMHCDARWINHMACPCCSTATE
1211{
1212 /** Input: Write access. */
1213 bool fWriteAccess;
1214 /** Output: Set if we did something. */
1215 bool fDidSomething;
1216 /** Output: Set it we should resume. */
1217 bool fCanResume;
1218} NEMHCDARWINHMACPCCSTATE;
1219
1220/**
1221 * @callback_method_impl{FNPGMPHYSNEMCHECKPAGE,
1222 * Worker for nemR3WinHandleMemoryAccess; pvUser points to a
1223 * NEMHCDARWINHMACPCCSTATE structure. }
1224 */
1225static DECLCALLBACK(int)
1226nemR3DarwinHandleMemoryAccessPageCheckerCallback(PVMCC pVM, PVMCPUCC pVCpu, RTGCPHYS GCPhys, PPGMPHYSNEMPAGEINFO pInfo, void *pvUser)
1227{
1228 NEMHCDARWINHMACPCCSTATE *pState = (NEMHCDARWINHMACPCCSTATE *)pvUser;
1229 pState->fDidSomething = false;
1230 pState->fCanResume = false;
1231
1232 uint8_t u2State = pInfo->u2NemState;
1233
1234 /*
1235 * Consolidate current page state with actual page protection and access type.
1236 * We don't really consider downgrades here, as they shouldn't happen.
1237 */
1238 int rc;
1239 switch (u2State)
1240 {
1241 case NEM_DARWIN_PAGE_STATE_UNMAPPED:
1242 case NEM_DARWIN_PAGE_STATE_NOT_SET:
1243 if (pInfo->fNemProt == NEM_PAGE_PROT_NONE)
1244 {
1245 Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #1\n", GCPhys));
1246 return VINF_SUCCESS;
1247 }
1248
1249 /* Don't bother remapping it if it's a write request to a non-writable page. */
1250 if ( pState->fWriteAccess
1251 && !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE))
1252 {
1253 Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #1w\n", GCPhys));
1254 return VINF_SUCCESS;
1255 }
1256
1257 /* Map the page. */
1258 rc = nemHCNativeSetPhysPage(pVM,
1259 pVCpu,
1260 GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1261 GCPhys & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK,
1262 pInfo->fNemProt,
1263 &u2State,
1264 true /*fBackingState*/);
1265 pInfo->u2NemState = u2State;
1266 Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - synced => %s + %Rrc\n",
1267 GCPhys, g_apszPageStates[u2State], rc));
1268 pState->fDidSomething = true;
1269 pState->fCanResume = true;
1270 return rc;
1271
1272 case NEM_DARWIN_PAGE_STATE_READABLE:
1273 if ( !(pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1274 && (pInfo->fNemProt & (NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE)))
1275 {
1276 pState->fCanResume = true;
1277 Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #2\n", GCPhys));
1278 return VINF_SUCCESS;
1279 }
1280 break;
1281
1282 case NEM_DARWIN_PAGE_STATE_WRITABLE:
1283 if (pInfo->fNemProt & NEM_PAGE_PROT_WRITE)
1284 {
1285 /* We get spurious EPT exit violations when everything is fine (#3a case) but can resume without issues here... */
1286 pState->fCanResume = true;
1287 if (pInfo->u2OldNemState == NEM_DARWIN_PAGE_STATE_WRITABLE)
1288 Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #3a\n", GCPhys));
1289 else
1290 Log4(("nemR3DarwinHandleMemoryAccessPageCheckerCallback: %RGp - #3b (%s -> %s)\n",
1291 GCPhys, g_apszPageStates[pInfo->u2OldNemState], g_apszPageStates[u2State]));
1292 return VINF_SUCCESS;
1293 }
1294
1295 break;
1296
1297 default:
1298 AssertLogRelMsgFailedReturn(("u2State=%#x\n", u2State), VERR_NEM_IPE_4);
1299 }
1300
1301 /*
1302 * Unmap and restart the instruction.
1303 * If this fails, which it does every so often, just unmap everything for now.
1304 */
1305 rc = nemR3DarwinUnmap(pVM, GCPhys, X86_PAGE_SIZE);
1306 if (RT_SUCCESS(rc))
1307 {
1308 pState->fDidSomething = true;
1309 pState->fCanResume = true;
1310 pInfo->u2NemState = NEM_DARWIN_PAGE_STATE_UNMAPPED;
1311 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
1312 Log5(("NEM GPA unmapped/exit: %RGp (was %s)\n", GCPhys, g_apszPageStates[u2State]));
1313 return VINF_SUCCESS;
1314 }
1315 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
1316 LogRel(("nemR3DarwinHandleMemoryAccessPageCheckerCallback/unmap: GCPhysDst=%RGp %s rc=%Rrc\n",
1317 GCPhys, g_apszPageStates[u2State], rc));
1318 return VERR_NEM_UNMAP_PAGES_FAILED;
1319}
1320
1321
1322DECL_FORCE_INLINE(bool) nemR3DarwinIsUnrestrictedGuest(PCVMCC pVM)
1323{
1324 RT_NOREF(pVM);
1325 return true;
1326}
1327
1328
1329DECL_FORCE_INLINE(bool) nemR3DarwinIsNestedPaging(PCVMCC pVM)
1330{
1331 RT_NOREF(pVM);
1332 return true;
1333}
1334
1335
1336DECL_FORCE_INLINE(bool) nemR3DarwinIsPreemptTimerUsed(PCVMCC pVM)
1337{
1338 RT_NOREF(pVM);
1339 return false;
1340}
1341
1342
1343#if 0 /* unused */
1344DECL_FORCE_INLINE(bool) nemR3DarwinIsVmxLbr(PCVMCC pVM)
1345{
1346 RT_NOREF(pVM);
1347 return false;
1348}
1349#endif
1350
1351
1352/*
1353 * Instantiate the code we share with ring-0.
1354 */
1355#define IN_NEM_DARWIN
1356//#define HMVMX_ALWAYS_TRAP_ALL_XCPTS
1357//#define HMVMX_ALWAYS_SYNC_FULL_GUEST_STATE
1358#define HMVMX_ALWAYS_INTERCEPT_CR3_ACCESS /* Temporary to investigate an issue with 32bit guests whete seem to end up with an invalid page table root address. */
1359#define VCPU_2_VMXSTATE(a_pVCpu) (a_pVCpu)->nem.s
1360#define VCPU_2_VMXSTATS(a_pVCpu) (*(a_pVCpu)->nem.s.pVmxStats)
1361
1362#define VM_IS_VMX_UNRESTRICTED_GUEST(a_pVM) nemR3DarwinIsUnrestrictedGuest((a_pVM))
1363#define VM_IS_VMX_NESTED_PAGING(a_pVM) nemR3DarwinIsNestedPaging((a_pVM))
1364#define VM_IS_VMX_PREEMPT_TIMER_USED(a_pVM) nemR3DarwinIsPreemptTimerUsed((a_pVM))
1365#define VM_IS_VMX_LBR(a_pVM) nemR3DarwinIsVmxLbr((a_pVM))
1366
1367#define VMX_VMCS_WRITE_16(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs16((a_pVCpu), (a_FieldEnc), (a_Val))
1368#define VMX_VMCS_WRITE_32(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs32((a_pVCpu), (a_FieldEnc), (a_Val))
1369#define VMX_VMCS_WRITE_64(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs64((a_pVCpu), (a_FieldEnc), (a_Val))
1370#define VMX_VMCS_WRITE_NW(a_pVCpu, a_FieldEnc, a_Val) nemR3DarwinWriteVmcs64((a_pVCpu), (a_FieldEnc), (a_Val))
1371
1372#define VMX_VMCS_READ_16(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs16((a_pVCpu), (a_FieldEnc), (a_pVal))
1373#define VMX_VMCS_READ_32(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs32((a_pVCpu), (a_FieldEnc), (a_pVal))
1374#define VMX_VMCS_READ_64(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs64((a_pVCpu), (a_FieldEnc), (a_pVal))
1375#define VMX_VMCS_READ_NW(a_pVCpu, a_FieldEnc, a_pVal) nemR3DarwinReadVmcs64((a_pVCpu), (a_FieldEnc), (a_pVal))
1376
1377#include "../VMMAll/VMXAllTemplate.cpp.h"
1378
1379#undef VMX_VMCS_WRITE_16
1380#undef VMX_VMCS_WRITE_32
1381#undef VMX_VMCS_WRITE_64
1382#undef VMX_VMCS_WRITE_NW
1383
1384#undef VMX_VMCS_READ_16
1385#undef VMX_VMCS_READ_32
1386#undef VMX_VMCS_READ_64
1387#undef VMX_VMCS_READ_NW
1388
1389#undef VM_IS_VMX_PREEMPT_TIMER_USED
1390#undef VM_IS_VMX_NESTED_PAGING
1391#undef VM_IS_VMX_UNRESTRICTED_GUEST
1392#undef VCPU_2_VMXSTATS
1393#undef VCPU_2_VMXSTATE
1394
1395
1396/**
1397 * Exports the guest GP registers to HV for execution.
1398 *
1399 * @returns VBox status code.
1400 * @param pVCpu The cross context virtual CPU structure of the
1401 * calling EMT.
1402 */
1403static int nemR3DarwinExportGuestGprs(PVMCPUCC pVCpu)
1404{
1405#define WRITE_GREG(a_GReg, a_Value) \
1406 do \
1407 { \
1408 hv_return_t hrc = hv_vcpu_write_register(pVCpu->nem.s.hVCpuId, (a_GReg), (a_Value)); \
1409 if (RT_LIKELY(hrc == HV_SUCCESS)) \
1410 { /* likely */ } \
1411 else \
1412 return VERR_INTERNAL_ERROR; \
1413 } while(0)
1414
1415 uint64_t fCtxChanged = ASMAtomicUoReadU64(&pVCpu->nem.s.fCtxChanged);
1416 if (fCtxChanged & HM_CHANGED_GUEST_GPRS_MASK)
1417 {
1418 if (fCtxChanged & HM_CHANGED_GUEST_RAX)
1419 WRITE_GREG(HV_X86_RAX, pVCpu->cpum.GstCtx.rax);
1420 if (fCtxChanged & HM_CHANGED_GUEST_RCX)
1421 WRITE_GREG(HV_X86_RCX, pVCpu->cpum.GstCtx.rcx);
1422 if (fCtxChanged & HM_CHANGED_GUEST_RDX)
1423 WRITE_GREG(HV_X86_RDX, pVCpu->cpum.GstCtx.rdx);
1424 if (fCtxChanged & HM_CHANGED_GUEST_RBX)
1425 WRITE_GREG(HV_X86_RBX, pVCpu->cpum.GstCtx.rbx);
1426 if (fCtxChanged & HM_CHANGED_GUEST_RSP)
1427 WRITE_GREG(HV_X86_RSP, pVCpu->cpum.GstCtx.rsp);
1428 if (fCtxChanged & HM_CHANGED_GUEST_RBP)
1429 WRITE_GREG(HV_X86_RBP, pVCpu->cpum.GstCtx.rbp);
1430 if (fCtxChanged & HM_CHANGED_GUEST_RSI)
1431 WRITE_GREG(HV_X86_RSI, pVCpu->cpum.GstCtx.rsi);
1432 if (fCtxChanged & HM_CHANGED_GUEST_RDI)
1433 WRITE_GREG(HV_X86_RDI, pVCpu->cpum.GstCtx.rdi);
1434 if (fCtxChanged & HM_CHANGED_GUEST_R8_R15)
1435 {
1436 WRITE_GREG(HV_X86_R8, pVCpu->cpum.GstCtx.r8);
1437 WRITE_GREG(HV_X86_R9, pVCpu->cpum.GstCtx.r9);
1438 WRITE_GREG(HV_X86_R10, pVCpu->cpum.GstCtx.r10);
1439 WRITE_GREG(HV_X86_R11, pVCpu->cpum.GstCtx.r11);
1440 WRITE_GREG(HV_X86_R12, pVCpu->cpum.GstCtx.r12);
1441 WRITE_GREG(HV_X86_R13, pVCpu->cpum.GstCtx.r13);
1442 WRITE_GREG(HV_X86_R14, pVCpu->cpum.GstCtx.r14);
1443 WRITE_GREG(HV_X86_R15, pVCpu->cpum.GstCtx.r15);
1444 }
1445
1446 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_GPRS_MASK);
1447 }
1448
1449 if (fCtxChanged & HM_CHANGED_GUEST_CR2)
1450 {
1451 WRITE_GREG(HV_X86_CR2, pVCpu->cpum.GstCtx.cr2);
1452 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_CR2);
1453 }
1454
1455 return VINF_SUCCESS;
1456#undef WRITE_GREG
1457}
1458
1459
1460/**
1461 * Converts the given CPUM externalized bitmask to the appropriate HM changed bitmask.
1462 *
1463 * @returns Bitmask of HM changed flags.
1464 * @param fCpumExtrn The CPUM extern bitmask.
1465 */
1466static uint64_t nemR3DarwinCpumExtrnToHmChanged(uint64_t fCpumExtrn)
1467{
1468 uint64_t fHmChanged = 0;
1469
1470 /* Invert to gt a mask of things which are kept in CPUM. */
1471 uint64_t fCpumIntern = ~fCpumExtrn;
1472
1473 if (fCpumIntern & CPUMCTX_EXTRN_GPRS_MASK)
1474 {
1475 if (fCpumIntern & CPUMCTX_EXTRN_RAX)
1476 fHmChanged |= HM_CHANGED_GUEST_RAX;
1477 if (fCpumIntern & CPUMCTX_EXTRN_RCX)
1478 fHmChanged |= HM_CHANGED_GUEST_RCX;
1479 if (fCpumIntern & CPUMCTX_EXTRN_RDX)
1480 fHmChanged |= HM_CHANGED_GUEST_RDX;
1481 if (fCpumIntern & CPUMCTX_EXTRN_RBX)
1482 fHmChanged |= HM_CHANGED_GUEST_RBX;
1483 if (fCpumIntern & CPUMCTX_EXTRN_RSP)
1484 fHmChanged |= HM_CHANGED_GUEST_RSP;
1485 if (fCpumIntern & CPUMCTX_EXTRN_RBP)
1486 fHmChanged |= HM_CHANGED_GUEST_RBP;
1487 if (fCpumIntern & CPUMCTX_EXTRN_RSI)
1488 fHmChanged |= HM_CHANGED_GUEST_RSI;
1489 if (fCpumIntern & CPUMCTX_EXTRN_RDI)
1490 fHmChanged |= HM_CHANGED_GUEST_RDI;
1491 if (fCpumIntern & CPUMCTX_EXTRN_R8_R15)
1492 fHmChanged |= HM_CHANGED_GUEST_R8_R15;
1493 }
1494
1495 /* RIP & Flags */
1496 if (fCpumIntern & CPUMCTX_EXTRN_RIP)
1497 fHmChanged |= HM_CHANGED_GUEST_RIP;
1498 if (fCpumIntern & CPUMCTX_EXTRN_RFLAGS)
1499 fHmChanged |= HM_CHANGED_GUEST_RFLAGS;
1500
1501 /* Segments */
1502 if (fCpumIntern & CPUMCTX_EXTRN_SREG_MASK)
1503 {
1504 if (fCpumIntern & CPUMCTX_EXTRN_ES)
1505 fHmChanged |= HM_CHANGED_GUEST_ES;
1506 if (fCpumIntern & CPUMCTX_EXTRN_CS)
1507 fHmChanged |= HM_CHANGED_GUEST_CS;
1508 if (fCpumIntern & CPUMCTX_EXTRN_SS)
1509 fHmChanged |= HM_CHANGED_GUEST_SS;
1510 if (fCpumIntern & CPUMCTX_EXTRN_DS)
1511 fHmChanged |= HM_CHANGED_GUEST_DS;
1512 if (fCpumIntern & CPUMCTX_EXTRN_FS)
1513 fHmChanged |= HM_CHANGED_GUEST_FS;
1514 if (fCpumIntern & CPUMCTX_EXTRN_GS)
1515 fHmChanged |= HM_CHANGED_GUEST_GS;
1516 }
1517
1518 /* Descriptor tables & task segment. */
1519 if (fCpumIntern & CPUMCTX_EXTRN_TABLE_MASK)
1520 {
1521 if (fCpumIntern & CPUMCTX_EXTRN_LDTR)
1522 fHmChanged |= HM_CHANGED_GUEST_LDTR;
1523 if (fCpumIntern & CPUMCTX_EXTRN_TR)
1524 fHmChanged |= HM_CHANGED_GUEST_TR;
1525 if (fCpumIntern & CPUMCTX_EXTRN_IDTR)
1526 fHmChanged |= HM_CHANGED_GUEST_IDTR;
1527 if (fCpumIntern & CPUMCTX_EXTRN_GDTR)
1528 fHmChanged |= HM_CHANGED_GUEST_GDTR;
1529 }
1530
1531 /* Control registers. */
1532 if (fCpumIntern & CPUMCTX_EXTRN_CR_MASK)
1533 {
1534 if (fCpumIntern & CPUMCTX_EXTRN_CR0)
1535 fHmChanged |= HM_CHANGED_GUEST_CR0;
1536 if (fCpumIntern & CPUMCTX_EXTRN_CR2)
1537 fHmChanged |= HM_CHANGED_GUEST_CR2;
1538 if (fCpumIntern & CPUMCTX_EXTRN_CR3)
1539 fHmChanged |= HM_CHANGED_GUEST_CR3;
1540 if (fCpumIntern & CPUMCTX_EXTRN_CR4)
1541 fHmChanged |= HM_CHANGED_GUEST_CR4;
1542 }
1543 if (fCpumIntern & CPUMCTX_EXTRN_APIC_TPR)
1544 fHmChanged |= HM_CHANGED_GUEST_APIC_TPR;
1545
1546 /* Debug registers. */
1547 if (fCpumIntern & CPUMCTX_EXTRN_DR0_DR3)
1548 fHmChanged |= HM_CHANGED_GUEST_DR0_DR3;
1549 if (fCpumIntern & CPUMCTX_EXTRN_DR6)
1550 fHmChanged |= HM_CHANGED_GUEST_DR6;
1551 if (fCpumIntern & CPUMCTX_EXTRN_DR7)
1552 fHmChanged |= HM_CHANGED_GUEST_DR7;
1553
1554 /* Floating point state. */
1555 if (fCpumIntern & CPUMCTX_EXTRN_X87)
1556 fHmChanged |= HM_CHANGED_GUEST_X87;
1557 if (fCpumIntern & CPUMCTX_EXTRN_SSE_AVX)
1558 fHmChanged |= HM_CHANGED_GUEST_SSE_AVX;
1559 if (fCpumIntern & CPUMCTX_EXTRN_OTHER_XSAVE)
1560 fHmChanged |= HM_CHANGED_GUEST_OTHER_XSAVE;
1561 if (fCpumIntern & CPUMCTX_EXTRN_XCRx)
1562 fHmChanged |= HM_CHANGED_GUEST_XCRx;
1563
1564 /* MSRs */
1565 if (fCpumIntern & CPUMCTX_EXTRN_EFER)
1566 fHmChanged |= HM_CHANGED_GUEST_EFER_MSR;
1567 if (fCpumIntern & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1568 fHmChanged |= HM_CHANGED_GUEST_KERNEL_GS_BASE;
1569 if (fCpumIntern & CPUMCTX_EXTRN_SYSENTER_MSRS)
1570 fHmChanged |= HM_CHANGED_GUEST_SYSENTER_MSR_MASK;
1571 if (fCpumIntern & CPUMCTX_EXTRN_SYSCALL_MSRS)
1572 fHmChanged |= HM_CHANGED_GUEST_SYSCALL_MSRS;
1573 if (fCpumIntern & CPUMCTX_EXTRN_TSC_AUX)
1574 fHmChanged |= HM_CHANGED_GUEST_TSC_AUX;
1575 if (fCpumIntern & CPUMCTX_EXTRN_OTHER_MSRS)
1576 fHmChanged |= HM_CHANGED_GUEST_OTHER_MSRS;
1577
1578 return fHmChanged;
1579}
1580
1581
1582/**
1583 * Exports the guest state to HV for execution.
1584 *
1585 * @returns VBox status code.
1586 * @param pVM The cross context VM structure.
1587 * @param pVCpu The cross context virtual CPU structure of the
1588 * calling EMT.
1589 * @param pVmxTransient The transient VMX structure.
1590 */
1591static int nemR3DarwinExportGuestState(PVMCC pVM, PVMCPUCC pVCpu, PVMXTRANSIENT pVmxTransient)
1592{
1593#define WRITE_GREG(a_GReg, a_Value) \
1594 do \
1595 { \
1596 hv_return_t hrc = hv_vcpu_write_register(pVCpu->nem.s.hVCpuId, (a_GReg), (a_Value)); \
1597 if (RT_LIKELY(hrc == HV_SUCCESS)) \
1598 { /* likely */ } \
1599 else \
1600 return VERR_INTERNAL_ERROR; \
1601 } while(0)
1602#define WRITE_VMCS_FIELD(a_Field, a_Value) \
1603 do \
1604 { \
1605 hv_return_t hrc = hv_vmx_vcpu_write_vmcs(pVCpu->nem.s.hVCpuId, (a_Field), (a_Value)); \
1606 if (RT_LIKELY(hrc == HV_SUCCESS)) \
1607 { /* likely */ } \
1608 else \
1609 return VERR_INTERNAL_ERROR; \
1610 } while(0)
1611#define WRITE_MSR(a_Msr, a_Value) \
1612 do \
1613 { \
1614 hv_return_t hrc = hv_vcpu_write_msr(pVCpu->nem.s.hVCpuId, (a_Msr), (a_Value)); \
1615 if (RT_LIKELY(hrc == HV_SUCCESS)) \
1616 { /* likely */ } \
1617 else \
1618 AssertFailedReturn(VERR_INTERNAL_ERROR); \
1619 } while(0)
1620
1621 RT_NOREF(pVM);
1622
1623#ifdef LOG_ENABLED
1624 nemR3DarwinLogState(pVM, pVCpu);
1625#endif
1626
1627 STAM_PROFILE_ADV_START(&pVCpu->nem.s.StatProfGstStateExport, x);
1628
1629 uint64_t const fWhat = ~pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL;
1630 if (!fWhat)
1631 return VINF_SUCCESS;
1632
1633 pVCpu->nem.s.fCtxChanged |= nemR3DarwinCpumExtrnToHmChanged(pVCpu->cpum.GstCtx.fExtrn);
1634
1635 int rc = vmxHCExportGuestEntryExitCtls(pVCpu, pVmxTransient);
1636 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1637
1638 rc = nemR3DarwinExportGuestGprs(pVCpu);
1639 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1640
1641 rc = vmxHCExportGuestCR0(pVCpu, pVmxTransient);
1642 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1643
1644 VBOXSTRICTRC rcStrict = vmxHCExportGuestCR3AndCR4(pVCpu, pVmxTransient);
1645 if (rcStrict == VINF_SUCCESS)
1646 { /* likely */ }
1647 else
1648 {
1649 Assert(rcStrict == VINF_EM_RESCHEDULE_REM || RT_FAILURE_NP(rcStrict));
1650 return VBOXSTRICTRC_VAL(rcStrict);
1651 }
1652
1653 vmxHCExportGuestXcptIntercepts(pVCpu, pVmxTransient);
1654 vmxHCExportGuestRip(pVCpu);
1655 //vmxHCExportGuestRsp(pVCpu);
1656 vmxHCExportGuestRflags(pVCpu, pVmxTransient);
1657
1658 rc = vmxHCExportGuestSegRegsXdtr(pVCpu, pVmxTransient);
1659 AssertLogRelMsgRCReturn(rc, ("rc=%Rrc\n", rc), rc);
1660
1661 if (fWhat & CPUMCTX_EXTRN_XCRx)
1662 {
1663 WRITE_GREG(HV_X86_XCR0, pVCpu->cpum.GstCtx.aXcr[0]);
1664 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_XCRx);
1665 }
1666
1667 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1668 {
1669 Assert(pVCpu->nem.s.fCtxChanged & HM_CHANGED_GUEST_APIC_TPR);
1670 vmxHCExportGuestApicTpr(pVCpu, pVmxTransient);
1671
1672 rc = APICGetTpr(pVCpu, &pVmxTransient->u8GuestTpr, NULL /*pfPending*/, NULL /*pu8PendingIntr*/);
1673 AssertRC(rc);
1674
1675 WRITE_GREG(HV_X86_TPR, pVmxTransient->u8GuestTpr);
1676 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_APIC_TPR);
1677 }
1678
1679 /* Debug registers. */
1680 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1681 {
1682 WRITE_GREG(HV_X86_DR0, pVCpu->cpum.GstCtx.dr[0]); // CPUMGetHyperDR0(pVCpu));
1683 WRITE_GREG(HV_X86_DR1, pVCpu->cpum.GstCtx.dr[1]); // CPUMGetHyperDR1(pVCpu));
1684 WRITE_GREG(HV_X86_DR2, pVCpu->cpum.GstCtx.dr[2]); // CPUMGetHyperDR2(pVCpu));
1685 WRITE_GREG(HV_X86_DR3, pVCpu->cpum.GstCtx.dr[3]); // CPUMGetHyperDR3(pVCpu));
1686 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_DR0_DR3);
1687 }
1688 if (fWhat & CPUMCTX_EXTRN_DR6)
1689 {
1690 WRITE_GREG(HV_X86_DR6, pVCpu->cpum.GstCtx.dr[6]); // CPUMGetHyperDR6(pVCpu));
1691 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_DR6);
1692 }
1693 if (fWhat & CPUMCTX_EXTRN_DR7)
1694 {
1695 WRITE_GREG(HV_X86_DR7, pVCpu->cpum.GstCtx.dr[7]); // CPUMGetHyperDR7(pVCpu));
1696 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_DR7);
1697 }
1698
1699 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))
1700 {
1701 hv_return_t hrc = hv_vcpu_write_fpstate(pVCpu->nem.s.hVCpuId, &pVCpu->cpum.GstCtx.XState, sizeof(pVCpu->cpum.GstCtx.XState));
1702 if (hrc == HV_SUCCESS)
1703 { /* likely */ }
1704 else
1705 return nemR3DarwinHvSts2Rc(hrc);
1706
1707 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~(HM_CHANGED_GUEST_X87 | HM_CHANGED_GUEST_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE));
1708 }
1709
1710 /* MSRs */
1711 if (fWhat & CPUMCTX_EXTRN_EFER)
1712 {
1713 WRITE_VMCS_FIELD(VMX_VMCS64_GUEST_EFER_FULL, pVCpu->cpum.GstCtx.msrEFER);
1714 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_EFER_MSR);
1715 }
1716 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1717 {
1718 WRITE_MSR(MSR_K8_KERNEL_GS_BASE, pVCpu->cpum.GstCtx.msrKERNELGSBASE);
1719 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_KERNEL_GS_BASE);
1720 }
1721 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1722 {
1723 WRITE_MSR(MSR_IA32_SYSENTER_CS, pVCpu->cpum.GstCtx.SysEnter.cs);
1724 WRITE_MSR(MSR_IA32_SYSENTER_EIP, pVCpu->cpum.GstCtx.SysEnter.eip);
1725 WRITE_MSR(MSR_IA32_SYSENTER_ESP, pVCpu->cpum.GstCtx.SysEnter.esp);
1726 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSENTER_MSR_MASK);
1727 }
1728 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1729 {
1730 WRITE_MSR(MSR_K6_STAR, pVCpu->cpum.GstCtx.msrSTAR);
1731 WRITE_MSR(MSR_K8_LSTAR, pVCpu->cpum.GstCtx.msrLSTAR);
1732 WRITE_MSR(MSR_K8_CSTAR, pVCpu->cpum.GstCtx.msrCSTAR);
1733 WRITE_MSR(MSR_K8_SF_MASK, pVCpu->cpum.GstCtx.msrSFMASK);
1734 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_SYSCALL_MSRS);
1735 }
1736 if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
1737 {
1738 PCPUMCTXMSRS pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1739
1740 WRITE_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1741 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_TSC_AUX);
1742 }
1743 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1744 {
1745 /* Last Branch Record. */
1746 if (pVM->nem.s.fLbr)
1747 {
1748 PVMXVMCSINFOSHARED const pVmcsInfoShared = &pVCpu->nem.s.vmx.VmcsInfo;
1749 uint32_t const idFromIpMsrStart = pVM->nem.s.idLbrFromIpMsrFirst;
1750 uint32_t const idToIpMsrStart = pVM->nem.s.idLbrToIpMsrFirst;
1751 uint32_t const cLbrStack = pVM->nem.s.idLbrFromIpMsrLast - pVM->nem.s.idLbrFromIpMsrFirst + 1;
1752 Assert(cLbrStack <= 32);
1753 for (uint32_t i = 0; i < cLbrStack; i++)
1754 {
1755 WRITE_MSR(idFromIpMsrStart + i, pVmcsInfoShared->au64LbrFromIpMsr[i]);
1756
1757 /* Some CPUs don't have a Branch-To-IP MSR (P4 and related Xeons). */
1758 if (idToIpMsrStart != 0)
1759 WRITE_MSR(idToIpMsrStart + i, pVmcsInfoShared->au64LbrToIpMsr[i]);
1760 }
1761
1762 WRITE_MSR(pVM->nem.s.idLbrTosMsr, pVmcsInfoShared->u64LbrTosMsr);
1763 }
1764
1765 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_OTHER_MSRS);
1766 }
1767
1768 hv_vcpu_invalidate_tlb(pVCpu->nem.s.hVCpuId);
1769 hv_vcpu_flush(pVCpu->nem.s.hVCpuId);
1770
1771 pVCpu->cpum.GstCtx.fExtrn |= CPUMCTX_EXTRN_ALL | CPUMCTX_EXTRN_KEEPER_NEM;
1772
1773 /* Clear any bits that may be set but exported unconditionally or unused/reserved bits. */
1774 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~( HM_CHANGED_GUEST_HWVIRT
1775 | HM_CHANGED_VMX_GUEST_AUTO_MSRS
1776 | HM_CHANGED_VMX_GUEST_LAZY_MSRS
1777 | (HM_CHANGED_KEEPER_STATE_MASK & ~HM_CHANGED_VMX_MASK)));
1778
1779 STAM_PROFILE_ADV_STOP(&pVCpu->nem.s.StatProfGstStateExport, x);
1780 return VINF_SUCCESS;
1781#undef WRITE_GREG
1782#undef WRITE_VMCS_FIELD
1783}
1784
1785
1786/**
1787 * Handles an exit from hv_vcpu_run().
1788 *
1789 * @returns VBox strict status code.
1790 * @param pVM The cross context VM structure.
1791 * @param pVCpu The cross context virtual CPU structure of the
1792 * calling EMT.
1793 * @param pVmxTransient The transient VMX structure.
1794 */
1795static VBOXSTRICTRC nemR3DarwinHandleExit(PVM pVM, PVMCPU pVCpu, PVMXTRANSIENT pVmxTransient)
1796{
1797 uint32_t uExitReason;
1798 int rc = nemR3DarwinReadVmcs32(pVCpu, VMX_VMCS32_RO_EXIT_REASON, &uExitReason);
1799 AssertRC(rc);
1800 pVmxTransient->fVmcsFieldsRead = 0;
1801 pVmxTransient->fIsNestedGuest = false;
1802 pVmxTransient->uExitReason = VMX_EXIT_REASON_BASIC(uExitReason);
1803 pVmxTransient->fVMEntryFailed = VMX_EXIT_REASON_HAS_ENTRY_FAILED(uExitReason);
1804
1805 if (RT_UNLIKELY(pVmxTransient->fVMEntryFailed))
1806 AssertLogRelMsgFailedReturn(("Running guest failed for CPU #%u: %#x %u\n",
1807 pVCpu->idCpu, pVmxTransient->uExitReason, vmxHCCheckGuestState(pVCpu, &pVCpu->nem.s.VmcsInfo)),
1808 VERR_NEM_IPE_0);
1809
1810 /** @todo Only copy the state on demand (the R0 VT-x code saves some stuff unconditionally and the VMX template assumes that
1811 * when handling exits). */
1812 rc = nemR3DarwinCopyStateFromHv(pVM, pVCpu, CPUMCTX_EXTRN_ALL);
1813 AssertRCReturn(rc, rc);
1814
1815 STAM_COUNTER_INC(&pVCpu->nem.s.pVmxStats->aStatExitReason[pVmxTransient->uExitReason & MASK_EXITREASON_STAT]);
1816 STAM_REL_COUNTER_INC(&pVCpu->nem.s.pVmxStats->StatExitAll);
1817
1818#ifndef HMVMX_USE_FUNCTION_TABLE
1819 return vmxHCHandleExit(pVCpu, pVmxTransient);
1820#else
1821 return g_aVMExitHandlers[pVmxTransient->uExitReason].pfn(pVCpu, pVmxTransient);
1822#endif
1823}
1824
1825
1826/**
1827 * Worker for nemR3NativeInit that loads the Hypervisor.framework shared library.
1828 *
1829 * @returns VBox status code.
1830 * @param fForced Whether the HMForced flag is set and we should
1831 * fail if we cannot initialize.
1832 * @param pErrInfo Where to always return error info.
1833 */
1834static int nemR3DarwinLoadHv(bool fForced, PRTERRINFO pErrInfo)
1835{
1836 RTLDRMOD hMod = NIL_RTLDRMOD;
1837 static const char *s_pszHvPath = "/System/Library/Frameworks/Hypervisor.framework/Hypervisor";
1838
1839 int rc = RTLdrLoadEx(s_pszHvPath, &hMod, RTLDRLOAD_FLAGS_NO_UNLOAD | RTLDRLOAD_FLAGS_NO_SUFFIX, pErrInfo);
1840 if (RT_SUCCESS(rc))
1841 {
1842 for (unsigned i = 0; i < RT_ELEMENTS(g_aImports); i++)
1843 {
1844 int rc2 = RTLdrGetSymbol(hMod, g_aImports[i].pszName, (void **)g_aImports[i].ppfn);
1845 if (RT_SUCCESS(rc2))
1846 {
1847 if (g_aImports[i].fOptional)
1848 LogRel(("NEM: info: Found optional import Hypervisor!%s.\n",
1849 g_aImports[i].pszName));
1850 }
1851 else
1852 {
1853 *g_aImports[i].ppfn = NULL;
1854
1855 LogRel(("NEM: %s: Failed to import Hypervisor!%s: %Rrc\n",
1856 g_aImports[i].fOptional ? "info" : fForced ? "fatal" : "error",
1857 g_aImports[i].pszName, rc2));
1858 if (!g_aImports[i].fOptional)
1859 {
1860 if (RTErrInfoIsSet(pErrInfo))
1861 RTErrInfoAddF(pErrInfo, rc2, ", Hypervisor!%s", g_aImports[i].pszName);
1862 else
1863 rc = RTErrInfoSetF(pErrInfo, rc2, "Failed to import: Hypervisor!%s", g_aImports[i].pszName);
1864 Assert(RT_FAILURE(rc));
1865 }
1866 }
1867 }
1868 if (RT_SUCCESS(rc))
1869 {
1870 Assert(!RTErrInfoIsSet(pErrInfo));
1871 }
1872
1873 RTLdrClose(hMod);
1874 }
1875 else
1876 {
1877 RTErrInfoAddF(pErrInfo, rc, "Failed to load Hypervisor.framwork: %s: %Rrc", s_pszHvPath, rc);
1878 rc = VERR_NEM_INIT_FAILED;
1879 }
1880
1881 return rc;
1882}
1883
1884
1885/**
1886 * Read and initialize the global capabilities supported by this CPU.
1887 *
1888 * @returns VBox status code.
1889 */
1890static int nemR3DarwinCapsInit(void)
1891{
1892 RT_ZERO(g_HmMsrs);
1893
1894 hv_return_t hrc = hv_vmx_read_capability(HV_VMX_CAP_PINBASED, &g_HmMsrs.u.vmx.PinCtls.u);
1895 if (hrc == HV_SUCCESS)
1896 hrc = hv_vmx_read_capability(HV_VMX_CAP_PROCBASED, &g_HmMsrs.u.vmx.ProcCtls.u);
1897 if (hrc == HV_SUCCESS)
1898 hrc = hv_vmx_read_capability(HV_VMX_CAP_ENTRY, &g_HmMsrs.u.vmx.EntryCtls.u);
1899 if (hrc == HV_SUCCESS)
1900 hrc = hv_vmx_read_capability(HV_VMX_CAP_EXIT, &g_HmMsrs.u.vmx.ExitCtls.u);
1901 if (hrc == HV_SUCCESS)
1902 {
1903 hrc = hv_vmx_read_capability(HV_VMX_CAP_BASIC, &g_HmMsrs.u.vmx.u64Basic);
1904 if (hrc == HV_SUCCESS)
1905 {
1906 if (hrc == HV_SUCCESS)
1907 hrc = hv_vmx_read_capability(HV_VMX_CAP_MISC, &g_HmMsrs.u.vmx.u64Misc);
1908 if (hrc == HV_SUCCESS)
1909 hrc = hv_vmx_read_capability(HV_VMX_CAP_CR0_FIXED0, &g_HmMsrs.u.vmx.u64Cr0Fixed0);
1910 if (hrc == HV_SUCCESS)
1911 hrc = hv_vmx_read_capability(HV_VMX_CAP_CR0_FIXED1, &g_HmMsrs.u.vmx.u64Cr0Fixed1);
1912 if (hrc == HV_SUCCESS)
1913 hrc = hv_vmx_read_capability(HV_VMX_CAP_CR4_FIXED0, &g_HmMsrs.u.vmx.u64Cr4Fixed0);
1914 if (hrc == HV_SUCCESS)
1915 hrc = hv_vmx_read_capability(HV_VMX_CAP_CR4_FIXED1, &g_HmMsrs.u.vmx.u64Cr4Fixed1);
1916 if (hrc == HV_SUCCESS)
1917 hrc = hv_vmx_read_capability(HV_VMX_CAP_VMCS_ENUM, &g_HmMsrs.u.vmx.u64VmcsEnum);
1918 if ( hrc == HV_SUCCESS
1919 && RT_BF_GET(g_HmMsrs.u.vmx.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1920 {
1921 hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_PINBASED, &g_HmMsrs.u.vmx.TruePinCtls.u);
1922 if (hrc == HV_SUCCESS)
1923 hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_PROCBASED, &g_HmMsrs.u.vmx.TrueProcCtls.u);
1924 if (hrc == HV_SUCCESS)
1925 hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_ENTRY, &g_HmMsrs.u.vmx.TrueEntryCtls.u);
1926 if (hrc == HV_SUCCESS)
1927 hrc = hv_vmx_read_capability(HV_VMX_CAP_TRUE_EXIT, &g_HmMsrs.u.vmx.TrueExitCtls.u);
1928 }
1929 }
1930 else
1931 {
1932 /* Likely running on anything < 11.0 (BigSur) so provide some sensible defaults. */
1933 g_HmMsrs.u.vmx.u64Cr0Fixed0 = 0x80000021;
1934 g_HmMsrs.u.vmx.u64Cr0Fixed1 = 0xffffffff;
1935 g_HmMsrs.u.vmx.u64Cr4Fixed0 = 0x2000;
1936 g_HmMsrs.u.vmx.u64Cr4Fixed1 = 0x1767ff;
1937 hrc = HV_SUCCESS;
1938 }
1939 }
1940
1941 if ( hrc == HV_SUCCESS
1942 && g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1943 {
1944 hrc = hv_vmx_read_capability(HV_VMX_CAP_PROCBASED2, &g_HmMsrs.u.vmx.ProcCtls2.u);
1945
1946 if ( hrc == HV_SUCCESS
1947 && g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & (VMX_PROC_CTLS2_EPT | VMX_PROC_CTLS2_VPID))
1948 {
1949 hrc = hv_vmx_read_capability(HV_VMX_CAP_EPT_VPID_CAP, &g_HmMsrs.u.vmx.u64EptVpidCaps);
1950 if (hrc != HV_SUCCESS)
1951 hrc = HV_SUCCESS; /* Probably just outdated OS. */
1952 }
1953
1954 g_HmMsrs.u.vmx.u64VmFunc = 0; /* No way to read that on macOS. */
1955 }
1956
1957 if (hrc == HV_SUCCESS)
1958 {
1959 /*
1960 * Check for EFER swapping support.
1961 */
1962 g_fHmVmxSupportsVmcsEfer = true; //(g_HmMsrs.u.vmx.EntryCtls.n.allowed1 & VMX_ENTRY_CTLS_LOAD_EFER_MSR)
1963 //&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_LOAD_EFER_MSR)
1964 //&& (g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_SAVE_EFER_MSR);
1965 }
1966
1967 return nemR3DarwinHvSts2Rc(hrc);
1968}
1969
1970
1971/**
1972 * Sets up the LBR MSR ranges based on the host CPU.
1973 *
1974 * @returns VBox status code.
1975 * @param pVM The cross context VM structure.
1976 *
1977 * @sa hmR0VmxSetupLbrMsrRange
1978 */
1979static int nemR3DarwinSetupLbrMsrRange(PVMCC pVM)
1980{
1981 Assert(pVM->nem.s.fLbr);
1982 uint32_t idLbrFromIpMsrFirst;
1983 uint32_t idLbrFromIpMsrLast;
1984 uint32_t idLbrToIpMsrFirst;
1985 uint32_t idLbrToIpMsrLast;
1986 uint32_t idLbrTosMsr;
1987
1988 /*
1989 * Determine the LBR MSRs supported for this host CPU family and model.
1990 *
1991 * See Intel spec. 17.4.8 "LBR Stack".
1992 * See Intel "Model-Specific Registers" spec.
1993 */
1994 uint32_t const uFamilyModel = (pVM->cpum.ro.HostFeatures.uFamily << 8)
1995 | pVM->cpum.ro.HostFeatures.uModel;
1996 switch (uFamilyModel)
1997 {
1998 case 0x0f01: case 0x0f02:
1999 idLbrFromIpMsrFirst = MSR_P4_LASTBRANCH_0;
2000 idLbrFromIpMsrLast = MSR_P4_LASTBRANCH_3;
2001 idLbrToIpMsrFirst = 0x0;
2002 idLbrToIpMsrLast = 0x0;
2003 idLbrTosMsr = MSR_P4_LASTBRANCH_TOS;
2004 break;
2005
2006 case 0x065c: case 0x065f: case 0x064e: case 0x065e: case 0x068e:
2007 case 0x069e: case 0x0655: case 0x0666: case 0x067a: case 0x0667:
2008 case 0x066a: case 0x066c: case 0x067d: case 0x067e:
2009 idLbrFromIpMsrFirst = MSR_LASTBRANCH_0_FROM_IP;
2010 idLbrFromIpMsrLast = MSR_LASTBRANCH_31_FROM_IP;
2011 idLbrToIpMsrFirst = MSR_LASTBRANCH_0_TO_IP;
2012 idLbrToIpMsrLast = MSR_LASTBRANCH_31_TO_IP;
2013 idLbrTosMsr = MSR_LASTBRANCH_TOS;
2014 break;
2015
2016 case 0x063d: case 0x0647: case 0x064f: case 0x0656: case 0x063c:
2017 case 0x0645: case 0x0646: case 0x063f: case 0x062a: case 0x062d:
2018 case 0x063a: case 0x063e: case 0x061a: case 0x061e: case 0x061f:
2019 case 0x062e: case 0x0625: case 0x062c: case 0x062f:
2020 idLbrFromIpMsrFirst = MSR_LASTBRANCH_0_FROM_IP;
2021 idLbrFromIpMsrLast = MSR_LASTBRANCH_15_FROM_IP;
2022 idLbrToIpMsrFirst = MSR_LASTBRANCH_0_TO_IP;
2023 idLbrToIpMsrLast = MSR_LASTBRANCH_15_TO_IP;
2024 idLbrTosMsr = MSR_LASTBRANCH_TOS;
2025 break;
2026
2027 case 0x0617: case 0x061d: case 0x060f:
2028 idLbrFromIpMsrFirst = MSR_CORE2_LASTBRANCH_0_FROM_IP;
2029 idLbrFromIpMsrLast = MSR_CORE2_LASTBRANCH_3_FROM_IP;
2030 idLbrToIpMsrFirst = MSR_CORE2_LASTBRANCH_0_TO_IP;
2031 idLbrToIpMsrLast = MSR_CORE2_LASTBRANCH_3_TO_IP;
2032 idLbrTosMsr = MSR_CORE2_LASTBRANCH_TOS;
2033 break;
2034
2035 /* Atom and related microarchitectures we don't care about:
2036 case 0x0637: case 0x064a: case 0x064c: case 0x064d: case 0x065a:
2037 case 0x065d: case 0x061c: case 0x0626: case 0x0627: case 0x0635:
2038 case 0x0636: */
2039 /* All other CPUs: */
2040 default:
2041 {
2042 LogRelFunc(("Could not determine LBR stack size for the CPU model %#x\n", uFamilyModel));
2043 VMCC_GET_CPU_0(pVM)->nem.s.u32HMError = VMX_UFC_LBR_STACK_SIZE_UNKNOWN;
2044 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2045 }
2046 }
2047
2048 /*
2049 * Validate.
2050 */
2051 uint32_t const cLbrStack = idLbrFromIpMsrLast - idLbrFromIpMsrFirst + 1;
2052 PCVMCPU pVCpu0 = VMCC_GET_CPU_0(pVM);
2053 AssertCompile( RT_ELEMENTS(pVCpu0->nem.s.vmx.VmcsInfo.au64LbrFromIpMsr)
2054 == RT_ELEMENTS(pVCpu0->nem.s.vmx.VmcsInfo.au64LbrToIpMsr));
2055 if (cLbrStack > RT_ELEMENTS(pVCpu0->nem.s.vmx.VmcsInfo.au64LbrFromIpMsr))
2056 {
2057 LogRelFunc(("LBR stack size of the CPU (%u) exceeds our buffer size\n", cLbrStack));
2058 VMCC_GET_CPU_0(pVM)->nem.s.u32HMError = VMX_UFC_LBR_STACK_SIZE_OVERFLOW;
2059 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2060 }
2061 NOREF(pVCpu0);
2062
2063 /*
2064 * Update the LBR info. to the VM struct. for use later.
2065 */
2066 pVM->nem.s.idLbrTosMsr = idLbrTosMsr;
2067
2068 pVM->nem.s.idLbrFromIpMsrFirst = idLbrFromIpMsrFirst;
2069 pVM->nem.s.idLbrFromIpMsrLast = idLbrFromIpMsrLast;
2070
2071 pVM->nem.s.idLbrToIpMsrFirst = idLbrToIpMsrFirst;
2072 pVM->nem.s.idLbrToIpMsrLast = idLbrToIpMsrLast;
2073 return VINF_SUCCESS;
2074}
2075
2076
2077/**
2078 * Sets up pin-based VM-execution controls in the VMCS.
2079 *
2080 * @returns VBox status code.
2081 * @param pVCpu The cross context virtual CPU structure.
2082 * @param pVmcsInfo The VMCS info. object.
2083 */
2084static int nemR3DarwinVmxSetupVmcsPinCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2085{
2086 //PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2087 uint32_t fVal = g_HmMsrs.u.vmx.PinCtls.n.allowed0; /* Bits set here must always be set. */
2088 uint32_t const fZap = g_HmMsrs.u.vmx.PinCtls.n.allowed1; /* Bits cleared here must always be cleared. */
2089
2090 if (g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_VIRT_NMI)
2091 fVal |= VMX_PIN_CTLS_VIRT_NMI; /* Use virtual NMIs and virtual-NMI blocking features. */
2092
2093#if 0 /** @todo Use preemption timer */
2094 /* Enable the VMX-preemption timer. */
2095 if (pVM->hmr0.s.vmx.fUsePreemptTimer)
2096 {
2097 Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_PREEMPT_TIMER);
2098 fVal |= VMX_PIN_CTLS_PREEMPT_TIMER;
2099 }
2100
2101 /* Enable posted-interrupt processing. */
2102 if (pVM->hm.s.fPostedIntrs)
2103 {
2104 Assert(g_HmMsrs.u.vmx.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT);
2105 Assert(g_HmMsrs.u.vmx.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT);
2106 fVal |= VMX_PIN_CTLS_POSTED_INT;
2107 }
2108#endif
2109
2110 if ((fVal & fZap) != fVal)
2111 {
2112 LogRelFunc(("Invalid pin-based VM-execution controls combo! Cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2113 g_HmMsrs.u.vmx.PinCtls.n.allowed0, fVal, fZap));
2114 pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PIN_EXEC;
2115 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2116 }
2117
2118 /* Commit it to the VMCS and update our cache. */
2119 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PIN_EXEC, fVal);
2120 AssertRC(rc);
2121 pVmcsInfo->u32PinCtls = fVal;
2122
2123 return VINF_SUCCESS;
2124}
2125
2126
2127/**
2128 * Sets up secondary processor-based VM-execution controls in the VMCS.
2129 *
2130 * @returns VBox status code.
2131 * @param pVCpu The cross context virtual CPU structure.
2132 * @param pVmcsInfo The VMCS info. object.
2133 */
2134static int nemR3DarwinVmxSetupVmcsProcCtls2(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2135{
2136 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2137 uint32_t fVal = g_HmMsrs.u.vmx.ProcCtls2.n.allowed0; /* Bits set here must be set in the VMCS. */
2138 uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls2.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2139
2140 /* WBINVD causes a VM-exit. */
2141 if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_WBINVD_EXIT)
2142 fVal |= VMX_PROC_CTLS2_WBINVD_EXIT;
2143
2144 /* Enable the INVPCID instruction if we expose it to the guest and is supported
2145 by the hardware. Without this, guest executing INVPCID would cause a #UD. */
2146 if ( pVM->cpum.ro.GuestFeatures.fInvpcid
2147 && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_INVPCID))
2148 fVal |= VMX_PROC_CTLS2_INVPCID;
2149
2150#if 0 /** @todo */
2151 /* Enable VPID. */
2152 if (pVM->hmr0.s.vmx.fVpid)
2153 fVal |= VMX_PROC_CTLS2_VPID;
2154
2155 if (pVM->hm.s.fVirtApicRegs)
2156 {
2157 /* Enable APIC-register virtualization. */
2158 Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT);
2159 fVal |= VMX_PROC_CTLS2_APIC_REG_VIRT;
2160
2161 /* Enable virtual-interrupt delivery. */
2162 Assert(g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY);
2163 fVal |= VMX_PROC_CTLS2_VIRT_INTR_DELIVERY;
2164 }
2165
2166 /* Virtualize-APIC accesses if supported by the CPU. The virtual-APIC page is
2167 where the TPR shadow resides. */
2168 /** @todo VIRT_X2APIC support, it's mutually exclusive with this. So must be
2169 * done dynamically. */
2170 if (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_APIC_ACCESS)
2171 {
2172 fVal |= VMX_PROC_CTLS2_VIRT_APIC_ACCESS;
2173 hmR0VmxSetupVmcsApicAccessAddr(pVCpu);
2174 }
2175#endif
2176
2177 /* Enable the RDTSCP instruction if we expose it to the guest and is supported
2178 by the hardware. Without this, guest executing RDTSCP would cause a #UD. */
2179 if ( pVM->cpum.ro.GuestFeatures.fRdTscP
2180 && (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_RDTSCP))
2181 fVal |= VMX_PROC_CTLS2_RDTSCP;
2182
2183 /* Enable Pause-Loop exiting. */
2184 if ( (g_HmMsrs.u.vmx.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_PAUSE_LOOP_EXIT)
2185 && pVM->nem.s.cPleGapTicks
2186 && pVM->nem.s.cPleWindowTicks)
2187 {
2188 fVal |= VMX_PROC_CTLS2_PAUSE_LOOP_EXIT;
2189
2190 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PLE_GAP, pVM->nem.s.cPleGapTicks); AssertRC(rc);
2191 rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PLE_WINDOW, pVM->nem.s.cPleWindowTicks); AssertRC(rc);
2192 }
2193
2194 if ((fVal & fZap) != fVal)
2195 {
2196 LogRelFunc(("Invalid secondary processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2197 g_HmMsrs.u.vmx.ProcCtls2.n.allowed0, fVal, fZap));
2198 pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC2;
2199 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2200 }
2201
2202 /* Commit it to the VMCS and update our cache. */
2203 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC2, fVal);
2204 AssertRC(rc);
2205 pVmcsInfo->u32ProcCtls2 = fVal;
2206
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/**
2212 * Enables native access for the given MSR.
2213 *
2214 * @returns VBox status code.
2215 * @param pVCpu The cross context virtual CPU structure.
2216 * @param idMsr The MSR to enable native access for.
2217 */
2218static int nemR3DarwinMsrSetNative(PVMCPUCC pVCpu, uint32_t idMsr)
2219{
2220 hv_return_t hrc = hv_vcpu_enable_native_msr(pVCpu->nem.s.hVCpuId, idMsr, true /*enable*/);
2221 if (hrc == HV_SUCCESS)
2222 return VINF_SUCCESS;
2223
2224 return nemR3DarwinHvSts2Rc(hrc);
2225}
2226
2227
2228/**
2229 * Sets the MSR to managed for the given vCPU allowing the guest to access it.
2230 *
2231 * @returns VBox status code.
2232 * @param pVCpu The cross context virtual CPU structure.
2233 * @param idMsr The MSR to enable managed access for.
2234 * @param fMsrPerm The MSR permissions flags.
2235 */
2236static int nemR3DarwinMsrSetManaged(PVMCPUCC pVCpu, uint32_t idMsr, hv_msr_flags_t fMsrPerm)
2237{
2238 Assert(hv_vcpu_enable_managed_msr);
2239
2240 hv_return_t hrc = hv_vcpu_enable_managed_msr(pVCpu->nem.s.hVCpuId, idMsr, true /*enable*/);
2241 if (hrc == HV_SUCCESS)
2242 {
2243 hrc = hv_vcpu_set_msr_access(pVCpu->nem.s.hVCpuId, idMsr, fMsrPerm);
2244 if (hrc == HV_SUCCESS)
2245 return VINF_SUCCESS;
2246 }
2247
2248 return nemR3DarwinHvSts2Rc(hrc);
2249}
2250
2251
2252/**
2253 * Sets up the MSR permissions which don't change through the lifetime of the VM.
2254 *
2255 * @returns VBox status code.
2256 * @param pVCpu The cross context virtual CPU structure.
2257 * @param pVmcsInfo The VMCS info. object.
2258 */
2259static int nemR3DarwinSetupVmcsMsrPermissions(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2260{
2261 RT_NOREF(pVmcsInfo);
2262
2263 /*
2264 * The guest can access the following MSRs (read, write) without causing
2265 * VM-exits; they are loaded/stored automatically using fields in the VMCS.
2266 */
2267 PVMCC pVM = pVCpu->CTX_SUFF(pVM);
2268 int rc;
2269 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SYSENTER_CS); AssertRCReturn(rc, rc);
2270 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SYSENTER_ESP); AssertRCReturn(rc, rc);
2271 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SYSENTER_EIP); AssertRCReturn(rc, rc);
2272 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_GS_BASE); AssertRCReturn(rc, rc);
2273 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_FS_BASE); AssertRCReturn(rc, rc);
2274
2275 /*
2276 * The IA32_PRED_CMD and IA32_FLUSH_CMD MSRs are write-only and has no state
2277 * associated with then. We never need to intercept access (writes need to be
2278 * executed without causing a VM-exit, reads will #GP fault anyway).
2279 *
2280 * The IA32_SPEC_CTRL MSR is read/write and has state. We allow the guest to
2281 * read/write them. We swap the guest/host MSR value using the
2282 * auto-load/store MSR area.
2283 */
2284 if (pVM->cpum.ro.GuestFeatures.fIbpb)
2285 {
2286 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_PRED_CMD);
2287 AssertRCReturn(rc, rc);
2288 }
2289#if 0 /* Doesn't work. */
2290 if (pVM->cpum.ro.GuestFeatures.fFlushCmd)
2291 {
2292 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_FLUSH_CMD);
2293 AssertRCReturn(rc, rc);
2294 }
2295#endif
2296 if (pVM->cpum.ro.GuestFeatures.fIbrs)
2297 {
2298 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_IA32_SPEC_CTRL);
2299 AssertRCReturn(rc, rc);
2300 }
2301
2302 /*
2303 * Allow full read/write access for the following MSRs (mandatory for VT-x)
2304 * required for 64-bit guests.
2305 */
2306 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_LSTAR); AssertRCReturn(rc, rc);
2307 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K6_STAR); AssertRCReturn(rc, rc);
2308 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_SF_MASK); AssertRCReturn(rc, rc);
2309 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_KERNEL_GS_BASE); AssertRCReturn(rc, rc);
2310
2311 /* Required for enabling the RDTSCP instruction. */
2312 rc = nemR3DarwinMsrSetNative(pVCpu, MSR_K8_TSC_AUX); AssertRCReturn(rc, rc);
2313
2314 /* Last Branch Record. */
2315 if (pVM->nem.s.fLbr)
2316 {
2317 uint32_t const idFromIpMsrStart = pVM->nem.s.idLbrFromIpMsrFirst;
2318 uint32_t const idToIpMsrStart = pVM->nem.s.idLbrToIpMsrFirst;
2319 uint32_t const cLbrStack = pVM->nem.s.idLbrFromIpMsrLast - pVM->nem.s.idLbrFromIpMsrFirst + 1;
2320 Assert(cLbrStack <= 32);
2321 for (uint32_t i = 0; i < cLbrStack; i++)
2322 {
2323 rc = nemR3DarwinMsrSetManaged(pVCpu, idFromIpMsrStart + i, HV_MSR_READ); AssertRCReturn(rc, rc);
2324
2325 /* Some CPUs don't have a Branch-To-IP MSR (P4 and related Xeons). */
2326 if (idToIpMsrStart != 0)
2327 {
2328 rc = nemR3DarwinMsrSetManaged(pVCpu, idToIpMsrStart + i, HV_MSR_READ); AssertRCReturn(rc, rc);
2329 }
2330 }
2331
2332 rc = nemR3DarwinMsrSetManaged(pVCpu, pVM->nem.s.idLbrTosMsr, HV_MSR_READ); AssertRCReturn(rc, rc);
2333 }
2334
2335 return VINF_SUCCESS;
2336}
2337
2338
2339/**
2340 * Sets up processor-based VM-execution controls in the VMCS.
2341 *
2342 * @returns VBox status code.
2343 * @param pVCpu The cross context virtual CPU structure.
2344 * @param pVmcsInfo The VMCS info. object.
2345 */
2346static int nemR3DarwinVmxSetupVmcsProcCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2347{
2348 uint32_t fVal = g_HmMsrs.u.vmx.ProcCtls.n.allowed0; /* Bits set here must be set in the VMCS. */
2349 uint32_t const fZap = g_HmMsrs.u.vmx.ProcCtls.n.allowed1; /* Bits cleared here must be cleared in the VMCS. */
2350
2351 fVal |= VMX_PROC_CTLS_HLT_EXIT /* HLT causes a VM-exit. */
2352// | VMX_PROC_CTLS_USE_TSC_OFFSETTING /* Use TSC-offsetting. */
2353 | VMX_PROC_CTLS_MOV_DR_EXIT /* MOV DRx causes a VM-exit. */
2354 | VMX_PROC_CTLS_UNCOND_IO_EXIT /* All IO instructions cause a VM-exit. */
2355 | VMX_PROC_CTLS_RDPMC_EXIT /* RDPMC causes a VM-exit. */
2356 | VMX_PROC_CTLS_MONITOR_EXIT /* MONITOR causes a VM-exit. */
2357 | VMX_PROC_CTLS_MWAIT_EXIT; /* MWAIT causes a VM-exit. */
2358
2359#ifdef HMVMX_ALWAYS_INTERCEPT_CR3_ACCESS
2360 fVal |= VMX_PROC_CTLS_CR3_LOAD_EXIT
2361 | VMX_PROC_CTLS_CR3_STORE_EXIT;
2362#endif
2363
2364 /* We toggle VMX_PROC_CTLS_MOV_DR_EXIT later, check if it's not -always- needed to be set or clear. */
2365 if ( !(g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_MOV_DR_EXIT)
2366 || (g_HmMsrs.u.vmx.ProcCtls.n.allowed0 & VMX_PROC_CTLS_MOV_DR_EXIT))
2367 {
2368 pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PROC_MOV_DRX_EXIT;
2369 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2370 }
2371
2372 /* Use the secondary processor-based VM-execution controls if supported by the CPU. */
2373 if (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
2374 fVal |= VMX_PROC_CTLS_USE_SECONDARY_CTLS;
2375
2376 if ((fVal & fZap) != fVal)
2377 {
2378 LogRelFunc(("Invalid processor-based VM-execution controls combo! cpu=%#RX32 fVal=%#RX32 fZap=%#RX32\n",
2379 g_HmMsrs.u.vmx.ProcCtls.n.allowed0, fVal, fZap));
2380 pVCpu->nem.s.u32HMError = VMX_UFC_CTRL_PROC_EXEC;
2381 return VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO;
2382 }
2383
2384 /* Commit it to the VMCS and update our cache. */
2385 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, fVal);
2386 AssertRC(rc);
2387 pVmcsInfo->u32ProcCtls = fVal;
2388
2389 /* Set up MSR permissions that don't change through the lifetime of the VM. */
2390 rc = nemR3DarwinSetupVmcsMsrPermissions(pVCpu, pVmcsInfo);
2391 AssertRCReturn(rc, rc);
2392
2393 /*
2394 * Set up secondary processor-based VM-execution controls
2395 * (we assume the CPU to always support it as we rely on unrestricted guest execution support).
2396 */
2397 Assert(pVmcsInfo->u32ProcCtls & VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2398 return nemR3DarwinVmxSetupVmcsProcCtls2(pVCpu, pVmcsInfo);
2399}
2400
2401
2402/**
2403 * Sets up miscellaneous (everything other than Pin, Processor and secondary
2404 * Processor-based VM-execution) control fields in the VMCS.
2405 *
2406 * @returns VBox status code.
2407 * @param pVCpu The cross context virtual CPU structure.
2408 * @param pVmcsInfo The VMCS info. object.
2409 */
2410static int nemR3DarwinVmxSetupVmcsMiscCtls(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2411{
2412 int rc = VINF_SUCCESS;
2413 //rc = hmR0VmxSetupVmcsAutoLoadStoreMsrAddrs(pVmcsInfo); TODO
2414 if (RT_SUCCESS(rc))
2415 {
2416 uint64_t const u64Cr0Mask = vmxHCGetFixedCr0Mask(pVCpu);
2417 uint64_t const u64Cr4Mask = vmxHCGetFixedCr4Mask(pVCpu);
2418
2419 rc = nemR3DarwinWriteVmcs64(pVCpu, VMX_VMCS_CTRL_CR0_MASK, u64Cr0Mask); AssertRC(rc);
2420 rc = nemR3DarwinWriteVmcs64(pVCpu, VMX_VMCS_CTRL_CR4_MASK, u64Cr4Mask); AssertRC(rc);
2421
2422 pVmcsInfo->u64Cr0Mask = u64Cr0Mask;
2423 pVmcsInfo->u64Cr4Mask = u64Cr4Mask;
2424
2425 if (pVCpu->CTX_SUFF(pVM)->nem.s.fLbr)
2426 {
2427 rc = nemR3DarwinWriteVmcs64(pVCpu, VMX_VMCS64_GUEST_DEBUGCTL_FULL, MSR_IA32_DEBUGCTL_LBR);
2428 AssertRC(rc);
2429 }
2430 return VINF_SUCCESS;
2431 }
2432 else
2433 LogRelFunc(("Failed to initialize VMCS auto-load/store MSR addresses. rc=%Rrc\n", rc));
2434 return rc;
2435}
2436
2437
2438/**
2439 * Sets up the initial exception bitmap in the VMCS based on static conditions.
2440 *
2441 * We shall setup those exception intercepts that don't change during the
2442 * lifetime of the VM here. The rest are done dynamically while loading the
2443 * guest state.
2444 *
2445 * @param pVCpu The cross context virtual CPU structure.
2446 * @param pVmcsInfo The VMCS info. object.
2447 */
2448static void nemR3DarwinVmxSetupVmcsXcptBitmap(PVMCPUCC pVCpu, PVMXVMCSINFO pVmcsInfo)
2449{
2450 /*
2451 * The following exceptions are always intercepted:
2452 *
2453 * #AC - To prevent the guest from hanging the CPU and for dealing with
2454 * split-lock detecting host configs.
2455 * #DB - To maintain the DR6 state even when intercepting DRx reads/writes and
2456 * recursive #DBs can cause a CPU hang.
2457 */
2458 uint32_t const uXcptBitmap = RT_BIT(X86_XCPT_AC)
2459 | RT_BIT(X86_XCPT_DB);
2460
2461 /* Commit it to the VMCS. */
2462 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_EXCEPTION_BITMAP, uXcptBitmap);
2463 AssertRC(rc);
2464
2465 /* Update our cache of the exception bitmap. */
2466 pVmcsInfo->u32XcptBitmap = uXcptBitmap;
2467}
2468
2469
2470/**
2471 * Initialize the VMCS information field for the given vCPU.
2472 *
2473 * @returns VBox status code.
2474 * @param pVCpu The cross context virtual CPU structure of the
2475 * calling EMT.
2476 */
2477static int nemR3DarwinInitVmcs(PVMCPU pVCpu)
2478{
2479 int rc = nemR3DarwinVmxSetupVmcsPinCtls(pVCpu, &pVCpu->nem.s.VmcsInfo);
2480 if (RT_SUCCESS(rc))
2481 {
2482 rc = nemR3DarwinVmxSetupVmcsProcCtls(pVCpu, &pVCpu->nem.s.VmcsInfo);
2483 if (RT_SUCCESS(rc))
2484 {
2485 rc = nemR3DarwinVmxSetupVmcsMiscCtls(pVCpu, &pVCpu->nem.s.VmcsInfo);
2486 if (RT_SUCCESS(rc))
2487 {
2488 rc = nemR3DarwinReadVmcs32(pVCpu, VMX_VMCS32_CTRL_ENTRY, &pVCpu->nem.s.VmcsInfo.u32EntryCtls);
2489 if (RT_SUCCESS(rc))
2490 {
2491 rc = nemR3DarwinReadVmcs32(pVCpu, VMX_VMCS32_CTRL_EXIT, &pVCpu->nem.s.VmcsInfo.u32ExitCtls);
2492 if (RT_SUCCESS(rc))
2493 {
2494 nemR3DarwinVmxSetupVmcsXcptBitmap(pVCpu, &pVCpu->nem.s.VmcsInfo);
2495 return VINF_SUCCESS;
2496 }
2497 else
2498 LogRelFunc(("Failed to read the exit controls. rc=%Rrc\n", rc));
2499 }
2500 else
2501 LogRelFunc(("Failed to read the entry controls. rc=%Rrc\n", rc));
2502 }
2503 else
2504 LogRelFunc(("Failed to setup miscellaneous controls. rc=%Rrc\n", rc));
2505 }
2506 else
2507 LogRelFunc(("Failed to setup processor-based VM-execution controls. rc=%Rrc\n", rc));
2508 }
2509 else
2510 LogRelFunc(("Failed to setup pin-based controls. rc=%Rrc\n", rc));
2511
2512 return rc;
2513}
2514
2515
2516/**
2517 * Registers statistics for the given vCPU.
2518 *
2519 * @returns VBox status code.
2520 * @param pVM The cross context VM structure.
2521 * @param idCpu The CPU ID.
2522 * @param pNemCpu The NEM CPU structure.
2523 */
2524static int nemR3DarwinStatisticsRegister(PVM pVM, VMCPUID idCpu, PNEMCPU pNemCpu)
2525{
2526#define NEM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
2527 int rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
2528 AssertRC(rc); \
2529 } while (0)
2530#define NEM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
2531 NEM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
2532#define NEM_REG_COUNTER(a, b, desc) NEM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
2533
2534 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR0Read, "/NEM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
2535 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR2Read, "/NEM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
2536 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR3Read, "/NEM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
2537 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR4Read, "/NEM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
2538 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR8Read, "/NEM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
2539 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR0Write, "/NEM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
2540 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR2Write, "/NEM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
2541 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR3Write, "/NEM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
2542 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR4Write, "/NEM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
2543 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitCR8Write, "/NEM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
2544
2545 NEM_REG_COUNTER(&pNemCpu->pVmxStats->StatExitAll, "/NEM/CPU%u/Exit/All", "Total exits (including nested-guest exits).");
2546
2547#ifdef VBOX_WITH_STATISTICS
2548 NEM_REG_PROFILE(&pNemCpu->StatProfGstStateImport, "/NEM/CPU%u/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
2549 NEM_REG_PROFILE(&pNemCpu->StatProfGstStateExport, "/NEM/CPU%u/ExportGuestState", "Profiling of exporting guest state from hardware after VM-exit.");
2550
2551 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
2552 {
2553 const char *pszExitName = HMGetVmxExitName(j);
2554 if (pszExitName)
2555 {
2556 int rc = STAMR3RegisterF(pVM, &pNemCpu->pVmxStats->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
2557 STAMUNIT_OCCURENCES, pszExitName, "/NEM/CPU%u/Exit/Reason/%02x", idCpu, j);
2558 AssertRCReturn(rc, rc);
2559 }
2560 }
2561#endif
2562
2563 return VINF_SUCCESS;
2564
2565#undef NEM_REG_COUNTER
2566#undef NEM_REG_PROFILE
2567#undef NEM_REG_STAT
2568}
2569
2570
2571/**
2572 * Displays the HM Last-Branch-Record info. for the guest.
2573 *
2574 * @param pVM The cross context VM structure.
2575 * @param pHlp The info helper functions.
2576 * @param pszArgs Arguments, ignored.
2577 */
2578static DECLCALLBACK(void) nemR3DarwinInfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2579{
2580 NOREF(pszArgs);
2581 PVMCPU pVCpu = VMMGetCpu(pVM);
2582 if (!pVCpu)
2583 pVCpu = pVM->apCpusR3[0];
2584
2585 Assert(pVM->nem.s.fLbr);
2586
2587 PCVMXVMCSINFOSHARED pVmcsInfoShared = &pVCpu->nem.s.vmx.VmcsInfo;
2588 uint32_t const cLbrStack = pVM->nem.s.idLbrFromIpMsrLast - pVM->nem.s.idLbrFromIpMsrFirst + 1;
2589
2590 /** @todo r=ramshankar: The index technically varies depending on the CPU, but
2591 * 0xf should cover everything we support thus far. Fix if necessary
2592 * later. */
2593 uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
2594 if (idxTopOfStack > cLbrStack)
2595 {
2596 pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
2597 idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
2598 return;
2599 }
2600
2601 /*
2602 * Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
2603 */
2604 pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
2605 uint32_t idxCurrent = idxTopOfStack;
2606 Assert(idxTopOfStack < cLbrStack);
2607 Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
2608 Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
2609 for (;;)
2610 {
2611 if (pVM->nem.s.idLbrToIpMsrFirst)
2612 pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
2613 pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
2614 else
2615 pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
2616
2617 idxCurrent = (idxCurrent - 1) % cLbrStack;
2618 if (idxCurrent == idxTopOfStack)
2619 break;
2620 }
2621}
2622
2623
2624/**
2625 * Try initialize the native API.
2626 *
2627 * This may only do part of the job, more can be done in
2628 * nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
2629 *
2630 * @returns VBox status code.
2631 * @param pVM The cross context VM structure.
2632 * @param fFallback Whether we're in fallback mode or use-NEM mode. In
2633 * the latter we'll fail if we cannot initialize.
2634 * @param fForced Whether the HMForced flag is set and we should
2635 * fail if we cannot initialize.
2636 */
2637int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
2638{
2639 AssertReturn(!pVM->nem.s.fCreatedVm, VERR_WRONG_ORDER);
2640
2641 /*
2642 * Some state init.
2643 */
2644 PCFGMNODE pCfgNem = CFGMR3GetChild(CFGMR3GetRoot(pVM), "NEM/");
2645
2646 /** @cfgm{/NEM/VmxPleGap, uint32_t, 0}
2647 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
2648 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
2649 * latest PAUSE instruction to be start of a new PAUSE loop.
2650 */
2651 int rc = CFGMR3QueryU32Def(pCfgNem, "VmxPleGap", &pVM->nem.s.cPleGapTicks, 0);
2652 AssertRCReturn(rc, rc);
2653
2654 /** @cfgm{/NEM/VmxPleWindow, uint32_t, 0}
2655 * The pause-filter exiting window in TSC ticks. When the number of ticks
2656 * between the current PAUSE instruction and first PAUSE of a loop exceeds
2657 * VmxPleWindow, a VM-exit is triggered.
2658 *
2659 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
2660 */
2661 rc = CFGMR3QueryU32Def(pCfgNem, "VmxPleWindow", &pVM->nem.s.cPleWindowTicks, 0);
2662 AssertRCReturn(rc, rc);
2663
2664 /** @cfgm{/NEM/VmxLbr, bool, false}
2665 * Whether to enable LBR for the guest. This is disabled by default as it's only
2666 * useful while debugging and enabling it causes a noticeable performance hit. */
2667 rc = CFGMR3QueryBoolDef(pCfgNem, "VmxLbr", &pVM->nem.s.fLbr, false);
2668 AssertRCReturn(rc, rc);
2669
2670 /*
2671 * Error state.
2672 * The error message will be non-empty on failure and 'rc' will be set too.
2673 */
2674 RTERRINFOSTATIC ErrInfo;
2675 PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
2676 rc = nemR3DarwinLoadHv(fForced, pErrInfo);
2677 if (RT_SUCCESS(rc))
2678 {
2679 if ( !hv_vcpu_enable_managed_msr
2680 && pVM->nem.s.fLbr)
2681 {
2682 LogRel(("NEM: LBR recording is disabled because the Hypervisor API misses hv_vcpu_enable_managed_msr/hv_vcpu_set_msr_access functionality\n"));
2683 pVM->nem.s.fLbr = false;
2684 }
2685
2686 if (hv_vcpu_run_until)
2687 {
2688 struct mach_timebase_info TimeInfo;
2689
2690 if (mach_timebase_info(&TimeInfo) == KERN_SUCCESS)
2691 {
2692 pVM->nem.s.cMachTimePerNs = RT_MIN(1, (double)TimeInfo.denom / (double)TimeInfo.numer);
2693 LogRel(("NEM: cMachTimePerNs=%llu (TimeInfo.numer=%u TimeInfo.denom=%u)\n",
2694 pVM->nem.s.cMachTimePerNs, TimeInfo.numer, TimeInfo.denom));
2695 }
2696 else
2697 hv_vcpu_run_until = NULL; /* To avoid running forever (TM asserts when the guest runs for longer than 4 seconds). */
2698 }
2699
2700 hv_return_t hrc = hv_vm_create(HV_VM_DEFAULT);
2701 if (hrc == HV_SUCCESS)
2702 {
2703 if (hv_vm_space_create)
2704 {
2705 hrc = hv_vm_space_create(&pVM->nem.s.uVmAsid);
2706 if (hrc == HV_SUCCESS)
2707 {
2708 LogRel(("NEM: Successfully created ASID: %u\n", pVM->nem.s.uVmAsid));
2709 pVM->nem.s.fCreatedAsid = true;
2710 }
2711 else
2712 LogRel(("NEM: Failed to create ASID for VM (hrc=%#x), continuing...\n", pVM->nem.s.uVmAsid));
2713 }
2714 pVM->nem.s.fCreatedVm = true;
2715
2716 /* Register release statistics */
2717 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2718 {
2719 PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
2720 PVMXSTATISTICS pVmxStats = (PVMXSTATISTICS)RTMemAllocZ(sizeof(*pVmxStats));
2721 if (RT_LIKELY(pVmxStats))
2722 {
2723 pNemCpu->pVmxStats = pVmxStats;
2724 rc = nemR3DarwinStatisticsRegister(pVM, idCpu, pNemCpu);
2725 AssertRC(rc);
2726 }
2727 else
2728 {
2729 rc = VERR_NO_MEMORY;
2730 break;
2731 }
2732 }
2733
2734 if (RT_SUCCESS(rc))
2735 {
2736 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
2737 Log(("NEM: Marked active!\n"));
2738 PGMR3EnableNemMode(pVM);
2739 }
2740 }
2741 else
2742 rc = RTErrInfoSetF(pErrInfo, VERR_NEM_INIT_FAILED,
2743 "hv_vm_create() failed: %#x", hrc);
2744 }
2745
2746 /*
2747 * We only fail if in forced mode, otherwise just log the complaint and return.
2748 */
2749 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API || RTErrInfoIsSet(pErrInfo));
2750 if ( (fForced || !fFallback)
2751 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
2752 return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
2753
2754 if (pVM->nem.s.fLbr)
2755 {
2756 rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the NEM LBR info.", nemR3DarwinInfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
2757 AssertRCReturn(rc, rc);
2758 }
2759
2760 if (RTErrInfoIsSet(pErrInfo))
2761 LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
2762 return VINF_SUCCESS;
2763}
2764
2765
2766/**
2767 * Worker to create the vCPU handle on the EMT running it later on (as required by HV).
2768 *
2769 * @returns VBox status code
2770 * @param pVM The VM handle.
2771 * @param pVCpu The vCPU handle.
2772 * @param idCpu ID of the CPU to create.
2773 */
2774static DECLCALLBACK(int) nemR3DarwinNativeInitVCpuOnEmt(PVM pVM, PVMCPU pVCpu, VMCPUID idCpu)
2775{
2776 hv_return_t hrc = hv_vcpu_create(&pVCpu->nem.s.hVCpuId, HV_VCPU_DEFAULT);
2777 if (hrc != HV_SUCCESS)
2778 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
2779 "Call to hv_vcpu_create failed on vCPU %u: %#x (%Rrc)", idCpu, hrc, nemR3DarwinHvSts2Rc(hrc));
2780
2781 if (idCpu == 0)
2782 {
2783 /* First call initializs the MSR structure holding the capabilities of the host CPU. */
2784 int rc = nemR3DarwinCapsInit();
2785 AssertRCReturn(rc, rc);
2786
2787 if (hv_vmx_vcpu_get_cap_write_vmcs)
2788 {
2789 /* Log the VMCS field write capabilities. */
2790 for (uint32_t i = 0; i < RT_ELEMENTS(g_aVmcsFieldsCap); i++)
2791 {
2792 uint64_t u64Allowed0 = 0;
2793 uint64_t u64Allowed1 = 0;
2794
2795 hrc = hv_vmx_vcpu_get_cap_write_vmcs(pVCpu->nem.s.hVCpuId, g_aVmcsFieldsCap[i].u32VmcsFieldId,
2796 &u64Allowed0, &u64Allowed1);
2797 if (hrc == HV_SUCCESS)
2798 {
2799 if (g_aVmcsFieldsCap[i].f64Bit)
2800 LogRel(("NEM: %s = (allowed_0=%#016RX64 allowed_1=%#016RX64)\n",
2801 g_aVmcsFieldsCap[i].pszVmcsField, u64Allowed0, u64Allowed1));
2802 else
2803 LogRel(("NEM: %s = (allowed_0=%#08RX32 allowed_1=%#08RX32)\n",
2804 g_aVmcsFieldsCap[i].pszVmcsField, (uint32_t)u64Allowed0, (uint32_t)u64Allowed1));
2805
2806 uint32_t cBits = g_aVmcsFieldsCap[i].f64Bit ? 64 : 32;
2807 for (uint32_t iBit = 0; iBit < cBits; iBit++)
2808 {
2809 bool fAllowed0 = RT_BOOL(u64Allowed0 & RT_BIT_64(iBit));
2810 bool fAllowed1 = RT_BOOL(u64Allowed1 & RT_BIT_64(iBit));
2811
2812 if (!fAllowed0 && !fAllowed1)
2813 LogRel(("NEM: Bit %02u = Must NOT be set\n", iBit));
2814 else if (!fAllowed0 && fAllowed1)
2815 LogRel(("NEM: Bit %02u = Can be set or not be set\n", iBit));
2816 else if (fAllowed0 && !fAllowed1)
2817 LogRel(("NEM: Bit %02u = UNDEFINED (AppleHV error)!\n", iBit));
2818 else if (fAllowed0 && fAllowed1)
2819 LogRel(("NEM: Bit %02u = MUST be set\n", iBit));
2820 else
2821 AssertFailed();
2822 }
2823 }
2824 else
2825 LogRel(("NEM: %s = failed to query (hrc=%d)\n", g_aVmcsFieldsCap[i].pszVmcsField, hrc));
2826 }
2827 }
2828 }
2829
2830 int rc = nemR3DarwinInitVmcs(pVCpu);
2831 AssertRCReturn(rc, rc);
2832
2833 if (pVM->nem.s.fCreatedAsid)
2834 {
2835 hrc = hv_vcpu_set_space(pVCpu->nem.s.hVCpuId, pVM->nem.s.uVmAsid);
2836 AssertReturn(hrc == HV_SUCCESS, VERR_NEM_VM_CREATE_FAILED);
2837 }
2838
2839 ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
2840
2841 return VINF_SUCCESS;
2842}
2843
2844
2845/**
2846 * Worker to destroy the vCPU handle on the EMT running it later on (as required by HV).
2847 *
2848 * @returns VBox status code
2849 * @param pVCpu The vCPU handle.
2850 */
2851static DECLCALLBACK(int) nemR3DarwinNativeTermVCpuOnEmt(PVMCPU pVCpu)
2852{
2853 hv_return_t hrc = hv_vcpu_set_space(pVCpu->nem.s.hVCpuId, 0 /*asid*/);
2854 Assert(hrc == HV_SUCCESS);
2855
2856 hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpuId);
2857 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
2858 return VINF_SUCCESS;
2859}
2860
2861
2862/**
2863 * Worker to setup the TPR shadowing feature if available on the CPU and the VM has an APIC enabled.
2864 *
2865 * @returns VBox status code
2866 * @param pVM The VM handle.
2867 * @param pVCpu The vCPU handle.
2868 */
2869static DECLCALLBACK(int) nemR3DarwinNativeInitTprShadowing(PVM pVM, PVMCPU pVCpu)
2870{
2871 PVMXVMCSINFO pVmcsInfo = &pVCpu->nem.s.VmcsInfo;
2872 uint32_t fVal = pVmcsInfo->u32ProcCtls;
2873
2874 /* Use TPR shadowing if supported by the CPU. */
2875 if ( PDMHasApic(pVM)
2876 && (g_HmMsrs.u.vmx.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TPR_SHADOW))
2877 {
2878 fVal |= VMX_PROC_CTLS_USE_TPR_SHADOW; /* CR8 reads from the Virtual-APIC page. */
2879 /* CR8 writes cause a VM-exit based on TPR threshold. */
2880 Assert(!(fVal & VMX_PROC_CTLS_CR8_STORE_EXIT));
2881 Assert(!(fVal & VMX_PROC_CTLS_CR8_LOAD_EXIT));
2882 }
2883 else
2884 {
2885 fVal |= VMX_PROC_CTLS_CR8_STORE_EXIT /* CR8 reads cause a VM-exit. */
2886 | VMX_PROC_CTLS_CR8_LOAD_EXIT; /* CR8 writes cause a VM-exit. */
2887 }
2888
2889 /* Commit it to the VMCS and update our cache. */
2890 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_PROC_EXEC, fVal);
2891 AssertRC(rc);
2892 pVmcsInfo->u32ProcCtls = fVal;
2893
2894 return VINF_SUCCESS;
2895}
2896
2897
2898/**
2899 * This is called after CPUMR3Init is done.
2900 *
2901 * @returns VBox status code.
2902 * @param pVM The VM handle..
2903 */
2904int nemR3NativeInitAfterCPUM(PVM pVM)
2905{
2906 /*
2907 * Validate sanity.
2908 */
2909 AssertReturn(!pVM->nem.s.fCreatedEmts, VERR_WRONG_ORDER);
2910 AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
2911
2912 if (pVM->nem.s.fLbr)
2913 {
2914 int rc = nemR3DarwinSetupLbrMsrRange(pVM);
2915 AssertRCReturn(rc, rc);
2916 }
2917
2918 /*
2919 * Setup the EMTs.
2920 */
2921 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2922 {
2923 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2924
2925 int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitVCpuOnEmt, 3, pVM, pVCpu, idCpu);
2926 if (RT_FAILURE(rc))
2927 {
2928 /* Rollback. */
2929 while (idCpu--)
2930 VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeTermVCpuOnEmt, 1, pVCpu);
2931
2932 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Call to hv_vcpu_create failed: %Rrc", rc);
2933 }
2934 }
2935
2936 pVM->nem.s.fCreatedEmts = true;
2937 return VINF_SUCCESS;
2938}
2939
2940
2941int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2942{
2943 if (enmWhat == VMINITCOMPLETED_RING3)
2944 {
2945 /* Now that PDM is initialized the APIC state is known in order to enable the TPR shadowing feature on all EMTs. */
2946 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2947 {
2948 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2949
2950 int rc = VMR3ReqCallWait(pVM, idCpu, (PFNRT)nemR3DarwinNativeInitTprShadowing, 2, pVM, pVCpu);
2951 if (RT_FAILURE(rc))
2952 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "Setting up TPR shadowing failed: %Rrc", rc);
2953 }
2954 }
2955 return VINF_SUCCESS;
2956}
2957
2958
2959int nemR3NativeTerm(PVM pVM)
2960{
2961 /*
2962 * Delete the VM.
2963 */
2964
2965 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu--)
2966 {
2967 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2968
2969 /*
2970 * Need to do this or hv_vm_space_destroy() fails later on (on 10.15 at least). Could've been documented in
2971 * API reference so I wouldn't have to decompile the kext to find this out but we are talking
2972 * about Apple here unfortunately, API documentation is not their strong suit...
2973 * Would have been of course even better to just automatically drop the address space reference when the vCPU
2974 * gets destroyed.
2975 */
2976 hv_return_t hrc = hv_vcpu_set_space(pVCpu->nem.s.hVCpuId, 0 /*asid*/);
2977 Assert(hrc == HV_SUCCESS);
2978
2979 /*
2980 * Apple's documentation states that the vCPU should be destroyed
2981 * on the thread running the vCPU but as all the other EMTs are gone
2982 * at this point, destroying the VM would hang.
2983 *
2984 * We seem to be at luck here though as destroying apparently works
2985 * from EMT(0) as well.
2986 */
2987 hrc = hv_vcpu_destroy(pVCpu->nem.s.hVCpuId);
2988 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
2989
2990 if (pVCpu->nem.s.pVmxStats)
2991 {
2992 RTMemFree(pVCpu->nem.s.pVmxStats);
2993 pVCpu->nem.s.pVmxStats = NULL;
2994 }
2995 }
2996
2997 pVM->nem.s.fCreatedEmts = false;
2998
2999 if (pVM->nem.s.fCreatedAsid)
3000 {
3001 hv_return_t hrc = hv_vm_space_destroy(pVM->nem.s.uVmAsid);
3002 Assert(hrc == HV_SUCCESS); RT_NOREF(hrc);
3003 pVM->nem.s.fCreatedAsid = false;
3004 }
3005
3006 if (pVM->nem.s.fCreatedVm)
3007 {
3008 hv_return_t hrc = hv_vm_destroy();
3009 if (hrc != HV_SUCCESS)
3010 LogRel(("NEM: hv_vm_destroy() failed with %#x\n", hrc));
3011
3012 pVM->nem.s.fCreatedVm = false;
3013 }
3014 return VINF_SUCCESS;
3015}
3016
3017
3018/**
3019 * VM reset notification.
3020 *
3021 * @param pVM The cross context VM structure.
3022 */
3023void nemR3NativeReset(PVM pVM)
3024{
3025 RT_NOREF(pVM);
3026}
3027
3028
3029/**
3030 * Reset CPU due to INIT IPI or hot (un)plugging.
3031 *
3032 * @param pVCpu The cross context virtual CPU structure of the CPU being
3033 * reset.
3034 * @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
3035 */
3036void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
3037{
3038 RT_NOREF(fInitIpi);
3039 ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3040}
3041
3042
3043VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
3044{
3045 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 <=\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags));
3046#ifdef LOG_ENABLED
3047 if (LogIs3Enabled())
3048 nemR3DarwinLogState(pVM, pVCpu);
3049#endif
3050
3051 AssertReturn(NEMR3CanExecuteGuest(pVM, pVCpu), VERR_NEM_IPE_9);
3052
3053 /*
3054 * Try switch to NEM runloop state.
3055 */
3056 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
3057 { /* likely */ }
3058 else
3059 {
3060 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
3061 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
3062 return VINF_SUCCESS;
3063 }
3064
3065 /*
3066 * The run loop.
3067 *
3068 * Current approach to state updating to use the sledgehammer and sync
3069 * everything every time. This will be optimized later.
3070 */
3071
3072 VMXTRANSIENT VmxTransient;
3073 RT_ZERO(VmxTransient);
3074 VmxTransient.pVmcsInfo = &pVCpu->nem.s.VmcsInfo;
3075
3076 /*
3077 * Poll timers and run for a bit.
3078 */
3079 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
3080 * the whole polling job when timers have changed... */
3081 uint64_t offDeltaIgnored;
3082 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
3083
3084 const bool fSingleStepping = DBGFIsStepping(pVCpu);
3085 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
3086 for (unsigned iLoop = 0;; iLoop++)
3087 {
3088 /*
3089 * Check and process force flag actions, some of which might require us to go back to ring-3.
3090 */
3091 rcStrict = vmxHCCheckForceFlags(pVCpu, false /*fIsNestedGuest*/, fSingleStepping);
3092 if (rcStrict == VINF_SUCCESS)
3093 { /*likely */ }
3094 else
3095 {
3096 if (rcStrict == VINF_EM_RAW_TO_R3)
3097 rcStrict = VINF_SUCCESS;
3098 break;
3099 }
3100
3101 /*
3102 * Do not execute in HV if the A20 isn't enabled.
3103 */
3104 if (PGMPhysIsA20Enabled(pVCpu))
3105 { /* likely */ }
3106 else
3107 {
3108 rcStrict = VINF_EM_RESCHEDULE_REM;
3109 LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
3110 break;
3111 }
3112
3113 /*
3114 * Evaluate events to be injected into the guest.
3115 *
3116 * Events in TRPM can be injected without inspecting the guest state.
3117 * If any new events (interrupts/NMI) are pending currently, we try to set up the
3118 * guest to cause a VM-exit the next time they are ready to receive the event.
3119 */
3120 if (TRPMHasTrap(pVCpu))
3121 vmxHCTrpmTrapToPendingEvent(pVCpu);
3122
3123 uint32_t fIntrState;
3124 rcStrict = vmxHCEvaluatePendingEvent(pVCpu, &pVCpu->nem.s.VmcsInfo, false /*fIsNestedGuest*/, &fIntrState);
3125
3126 /*
3127 * Event injection may take locks (currently the PGM lock for real-on-v86 case) and thus
3128 * needs to be done with longjmps or interrupts + preemption enabled. Event injection might
3129 * also result in triple-faulting the VM.
3130 *
3131 * With nested-guests, the above does not apply since unrestricted guest execution is a
3132 * requirement. Regardless, we do this here to avoid duplicating code elsewhere.
3133 */
3134 rcStrict = vmxHCInjectPendingEvent(pVCpu, &pVCpu->nem.s.VmcsInfo, false /*fIsNestedGuest*/, fIntrState, fSingleStepping);
3135 if (RT_LIKELY(rcStrict == VINF_SUCCESS))
3136 { /* likely */ }
3137 else
3138 {
3139 AssertMsg(rcStrict == VINF_EM_RESET || (rcStrict == VINF_EM_DBG_STEPPED && fSingleStepping),
3140 ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
3141 break;
3142 }
3143
3144 int rc = nemR3DarwinExportGuestState(pVM, pVCpu, &VmxTransient);
3145 AssertRCReturn(rc, rc);
3146
3147 LogFlowFunc(("Running vCPU\n"));
3148 pVCpu->nem.s.Event.fPending = false;
3149
3150 TMNotifyStartOfExecution(pVM, pVCpu);
3151
3152 Assert(!pVCpu->nem.s.fCtxChanged);
3153 hv_return_t hrc;
3154 if (hv_vcpu_run_until) /** @todo Configur the deadline dynamically based on when the next timer triggers. */
3155 hrc = hv_vcpu_run_until(pVCpu->nem.s.hVCpuId, mach_absolute_time() + 2 * RT_NS_1SEC_64 * pVM->nem.s.cMachTimePerNs);
3156 else
3157 hrc = hv_vcpu_run(pVCpu->nem.s.hVCpuId);
3158
3159 TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
3160
3161 /*
3162 * Sync the TPR shadow with our APIC state.
3163 */
3164 if ( !VmxTransient.fIsNestedGuest
3165 && (pVCpu->nem.s.VmcsInfo.u32ProcCtls & VMX_PROC_CTLS_USE_TPR_SHADOW))
3166 {
3167 uint64_t u64Tpr;
3168 hrc = hv_vcpu_read_register(pVCpu->nem.s.hVCpuId, HV_X86_TPR, &u64Tpr);
3169 Assert(hrc == HV_SUCCESS);
3170
3171 if (VmxTransient.u8GuestTpr != (uint8_t)u64Tpr)
3172 {
3173 rc = APICSetTpr(pVCpu, (uint8_t)u64Tpr);
3174 AssertRC(rc);
3175 ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_GUEST_APIC_TPR);
3176 }
3177 }
3178
3179 if (hrc == HV_SUCCESS)
3180 {
3181 /*
3182 * Deal with the message.
3183 */
3184 rcStrict = nemR3DarwinHandleExit(pVM, pVCpu, &VmxTransient);
3185 if (rcStrict == VINF_SUCCESS)
3186 { /* hopefully likely */ }
3187 else
3188 {
3189 LogFlow(("NEM/%u: breaking: nemR3DarwinHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
3190 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
3191 break;
3192 }
3193 //Assert(!pVCpu->cpum.GstCtx.fExtrn);
3194 }
3195 else
3196 {
3197 AssertLogRelMsgFailedReturn(("hv_vcpu_run()) failed for CPU #%u: %#x %u\n",
3198 pVCpu->idCpu, hrc, vmxHCCheckGuestState(pVCpu, &pVCpu->nem.s.VmcsInfo)),
3199 VERR_NEM_IPE_0);
3200 }
3201 } /* the run loop */
3202
3203
3204 /*
3205 * Convert any pending HM events back to TRPM due to premature exits.
3206 *
3207 * This is because execution may continue from IEM and we would need to inject
3208 * the event from there (hence place it back in TRPM).
3209 */
3210 if (pVCpu->nem.s.Event.fPending)
3211 {
3212 vmxHCPendingEventToTrpmTrap(pVCpu);
3213 Assert(!pVCpu->nem.s.Event.fPending);
3214
3215 /* Clear the events from the VMCS. */
3216 int rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS32_CTRL_ENTRY_INTERRUPTION_INFO, 0); AssertRC(rc);
3217 rc = nemR3DarwinWriteVmcs32(pVCpu, VMX_VMCS_GUEST_PENDING_DEBUG_XCPTS, 0); AssertRC(rc);
3218 }
3219
3220
3221 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
3222 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
3223
3224 if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_ALL))
3225 {
3226 /* Try anticipate what we might need. */
3227 uint64_t fImport = NEM_DARWIN_CPUMCTX_EXTRN_MASK_FOR_IEM;
3228 if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
3229 || RT_FAILURE(rcStrict))
3230 fImport = CPUMCTX_EXTRN_ALL;
3231 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC
3232 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
3233 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;
3234
3235 if (pVCpu->cpum.GstCtx.fExtrn & fImport)
3236 {
3237 /* Only import what is external currently. */
3238 int rc2 = nemR3DarwinCopyStateFromHv(pVM, pVCpu, fImport);
3239 if (RT_SUCCESS(rc2))
3240 pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
3241 else if (RT_SUCCESS(rcStrict))
3242 rcStrict = rc2;
3243 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
3244 {
3245 pVCpu->cpum.GstCtx.fExtrn = 0;
3246 ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3247 }
3248 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
3249 }
3250 else
3251 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
3252 }
3253 else
3254 {
3255 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
3256 pVCpu->cpum.GstCtx.fExtrn = 0;
3257 ASMAtomicUoOrU64(&pVCpu->nem.s.fCtxChanged, HM_CHANGED_ALL_GUEST);
3258 }
3259
3260 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n",
3261 pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags, VBOXSTRICTRC_VAL(rcStrict) ));
3262 return rcStrict;
3263}
3264
3265
3266VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
3267{
3268 NOREF(pVM);
3269 return PGMPhysIsA20Enabled(pVCpu);
3270}
3271
3272
3273bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
3274{
3275 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
3276 return false;
3277}
3278
3279
3280/**
3281 * Forced flag notification call from VMEmt.h.
3282 *
3283 * This is only called when pVCpu is in the VMCPUSTATE_STARTED_EXEC_NEM state.
3284 *
3285 * @param pVM The cross context VM structure.
3286 * @param pVCpu The cross context virtual CPU structure of the CPU
3287 * to be notified.
3288 * @param fFlags Notification flags, VMNOTIFYFF_FLAGS_XXX.
3289 */
3290void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
3291{
3292 LogFlowFunc(("pVM=%p pVCpu=%p fFlags=%#x\n", pVM, pVCpu, fFlags));
3293
3294 RT_NOREF(pVM, fFlags);
3295
3296 hv_return_t hrc = hv_vcpu_interrupt(&pVCpu->nem.s.hVCpuId, 1);
3297 if (hrc != HV_SUCCESS)
3298 LogRel(("NEM: hv_vcpu_interrupt(%u, 1) failed with %#x\n", pVCpu->nem.s.hVCpuId, hrc));
3299}
3300
3301
3302VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
3303 uint8_t *pu2State, uint32_t *puNemRange)
3304{
3305 RT_NOREF(pVM, puNemRange);
3306
3307 Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p\n", GCPhys, cb, pvR3));
3308#if defined(VBOX_WITH_PGM_NEM_MODE)
3309 if (pvR3)
3310 {
3311 int rc = nemR3DarwinMap(pVM, GCPhys, pvR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE);
3312 if (RT_SUCCESS(rc))
3313 *pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
3314 else
3315 {
3316 LogRel(("NEMR3NotifyPhysRamRegister: GCPhys=%RGp LB %RGp pvR3=%p rc=%Rrc\n", GCPhys, cb, pvR3, rc));
3317 return VERR_NEM_MAP_PAGES_FAILED;
3318 }
3319 }
3320 return VINF_SUCCESS;
3321#else
3322 RT_NOREF(pVM, GCPhys, cb, pvR3);
3323 return VERR_NEM_MAP_PAGES_FAILED;
3324#endif
3325}
3326
3327
3328VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
3329{
3330 RT_NOREF(pVM);
3331 return false;
3332}
3333
3334
3335VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
3336 void *pvRam, void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
3337{
3338 RT_NOREF(pVM, puNemRange, pvRam, fFlags);
3339
3340 Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d)\n",
3341 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State));
3342
3343#if defined(VBOX_WITH_PGM_NEM_MODE)
3344 /*
3345 * Unmap the RAM we're replacing.
3346 */
3347 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
3348 {
3349 int rc = nemR3DarwinUnmap(pVM, GCPhys, cb);
3350 if (RT_SUCCESS(rc))
3351 { /* likely */ }
3352 else if (pvMmio2)
3353 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rc(ignored)\n",
3354 GCPhys, cb, fFlags, rc));
3355 else
3356 {
3357 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
3358 GCPhys, cb, fFlags, rc));
3359 return VERR_NEM_UNMAP_PAGES_FAILED;
3360 }
3361 }
3362
3363 /*
3364 * Map MMIO2 if any.
3365 */
3366 if (pvMmio2)
3367 {
3368 Assert(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2);
3369 int rc = nemR3DarwinMap(pVM, GCPhys, pvMmio2, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE);
3370 if (RT_SUCCESS(rc))
3371 *pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
3372 else
3373 {
3374 LogRel(("NEMR3NotifyPhysMmioExMapEarly: GCPhys=%RGp LB %RGp fFlags=%#x pvMmio2=%p: Map -> rc=%Rrc\n",
3375 GCPhys, cb, fFlags, pvMmio2, rc));
3376 return VERR_NEM_MAP_PAGES_FAILED;
3377 }
3378 }
3379 else
3380 {
3381 Assert(!(fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2));
3382 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
3383 }
3384
3385#else
3386 RT_NOREF(pVM, GCPhys, cb, pvRam, pvMmio2);
3387 *pu2State = (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE) ? UINT8_MAX : NEM_DARWIN_PAGE_STATE_UNMAPPED;
3388#endif
3389 return VINF_SUCCESS;
3390}
3391
3392
3393VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
3394 void *pvRam, void *pvMmio2, uint32_t *puNemRange)
3395{
3396 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
3397 return VINF_SUCCESS;
3398}
3399
3400
3401VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
3402 void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
3403{
3404 RT_NOREF(pVM, puNemRange);
3405
3406 Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p uNemRange=%#x (%#x)\n",
3407 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
3408
3409 int rc = VINF_SUCCESS;
3410#if defined(VBOX_WITH_PGM_NEM_MODE)
3411 /*
3412 * Unmap the MMIO2 pages.
3413 */
3414 /** @todo If we implement aliasing (MMIO2 page aliased into MMIO range),
3415 * we may have more stuff to unmap even in case of pure MMIO... */
3416 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
3417 {
3418 rc = nemR3DarwinUnmap(pVM, GCPhys, cb);
3419 if (RT_FAILURE(rc))
3420 {
3421 LogRel2(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp fFlags=%#x: Unmap -> rc=%Rrc\n",
3422 GCPhys, cb, fFlags, rc));
3423 rc = VERR_NEM_UNMAP_PAGES_FAILED;
3424 }
3425 }
3426
3427 /*
3428 * Restore the RAM we replaced.
3429 */
3430 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
3431 {
3432 AssertPtr(pvRam);
3433 rc = nemR3DarwinMap(pVM, GCPhys, pvRam, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE);
3434 if (RT_SUCCESS(rc))
3435 { /* likely */ }
3436 else
3437 {
3438 LogRel(("NEMR3NotifyPhysMmioExUnmap: GCPhys=%RGp LB %RGp pvMmio2=%p rc=%Rrc\n", GCPhys, cb, pvMmio2, rc));
3439 rc = VERR_NEM_MAP_PAGES_FAILED;
3440 }
3441 if (pu2State)
3442 *pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
3443 }
3444 /* Mark the pages as unmapped if relevant. */
3445 else if (pu2State)
3446 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
3447
3448 RT_NOREF(pvMmio2);
3449#else
3450 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
3451 if (pu2State)
3452 *pu2State = UINT8_MAX;
3453 rc = VERR_NEM_UNMAP_PAGES_FAILED;
3454#endif
3455 return rc;
3456}
3457
3458
3459VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
3460 void *pvBitmap, size_t cbBitmap)
3461{
3462 RT_NOREF(pVM, GCPhys, cb, uNemRange, pvBitmap, cbBitmap);
3463 AssertFailed();
3464 return VERR_NOT_IMPLEMENTED;
3465}
3466
3467
3468VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
3469 uint8_t *pu2State, uint32_t *puNemRange)
3470{
3471 RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
3472
3473 Log5(("nemR3NativeNotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
3474 *pu2State = UINT8_MAX;
3475 *puNemRange = 0;
3476 return VINF_SUCCESS;
3477}
3478
3479
3480VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
3481 uint32_t fFlags, uint8_t *pu2State, uint32_t *puNemRange)
3482{
3483 Log5(("nemR3NativeNotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
3484 GCPhys, cb, pvPages, fFlags, pu2State, *pu2State, puNemRange, *puNemRange));
3485 *pu2State = UINT8_MAX;
3486
3487#if defined(VBOX_WITH_PGM_NEM_MODE)
3488 /*
3489 * (Re-)map readonly.
3490 */
3491 AssertPtrReturn(pvPages, VERR_INVALID_POINTER);
3492 int rc = nemR3DarwinMap(pVM, GCPhys, pvPages, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_EXECUTE);
3493 if (RT_SUCCESS(rc))
3494 *pu2State = NEM_DARWIN_PAGE_STATE_READABLE;
3495 else
3496 {
3497 LogRel(("nemR3NativeNotifyPhysRomRegisterLate: GCPhys=%RGp LB %RGp pvPages=%p fFlags=%#x rc=%Rrc\n",
3498 GCPhys, cb, pvPages, fFlags, rc));
3499 return VERR_NEM_MAP_PAGES_FAILED;
3500 }
3501 RT_NOREF(pVM, fFlags, puNemRange);
3502 return VINF_SUCCESS;
3503#else
3504 RT_NOREF(pVM, GCPhys, cb, pvPages, fFlags, puNemRange);
3505 return VERR_NEM_MAP_PAGES_FAILED;
3506#endif
3507}
3508
3509
3510VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
3511 RTR3PTR pvMemR3, uint8_t *pu2State)
3512{
3513 RT_NOREF(pVM);
3514
3515 Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
3516 GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
3517
3518 *pu2State = UINT8_MAX;
3519#if defined(VBOX_WITH_PGM_NEM_MODE)
3520 if (pvMemR3)
3521 {
3522 int rc = nemR3DarwinMap(pVM, GCPhys, pvMemR3, cb, NEM_PAGE_PROT_READ | NEM_PAGE_PROT_WRITE | NEM_PAGE_PROT_EXECUTE);
3523 if (RT_SUCCESS(rc))
3524 *pu2State = NEM_DARWIN_PAGE_STATE_WRITABLE;
3525 else
3526 AssertLogRelMsgFailed(("NEMHCNotifyHandlerPhysicalDeregister: nemR3DarwinMap(,%p,%RGp,%RGp,) -> %Rrc\n",
3527 pvMemR3, GCPhys, cb, rc));
3528 }
3529 RT_NOREF(enmKind);
3530#else
3531 RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
3532 AssertFailed();
3533#endif
3534}
3535
3536
3537static int nemHCJustUnmapPage(PVMCC pVM, RTGCPHYS GCPhysDst, uint8_t *pu2State)
3538{
3539 if (*pu2State <= NEM_DARWIN_PAGE_STATE_UNMAPPED)
3540 {
3541 Log5(("nemHCJustUnmapPage: %RGp == unmapped\n", GCPhysDst));
3542 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
3543 return VINF_SUCCESS;
3544 }
3545
3546 int rc = nemR3DarwinUnmap(pVM, GCPhysDst & ~(RTGCPHYS)X86_PAGE_OFFSET_MASK, X86_PAGE_SIZE);
3547 if (RT_SUCCESS(rc))
3548 {
3549 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPage);
3550 *pu2State = NEM_DARWIN_PAGE_STATE_UNMAPPED;
3551 Log5(("nemHCJustUnmapPage: %RGp => unmapped\n", GCPhysDst));
3552 return VINF_SUCCESS;
3553 }
3554 STAM_REL_COUNTER_INC(&pVM->nem.s.StatUnmapPageFailed);
3555 LogRel(("nemHCJustUnmapPage(%RGp): failed! rc=%Rrc\n",
3556 GCPhysDst, rc));
3557 return VERR_NEM_IPE_6;
3558}
3559
3560
3561/**
3562 * Called when the A20 state changes.
3563 *
3564 * @param pVCpu The CPU the A20 state changed on.
3565 * @param fEnabled Whether it was enabled (true) or disabled.
3566 */
3567VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
3568{
3569 Log(("NEMR3NotifySetA20: fEnabled=%RTbool\n", fEnabled));
3570 RT_NOREF(pVCpu, fEnabled);
3571}
3572
3573
3574void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
3575{
3576 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
3577 NOREF(pVM); NOREF(enmKind); NOREF(GCPhys); NOREF(cb);
3578}
3579
3580
3581void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
3582 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
3583{
3584 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
3585 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
3586 NOREF(pVM); NOREF(enmKind); NOREF(GCPhysOld); NOREF(GCPhysNew); NOREF(cb); NOREF(fRestoreAsRAM);
3587}
3588
3589
3590int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
3591 PGMPAGETYPE enmType, uint8_t *pu2State)
3592{
3593 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3594 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3595 RT_NOREF(HCPhys, fPageProt, enmType);
3596
3597 return nemHCJustUnmapPage(pVM, GCPhys, pu2State);
3598}
3599
3600
3601VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
3602 PGMPAGETYPE enmType, uint8_t *pu2State)
3603{
3604 Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3605 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
3606 RT_NOREF(HCPhys, pvR3, fPageProt, enmType)
3607
3608 nemHCJustUnmapPage(pVM, GCPhys, pu2State);
3609}
3610
3611
3612VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
3613 RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
3614{
3615 Log5(("NEMHCNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
3616 GCPhys, HCPhysPrev, HCPhysNew, fPageProt, enmType, *pu2State));
3617 RT_NOREF(HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType);
3618
3619 nemHCJustUnmapPage(pVM, GCPhys, pu2State);
3620}
3621
3622
3623/**
3624 * Interface for importing state on demand (used by IEM).
3625 *
3626 * @returns VBox status code.
3627 * @param pVCpu The cross context CPU structure.
3628 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
3629 */
3630VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
3631{
3632 LogFlowFunc(("pVCpu=%p fWhat=%RX64\n", pVCpu, fWhat));
3633 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
3634
3635 return nemR3DarwinCopyStateFromHv(pVCpu->pVMR3, pVCpu, fWhat);
3636}
3637
3638
3639/**
3640 * Query the CPU tick counter and optionally the TSC_AUX MSR value.
3641 *
3642 * @returns VBox status code.
3643 * @param pVCpu The cross context CPU structure.
3644 * @param pcTicks Where to return the CPU tick count.
3645 * @param puAux Where to return the TSC_AUX register value.
3646 */
3647VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)
3648{
3649 LogFlowFunc(("pVCpu=%p pcTicks=%RX64 puAux=%RX32\n", pVCpu, pcTicks, puAux));
3650 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
3651
3652 int rc = nemR3DarwinMsrRead(pVCpu, MSR_IA32_TSC, pcTicks);
3653 if ( RT_SUCCESS(rc)
3654 && puAux)
3655 {
3656 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_TSC_AUX)
3657 {
3658 uint64_t u64Aux;
3659 rc = nemR3DarwinMsrRead(pVCpu, MSR_K8_TSC_AUX, &u64Aux);
3660 if (RT_SUCCESS(rc))
3661 *puAux = (uint32_t)u64Aux;
3662 }
3663 else
3664 *puAux = CPUMGetGuestTscAux(pVCpu);
3665 }
3666
3667 return rc;
3668}
3669
3670
3671/**
3672 * Resumes CPU clock (TSC) on all virtual CPUs.
3673 *
3674 * This is called by TM when the VM is started, restored, resumed or similar.
3675 *
3676 * @returns VBox status code.
3677 * @param pVM The cross context VM structure.
3678 * @param pVCpu The cross context CPU structure of the calling EMT.
3679 * @param uPausedTscValue The TSC value at the time of pausing.
3680 */
3681VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
3682{
3683 LogFlowFunc(("pVM=%p pVCpu=%p uPausedTscValue=%RX64\n", pVCpu, uPausedTscValue));
3684 VMCPU_ASSERT_EMT_RETURN(pVCpu, VERR_VM_THREAD_NOT_EMT);
3685 AssertReturn(VM_IS_NEM_ENABLED(pVM), VERR_NEM_IPE_9);
3686
3687 hv_return_t hrc = hv_vm_sync_tsc(uPausedTscValue);
3688 if (RT_LIKELY(hrc == HV_SUCCESS))
3689 {
3690 ASMAtomicUoAndU64(&pVCpu->nem.s.fCtxChanged, ~HM_CHANGED_GUEST_TSC_AUX);
3691 return VINF_SUCCESS;
3692 }
3693
3694 return nemR3DarwinHvSts2Rc(hrc);
3695}
3696
3697
3698/**
3699 * Returns features supported by the NEM backend.
3700 *
3701 * @returns Flags of features supported by the native NEM backend.
3702 * @param pVM The cross context VM structure.
3703 */
3704VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
3705{
3706 RT_NOREF(pVM);
3707 /*
3708 * Apple's Hypervisor.framework is not supported if the CPU doesn't support nested paging
3709 * and unrestricted guest execution support so we can safely return these flags here always.
3710 */
3711 return NEM_FEAT_F_NESTED_PAGING | NEM_FEAT_F_FULL_GST_EXEC | NEM_FEAT_F_XSAVE_XRSTOR;
3712}
3713
3714
3715/** @page pg_nem_darwin NEM/darwin - Native Execution Manager, macOS.
3716 *
3717 * @todo Add notes as the implementation progresses...
3718 */
3719
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