VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp@ 92525

Last change on this file since 92525 was 92525, checked in by vboxsync, 3 years ago

VMM/NEM-linux: Exit history updates. bugref:9044
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1/* $Id: NEMR3Native-linux.cpp 92525 2021-11-21 00:08:49Z vboxsync $ */
2/** @file
3 * NEM - Native execution manager, native ring-3 Linux backend.
4 */
5
6/*
7 * Copyright (C) 2021 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_NEM
23#define VMCPU_INCL_CPUM_GST_CTX
24#include <VBox/vmm/nem.h>
25#include <VBox/vmm/iem.h>
26#include <VBox/vmm/em.h>
27#include <VBox/vmm/apic.h>
28#include <VBox/vmm/pdm.h>
29#include <VBox/vmm/trpm.h>
30#include "NEMInternal.h"
31#include <VBox/vmm/vmcc.h>
32
33#include <iprt/alloca.h>
34#include <iprt/string.h>
35#include <iprt/system.h>
36
37#include <errno.h>
38#include <unistd.h>
39#include <sys/ioctl.h>
40#include <sys/fcntl.h>
41#include <sys/mman.h>
42#include <linux/kvm.h>
43
44/*
45 * Supply stuff missing from the kvm.h on the build box.
46 */
47#ifndef KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON /* since 5.4 */
48# define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4
49#endif
50
51
52
53/**
54 * Worker for nemR3NativeInit that gets the hypervisor capabilities.
55 *
56 * @returns VBox status code.
57 * @param pVM The cross context VM structure.
58 * @param pErrInfo Where to always return error info.
59 */
60static int nemR3LnxInitCheckCapabilities(PVM pVM, PRTERRINFO pErrInfo)
61{
62 AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
63
64 /*
65 * Capabilities.
66 */
67 static const struct
68 {
69 const char *pszName;
70 int iCap;
71 uint32_t offNem : 24;
72 uint32_t cbNem : 3;
73 uint32_t fReqNonZero : 1;
74 uint32_t uReserved : 4;
75 } s_aCaps[] =
76 {
77#define CAP_ENTRY__L(a_Define) { #a_Define, a_Define, UINT32_C(0x00ffffff), 0, 0, 0 }
78#define CAP_ENTRY__S(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 0, 0 }
79#define CAP_ENTRY_MS(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 1, 0 }
80#define CAP_ENTRY__U(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 0, 0 }
81#define CAP_ENTRY_ML(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 1, 0 }
82
83 CAP_ENTRY__L(KVM_CAP_IRQCHIP), /* 0 */
84 CAP_ENTRY_ML(KVM_CAP_HLT),
85 CAP_ENTRY__L(KVM_CAP_MMU_SHADOW_CACHE_CONTROL),
86 CAP_ENTRY_ML(KVM_CAP_USER_MEMORY),
87 CAP_ENTRY__L(KVM_CAP_SET_TSS_ADDR),
88 CAP_ENTRY__U(5),
89 CAP_ENTRY__L(KVM_CAP_VAPIC),
90 CAP_ENTRY__L(KVM_CAP_EXT_CPUID),
91 CAP_ENTRY__L(KVM_CAP_CLOCKSOURCE),
92 CAP_ENTRY__L(KVM_CAP_NR_VCPUS),
93 CAP_ENTRY_MS(KVM_CAP_NR_MEMSLOTS, cMaxMemSlots), /* 10 */
94 CAP_ENTRY__L(KVM_CAP_PIT),
95 CAP_ENTRY__L(KVM_CAP_NOP_IO_DELAY),
96 CAP_ENTRY__L(KVM_CAP_PV_MMU),
97 CAP_ENTRY__L(KVM_CAP_MP_STATE),
98 CAP_ENTRY__L(KVM_CAP_COALESCED_MMIO),
99 CAP_ENTRY__L(KVM_CAP_SYNC_MMU),
100 CAP_ENTRY__U(17),
101 CAP_ENTRY__L(KVM_CAP_IOMMU),
102 CAP_ENTRY__U(19), /* Buggy KVM_CAP_JOIN_MEMORY_REGIONS? */
103 CAP_ENTRY__U(20), /* Mon-working KVM_CAP_DESTROY_MEMORY_REGION? */
104 CAP_ENTRY__L(KVM_CAP_DESTROY_MEMORY_REGION_WORKS), /* 21 */
105 CAP_ENTRY__L(KVM_CAP_USER_NMI),
106#ifdef __KVM_HAVE_GUEST_DEBUG
107 CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG),
108#endif
109#ifdef __KVM_HAVE_PIT
110 CAP_ENTRY__L(KVM_CAP_REINJECT_CONTROL),
111#endif
112 CAP_ENTRY__L(KVM_CAP_IRQ_ROUTING),
113 CAP_ENTRY__L(KVM_CAP_IRQ_INJECT_STATUS),
114 CAP_ENTRY__U(27),
115 CAP_ENTRY__U(28),
116 CAP_ENTRY__L(KVM_CAP_ASSIGN_DEV_IRQ),
117 CAP_ENTRY__L(KVM_CAP_JOIN_MEMORY_REGIONS_WORKS), /* 30 */
118#ifdef __KVM_HAVE_MCE
119 CAP_ENTRY__L(KVM_CAP_MCE),
120#endif
121 CAP_ENTRY__L(KVM_CAP_IRQFD),
122#ifdef __KVM_HAVE_PIT
123 CAP_ENTRY__L(KVM_CAP_PIT2),
124#endif
125 CAP_ENTRY__L(KVM_CAP_SET_BOOT_CPU_ID),
126#ifdef __KVM_HAVE_PIT_STATE2
127 CAP_ENTRY__L(KVM_CAP_PIT_STATE2),
128#endif
129 CAP_ENTRY__L(KVM_CAP_IOEVENTFD),
130 CAP_ENTRY__L(KVM_CAP_SET_IDENTITY_MAP_ADDR),
131#ifdef __KVM_HAVE_XEN_HVM
132 CAP_ENTRY__L(KVM_CAP_XEN_HVM),
133#endif
134 CAP_ENTRY_ML(KVM_CAP_ADJUST_CLOCK),
135 CAP_ENTRY__L(KVM_CAP_INTERNAL_ERROR_DATA), /* 40 */
136#ifdef __KVM_HAVE_VCPU_EVENTS
137 CAP_ENTRY_ML(KVM_CAP_VCPU_EVENTS),
138#else
139 CAP_ENTRY_MU(41),
140#endif
141 CAP_ENTRY__L(KVM_CAP_S390_PSW),
142 CAP_ENTRY__L(KVM_CAP_PPC_SEGSTATE),
143 CAP_ENTRY__L(KVM_CAP_HYPERV),
144 CAP_ENTRY__L(KVM_CAP_HYPERV_VAPIC),
145 CAP_ENTRY__L(KVM_CAP_HYPERV_SPIN),
146 CAP_ENTRY__L(KVM_CAP_PCI_SEGMENT),
147 CAP_ENTRY__L(KVM_CAP_PPC_PAIRED_SINGLES),
148 CAP_ENTRY__L(KVM_CAP_INTR_SHADOW),
149#ifdef __KVM_HAVE_DEBUGREGS
150 CAP_ENTRY__L(KVM_CAP_DEBUGREGS), /* 50 */
151#endif
152 CAP_ENTRY__S(KVM_CAP_X86_ROBUST_SINGLESTEP, fRobustSingleStep),
153 CAP_ENTRY__L(KVM_CAP_PPC_OSI),
154 CAP_ENTRY__L(KVM_CAP_PPC_UNSET_IRQ),
155 CAP_ENTRY__L(KVM_CAP_ENABLE_CAP),
156#ifdef __KVM_HAVE_XSAVE
157 CAP_ENTRY_ML(KVM_CAP_XSAVE),
158#else
159 CAP_ENTRY_MU(55),
160#endif
161#ifdef __KVM_HAVE_XCRS
162 CAP_ENTRY_ML(KVM_CAP_XCRS),
163#else
164 CAP_ENTRY_MU(56),
165#endif
166 CAP_ENTRY__L(KVM_CAP_PPC_GET_PVINFO),
167 CAP_ENTRY__L(KVM_CAP_PPC_IRQ_LEVEL),
168 CAP_ENTRY__L(KVM_CAP_ASYNC_PF),
169 CAP_ENTRY__L(KVM_CAP_TSC_CONTROL), /* 60 */
170 CAP_ENTRY__L(KVM_CAP_GET_TSC_KHZ),
171 CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_SREGS),
172 CAP_ENTRY__L(KVM_CAP_SPAPR_TCE),
173 CAP_ENTRY__L(KVM_CAP_PPC_SMT),
174 CAP_ENTRY__L(KVM_CAP_PPC_RMA),
175 CAP_ENTRY__L(KVM_CAP_MAX_VCPUS),
176 CAP_ENTRY__L(KVM_CAP_PPC_HIOR),
177 CAP_ENTRY__L(KVM_CAP_PPC_PAPR),
178 CAP_ENTRY__L(KVM_CAP_SW_TLB),
179 CAP_ENTRY__L(KVM_CAP_ONE_REG), /* 70 */
180 CAP_ENTRY__L(KVM_CAP_S390_GMAP),
181 CAP_ENTRY__L(KVM_CAP_TSC_DEADLINE_TIMER),
182 CAP_ENTRY__L(KVM_CAP_S390_UCONTROL),
183 CAP_ENTRY__L(KVM_CAP_SYNC_REGS),
184 CAP_ENTRY__L(KVM_CAP_PCI_2_3),
185 CAP_ENTRY__L(KVM_CAP_KVMCLOCK_CTRL),
186 CAP_ENTRY__L(KVM_CAP_SIGNAL_MSI),
187 CAP_ENTRY__L(KVM_CAP_PPC_GET_SMMU_INFO),
188 CAP_ENTRY__L(KVM_CAP_S390_COW),
189 CAP_ENTRY__L(KVM_CAP_PPC_ALLOC_HTAB), /* 80 */
190 CAP_ENTRY__L(KVM_CAP_READONLY_MEM),
191 CAP_ENTRY__L(KVM_CAP_IRQFD_RESAMPLE),
192 CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_WATCHDOG),
193 CAP_ENTRY__L(KVM_CAP_PPC_HTAB_FD),
194 CAP_ENTRY__L(KVM_CAP_S390_CSS_SUPPORT),
195 CAP_ENTRY__L(KVM_CAP_PPC_EPR),
196 CAP_ENTRY__L(KVM_CAP_ARM_PSCI),
197 CAP_ENTRY__L(KVM_CAP_ARM_SET_DEVICE_ADDR),
198 CAP_ENTRY__L(KVM_CAP_DEVICE_CTRL),
199 CAP_ENTRY__L(KVM_CAP_IRQ_MPIC), /* 90 */
200 CAP_ENTRY__L(KVM_CAP_PPC_RTAS),
201 CAP_ENTRY__L(KVM_CAP_IRQ_XICS),
202 CAP_ENTRY__L(KVM_CAP_ARM_EL1_32BIT),
203 CAP_ENTRY__L(KVM_CAP_SPAPR_MULTITCE),
204 CAP_ENTRY__L(KVM_CAP_EXT_EMUL_CPUID),
205 CAP_ENTRY__L(KVM_CAP_HYPERV_TIME),
206 CAP_ENTRY__L(KVM_CAP_IOAPIC_POLARITY_IGNORED),
207 CAP_ENTRY__L(KVM_CAP_ENABLE_CAP_VM),
208 CAP_ENTRY__L(KVM_CAP_S390_IRQCHIP),
209 CAP_ENTRY__L(KVM_CAP_IOEVENTFD_NO_LENGTH), /* 100 */
210 CAP_ENTRY__L(KVM_CAP_VM_ATTRIBUTES),
211 CAP_ENTRY__L(KVM_CAP_ARM_PSCI_0_2),
212 CAP_ENTRY__L(KVM_CAP_PPC_FIXUP_HCALL),
213 CAP_ENTRY__L(KVM_CAP_PPC_ENABLE_HCALL),
214 CAP_ENTRY__L(KVM_CAP_CHECK_EXTENSION_VM),
215 CAP_ENTRY__L(KVM_CAP_S390_USER_SIGP),
216 CAP_ENTRY__L(KVM_CAP_S390_VECTOR_REGISTERS),
217 CAP_ENTRY__L(KVM_CAP_S390_MEM_OP),
218 CAP_ENTRY__L(KVM_CAP_S390_USER_STSI),
219 CAP_ENTRY__L(KVM_CAP_S390_SKEYS), /* 110 */
220 CAP_ENTRY__L(KVM_CAP_MIPS_FPU),
221 CAP_ENTRY__L(KVM_CAP_MIPS_MSA),
222 CAP_ENTRY__L(KVM_CAP_S390_INJECT_IRQ),
223 CAP_ENTRY__L(KVM_CAP_S390_IRQ_STATE),
224 CAP_ENTRY__L(KVM_CAP_PPC_HWRNG),
225 CAP_ENTRY__L(KVM_CAP_DISABLE_QUIRKS),
226 CAP_ENTRY__L(KVM_CAP_X86_SMM),
227 CAP_ENTRY__L(KVM_CAP_MULTI_ADDRESS_SPACE),
228 CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_BPS),
229 CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_WPS), /* 120 */
230 CAP_ENTRY__L(KVM_CAP_SPLIT_IRQCHIP),
231 CAP_ENTRY__L(KVM_CAP_IOEVENTFD_ANY_LENGTH),
232 CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC),
233 CAP_ENTRY__L(KVM_CAP_S390_RI),
234 CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_64),
235 CAP_ENTRY__L(KVM_CAP_ARM_PMU_V3),
236 CAP_ENTRY__L(KVM_CAP_VCPU_ATTRIBUTES),
237 CAP_ENTRY__L(KVM_CAP_MAX_VCPU_ID),
238 CAP_ENTRY__L(KVM_CAP_X2APIC_API),
239 CAP_ENTRY__L(KVM_CAP_S390_USER_INSTR0), /* 130 */
240 CAP_ENTRY__L(KVM_CAP_MSI_DEVID),
241 CAP_ENTRY__L(KVM_CAP_PPC_HTM),
242 CAP_ENTRY__L(KVM_CAP_SPAPR_RESIZE_HPT),
243 CAP_ENTRY__L(KVM_CAP_PPC_MMU_RADIX),
244 CAP_ENTRY__L(KVM_CAP_PPC_MMU_HASH_V3),
245 CAP_ENTRY__L(KVM_CAP_IMMEDIATE_EXIT),
246 CAP_ENTRY__L(KVM_CAP_MIPS_VZ),
247 CAP_ENTRY__L(KVM_CAP_MIPS_TE),
248 CAP_ENTRY__L(KVM_CAP_MIPS_64BIT),
249 CAP_ENTRY__L(KVM_CAP_S390_GS), /* 140 */
250 CAP_ENTRY__L(KVM_CAP_S390_AIS),
251 CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_VFIO),
252 CAP_ENTRY__L(KVM_CAP_X86_DISABLE_EXITS),
253 CAP_ENTRY__L(KVM_CAP_ARM_USER_IRQ),
254 CAP_ENTRY__L(KVM_CAP_S390_CMMA_MIGRATION),
255 CAP_ENTRY__L(KVM_CAP_PPC_FWNMI),
256 CAP_ENTRY__L(KVM_CAP_PPC_SMT_POSSIBLE),
257 CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC2),
258 CAP_ENTRY__L(KVM_CAP_HYPERV_VP_INDEX),
259 CAP_ENTRY__L(KVM_CAP_S390_AIS_MIGRATION), /* 150 */
260 CAP_ENTRY__L(KVM_CAP_PPC_GET_CPU_CHAR),
261 CAP_ENTRY__L(KVM_CAP_S390_BPB),
262 CAP_ENTRY__L(KVM_CAP_GET_MSR_FEATURES),
263 CAP_ENTRY__L(KVM_CAP_HYPERV_EVENTFD),
264 CAP_ENTRY__L(KVM_CAP_HYPERV_TLBFLUSH),
265 CAP_ENTRY__L(KVM_CAP_S390_HPAGE_1M),
266 CAP_ENTRY__L(KVM_CAP_NESTED_STATE),
267 CAP_ENTRY__L(KVM_CAP_ARM_INJECT_SERROR_ESR),
268 CAP_ENTRY__L(KVM_CAP_MSR_PLATFORM_INFO),
269 CAP_ENTRY__L(KVM_CAP_PPC_NESTED_HV), /* 160 */
270 CAP_ENTRY__L(KVM_CAP_HYPERV_SEND_IPI),
271 CAP_ENTRY__L(KVM_CAP_COALESCED_PIO),
272 CAP_ENTRY__L(KVM_CAP_HYPERV_ENLIGHTENED_VMCS),
273 CAP_ENTRY__L(KVM_CAP_EXCEPTION_PAYLOAD),
274 CAP_ENTRY__L(KVM_CAP_ARM_VM_IPA_SIZE),
275 CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT),
276 CAP_ENTRY__L(KVM_CAP_HYPERV_CPUID),
277 CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2),
278 CAP_ENTRY__L(KVM_CAP_PPC_IRQ_XIVE),
279 CAP_ENTRY__L(KVM_CAP_ARM_SVE), /* 170 */
280 CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_ADDRESS),
281 CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_GENERIC),
282 CAP_ENTRY__L(KVM_CAP_PMU_EVENT_FILTER),
283 CAP_ENTRY__L(KVM_CAP_ARM_IRQ_LINE_LAYOUT_2),
284 CAP_ENTRY__L(KVM_CAP_HYPERV_DIRECT_TLBFLUSH),
285 CAP_ENTRY__L(KVM_CAP_PPC_GUEST_DEBUG_SSTEP),
286 CAP_ENTRY__L(KVM_CAP_ARM_NISV_TO_USER),
287 CAP_ENTRY__L(KVM_CAP_ARM_INJECT_EXT_DABT),
288 CAP_ENTRY__L(KVM_CAP_S390_VCPU_RESETS),
289 CAP_ENTRY__L(KVM_CAP_S390_PROTECTED), /* 180 */
290 CAP_ENTRY__L(KVM_CAP_PPC_SECURE_GUEST),
291 CAP_ENTRY__L(KVM_CAP_HALT_POLL),
292 CAP_ENTRY__L(KVM_CAP_ASYNC_PF_INT),
293 CAP_ENTRY__L(KVM_CAP_LAST_CPU),
294 CAP_ENTRY__L(KVM_CAP_SMALLER_MAXPHYADDR),
295 CAP_ENTRY__L(KVM_CAP_S390_DIAG318),
296 CAP_ENTRY__L(KVM_CAP_STEAL_TIME),
297 CAP_ENTRY_ML(KVM_CAP_X86_USER_SPACE_MSR), /* (since 5.10) */
298 CAP_ENTRY_ML(KVM_CAP_X86_MSR_FILTER),
299 CAP_ENTRY__L(KVM_CAP_ENFORCE_PV_FEATURE_CPUID), /* 190 */
300 CAP_ENTRY__L(KVM_CAP_SYS_HYPERV_CPUID),
301 CAP_ENTRY__L(KVM_CAP_DIRTY_LOG_RING),
302 CAP_ENTRY__L(KVM_CAP_X86_BUS_LOCK_EXIT),
303 CAP_ENTRY__L(KVM_CAP_PPC_DAWR1),
304 CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG2),
305 CAP_ENTRY__L(KVM_CAP_SGX_ATTRIBUTE),
306 CAP_ENTRY__L(KVM_CAP_VM_COPY_ENC_CONTEXT_FROM),
307 CAP_ENTRY__L(KVM_CAP_PTP_KVM),
308 CAP_ENTRY__U(199),
309 CAP_ENTRY__U(200),
310 CAP_ENTRY__U(201),
311 CAP_ENTRY__U(202),
312 CAP_ENTRY__U(203),
313 CAP_ENTRY__U(204),
314 CAP_ENTRY__U(205),
315 CAP_ENTRY__U(206),
316 CAP_ENTRY__U(207),
317 CAP_ENTRY__U(208),
318 CAP_ENTRY__U(209),
319 CAP_ENTRY__U(210),
320 CAP_ENTRY__U(211),
321 CAP_ENTRY__U(212),
322 CAP_ENTRY__U(213),
323 CAP_ENTRY__U(214),
324 CAP_ENTRY__U(215),
325 CAP_ENTRY__U(216),
326 };
327
328 LogRel(("NEM: KVM capabilities (system):\n"));
329 int rcRet = VINF_SUCCESS;
330 for (unsigned i = 0; i < RT_ELEMENTS(s_aCaps); i++)
331 {
332 int rc = ioctl(pVM->nem.s.fdVm, KVM_CHECK_EXTENSION, s_aCaps[i].iCap);
333 if (rc >= 10)
334 LogRel(("NEM: %36s: %#x (%d)\n", s_aCaps[i].pszName, rc, rc));
335 else if (rc >= 0)
336 LogRel(("NEM: %36s: %d\n", s_aCaps[i].pszName, rc));
337 else
338 LogRel(("NEM: %s failed: %d/%d\n", s_aCaps[i].pszName, rc, errno));
339 switch (s_aCaps[i].cbNem)
340 {
341 case 0:
342 break;
343 case 1:
344 {
345 uint8_t *puValue = (uint8_t *)&pVM->nem.padding[s_aCaps[i].offNem];
346 AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
347 *puValue = (uint8_t)rc;
348 AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
349 break;
350 }
351 case 2:
352 {
353 uint16_t *puValue = (uint16_t *)&pVM->nem.padding[s_aCaps[i].offNem];
354 AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
355 *puValue = (uint16_t)rc;
356 AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
357 break;
358 }
359 case 4:
360 {
361 uint32_t *puValue = (uint32_t *)&pVM->nem.padding[s_aCaps[i].offNem];
362 AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
363 *puValue = (uint32_t)rc;
364 AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
365 break;
366 }
367 default:
368 rcRet = RTErrInfoSetF(pErrInfo, VERR_NEM_IPE_0, "s_aCaps[%u] is bad: cbNem=%#x - %s",
369 i, s_aCaps[i].pszName, s_aCaps[i].cbNem);
370 AssertFailedReturn(rcRet);
371 }
372
373 /*
374 * Is a require non-zero entry zero or failing?
375 */
376 if (s_aCaps[i].fReqNonZero && rc <= 0)
377 rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE,
378 "Required capability '%s' is missing!", s_aCaps[i].pszName);
379 }
380
381 /*
382 * Get per VCpu KVM_RUN MMAP area size.
383 */
384 int rc = ioctl(pVM->nem.s.fdKvm, KVM_GET_VCPU_MMAP_SIZE, 0UL);
385 if ((unsigned)rc < _64M)
386 {
387 pVM->nem.s.cbVCpuMmap = (uint32_t)rc;
388 LogRel(("NEM: %36s: %#x (%d)\n", "KVM_GET_VCPU_MMAP_SIZE", rc, rc));
389 }
390 else if (rc < 0)
391 rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE, "KVM_GET_VCPU_MMAP_SIZE failed: %d", errno);
392 else
393 rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_INIT_FAILED, "Odd KVM_GET_VCPU_MMAP_SIZE value: %#x (%d)", rc, rc);
394
395 /*
396 * Init the slot ID bitmap.
397 */
398 ASMBitSet(&pVM->nem.s.bmSlotIds[0], 0); /* don't use slot 0 */
399 if (pVM->nem.s.cMaxMemSlots < _32K)
400 ASMBitSetRange(&pVM->nem.s.bmSlotIds[0], pVM->nem.s.cMaxMemSlots, _32K);
401 ASMBitSet(&pVM->nem.s.bmSlotIds[0], _32K - 1); /* don't use the last slot */
402
403 return rcRet;
404}
405
406
407/**
408 * Does the early setup of a KVM VM.
409 *
410 * @returns VBox status code.
411 * @param pVM The cross context VM structure.
412 * @param pErrInfo Where to always return error info.
413 */
414static int nemR3LnxInitSetupVm(PVM pVM, PRTERRINFO pErrInfo)
415{
416 AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
417
418 /*
419 * Create the VCpus.
420 */
421 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
422 {
423 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
424
425 /* Create it. */
426 pVCpu->nem.s.fdVCpu = ioctl(pVM->nem.s.fdVm, KVM_CREATE_VCPU, (unsigned long)idCpu);
427 if (pVCpu->nem.s.fdVCpu < 0)
428 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
429 "KVM_CREATE_VCPU failed for VCpu #%u: %d", idCpu, errno);
430
431 /* Map the KVM_RUN area. */
432 pVCpu->nem.s.pRun = (struct kvm_run *)mmap(NULL, pVM->nem.s.cbVCpuMmap, PROT_READ | PROT_WRITE, MAP_SHARED,
433 pVCpu->nem.s.fdVCpu, 0 /*offset*/);
434 if ((void *)pVCpu->nem.s.pRun == MAP_FAILED)
435 return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS, "mmap failed for VCpu #%u: %d", idCpu, errno);
436
437 /* We want all x86 registers and events on each exit. */
438 pVCpu->nem.s.pRun->kvm_valid_regs = KVM_SYNC_X86_REGS | KVM_SYNC_X86_SREGS | KVM_SYNC_X86_EVENTS;
439 }
440 return VINF_SUCCESS;
441}
442
443
444/** @callback_method_impl{FNVMMEMTRENDEZVOUS} */
445static DECLCALLBACK(VBOXSTRICTRC) nemR3LnxFixThreadPoke(PVM pVM, PVMCPU pVCpu, void *pvUser)
446{
447 RT_NOREF(pVM, pvUser);
448 int rc = RTThreadControlPokeSignal(pVCpu->hThread, true /*fEnable*/);
449 AssertLogRelRC(rc);
450 return VINF_SUCCESS;
451}
452
453
454/**
455 * Try initialize the native API.
456 *
457 * This may only do part of the job, more can be done in
458 * nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
459 *
460 * @returns VBox status code.
461 * @param pVM The cross context VM structure.
462 * @param fFallback Whether we're in fallback mode or use-NEM mode. In
463 * the latter we'll fail if we cannot initialize.
464 * @param fForced Whether the HMForced flag is set and we should
465 * fail if we cannot initialize.
466 */
467int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
468{
469 RT_NOREF(pVM, fFallback, fForced);
470 /*
471 * Some state init.
472 */
473 pVM->nem.s.fdKvm = -1;
474 pVM->nem.s.fdVm = -1;
475 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
476 {
477 PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
478 pNemCpu->fdVCpu = -1;
479 }
480
481 /*
482 * Error state.
483 * The error message will be non-empty on failure and 'rc' will be set too.
484 */
485 RTERRINFOSTATIC ErrInfo;
486 PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
487
488 /*
489 * Open kvm subsystem so we can issue system ioctls.
490 */
491 int rc;
492 int fdKvm = open("/dev/kvm", O_RDWR | O_CLOEXEC);
493 if (fdKvm >= 0)
494 {
495 pVM->nem.s.fdKvm = fdKvm;
496
497 /*
498 * Create an empty VM since it is recommended we check capabilities on
499 * the VM rather than the system descriptor.
500 */
501 int fdVm = ioctl(fdKvm, KVM_CREATE_VM, 0UL /* Type must be zero on x86 */);
502 if (fdVm >= 0)
503 {
504 pVM->nem.s.fdVm = fdVm;
505
506 /*
507 * Check capabilities.
508 */
509 rc = nemR3LnxInitCheckCapabilities(pVM, pErrInfo);
510 if (RT_SUCCESS(rc))
511 {
512 /*
513 * Set up the VM (more on this later).
514 */
515 rc = nemR3LnxInitSetupVm(pVM, pErrInfo);
516 if (RT_SUCCESS(rc))
517 {
518 /*
519 * Set ourselves as the execution engine and make config adjustments.
520 */
521 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
522 Log(("NEM: Marked active!\n"));
523 PGMR3EnableNemMode(pVM);
524
525 /*
526 * Register release statistics
527 */
528 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
529 {
530 PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
531 STAMR3RegisterF(pVM, &pNemCpu->StatImportOnDemand, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of on-demand state imports", "/NEM/CPU%u/ImportOnDemand", idCpu);
532 STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of state imports on loop return", "/NEM/CPU%u/ImportOnReturn", idCpu);
533 STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturnSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped state imports on loop return", "/NEM/CPU%u/ImportOnReturnSkipped", idCpu);
534 STAMR3RegisterF(pVM, &pNemCpu->StatImportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when importing from KVM", "/NEM/CPU%u/ImportPendingInterrupt", idCpu);
535 STAMR3RegisterF(pVM, &pNemCpu->StatExportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when exporting to KVM", "/NEM/CPU%u/ExportPendingInterrupt", idCpu);
536 STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn", idCpu);
537 STAMR3RegisterF(pVM, &pNemCpu->StatQueryCpuTick, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSC queries", "/NEM/CPU%u/QueryCpuTick", idCpu);
538 STAMR3RegisterF(pVM, &pNemCpu->StatExitTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "All exits", "/NEM/CPU%u/Exit", idCpu);
539 STAMR3RegisterF(pVM, &pNemCpu->StatExitIo, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IO", "/NEM/CPU%u/Exit/Io", idCpu);
540 STAMR3RegisterF(pVM, &pNemCpu->StatExitMmio, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_MMIO", "/NEM/CPU%u/Exit/Mmio", idCpu);
541 STAMR3RegisterF(pVM, &pNemCpu->StatExitSetTpr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_SET_TRP", "/NEM/CPU%u/Exit/SetTpr", idCpu);
542 STAMR3RegisterF(pVM, &pNemCpu->StatExitTprAccess, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_TPR_ACCESS", "/NEM/CPU%u/Exit/TprAccess", idCpu);
543 STAMR3RegisterF(pVM, &pNemCpu->StatExitRdMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_RDMSR", "/NEM/CPU%u/Exit/RdMsr", idCpu);
544 STAMR3RegisterF(pVM, &pNemCpu->StatExitWrMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_WRMSR", "/NEM/CPU%u/Exit/WrMsr", idCpu);
545 STAMR3RegisterF(pVM, &pNemCpu->StatExitIrqWindowOpen, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IRQ_WINDOWS_OPEN", "/NEM/CPU%u/Exit/IrqWindowOpen", idCpu);
546 STAMR3RegisterF(pVM, &pNemCpu->StatExitHalt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HLT", "/NEM/CPU%u/Exit/Hlt", idCpu);
547 STAMR3RegisterF(pVM, &pNemCpu->StatExitIntr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTR", "/NEM/CPU%u/Exit/Intr", idCpu);
548 STAMR3RegisterF(pVM, &pNemCpu->StatExitHypercall, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HYPERCALL", "/NEM/CPU%u/Exit/Hypercall", idCpu);
549 STAMR3RegisterF(pVM, &pNemCpu->StatExitDebug, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_DEBUG", "/NEM/CPU%u/Exit/Debug", idCpu);
550 STAMR3RegisterF(pVM, &pNemCpu->StatExitBusLock, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_BUS_LOCK", "/NEM/CPU%u/Exit/BusLock", idCpu);
551 STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorEmulation, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/EMULATION", "/NEM/CPU%u/Exit/InternalErrorEmulation", idCpu);
552 STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorFatal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/*", "/NEM/CPU%u/Exit/InternalErrorFatal", idCpu);
553 }
554
555 /*
556 * Make RTThreadPoke work again (disabled for avoiding unnecessary
557 * critical section issues in ring-0).
558 */
559 VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE, nemR3LnxFixThreadPoke, NULL);
560
561 /*
562 * Success.
563 */
564 return VINF_SUCCESS;
565 }
566
567 /*
568 * Bail out.
569 */
570 }
571 close(fdVm);
572 pVM->nem.s.fdVm = -1;
573 }
574 else
575 rc = RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VM failed: %u", errno);
576 close(fdKvm);
577 pVM->nem.s.fdKvm = -1;
578 }
579 else if (errno == EACCES)
580 rc = RTErrInfoSet(pErrInfo, VERR_ACCESS_DENIED, "Do not have access to open /dev/kvm for reading & writing.");
581 else if (errno == ENOENT)
582 rc = RTErrInfoSet(pErrInfo, VERR_NOT_SUPPORTED, "KVM is not availble (/dev/kvm does not exist)");
583 else
584 rc = RTErrInfoSetF(pErrInfo, RTErrConvertFromErrno(errno), "Failed to open '/dev/kvm': %u", errno);
585
586 /*
587 * We only fail if in forced mode, otherwise just log the complaint and return.
588 */
589 Assert(RTErrInfoIsSet(pErrInfo));
590 if ( (fForced || !fFallback)
591 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
592 return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
593 LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
594 return VINF_SUCCESS;
595}
596
597
598/**
599 * This is called after CPUMR3Init is done.
600 *
601 * @returns VBox status code.
602 * @param pVM The VM handle..
603 */
604int nemR3NativeInitAfterCPUM(PVM pVM)
605{
606 /*
607 * Validate sanity.
608 */
609 AssertReturn(pVM->nem.s.fdKvm >= 0, VERR_WRONG_ORDER);
610 AssertReturn(pVM->nem.s.fdVm >= 0, VERR_WRONG_ORDER);
611 AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
612
613 /** @todo */
614
615 return VINF_SUCCESS;
616}
617
618
619/**
620 * Update the CPUID leaves for a VCPU.
621 *
622 * The KVM_SET_CPUID2 call replaces any previous leaves, so we have to redo
623 * everything when there really just are single bit changes. That said, it
624 * looks like KVM update the XCR/XSAVE related stuff as well as the APIC enabled
625 * bit(s), so it should suffice if we do this at startup, I hope.
626 */
627static int nemR3LnxUpdateCpuIdsLeaves(PVM pVM, PVMCPU pVCpu)
628{
629 uint32_t cLeaves = 0;
630 PCCPUMCPUIDLEAF const paLeaves = CPUMR3CpuIdGetPtr(pVM, &cLeaves);
631 struct kvm_cpuid2 *pReq = (struct kvm_cpuid2 *)alloca(RT_UOFFSETOF_DYN(struct kvm_cpuid2, entries[cLeaves + 2]));
632
633 pReq->nent = cLeaves;
634 pReq->padding = 0;
635
636 for (uint32_t i = 0; i < cLeaves; i++)
637 {
638 CPUMGetGuestCpuId(pVCpu, paLeaves[i].uLeaf, paLeaves[i].uSubLeaf,
639 &pReq->entries[i].eax,
640 &pReq->entries[i].ebx,
641 &pReq->entries[i].ecx,
642 &pReq->entries[i].edx);
643 pReq->entries[i].function = paLeaves[i].uLeaf;
644 pReq->entries[i].index = paLeaves[i].uSubLeaf;
645 pReq->entries[i].flags = !paLeaves[i].fSubLeafMask ? 0 : KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
646 pReq->entries[i].padding[0] = 0;
647 pReq->entries[i].padding[1] = 0;
648 pReq->entries[i].padding[2] = 0;
649 }
650
651 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_CPUID2, pReq);
652 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d cLeaves=%#x\n", rcLnx, errno, cLeaves), RTErrConvertFromErrno(errno));
653
654 return VINF_SUCCESS;
655}
656
657
658int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
659{
660 /*
661 * Configure CPUIDs after ring-3 init has been done.
662 */
663 if (enmWhat == VMINITCOMPLETED_RING3)
664 {
665 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
666 {
667 int rc = nemR3LnxUpdateCpuIdsLeaves(pVM, pVM->apCpusR3[idCpu]);
668 AssertRCReturn(rc, rc);
669 }
670 }
671
672 return VINF_SUCCESS;
673}
674
675
676int nemR3NativeTerm(PVM pVM)
677{
678 /*
679 * Per-cpu data
680 */
681 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
682 {
683 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
684
685 if (pVCpu->nem.s.fdVCpu != -1)
686 {
687 close(pVCpu->nem.s.fdVCpu);
688 pVCpu->nem.s.fdVCpu = -1;
689 }
690 if (pVCpu->nem.s.pRun)
691 {
692 munmap(pVCpu->nem.s.pRun, pVM->nem.s.cbVCpuMmap);
693 pVCpu->nem.s.pRun = NULL;
694 }
695 }
696
697 /*
698 * Global data.
699 */
700 if (pVM->nem.s.fdVm != -1)
701 {
702 close(pVM->nem.s.fdVm);
703 pVM->nem.s.fdVm = -1;
704 }
705
706 if (pVM->nem.s.fdKvm != -1)
707 {
708 close(pVM->nem.s.fdKvm);
709 pVM->nem.s.fdKvm = -1;
710 }
711 return VINF_SUCCESS;
712}
713
714
715/**
716 * VM reset notification.
717 *
718 * @param pVM The cross context VM structure.
719 */
720void nemR3NativeReset(PVM pVM)
721{
722 RT_NOREF(pVM);
723}
724
725
726/**
727 * Reset CPU due to INIT IPI or hot (un)plugging.
728 *
729 * @param pVCpu The cross context virtual CPU structure of the CPU being
730 * reset.
731 * @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
732 */
733void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
734{
735 RT_NOREF(pVCpu, fInitIpi);
736}
737
738
739/*********************************************************************************************************************************
740* Memory management *
741*********************************************************************************************************************************/
742
743
744/**
745 * Allocates a memory slot ID.
746 *
747 * @returns Slot ID on success, UINT16_MAX on failure.
748 */
749static uint16_t nemR3LnxMemSlotIdAlloc(PVM pVM)
750{
751 /* Use the hint first. */
752 uint16_t idHint = pVM->nem.s.idPrevSlot;
753 if (idHint < _32K - 1)
754 {
755 int32_t idx = ASMBitNextClear(&pVM->nem.s.bmSlotIds, _32K, idHint);
756 Assert(idx < _32K);
757 if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
758 return pVM->nem.s.idPrevSlot = (uint16_t)idx;
759 }
760
761 /*
762 * Search the whole map from the start.
763 */
764 int32_t idx = ASMBitFirstClear(&pVM->nem.s.bmSlotIds, _32K);
765 Assert(idx < _32K);
766 if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
767 return pVM->nem.s.idPrevSlot = (uint16_t)idx;
768
769 Assert(idx < 0 /*shouldn't trigger unless there is a race */);
770 return UINT16_MAX; /* caller is expected to assert. */
771}
772
773
774/**
775 * Frees a memory slot ID
776 */
777static void nemR3LnxMemSlotIdFree(PVM pVM, uint16_t idSlot)
778{
779 if (RT_LIKELY(idSlot < _32K && ASMAtomicBitTestAndClear(&pVM->nem.s.bmSlotIds, idSlot)))
780 { /*likely*/ }
781 else
782 AssertMsgFailed(("idSlot=%u (%#x)\n", idSlot, idSlot));
783}
784
785
786
787VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
788 uint8_t *pu2State, uint32_t *puNemRange)
789{
790 uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
791 AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
792
793 Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p pu2State=%p (%d) puNemRange=%p (%d) - idSlot=%#x\n",
794 GCPhys, cb, pvR3, pu2State, pu2State, puNemRange, *puNemRange, idSlot));
795
796 struct kvm_userspace_memory_region Region;
797 Region.slot = idSlot;
798 Region.flags = 0;
799 Region.guest_phys_addr = GCPhys;
800 Region.memory_size = cb;
801 Region.userspace_addr = (uintptr_t)pvR3;
802
803 int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
804 if (rc == 0)
805 {
806 *pu2State = 0;
807 *puNemRange = idSlot;
808 return VINF_SUCCESS;
809 }
810
811 LogRel(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p, idSlot=%#x failed: %u/%u\n", GCPhys, cb, pvR3, idSlot, rc, errno));
812 nemR3LnxMemSlotIdFree(pVM, idSlot);
813 return VERR_NEM_MAP_PAGES_FAILED;
814}
815
816
817VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
818{
819 RT_NOREF(pVM);
820 return true;
821}
822
823
824VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
825 void *pvRam, void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
826{
827 Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d) puNemRange=%p (%#x)\n",
828 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, *pu2State, puNemRange, puNemRange ? *puNemRange : UINT32_MAX));
829 RT_NOREF(pvRam);
830
831 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
832 {
833 /** @todo implement splitting and whatnot of ranges if we want to be 100%
834 * conforming (just modify RAM registrations in MM.cpp to test). */
835 AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
836 VERR_NEM_MAP_PAGES_FAILED);
837 }
838
839 /*
840 * Register MMIO2.
841 */
842 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
843 {
844 AssertReturn(pvMmio2, VERR_NEM_MAP_PAGES_FAILED);
845 AssertReturn(puNemRange, VERR_NEM_MAP_PAGES_FAILED);
846
847 uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
848 AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
849
850 struct kvm_userspace_memory_region Region;
851 Region.slot = idSlot;
852 Region.flags = fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES ? KVM_MEM_LOG_DIRTY_PAGES : 0;
853 Region.guest_phys_addr = GCPhys;
854 Region.memory_size = cb;
855 Region.userspace_addr = (uintptr_t)pvMmio2;
856
857 int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
858 if (rc == 0)
859 {
860 *pu2State = 0;
861 *puNemRange = idSlot;
862 Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvMmio2=%p - idSlot=%#x\n",
863 GCPhys, cb, fFlags, pvMmio2, idSlot));
864 return VINF_SUCCESS;
865 }
866
867 nemR3LnxMemSlotIdFree(pVM, idSlot);
868 AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
869 GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
870 VERR_NEM_MAP_PAGES_FAILED);
871 }
872
873 /* MMIO, don't care. */
874 *pu2State = 0;
875 *puNemRange = UINT32_MAX;
876 return VINF_SUCCESS;
877}
878
879
880VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
881 void *pvRam, void *pvMmio2, uint32_t *puNemRange)
882{
883 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
884 return VINF_SUCCESS;
885}
886
887
888VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
889 void *pvMmio2, uint8_t *pu2State, uint32_t *puNemRange)
890{
891 Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p puNemRange=%p (%#x)\n",
892 GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
893 RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
894
895 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
896 {
897 /** @todo implement splitting and whatnot of ranges if we want to be 100%
898 * conforming (just modify RAM registrations in MM.cpp to test). */
899 AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
900 VERR_NEM_UNMAP_PAGES_FAILED);
901 }
902
903 if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
904 {
905 uint32_t const idSlot = *puNemRange;
906 AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
907 AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
908
909 struct kvm_userspace_memory_region Region;
910 Region.slot = idSlot;
911 Region.flags = 0;
912 Region.guest_phys_addr = GCPhys;
913 Region.memory_size = 0; /* this deregisters it. */
914 Region.userspace_addr = (uintptr_t)pvMmio2;
915
916 int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
917 if (rc == 0)
918 {
919 if (pu2State)
920 *pu2State = 0;
921 *puNemRange = UINT32_MAX;
922 nemR3LnxMemSlotIdFree(pVM, idSlot);
923 return VINF_SUCCESS;
924 }
925
926 AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
927 GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
928 VERR_NEM_UNMAP_PAGES_FAILED);
929 }
930
931 if (pu2State)
932 *pu2State = UINT8_MAX;
933 return VINF_SUCCESS;
934}
935
936
937VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
938 void *pvBitmap, size_t cbBitmap)
939{
940 AssertReturn(uNemRange > 0 && uNemRange < _32K, VERR_NEM_IPE_4);
941 AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, uNemRange), VERR_NEM_IPE_4);
942
943 RT_NOREF(GCPhys, cbBitmap);
944
945 struct kvm_dirty_log DirtyLog;
946 DirtyLog.slot = uNemRange;
947 DirtyLog.padding1 = 0;
948 DirtyLog.dirty_bitmap = pvBitmap;
949
950 int rc = ioctl(pVM->nem.s.fdVm, KVM_GET_DIRTY_LOG, &DirtyLog);
951 AssertLogRelMsgReturn(rc == 0, ("%RGp LB %RGp idSlot=%#x failed: %u/%u\n", GCPhys, cb, uNemRange, errno, rc),
952 VERR_NEM_QUERY_DIRTY_BITMAP_FAILED);
953
954 return VINF_SUCCESS;
955}
956
957
958VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
959 uint8_t *pu2State, uint32_t *puNemRange)
960{
961 Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
962 *pu2State = UINT8_MAX;
963
964 /* Don't support puttint ROM where there is already RAM. For
965 now just shuffle the registrations till it works... */
966 AssertLogRelMsgReturn(!(fFlags & NEM_NOTIFY_PHYS_ROM_F_REPLACE), ("%RGp LB %RGp fFlags=%#x\n", GCPhys, cb, fFlags),
967 VERR_NEM_MAP_PAGES_FAILED);
968
969 /** @todo figure out how to do shadow ROMs. */
970
971 /*
972 * We only allocate a slot number here in case we need to use it to
973 * fend of physical handler fun.
974 */
975 uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
976 AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
977
978 *pu2State = 0;
979 *puNemRange = idSlot;
980 Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
981 GCPhys, cb, fFlags, pvPages, idSlot));
982 RT_NOREF(GCPhys, cb, fFlags, pvPages);
983 return VINF_SUCCESS;
984}
985
986
987VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
988 uint32_t fFlags, uint8_t *pu2State, uint32_t *puNemRange)
989{
990 Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
991 GCPhys, cb, pvPages, fFlags, pu2State, *pu2State, puNemRange, *puNemRange));
992
993 AssertPtrReturn(pvPages, VERR_NEM_IPE_5);
994
995 uint32_t const idSlot = *puNemRange;
996 AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
997 AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
998
999 *pu2State = UINT8_MAX;
1000
1001 /*
1002 * Do the actual setting of the user pages here now that we've
1003 * got a valid pvPages (typically isn't available during the early
1004 * notification, unless we're replacing RAM).
1005 */
1006 struct kvm_userspace_memory_region Region;
1007 Region.slot = idSlot;
1008 Region.flags = 0;
1009 Region.guest_phys_addr = GCPhys;
1010 Region.memory_size = cb;
1011 Region.userspace_addr = (uintptr_t)pvPages;
1012
1013 int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
1014 if (rc == 0)
1015 {
1016 *pu2State = 0;
1017 Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
1018 GCPhys, cb, fFlags, pvPages, idSlot));
1019 return VINF_SUCCESS;
1020 }
1021 AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvPages=%p, idSlot=%#x failed: %u/%u\n",
1022 GCPhys, cb, fFlags, pvPages, idSlot, errno, rc),
1023 VERR_NEM_MAP_PAGES_FAILED);
1024}
1025
1026
1027/**
1028 * Called when the A20 state changes.
1029 *
1030 * @param pVCpu The CPU the A20 state changed on.
1031 * @param fEnabled Whether it was enabled (true) or disabled.
1032 */
1033VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
1034{
1035 Log(("nemR3NativeNotifySetA20: fEnabled=%RTbool\n", fEnabled));
1036 Assert(VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)));
1037 RT_NOREF(pVCpu, fEnabled);
1038}
1039
1040
1041VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1042 RTR3PTR pvMemR3, uint8_t *pu2State)
1043{
1044 Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
1045 GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
1046
1047 *pu2State = UINT8_MAX;
1048 RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
1049}
1050
1051
1052void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1053{
1054 Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1055 RT_NOREF(pVM, enmKind, GCPhys, cb);
1056}
1057
1058
1059void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1060 RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1061{
1062 Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1063 GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1064 RT_NOREF(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fRestoreAsRAM);
1065}
1066
1067
1068int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
1069 PGMPAGETYPE enmType, uint8_t *pu2State)
1070{
1071 Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1072 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1073 RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
1074 return VINF_SUCCESS;
1075}
1076
1077
1078VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
1079 PGMPAGETYPE enmType, uint8_t *pu2State)
1080{
1081 Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1082 GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1083 Assert(VM_IS_NEM_ENABLED(pVM));
1084 RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
1085
1086}
1087
1088
1089VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
1090 RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
1091{
1092 Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp pvNewR3=%p fPageProt=%#x enmType=%d *pu2State=%d\n",
1093 GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, *pu2State));
1094 Assert(VM_IS_NEM_ENABLED(pVM));
1095 RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
1096}
1097
1098
1099/*********************************************************************************************************************************
1100* CPU State *
1101*********************************************************************************************************************************/
1102
1103/**
1104 * Worker that imports selected state from KVM.
1105 */
1106static int nemHCLnxImportState(PVMCPUCC pVCpu, uint64_t fWhat, PCPUMCTX pCtx, struct kvm_run *pRun)
1107{
1108 fWhat &= pVCpu->cpum.GstCtx.fExtrn;
1109 if (!fWhat)
1110 return VINF_SUCCESS;
1111
1112 /*
1113 * Stuff that goes into kvm_run::s.regs.regs:
1114 */
1115 if (fWhat & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_GPRS_MASK))
1116 {
1117 if (fWhat & CPUMCTX_EXTRN_RIP)
1118 pCtx->rip = pRun->s.regs.regs.rip;
1119 if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1120 pCtx->rflags.u = pRun->s.regs.regs.rflags;
1121
1122 if (fWhat & CPUMCTX_EXTRN_RAX)
1123 pCtx->rax = pRun->s.regs.regs.rax;
1124 if (fWhat & CPUMCTX_EXTRN_RCX)
1125 pCtx->rcx = pRun->s.regs.regs.rcx;
1126 if (fWhat & CPUMCTX_EXTRN_RDX)
1127 pCtx->rdx = pRun->s.regs.regs.rdx;
1128 if (fWhat & CPUMCTX_EXTRN_RBX)
1129 pCtx->rbx = pRun->s.regs.regs.rbx;
1130 if (fWhat & CPUMCTX_EXTRN_RSP)
1131 pCtx->rsp = pRun->s.regs.regs.rsp;
1132 if (fWhat & CPUMCTX_EXTRN_RBP)
1133 pCtx->rbp = pRun->s.regs.regs.rbp;
1134 if (fWhat & CPUMCTX_EXTRN_RSI)
1135 pCtx->rsi = pRun->s.regs.regs.rsi;
1136 if (fWhat & CPUMCTX_EXTRN_RDI)
1137 pCtx->rdi = pRun->s.regs.regs.rdi;
1138 if (fWhat & CPUMCTX_EXTRN_R8_R15)
1139 {
1140 pCtx->r8 = pRun->s.regs.regs.r8;
1141 pCtx->r9 = pRun->s.regs.regs.r9;
1142 pCtx->r10 = pRun->s.regs.regs.r10;
1143 pCtx->r11 = pRun->s.regs.regs.r11;
1144 pCtx->r12 = pRun->s.regs.regs.r12;
1145 pCtx->r13 = pRun->s.regs.regs.r13;
1146 pCtx->r14 = pRun->s.regs.regs.r14;
1147 pCtx->r15 = pRun->s.regs.regs.r15;
1148 }
1149 }
1150
1151 /*
1152 * Stuff that goes into kvm_run::s.regs.sregs:
1153 */
1154 /** @todo apic_base */
1155
1156 bool fMaybeChangedMode = false;
1157 bool fUpdateCr3 = false;
1158 if (fWhat & ( CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK
1159 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_APIC_TPR))
1160 {
1161 /** @todo what about Attr.n.u4LimitHigh? */
1162#define NEM_LNX_IMPORT_SEG(a_CtxSeg, a_KvmSeg) do { \
1163 (a_CtxSeg).u64Base = (a_KvmSeg).base; \
1164 (a_CtxSeg).u32Limit = (a_KvmSeg).limit; \
1165 (a_CtxSeg).ValidSel = (a_CtxSeg).Sel = (a_KvmSeg).selector; \
1166 (a_CtxSeg).Attr.n.u4Type = (a_KvmSeg).type; \
1167 (a_CtxSeg).Attr.n.u1DescType = (a_KvmSeg).s; \
1168 (a_CtxSeg).Attr.n.u2Dpl = (a_KvmSeg).dpl; \
1169 (a_CtxSeg).Attr.n.u1Present = (a_KvmSeg).present; \
1170 (a_CtxSeg).Attr.n.u1Available = (a_KvmSeg).avl; \
1171 (a_CtxSeg).Attr.n.u1Long = (a_KvmSeg).l; \
1172 (a_CtxSeg).Attr.n.u1DefBig = (a_KvmSeg).db; \
1173 (a_CtxSeg).Attr.n.u1Granularity = (a_KvmSeg).g; \
1174 (a_CtxSeg).Attr.n.u1Unusable = (a_KvmSeg).unusable; \
1175 (a_CtxSeg).fFlags = CPUMSELREG_FLAGS_VALID; \
1176 CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &(a_CtxSeg)); \
1177 } while (0)
1178
1179 if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1180 {
1181 if (fWhat & CPUMCTX_EXTRN_ES)
1182 NEM_LNX_IMPORT_SEG(pCtx->es, pRun->s.regs.sregs.es);
1183 if (fWhat & CPUMCTX_EXTRN_CS)
1184 NEM_LNX_IMPORT_SEG(pCtx->cs, pRun->s.regs.sregs.cs);
1185 if (fWhat & CPUMCTX_EXTRN_SS)
1186 NEM_LNX_IMPORT_SEG(pCtx->ss, pRun->s.regs.sregs.ss);
1187 if (fWhat & CPUMCTX_EXTRN_DS)
1188 NEM_LNX_IMPORT_SEG(pCtx->ds, pRun->s.regs.sregs.ds);
1189 if (fWhat & CPUMCTX_EXTRN_FS)
1190 NEM_LNX_IMPORT_SEG(pCtx->fs, pRun->s.regs.sregs.fs);
1191 if (fWhat & CPUMCTX_EXTRN_GS)
1192 NEM_LNX_IMPORT_SEG(pCtx->gs, pRun->s.regs.sregs.gs);
1193 }
1194 if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1195 {
1196 if (fWhat & CPUMCTX_EXTRN_GDTR)
1197 {
1198 pCtx->gdtr.pGdt = pRun->s.regs.sregs.gdt.base;
1199 pCtx->gdtr.cbGdt = pRun->s.regs.sregs.gdt.limit;
1200 }
1201 if (fWhat & CPUMCTX_EXTRN_IDTR)
1202 {
1203 pCtx->idtr.pIdt = pRun->s.regs.sregs.idt.base;
1204 pCtx->idtr.cbIdt = pRun->s.regs.sregs.idt.limit;
1205 }
1206 if (fWhat & CPUMCTX_EXTRN_LDTR)
1207 NEM_LNX_IMPORT_SEG(pCtx->ldtr, pRun->s.regs.sregs.ldt);
1208 if (fWhat & CPUMCTX_EXTRN_TR)
1209 NEM_LNX_IMPORT_SEG(pCtx->tr, pRun->s.regs.sregs.tr);
1210 }
1211 if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1212 {
1213 if (fWhat & CPUMCTX_EXTRN_CR0)
1214 {
1215 if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1216 {
1217 CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1218 fMaybeChangedMode = true;
1219 }
1220 }
1221 if (fWhat & CPUMCTX_EXTRN_CR2)
1222 pCtx->cr2 = pRun->s.regs.sregs.cr2;
1223 if (fWhat & CPUMCTX_EXTRN_CR3)
1224 {
1225 if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1226 {
1227 CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1228 fUpdateCr3 = true;
1229 }
1230 }
1231 if (fWhat & CPUMCTX_EXTRN_CR4)
1232 {
1233 if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1234 {
1235 CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1236 fMaybeChangedMode = true;
1237 }
1238 }
1239 }
1240 if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1241 APICSetTpr(pVCpu, (uint8_t)pRun->s.regs.sregs.cr8 << 4);
1242 if (fWhat & CPUMCTX_EXTRN_EFER)
1243 {
1244 if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1245 {
1246 Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1247 if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1248 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1249 pCtx->msrEFER = pRun->s.regs.sregs.efer;
1250 fMaybeChangedMode = true;
1251 }
1252 }
1253
1254 /** @todo apic_base */
1255#undef NEM_LNX_IMPORT_SEG
1256 }
1257
1258 /*
1259 * Debug registers.
1260 */
1261 if (fWhat & CPUMCTX_EXTRN_DR_MASK)
1262 {
1263 struct kvm_debugregs DbgRegs = {{0}};
1264 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1265 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1266
1267 if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1268 {
1269 pCtx->dr[0] = DbgRegs.db[0];
1270 pCtx->dr[1] = DbgRegs.db[1];
1271 pCtx->dr[2] = DbgRegs.db[2];
1272 pCtx->dr[3] = DbgRegs.db[3];
1273 }
1274 if (fWhat & CPUMCTX_EXTRN_DR6)
1275 pCtx->dr[6] = DbgRegs.dr6;
1276 if (fWhat & CPUMCTX_EXTRN_DR7)
1277 pCtx->dr[7] = DbgRegs.dr7;
1278 }
1279
1280 /*
1281 * FPU, SSE, AVX, ++.
1282 */
1283 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx))
1284 {
1285 if (fWhat & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))
1286 {
1287 fWhat |= CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE; /* we do all or nothing at all */
1288
1289 AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1290 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XSAVE, &pCtx->XState);
1291 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1292 }
1293
1294 if (fWhat & CPUMCTX_EXTRN_XCRx)
1295 {
1296 struct kvm_xcrs Xcrs =
1297 { /*.nr_xcrs = */ 2,
1298 /*.flags = */ 0,
1299 /*.xcrs= */ {
1300 { /*.xcr =*/ 0, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[0] },
1301 { /*.xcr =*/ 1, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[1] },
1302 }
1303 };
1304
1305 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XCRS, &Xcrs);
1306 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1307
1308 pCtx->aXcr[0] = Xcrs.xcrs[0].value;
1309 pCtx->aXcr[1] = Xcrs.xcrs[1].value;
1310 }
1311 }
1312
1313 /*
1314 * MSRs.
1315 */
1316 if (fWhat & ( CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_SYSENTER_MSRS
1317 | CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
1318 {
1319 union
1320 {
1321 struct kvm_msrs Core;
1322 uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1323 } uBuf;
1324 uint64_t *pauDsts[32];
1325 uint32_t iMsr = 0;
1326 PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1327
1328#define ADD_MSR(a_Msr, a_uValue) do { \
1329 Assert(iMsr < 32); \
1330 uBuf.Core.entries[iMsr].index = (a_Msr); \
1331 uBuf.Core.entries[iMsr].reserved = 0; \
1332 uBuf.Core.entries[iMsr].data = UINT64_MAX; \
1333 pauDsts[iMsr] = &(a_uValue); \
1334 iMsr += 1; \
1335 } while (0)
1336
1337 if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1338 ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1339 if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1340 {
1341 ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1342 ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1343 ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1344 ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1345 }
1346 if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1347 {
1348 ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1349 ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1350 ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1351 }
1352 if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
1353 ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1354 if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1355 {
1356 ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1357 /** @todo What do we _have_ to add here?
1358 * We also have: Mttr*, MiscEnable, FeatureControl. */
1359 }
1360
1361 uBuf.Core.pad = 0;
1362 uBuf.Core.nmsrs = iMsr;
1363 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MSRS, &uBuf);
1364 AssertMsgReturn(rc == (int)iMsr,
1365 ("rc=%d iMsr=%d (->%#x) errno=%d\n",
1366 rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1367 VERR_NEM_IPE_3);
1368
1369 while (iMsr-- > 0)
1370 *pauDsts[iMsr] = uBuf.Core.entries[iMsr].data;
1371#undef ADD_MSR
1372 }
1373
1374 /*
1375 * Interruptibility state and pending interrupts.
1376 */
1377 if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
1378 {
1379 fWhat |= CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI; /* always do both, see export and interrupt FF handling */
1380
1381 struct kvm_vcpu_events KvmEvents = {0};
1382 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
1383 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1384
1385 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP)
1386 pVCpu->cpum.GstCtx.rip = pRun->s.regs.regs.rip;
1387
1388 if (KvmEvents.interrupt.shadow)
1389 EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
1390 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1391 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1392
1393 if (KvmEvents.nmi.masked)
1394 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1395 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1396 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1397
1398 if (KvmEvents.interrupt.injected)
1399 {
1400 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportPendingInterrupt);
1401 TRPMAssertTrap(pVCpu, KvmEvents.interrupt.nr, !KvmEvents.interrupt.soft ? TRPM_HARDWARE_INT : TRPM_SOFTWARE_INT);
1402 }
1403
1404 Assert(KvmEvents.nmi.injected == 0);
1405 Assert(KvmEvents.nmi.pending == 0);
1406 }
1407
1408 /*
1409 * Update the external mask.
1410 */
1411 pCtx->fExtrn &= ~fWhat;
1412 pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1413 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1414 pVCpu->cpum.GstCtx.fExtrn = 0;
1415
1416 /*
1417 * We sometimes need to update PGM on the guest status.
1418 */
1419 if (!fMaybeChangedMode && !fUpdateCr3)
1420 { /* likely */ }
1421 else
1422 {
1423 /*
1424 * Make sure we got all the state PGM might need.
1425 */
1426 Log7(("nemHCLnxImportState: fMaybeChangedMode=%d fUpdateCr3=%d fExtrnNeeded=%#RX64\n", fMaybeChangedMode, fUpdateCr3,
1427 pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_EFER) ));
1428 if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_EFER))
1429 {
1430 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR0)
1431 {
1432 if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1433 {
1434 CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1435 fMaybeChangedMode = true;
1436 }
1437 }
1438 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR3)
1439 {
1440 if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1441 {
1442 CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1443 fUpdateCr3 = true;
1444 }
1445 }
1446 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR4)
1447 {
1448 if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1449 {
1450 CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1451 fMaybeChangedMode = true;
1452 }
1453 }
1454 if (fWhat & CPUMCTX_EXTRN_EFER)
1455 {
1456 if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1457 {
1458 Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1459 if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1460 PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1461 pCtx->msrEFER = pRun->s.regs.sregs.efer;
1462 fMaybeChangedMode = true;
1463 }
1464 }
1465
1466 pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR4 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_EFER);
1467 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1468 pVCpu->cpum.GstCtx.fExtrn = 0;
1469 }
1470
1471 /*
1472 * Notify PGM about the changes.
1473 */
1474 if (fMaybeChangedMode)
1475 {
1476 int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4, pVCpu->cpum.GstCtx.msrEFER);
1477 AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1478 }
1479
1480 if (fUpdateCr3)
1481 {
1482 int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3, false /*fPdpesMapped*/);
1483 if (rc == VINF_SUCCESS)
1484 { /* likely */ }
1485 else
1486 AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1487 }
1488 }
1489
1490 return VINF_SUCCESS;
1491}
1492
1493
1494/**
1495 * Interface for importing state on demand (used by IEM).
1496 *
1497 * @returns VBox status code.
1498 * @param pVCpu The cross context CPU structure.
1499 * @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1500 */
1501VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1502{
1503 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1504 return nemHCLnxImportState(pVCpu, fWhat, &pVCpu->cpum.GstCtx, pVCpu->nem.s.pRun);
1505}
1506
1507
1508/**
1509 * Exports state to KVM.
1510 */
1511static int nemHCLnxExportState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, struct kvm_run *pRun)
1512{
1513 uint64_t const fExtrn = ~pCtx->fExtrn & CPUMCTX_EXTRN_ALL;
1514 Assert((~fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL);
1515
1516 /*
1517 * Stuff that goes into kvm_run::s.regs.regs:
1518 */
1519 if (fExtrn & (CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RFLAGS | CPUMCTX_EXTRN_GPRS_MASK))
1520 {
1521 if (fExtrn & CPUMCTX_EXTRN_RIP)
1522 pRun->s.regs.regs.rip = pCtx->rip;
1523 if (fExtrn & CPUMCTX_EXTRN_RFLAGS)
1524 pRun->s.regs.regs.rflags = pCtx->rflags.u;
1525
1526 if (fExtrn & CPUMCTX_EXTRN_RAX)
1527 pRun->s.regs.regs.rax = pCtx->rax;
1528 if (fExtrn & CPUMCTX_EXTRN_RCX)
1529 pRun->s.regs.regs.rcx = pCtx->rcx;
1530 if (fExtrn & CPUMCTX_EXTRN_RDX)
1531 pRun->s.regs.regs.rdx = pCtx->rdx;
1532 if (fExtrn & CPUMCTX_EXTRN_RBX)
1533 pRun->s.regs.regs.rbx = pCtx->rbx;
1534 if (fExtrn & CPUMCTX_EXTRN_RSP)
1535 pRun->s.regs.regs.rsp = pCtx->rsp;
1536 if (fExtrn & CPUMCTX_EXTRN_RBP)
1537 pRun->s.regs.regs.rbp = pCtx->rbp;
1538 if (fExtrn & CPUMCTX_EXTRN_RSI)
1539 pRun->s.regs.regs.rsi = pCtx->rsi;
1540 if (fExtrn & CPUMCTX_EXTRN_RDI)
1541 pRun->s.regs.regs.rdi = pCtx->rdi;
1542 if (fExtrn & CPUMCTX_EXTRN_R8_R15)
1543 {
1544 pRun->s.regs.regs.r8 = pCtx->r8;
1545 pRun->s.regs.regs.r9 = pCtx->r9;
1546 pRun->s.regs.regs.r10 = pCtx->r10;
1547 pRun->s.regs.regs.r11 = pCtx->r11;
1548 pRun->s.regs.regs.r12 = pCtx->r12;
1549 pRun->s.regs.regs.r13 = pCtx->r13;
1550 pRun->s.regs.regs.r14 = pCtx->r14;
1551 pRun->s.regs.regs.r15 = pCtx->r15;
1552 }
1553 pRun->kvm_dirty_regs |= KVM_SYNC_X86_REGS;
1554 }
1555
1556 /*
1557 * Stuff that goes into kvm_run::s.regs.sregs:
1558 */
1559 /** @todo apic_base */
1560 if (fExtrn & ( CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_TABLE_MASK | CPUMCTX_EXTRN_CR_MASK
1561 | CPUMCTX_EXTRN_EFER | CPUMCTX_EXTRN_APIC_TPR))
1562 {
1563#define NEM_LNX_EXPORT_SEG(a_KvmSeg, a_CtxSeg) do { \
1564 (a_KvmSeg).base = (a_CtxSeg).u64Base; \
1565 (a_KvmSeg).limit = (a_CtxSeg).u32Limit; \
1566 (a_KvmSeg).selector = (a_CtxSeg).Sel; \
1567 (a_KvmSeg).type = (a_CtxSeg).Attr.n.u4Type; \
1568 (a_KvmSeg).s = (a_CtxSeg).Attr.n.u1DescType; \
1569 (a_KvmSeg).dpl = (a_CtxSeg).Attr.n.u2Dpl; \
1570 (a_KvmSeg).present = (a_CtxSeg).Attr.n.u1Present; \
1571 (a_KvmSeg).avl = (a_CtxSeg).Attr.n.u1Available; \
1572 (a_KvmSeg).l = (a_CtxSeg).Attr.n.u1Long; \
1573 (a_KvmSeg).db = (a_CtxSeg).Attr.n.u1DefBig; \
1574 (a_KvmSeg).g = (a_CtxSeg).Attr.n.u1Granularity; \
1575 (a_KvmSeg).unusable = (a_CtxSeg).Attr.n.u1Unusable; \
1576 (a_KvmSeg).padding = 0; \
1577 } while (0)
1578
1579 if (fExtrn & CPUMCTX_EXTRN_SREG_MASK)
1580 {
1581 if (fExtrn & CPUMCTX_EXTRN_ES)
1582 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.es, pCtx->es);
1583 if (fExtrn & CPUMCTX_EXTRN_CS)
1584 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.cs, pCtx->cs);
1585 if (fExtrn & CPUMCTX_EXTRN_SS)
1586 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ss, pCtx->ss);
1587 if (fExtrn & CPUMCTX_EXTRN_DS)
1588 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ds, pCtx->ds);
1589 if (fExtrn & CPUMCTX_EXTRN_FS)
1590 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.fs, pCtx->fs);
1591 if (fExtrn & CPUMCTX_EXTRN_GS)
1592 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.gs, pCtx->gs);
1593 }
1594 if (fExtrn & CPUMCTX_EXTRN_TABLE_MASK)
1595 {
1596 if (fExtrn & CPUMCTX_EXTRN_GDTR)
1597 {
1598 pRun->s.regs.sregs.gdt.base = pCtx->gdtr.pGdt;
1599 pRun->s.regs.sregs.gdt.limit = pCtx->gdtr.cbGdt;
1600 pRun->s.regs.sregs.gdt.padding[0] = 0;
1601 pRun->s.regs.sregs.gdt.padding[1] = 0;
1602 pRun->s.regs.sregs.gdt.padding[2] = 0;
1603 }
1604 if (fExtrn & CPUMCTX_EXTRN_IDTR)
1605 {
1606 pRun->s.regs.sregs.idt.base = pCtx->idtr.pIdt;
1607 pRun->s.regs.sregs.idt.limit = pCtx->idtr.cbIdt;
1608 pRun->s.regs.sregs.idt.padding[0] = 0;
1609 pRun->s.regs.sregs.idt.padding[1] = 0;
1610 pRun->s.regs.sregs.idt.padding[2] = 0;
1611 }
1612 if (fExtrn & CPUMCTX_EXTRN_LDTR)
1613 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ldt, pCtx->ldtr);
1614 if (fExtrn & CPUMCTX_EXTRN_TR)
1615 NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.tr, pCtx->tr);
1616 }
1617 if (fExtrn & CPUMCTX_EXTRN_CR_MASK)
1618 {
1619 if (fExtrn & CPUMCTX_EXTRN_CR0)
1620 pRun->s.regs.sregs.cr0 = pCtx->cr0;
1621 if (fExtrn & CPUMCTX_EXTRN_CR2)
1622 pRun->s.regs.sregs.cr2 = pCtx->cr2;
1623 if (fExtrn & CPUMCTX_EXTRN_CR3)
1624 pRun->s.regs.sregs.cr3 = pCtx->cr3;
1625 if (fExtrn & CPUMCTX_EXTRN_CR4)
1626 pRun->s.regs.sregs.cr4 = pCtx->cr4;
1627 }
1628 if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)
1629 pRun->s.regs.sregs.cr8 = CPUMGetGuestCR8(pVCpu);
1630 if (fExtrn & CPUMCTX_EXTRN_EFER)
1631 pRun->s.regs.sregs.efer = pCtx->msrEFER;
1632
1633 /** @todo apic_base */
1634
1635 RT_ZERO(pRun->s.regs.sregs.interrupt_bitmap); /* this is an alternative interrupt injection interface */
1636
1637 pRun->kvm_dirty_regs |= KVM_SYNC_X86_SREGS;
1638 }
1639
1640 /*
1641 * Debug registers.
1642 */
1643 if (fExtrn & CPUMCTX_EXTRN_DR_MASK)
1644 {
1645 struct kvm_debugregs DbgRegs = {{0}};
1646
1647 if ((fExtrn & CPUMCTX_EXTRN_DR_MASK) != CPUMCTX_EXTRN_DR_MASK)
1648 {
1649 /* Partial debug state, we must get DbgRegs first so we can merge: */
1650 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1651 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1652 }
1653
1654 if (fExtrn & CPUMCTX_EXTRN_DR0_DR3)
1655 {
1656 DbgRegs.db[0] = pCtx->dr[0];
1657 DbgRegs.db[1] = pCtx->dr[1];
1658 DbgRegs.db[2] = pCtx->dr[2];
1659 DbgRegs.db[3] = pCtx->dr[3];
1660 }
1661 if (fExtrn & CPUMCTX_EXTRN_DR6)
1662 DbgRegs.dr6 = pCtx->dr[6];
1663 if (fExtrn & CPUMCTX_EXTRN_DR7)
1664 DbgRegs.dr7 = pCtx->dr[7];
1665
1666 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_DEBUGREGS, &DbgRegs);
1667 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1668 }
1669
1670 /*
1671 * FPU, SSE, AVX, ++.
1672 */
1673 if (fExtrn & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE | CPUMCTX_EXTRN_XCRx))
1674 {
1675 if (fExtrn & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))
1676 {
1677 /** @todo could IEM just grab state partial control in some situations? */
1678 Assert( (fExtrn & (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE))
1679 == (CPUMCTX_EXTRN_X87 | CPUMCTX_EXTRN_SSE_AVX | CPUMCTX_EXTRN_OTHER_XSAVE)); /* no partial states */
1680
1681 AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1682 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XSAVE, &pCtx->XState);
1683 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1684 }
1685
1686 if (fExtrn & CPUMCTX_EXTRN_XCRx)
1687 {
1688 struct kvm_xcrs Xcrs =
1689 { /*.nr_xcrs = */ 2,
1690 /*.flags = */ 0,
1691 /*.xcrs= */ {
1692 { /*.xcr =*/ 0, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[0] },
1693 { /*.xcr =*/ 1, /*.reserved=*/ 0, /*.value=*/ pCtx->aXcr[1] },
1694 }
1695 };
1696
1697 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XCRS, &Xcrs);
1698 AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1699 }
1700 }
1701
1702 /*
1703 * MSRs.
1704 */
1705 if (fExtrn & ( CPUMCTX_EXTRN_KERNEL_GS_BASE | CPUMCTX_EXTRN_SYSCALL_MSRS | CPUMCTX_EXTRN_SYSENTER_MSRS
1706 | CPUMCTX_EXTRN_TSC_AUX | CPUMCTX_EXTRN_OTHER_MSRS))
1707 {
1708 union
1709 {
1710 struct kvm_msrs Core;
1711 uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1712 } uBuf;
1713 uint32_t iMsr = 0;
1714 PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1715
1716#define ADD_MSR(a_Msr, a_uValue) do { \
1717 Assert(iMsr < 32); \
1718 uBuf.Core.entries[iMsr].index = (a_Msr); \
1719 uBuf.Core.entries[iMsr].reserved = 0; \
1720 uBuf.Core.entries[iMsr].data = (a_uValue); \
1721 iMsr += 1; \
1722 } while (0)
1723
1724 if (fExtrn & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1725 ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1726 if (fExtrn & CPUMCTX_EXTRN_SYSCALL_MSRS)
1727 {
1728 ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1729 ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1730 ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1731 ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1732 }
1733 if (fExtrn & CPUMCTX_EXTRN_SYSENTER_MSRS)
1734 {
1735 ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1736 ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1737 ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1738 }
1739 if (fExtrn & CPUMCTX_EXTRN_TSC_AUX)
1740 ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1741 if (fExtrn & CPUMCTX_EXTRN_OTHER_MSRS)
1742 {
1743 ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1744 /** @todo What do we _have_ to add here?
1745 * We also have: Mttr*, MiscEnable, FeatureControl. */
1746 }
1747
1748 uBuf.Core.pad = 0;
1749 uBuf.Core.nmsrs = iMsr;
1750 int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_MSRS, &uBuf);
1751 AssertMsgReturn(rc == (int)iMsr,
1752 ("rc=%d iMsr=%d (->%#x) errno=%d\n",
1753 rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1754 VERR_NEM_IPE_3);
1755 }
1756
1757 /*
1758 * Interruptibility state.
1759 *
1760 * Note! This I/O control function sets most fields passed in, so when
1761 * raising an interrupt, NMI, SMI or exception, this must be done
1762 * by the code doing the rasing or we'll overwrite it here.
1763 */
1764 if (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
1765 {
1766 Assert( (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI))
1767 == (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI));
1768
1769 struct kvm_vcpu_events KvmEvents = {0};
1770
1771 KvmEvents.flags = KVM_VCPUEVENT_VALID_SHADOW;
1772 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1773 {
1774 if (pRun->s.regs.regs.rip == EMGetInhibitInterruptsPC(pVCpu))
1775 KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI;
1776 else
1777 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1778 }
1779
1780 /* No flag - this is updated unconditionally. */
1781 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1782 KvmEvents.nmi.masked = 1;
1783
1784 if (TRPMHasTrap(pVCpu))
1785 {
1786 TRPMEVENT enmType = TRPM_32BIT_HACK;
1787 uint8_t bTrapNo = 0;
1788 TRPMQueryTrap(pVCpu, &bTrapNo, &enmType);
1789 Log(("nemHCLnxExportState: Pending trap: bTrapNo=%#x enmType=%d\n", bTrapNo, enmType));
1790 if ( enmType == TRPM_HARDWARE_INT
1791 || enmType == TRPM_SOFTWARE_INT)
1792 {
1793 KvmEvents.interrupt.soft = enmType == TRPM_SOFTWARE_INT;
1794 KvmEvents.interrupt.nr = bTrapNo;
1795 KvmEvents.interrupt.injected = 1;
1796 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExportPendingInterrupt);
1797 TRPMResetTrap(pVCpu);
1798 }
1799 else
1800 AssertFailed();
1801 }
1802
1803 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
1804 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1805 }
1806
1807 /*
1808 * KVM now owns all the state.
1809 */
1810 pCtx->fExtrn = CPUMCTX_EXTRN_KEEPER_NEM | CPUMCTX_EXTRN_ALL;
1811
1812 RT_NOREF(pVM);
1813 return VINF_SUCCESS;
1814}
1815
1816
1817/**
1818 * Query the CPU tick counter and optionally the TSC_AUX MSR value.
1819 *
1820 * @returns VBox status code.
1821 * @param pVCpu The cross context CPU structure.
1822 * @param pcTicks Where to return the CPU tick count.
1823 * @param puAux Where to return the TSC_AUX register value.
1824 */
1825VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t *pcTicks, uint32_t *puAux)
1826{
1827 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1828 // KVM_GET_CLOCK?
1829 RT_NOREF(pVCpu, pcTicks, puAux);
1830 return VINF_SUCCESS;
1831}
1832
1833
1834/**
1835 * Resumes CPU clock (TSC) on all virtual CPUs.
1836 *
1837 * This is called by TM when the VM is started, restored, resumed or similar.
1838 *
1839 * @returns VBox status code.
1840 * @param pVM The cross context VM structure.
1841 * @param pVCpu The cross context CPU structure of the calling EMT.
1842 * @param uPausedTscValue The TSC value at the time of pausing.
1843 */
1844VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1845{
1846 // KVM_SET_CLOCK?
1847 RT_NOREF(pVM, pVCpu, uPausedTscValue);
1848 return VINF_SUCCESS;
1849}
1850
1851
1852VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
1853{
1854 RT_NOREF(pVM);
1855 return NEM_FEAT_F_NESTED_PAGING
1856 | NEM_FEAT_F_FULL_GST_EXEC
1857 | NEM_FEAT_F_XSAVE_XRSTOR;
1858}
1859
1860
1861
1862/*********************************************************************************************************************************
1863* Execution *
1864*********************************************************************************************************************************/
1865
1866
1867VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
1868{
1869 /*
1870 * Only execute when the A20 gate is enabled as I cannot immediately
1871 * spot any A20 support in KVM.
1872 */
1873 RT_NOREF(pVM);
1874 Assert(VM_IS_NEM_ENABLED(pVM));
1875 return PGMPhysIsA20Enabled(pVCpu);
1876}
1877
1878
1879bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
1880{
1881 NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
1882 return false;
1883}
1884
1885
1886/**
1887 * Forced flag notification call from VMEmt.cpp.
1888 *
1889 * This is only called when pVCpu is in the VMCPUSTATE_STARTED_EXEC_NEM state.
1890 *
1891 * @param pVM The cross context VM structure.
1892 * @param pVCpu The cross context virtual CPU structure of the CPU
1893 * to be notified.
1894 * @param fFlags Notification flags, VMNOTIFYFF_FLAGS_XXX.
1895 */
1896void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
1897{
1898 int rc = RTThreadPoke(pVCpu->hThread);
1899 LogFlow(("nemR3NativeNotifyFF: #%u -> %Rrc\n", pVCpu->idCpu, rc));
1900 AssertRC(rc);
1901 RT_NOREF(pVM, fFlags);
1902}
1903
1904
1905/**
1906 * Deals with pending interrupt FFs prior to executing guest code.
1907 */
1908static VBOXSTRICTRC nemHCLnxHandleInterruptFF(PVM pVM, PVMCPU pVCpu, struct kvm_run *pRun)
1909{
1910 RT_NOREF_PV(pVM);
1911
1912 /*
1913 * Do not doing anything if TRPM has something pending already as we can
1914 * only inject one event per KVM_RUN call. This can only happend if we
1915 * can directly from the loop in EM, so the inhibit bits must be internal.
1916 */
1917 if (!TRPMHasTrap(pVCpu))
1918 { /* semi likely */ }
1919 else
1920 {
1921 Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI)));
1922 Log8(("nemHCLnxHandleInterruptFF: TRPM has an pending event already\n"));
1923 return VINF_SUCCESS;
1924 }
1925
1926 /*
1927 * First update APIC. We ASSUME this won't need TPR/CR8.
1928 */
1929 if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
1930 {
1931 APICUpdatePendingInterrupts(pVCpu);
1932 if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
1933 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
1934 return VINF_SUCCESS;
1935 }
1936
1937 /*
1938 * We don't currently implement SMIs.
1939 */
1940 AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);
1941
1942 /*
1943 * In KVM the CPUMCTX_EXTRN_INHIBIT_INT and CPUMCTX_EXTRN_INHIBIT_NMI states
1944 * are tied together with interrupt and NMI delivery, so we must get and
1945 * synchronize these all in one go and set both CPUMCTX_EXTRN_INHIBIT_XXX flags.
1946 * If we don't we may lose the interrupt/NMI we marked pending here when the
1947 * state is exported again before execution.
1948 */
1949 struct kvm_vcpu_events KvmEvents = {0};
1950 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
1951 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
1952
1953 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP))
1954 pRun->s.regs.regs.rip = pVCpu->cpum.GstCtx.rip;
1955
1956 KvmEvents.flags |= KVM_VCPUEVENT_VALID_SHADOW;
1957 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))
1958 {
1959 if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1960 KvmEvents.interrupt.shadow = 0;
1961 else if (EMGetInhibitInterruptsPC(pVCpu) == pRun->s.regs.regs.rip)
1962 KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS | KVM_X86_SHADOW_INT_STI;
1963 else
1964 {
1965 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1966 KvmEvents.interrupt.shadow = 0;
1967 }
1968 }
1969 else if (KvmEvents.interrupt.shadow)
1970 EMSetInhibitInterruptsPC(pVCpu, pRun->s.regs.regs.rip);
1971 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1972 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1973
1974 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))
1975 KvmEvents.nmi.masked = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS) ? 1 : 0;
1976 else if (KvmEvents.nmi.masked)
1977 VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1978 else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1979 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1980
1981 /* KVM will own the INT + NMI inhibit state soon: */
1982 pVCpu->cpum.GstCtx.fExtrn = (pVCpu->cpum.GstCtx.fExtrn & ~CPUMCTX_EXTRN_KEEPER_MASK)
1983 | CPUMCTX_EXTRN_KEEPER_NEM | CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI;
1984
1985 /*
1986 * NMI? Try deliver it first.
1987 */
1988 if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))
1989 {
1990#if 0
1991 int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_NMI, 0UL);
1992 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
1993#else
1994 KvmEvents.flags |= KVM_VCPUEVENT_VALID_NMI_PENDING;
1995 KvmEvents.nmi.pending = 1;
1996#endif
1997 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
1998 Log8(("Queuing NMI on %u\n", pVCpu->idCpu));
1999 }
2000
2001 /*
2002 * APIC or PIC interrupt?
2003 */
2004 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2005 {
2006 if (pRun->s.regs.regs.rflags & X86_EFL_IF)
2007 {
2008 if (KvmEvents.interrupt.shadow == 0)
2009 {
2010 /*
2011 * If CR8 is in KVM, update the VBox copy so PDMGetInterrupt will
2012 * work correctly.
2013 */
2014 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_APIC_TPR)
2015 APICSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);
2016
2017 uint8_t bInterrupt;
2018 int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2019 if (RT_SUCCESS(rc))
2020 {
2021 Assert(KvmEvents.interrupt.injected == false);
2022#if 0
2023 int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_INTERRUPT, (unsigned long)bInterrupt);
2024 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2025#else
2026 KvmEvents.interrupt.nr = bInterrupt;
2027 KvmEvents.interrupt.soft = false;
2028 KvmEvents.interrupt.injected = true;
2029#endif
2030 Log8(("Queuing interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu,
2031 pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags));
2032 }
2033 else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) /** @todo this isn't extremely efficient if we get a lot of exits... */
2034 Log8(("VERR_APIC_INTR_MASKED_BY_TPR\n")); /* We'll get a TRP exit - no interrupt window needed. */
2035 else
2036 Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));
2037 }
2038 else
2039 {
2040 pRun->request_interrupt_window = 1;
2041 Log8(("Interrupt window pending on %u (#2)\n", pVCpu->idCpu));
2042 }
2043 }
2044 else
2045 {
2046 pRun->request_interrupt_window = 1;
2047 Log8(("Interrupt window pending on %u (#1)\n", pVCpu->idCpu));
2048 }
2049 }
2050
2051 /*
2052 * Now, update the state.
2053 */
2054 /** @todo skip when possible... */
2055 rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
2056 AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2057
2058 return VINF_SUCCESS;
2059}
2060
2061
2062/**
2063 * Handles KVM_EXIT_INTERNAL_ERROR.
2064 */
2065static VBOXSTRICTRC nemR3LnxHandleInternalError(PVMCPU pVCpu, struct kvm_run *pRun)
2066{
2067 Log(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%d) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror,
2068 pRun->internal.suberror, pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2069
2070 /*
2071 * Deal with each suberror, returning if we don't want IEM to handle it.
2072 */
2073 switch (pRun->internal.suberror)
2074 {
2075 case KVM_INTERNAL_ERROR_EMULATION:
2076 {
2077 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_EMULATION),
2078 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2079 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorEmulation);
2080 break;
2081 }
2082
2083 case KVM_INTERNAL_ERROR_SIMUL_EX:
2084 case KVM_INTERNAL_ERROR_DELIVERY_EV:
2085 case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON:
2086 default:
2087 {
2088 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_FATAL),
2089 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2090 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorFatal);
2091 const char *pszName;
2092 switch (pRun->internal.suberror)
2093 {
2094 case KVM_INTERNAL_ERROR_EMULATION: pszName = "KVM_INTERNAL_ERROR_EMULATION"; break;
2095 case KVM_INTERNAL_ERROR_SIMUL_EX: pszName = "KVM_INTERNAL_ERROR_SIMUL_EX"; break;
2096 case KVM_INTERNAL_ERROR_DELIVERY_EV: pszName = "KVM_INTERNAL_ERROR_DELIVERY_EV"; break;
2097 case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON: pszName = "KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON"; break;
2098 default: pszName = "unknown"; break;
2099 }
2100 LogRel(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%s) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror, pszName,
2101 pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2102 return VERR_NEM_IPE_0;
2103 }
2104 }
2105
2106 /*
2107 * Execute instruction in IEM and try get on with it.
2108 */
2109 Log2(("nemR3LnxHandleInternalError: Executing instruction at %04x:%08RX64 in IEM\n",
2110 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip));
2111 VBOXSTRICTRC rcStrict = nemHCLnxImportState(pVCpu,
2112 IEM_CPUMCTX_EXTRN_MUST_MASK | CPUMCTX_EXTRN_INHIBIT_INT
2113 | CPUMCTX_EXTRN_INHIBIT_NMI,
2114 &pVCpu->cpum.GstCtx, pRun);
2115 if (RT_SUCCESS(rcStrict))
2116 rcStrict = IEMExecOne(pVCpu);
2117 return rcStrict;
2118}
2119
2120
2121/**
2122 * Handles KVM_EXIT_IO.
2123 */
2124static VBOXSTRICTRC nemHCLnxHandleExitIo(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2125{
2126 /*
2127 * Input validation.
2128 */
2129 Assert(pRun->io.count > 0);
2130 Assert(pRun->io.size == 1 || pRun->io.size == 2 || pRun->io.size == 4);
2131 Assert(pRun->io.direction == KVM_EXIT_IO_IN || pRun->io.direction == KVM_EXIT_IO_OUT);
2132 Assert(pRun->io.data_offset < pVM->nem.s.cbVCpuMmap);
2133 Assert(pRun->io.data_offset + pRun->io.size * pRun->io.count <= pVM->nem.s.cbVCpuMmap);
2134
2135 /*
2136 * We cannot actually act on the exit history here, because the I/O port
2137 * exit is stateful and the instruction will be completed in the next
2138 * KVM_RUN call. There seems no way to avoid this.
2139 */
2140 EMHistoryAddExit(pVCpu,
2141 pRun->io.count == 1
2142 ? ( pRun->io.direction == KVM_EXIT_IO_IN
2143 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)
2144 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE))
2145 : ( pRun->io.direction == KVM_EXIT_IO_IN
2146 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)
2147 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)),
2148 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2149
2150 /*
2151 * Do the requested job.
2152 */
2153 VBOXSTRICTRC rcStrict;
2154 RTPTRUNION uPtrData;
2155 uPtrData.pu8 = (uint8_t *)pRun + pRun->io.data_offset;
2156 if (pRun->io.count == 1)
2157 {
2158 if (pRun->io.direction == KVM_EXIT_IO_IN)
2159 {
2160 uint32_t uValue = 0;
2161 rcStrict = IOMIOPortRead(pVM, pVCpu, pRun->io.port, &uValue, pRun->io.size);
2162 Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",
2163 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2164 pRun->io.port, pRun->io.size, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
2165 if (IOM_SUCCESS(rcStrict))
2166 {
2167 if (pRun->io.size == 4)
2168 *uPtrData.pu32 = uValue;
2169 else if (pRun->io.size == 2)
2170 *uPtrData.pu16 = (uint16_t)uValue;
2171 else
2172 *uPtrData.pu8 = (uint8_t)uValue;
2173 }
2174 }
2175 else
2176 {
2177 uint32_t const uValue = pRun->io.size == 4 ? *uPtrData.pu32
2178 : pRun->io.size == 2 ? *uPtrData.pu16
2179 : *uPtrData.pu8;
2180 rcStrict = IOMIOPortWrite(pVM, pVCpu, pRun->io.port, uValue, pRun->io.size);
2181 Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
2182 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2183 pRun->io.port, uValue, pRun->io.size, VBOXSTRICTRC_VAL(rcStrict) ));
2184 }
2185 }
2186 else
2187 {
2188 uint32_t cTransfers = pRun->io.count;
2189 if (pRun->io.direction == KVM_EXIT_IO_IN)
2190 {
2191 rcStrict = IOMIOPortReadString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2192 Log4(("IOExit/%u: %04x:%08RX64: REP INS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2193 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2194 pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2195 }
2196 else
2197 {
2198 rcStrict = IOMIOPortWriteString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2199 Log4(("IOExit/%u: %04x:%08RX64: REP OUTS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2200 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2201 pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2202 }
2203 Assert(cTransfers == 0);
2204 }
2205 return rcStrict;
2206}
2207
2208
2209/**
2210 * Handles KVM_EXIT_MMIO.
2211 */
2212static VBOXSTRICTRC nemHCLnxHandleExitMmio(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2213{
2214 /*
2215 * Input validation.
2216 */
2217 Assert(pRun->mmio.len <= sizeof(pRun->mmio.data));
2218 Assert(pRun->mmio.is_write <= 1);
2219
2220 /*
2221 * We cannot actually act on the exit history here, because the MMIO port
2222 * exit is stateful and the instruction will be completed in the next
2223 * KVM_RUN call. There seems no way to circumvent this.
2224 */
2225 EMHistoryAddExit(pVCpu,
2226 pRun->mmio.is_write
2227 ? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
2228 : EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
2229 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2230
2231 /*
2232 * Do the requested job.
2233 */
2234 VBOXSTRICTRC rcStrict;
2235 if (pRun->mmio.is_write)
2236 {
2237 rcStrict = PGMPhysWrite(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2238 Log4(("MmioExit/%u: %04x:%08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
2239 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2240 pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2241 }
2242 else
2243 {
2244 rcStrict = PGMPhysRead(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2245 Log4(("MmioExit/%u: %04x:%08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
2246 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2247 pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2248 }
2249 return rcStrict;
2250}
2251
2252
2253static VBOXSTRICTRC nemHCLnxHandleExit(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun, bool *pfStatefulExit)
2254{
2255 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTotal);
2256 switch (pRun->exit_reason)
2257 {
2258 case KVM_EXIT_EXCEPTION:
2259 AssertFailed();
2260 break;
2261
2262 case KVM_EXIT_IO:
2263 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIo);
2264 *pfStatefulExit = true;
2265 return nemHCLnxHandleExitIo(pVM, pVCpu, pRun);
2266
2267 case KVM_EXIT_MMIO:
2268 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMmio);
2269 *pfStatefulExit = true;
2270 return nemHCLnxHandleExitMmio(pVM, pVCpu, pRun);
2271
2272 case KVM_EXIT_IRQ_WINDOW_OPEN:
2273 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW),
2274 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2275 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIrqWindowOpen);
2276 Log5(("IrqWinOpen/%u: %d\n", pVCpu->idCpu, pRun->request_interrupt_window));
2277 pRun->request_interrupt_window = 0;
2278 return VINF_SUCCESS;
2279
2280 case KVM_EXIT_SET_TPR:
2281 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitSetTpr);
2282 AssertFailed();
2283 break;
2284
2285 case KVM_EXIT_TPR_ACCESS:
2286 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTprAccess);
2287 AssertFailed();
2288 break;
2289
2290 case KVM_EXIT_X86_RDMSR:
2291 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitRdMsr);
2292 AssertFailed();
2293 break;
2294
2295 case KVM_EXIT_X86_WRMSR:
2296 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitWrMsr);
2297 AssertFailed();
2298 break;
2299
2300 case KVM_EXIT_HLT:
2301 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT),
2302 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2303 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
2304 Log5(("Halt/%u\n", pVCpu->idCpu));
2305 return VINF_EM_HALT;
2306
2307 case KVM_EXIT_INTR: /* EINTR */
2308 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERRUPTED),
2309 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2310 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIntr);
2311 Log5(("Intr/%u\n", pVCpu->idCpu));
2312 return VINF_SUCCESS;
2313
2314 case KVM_EXIT_HYPERCALL:
2315 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHypercall);
2316 AssertFailed();
2317 break;
2318
2319 case KVM_EXIT_DEBUG:
2320 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitDebug);
2321 AssertFailed();
2322 break;
2323
2324 case KVM_EXIT_SYSTEM_EVENT:
2325 AssertFailed();
2326 break;
2327 case KVM_EXIT_IOAPIC_EOI:
2328 AssertFailed();
2329 break;
2330 case KVM_EXIT_HYPERV:
2331 AssertFailed();
2332 break;
2333
2334 case KVM_EXIT_DIRTY_RING_FULL:
2335 AssertFailed();
2336 break;
2337 case KVM_EXIT_AP_RESET_HOLD:
2338 AssertFailed();
2339 break;
2340 case KVM_EXIT_X86_BUS_LOCK:
2341 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitBusLock);
2342 AssertFailed();
2343 break;
2344
2345
2346 case KVM_EXIT_SHUTDOWN:
2347 AssertFailed();
2348 break;
2349
2350 case KVM_EXIT_FAIL_ENTRY:
2351 LogRel(("NEM: KVM_EXIT_FAIL_ENTRY! hardware_entry_failure_reason=%#x cpu=%#x\n",
2352 pRun->fail_entry.hardware_entry_failure_reason, pRun->fail_entry.cpu));
2353 EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_FAILED_ENTRY),
2354 pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2355 return VERR_NEM_IPE_1;
2356
2357 case KVM_EXIT_INTERNAL_ERROR:
2358 /* we're counting sub-reasons inside the function. */
2359 return nemR3LnxHandleInternalError(pVCpu, pRun);
2360
2361 /*
2362 * Foreign and unknowns.
2363 */
2364 case KVM_EXIT_NMI:
2365 AssertLogRelMsgFailedReturn(("KVM_EXIT_NMI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2366 case KVM_EXIT_EPR:
2367 AssertLogRelMsgFailedReturn(("KVM_EXIT_EPR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2368 case KVM_EXIT_WATCHDOG:
2369 AssertLogRelMsgFailedReturn(("KVM_EXIT_WATCHDOG on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2370 case KVM_EXIT_ARM_NISV:
2371 AssertLogRelMsgFailedReturn(("KVM_EXIT_ARM_NISV on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2372 case KVM_EXIT_S390_STSI:
2373 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_STSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2374 case KVM_EXIT_S390_TSCH:
2375 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_TSCH on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2376 case KVM_EXIT_OSI:
2377 AssertLogRelMsgFailedReturn(("KVM_EXIT_OSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2378 case KVM_EXIT_PAPR_HCALL:
2379 AssertLogRelMsgFailedReturn(("KVM_EXIT_PAPR_HCALL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2380 case KVM_EXIT_S390_UCONTROL:
2381 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_UCONTROL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2382 case KVM_EXIT_DCR:
2383 AssertLogRelMsgFailedReturn(("KVM_EXIT_DCR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2384 case KVM_EXIT_S390_SIEIC:
2385 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_SIEIC on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2386 case KVM_EXIT_S390_RESET:
2387 AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_RESET on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2388 case KVM_EXIT_UNKNOWN:
2389 AssertLogRelMsgFailedReturn(("KVM_EXIT_UNKNOWN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2390 case KVM_EXIT_XEN:
2391 AssertLogRelMsgFailedReturn(("KVM_EXIT_XEN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2392 default:
2393 AssertLogRelMsgFailedReturn(("Unknown exit reason %u on VCpu #%u at %04x:%RX64!\n", pRun->exit_reason, pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2394 }
2395
2396 RT_NOREF(pVM, pVCpu, pRun);
2397 return VERR_NOT_IMPLEMENTED;
2398}
2399
2400
2401VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2402{
2403 /*
2404 * Try switch to NEM runloop state.
2405 */
2406 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2407 { /* likely */ }
2408 else
2409 {
2410 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2411 LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2412 return VINF_SUCCESS;
2413 }
2414
2415 /*
2416 * The run loop.
2417 */
2418 struct kvm_run * const pRun = pVCpu->nem.s.pRun;
2419 const bool fSingleStepping = DBGFIsStepping(pVCpu);
2420 VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2421 bool fStatefulExit = false; /* For MMIO and IO exits. */
2422 for (unsigned iLoop = 0;; iLoop++)
2423 {
2424 /*
2425 * Pending interrupts or such? Need to check and deal with this prior
2426 * to the state syncing.
2427 */
2428 if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC
2429 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2430 {
2431 /* Try inject interrupt. */
2432 rcStrict = nemHCLnxHandleInterruptFF(pVM, pVCpu, pRun);
2433 if (rcStrict == VINF_SUCCESS)
2434 { /* likely */ }
2435 else
2436 {
2437 LogFlow(("NEM/%u: breaking: nemHCLnxHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2438 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2439 break;
2440 }
2441 }
2442
2443 /*
2444 * Do not execute in KVM if the A20 isn't enabled.
2445 */
2446 if (PGMPhysIsA20Enabled(pVCpu))
2447 { /* likely */ }
2448 else
2449 {
2450 rcStrict = VINF_EM_RESCHEDULE_REM;
2451 LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
2452 break;
2453 }
2454
2455 /*
2456 * Ensure KVM has the whole state.
2457 */
2458 if ((pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL)
2459 {
2460 int rc2 = nemHCLnxExportState(pVM, pVCpu, &pVCpu->cpum.GstCtx, pRun);
2461 AssertRCReturn(rc2, rc2);
2462 }
2463
2464 /*
2465 * Poll timers and run for a bit.
2466 *
2467 * With the VID approach (ring-0 or ring-3) we can specify a timeout here,
2468 * so we take the time of the next timer event and uses that as a deadline.
2469 * The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.
2470 */
2471 /** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2472 * the whole polling job when timers have changed... */
2473 uint64_t offDeltaIgnored;
2474 uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2475 if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS | VM_FF_TM_VIRTUAL_SYNC)
2476 && !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2477 {
2478 if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2479 {
2480 LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",
2481 pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2482 !!(pRun->s.regs.regs.rflags & X86_EFL_IF), pRun->s.regs.regs.rflags,
2483 pRun->s.regs.sregs.ss.selector, pRun->s.regs.regs.rsp, pRun->s.regs.sregs.cr0));
2484 TMNotifyStartOfExecution(pVM, pVCpu);
2485
2486 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2487
2488 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2489 TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2490
2491#ifdef LOG_ENABLED
2492 if (LogIsFlowEnabled())
2493 {
2494 struct kvm_mp_state MpState = {UINT32_MAX};
2495 ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MP_STATE, &MpState);
2496 LogFlow(("NEM/%u: Exit @ %04x:%08RX64 IF=%d EFL=%#RX64 CR8=%#x Reason=%#x IrqReady=%d Flags=%#x %#lx\n", pVCpu->idCpu,
2497 pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->if_flag,
2498 pRun->s.regs.regs.rflags, pRun->s.regs.sregs.cr8, pRun->exit_reason,
2499 pRun->ready_for_interrupt_injection, pRun->flags, MpState.mp_state));
2500 }
2501#endif
2502 fStatefulExit = false;
2503 if (RT_LIKELY(rcLnx == 0 || errno == EINTR))
2504 {
2505 /*
2506 * Deal with the exit.
2507 */
2508 rcStrict = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);
2509 if (rcStrict == VINF_SUCCESS)
2510 { /* hopefully likely */ }
2511 else
2512 {
2513 LogFlow(("NEM/%u: breaking: nemHCLnxHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2514 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2515 break;
2516 }
2517 }
2518 else
2519 {
2520 int rc2 = RTErrConvertFromErrno(errno);
2521 AssertLogRelMsgFailedReturn(("KVM_RUN failed: rcLnx=%d errno=%u rc=%Rrc\n", rcLnx, errno, rc2), rc2);
2522 }
2523
2524 /*
2525 * If no relevant FFs are pending, loop.
2526 */
2527 if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2528 && !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2529 continue;
2530
2531 /** @todo Try handle pending flags, not just return to EM loops. Take care
2532 * not to set important RCs here unless we've handled an exit. */
2533 LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2534 pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2535 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2536 }
2537 else
2538 {
2539 LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2540 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2541 }
2542 }
2543 else
2544 {
2545 LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2546 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2547 }
2548 break;
2549 } /* the run loop */
2550
2551
2552 /*
2553 * If the last exit was stateful, commit the state we provided before
2554 * returning to the EM loop so we have a consistent state and can safely
2555 * be rescheduled and whatnot. (There is no 'ing way to reset the kernel
2556 * side completion callback for these stateful i/o exits.)
2557 */
2558 if (fStatefulExit)
2559 {
2560 pRun->immediate_exit = 1;
2561 int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2562 pRun->immediate_exit = 0;
2563 Log(("NEM/%u: Flushed stateful exit -> %d/%d exit_reason=%d\n", pVCpu->idCpu, rcLnx, errno, pRun->exit_reason)); RT_NOREF(rcLnx);
2564 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn);
2565 }
2566
2567 /*
2568 * If the CPU is running, make sure to stop it before we try sync back the
2569 * state and return to EM. We don't sync back the whole state if we can help it.
2570 */
2571 if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2572 VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2573
2574 if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL)
2575 {
2576 /* Try anticipate what we might need. */
2577 uint64_t fImport = CPUMCTX_EXTRN_INHIBIT_INT | CPUMCTX_EXTRN_INHIBIT_NMI /* Required for processing APIC,PIC,NMI & SMI FFs. */
2578 | IEM_CPUMCTX_EXTRN_MUST_MASK /*?*/;
2579 if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2580 || RT_FAILURE(rcStrict))
2581 fImport = CPUMCTX_EXTRN_ALL;
2582# ifdef IN_RING0 /* Ring-3 I/O port access optimizations: */
2583 else if ( rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
2584 || rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
2585 fImport = CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS;
2586 else if (rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
2587 fImport = CPUMCTX_EXTRN_RAX | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_RFLAGS;
2588# endif
2589 else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC
2590 | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
2591 fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2592
2593 if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2594 {
2595 int rc2 = nemHCLnxImportState(pVCpu, fImport, &pVCpu->cpum.GstCtx, pRun);
2596 if (RT_SUCCESS(rc2))
2597 pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2598 else if (RT_SUCCESS(rcStrict))
2599 rcStrict = rc2;
2600 if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2601 pVCpu->cpum.GstCtx.fExtrn = 0;
2602 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2603 }
2604 else
2605 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2606 }
2607 else
2608 {
2609 pVCpu->cpum.GstCtx.fExtrn = 0;
2610 STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2611 }
2612
2613 LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
2614 pVCpu->cpum.GstCtx.rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2615 return rcStrict;
2616}
2617
2618
2619/** @page pg_nem_linux NEM/linux - Native Execution Manager, Linux.
2620 *
2621 * This is using KVM.
2622 *
2623 */
2624
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