NEMR3Native-linux.cpp@ 92676

Last change on this file since 92676 was 92626, checked in by vboxsync, 3 years ago
VMM: Nested VMX: bugref:10092 Adjust PGM APIs and translate nested-guest CR3 prior to mapping them when switching mode and other places.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 117.1 KB

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1	/* $Id: NEMR3Native-linux.cpp 92626 2021-11-29 12:32:58Z vboxsync $ */
2	/** @file
3	* NEM - Native execution manager, native ring-3 Linux backend.
4	*/
5
6	/*
7	* Copyright (C) 2021 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_NEM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/nem.h>
25	#include <VBox/vmm/iem.h>
26	#include <VBox/vmm/em.h>
27	#include <VBox/vmm/apic.h>
28	#include <VBox/vmm/pdm.h>
29	#include <VBox/vmm/trpm.h>
30	#include "NEMInternal.h"
31	#include <VBox/vmm/vmcc.h>
32
33	#include <iprt/alloca.h>
34	#include <iprt/string.h>
35	#include <iprt/system.h>
36	#include <iprt/x86.h>
37
38	#include <errno.h>
39	#include <unistd.h>
40	#include <sys/ioctl.h>
41	#include <sys/fcntl.h>
42	#include <sys/mman.h>
43	#include <linux/kvm.h>
44
45	/*
46	* Supply stuff missing from the kvm.h on the build box.
47	*/
48	#ifndef KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON /* since 5.4 */
49	# define KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON 4
50	#endif
51
52
53
54	/**
55	* Worker for nemR3NativeInit that gets the hypervisor capabilities.
56	*
57	* @returns VBox status code.
58	* @param pVM The cross context VM structure.
59	* @param pErrInfo Where to always return error info.
60	*/
61	static int nemR3LnxInitCheckCapabilities(PVM pVM, PRTERRINFO pErrInfo)
62	{
63	AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
64
65	/*
66	* Capabilities.
67	*/
68	static const struct
69	{
70	const char *pszName;
71	int iCap;
72	uint32_t offNem : 24;
73	uint32_t cbNem : 3;
74	uint32_t fReqNonZero : 1;
75	uint32_t uReserved : 4;
76	} s_aCaps[] =
77	{
78	#define CAP_ENTRY__L(a_Define) { #a_Define, a_Define, UINT32_C(0x00ffffff), 0, 0, 0 }
79	#define CAP_ENTRY__S(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 0, 0 }
80	#define CAP_ENTRY_MS(a_Define, a_Member) { #a_Define, a_Define, RT_UOFFSETOF(NEM, a_Member), RT_SIZEOFMEMB(NEM, a_Member), 1, 0 }
81	#define CAP_ENTRY__U(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 0, 0 }
82	#define CAP_ENTRY_ML(a_Number) { "KVM_CAP_" #a_Number, a_Number, UINT32_C(0x00ffffff), 0, 1, 0 }
83
84	CAP_ENTRY__L(KVM_CAP_IRQCHIP), /* 0 */
85	CAP_ENTRY_ML(KVM_CAP_HLT),
86	CAP_ENTRY__L(KVM_CAP_MMU_SHADOW_CACHE_CONTROL),
87	CAP_ENTRY_ML(KVM_CAP_USER_MEMORY),
88	CAP_ENTRY__L(KVM_CAP_SET_TSS_ADDR),
89	CAP_ENTRY__U(5),
90	CAP_ENTRY__L(KVM_CAP_VAPIC),
91	CAP_ENTRY__L(KVM_CAP_EXT_CPUID),
92	CAP_ENTRY__L(KVM_CAP_CLOCKSOURCE),
93	CAP_ENTRY__L(KVM_CAP_NR_VCPUS),
94	CAP_ENTRY_MS(KVM_CAP_NR_MEMSLOTS, cMaxMemSlots), /* 10 */
95	CAP_ENTRY__L(KVM_CAP_PIT),
96	CAP_ENTRY__L(KVM_CAP_NOP_IO_DELAY),
97	CAP_ENTRY__L(KVM_CAP_PV_MMU),
98	CAP_ENTRY__L(KVM_CAP_MP_STATE),
99	CAP_ENTRY__L(KVM_CAP_COALESCED_MMIO),
100	CAP_ENTRY__L(KVM_CAP_SYNC_MMU),
101	CAP_ENTRY__U(17),
102	CAP_ENTRY__L(KVM_CAP_IOMMU),
103	CAP_ENTRY__U(19), /* Buggy KVM_CAP_JOIN_MEMORY_REGIONS? */
104	CAP_ENTRY__U(20), /* Mon-working KVM_CAP_DESTROY_MEMORY_REGION? */
105	CAP_ENTRY__L(KVM_CAP_DESTROY_MEMORY_REGION_WORKS), /* 21 */
106	CAP_ENTRY__L(KVM_CAP_USER_NMI),
107	#ifdef __KVM_HAVE_GUEST_DEBUG
108	CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG),
109	#endif
110	#ifdef __KVM_HAVE_PIT
111	CAP_ENTRY__L(KVM_CAP_REINJECT_CONTROL),
112	#endif
113	CAP_ENTRY__L(KVM_CAP_IRQ_ROUTING),
114	CAP_ENTRY__L(KVM_CAP_IRQ_INJECT_STATUS),
115	CAP_ENTRY__U(27),
116	CAP_ENTRY__U(28),
117	CAP_ENTRY__L(KVM_CAP_ASSIGN_DEV_IRQ),
118	CAP_ENTRY__L(KVM_CAP_JOIN_MEMORY_REGIONS_WORKS), /* 30 */
119	#ifdef __KVM_HAVE_MCE
120	CAP_ENTRY__L(KVM_CAP_MCE),
121	#endif
122	CAP_ENTRY__L(KVM_CAP_IRQFD),
123	#ifdef __KVM_HAVE_PIT
124	CAP_ENTRY__L(KVM_CAP_PIT2),
125	#endif
126	CAP_ENTRY__L(KVM_CAP_SET_BOOT_CPU_ID),
127	#ifdef __KVM_HAVE_PIT_STATE2
128	CAP_ENTRY__L(KVM_CAP_PIT_STATE2),
129	#endif
130	CAP_ENTRY__L(KVM_CAP_IOEVENTFD),
131	CAP_ENTRY__L(KVM_CAP_SET_IDENTITY_MAP_ADDR),
132	#ifdef __KVM_HAVE_XEN_HVM
133	CAP_ENTRY__L(KVM_CAP_XEN_HVM),
134	#endif
135	CAP_ENTRY_ML(KVM_CAP_ADJUST_CLOCK),
136	CAP_ENTRY__L(KVM_CAP_INTERNAL_ERROR_DATA), /* 40 */
137	#ifdef __KVM_HAVE_VCPU_EVENTS
138	CAP_ENTRY_ML(KVM_CAP_VCPU_EVENTS),
139	#else
140	CAP_ENTRY_MU(41),
141	#endif
142	CAP_ENTRY__L(KVM_CAP_S390_PSW),
143	CAP_ENTRY__L(KVM_CAP_PPC_SEGSTATE),
144	CAP_ENTRY__L(KVM_CAP_HYPERV),
145	CAP_ENTRY__L(KVM_CAP_HYPERV_VAPIC),
146	CAP_ENTRY__L(KVM_CAP_HYPERV_SPIN),
147	CAP_ENTRY__L(KVM_CAP_PCI_SEGMENT),
148	CAP_ENTRY__L(KVM_CAP_PPC_PAIRED_SINGLES),
149	CAP_ENTRY__L(KVM_CAP_INTR_SHADOW),
150	#ifdef __KVM_HAVE_DEBUGREGS
151	CAP_ENTRY__L(KVM_CAP_DEBUGREGS), /* 50 */
152	#endif
153	CAP_ENTRY__S(KVM_CAP_X86_ROBUST_SINGLESTEP, fRobustSingleStep),
154	CAP_ENTRY__L(KVM_CAP_PPC_OSI),
155	CAP_ENTRY__L(KVM_CAP_PPC_UNSET_IRQ),
156	CAP_ENTRY__L(KVM_CAP_ENABLE_CAP),
157	#ifdef __KVM_HAVE_XSAVE
158	CAP_ENTRY_ML(KVM_CAP_XSAVE),
159	#else
160	CAP_ENTRY_MU(55),
161	#endif
162	#ifdef __KVM_HAVE_XCRS
163	CAP_ENTRY_ML(KVM_CAP_XCRS),
164	#else
165	CAP_ENTRY_MU(56),
166	#endif
167	CAP_ENTRY__L(KVM_CAP_PPC_GET_PVINFO),
168	CAP_ENTRY__L(KVM_CAP_PPC_IRQ_LEVEL),
169	CAP_ENTRY__L(KVM_CAP_ASYNC_PF),
170	CAP_ENTRY__L(KVM_CAP_TSC_CONTROL), /* 60 */
171	CAP_ENTRY__L(KVM_CAP_GET_TSC_KHZ),
172	CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_SREGS),
173	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE),
174	CAP_ENTRY__L(KVM_CAP_PPC_SMT),
175	CAP_ENTRY__L(KVM_CAP_PPC_RMA),
176	CAP_ENTRY__L(KVM_CAP_MAX_VCPUS),
177	CAP_ENTRY__L(KVM_CAP_PPC_HIOR),
178	CAP_ENTRY__L(KVM_CAP_PPC_PAPR),
179	CAP_ENTRY__L(KVM_CAP_SW_TLB),
180	CAP_ENTRY__L(KVM_CAP_ONE_REG), /* 70 */
181	CAP_ENTRY__L(KVM_CAP_S390_GMAP),
182	CAP_ENTRY__L(KVM_CAP_TSC_DEADLINE_TIMER),
183	CAP_ENTRY__L(KVM_CAP_S390_UCONTROL),
184	CAP_ENTRY__L(KVM_CAP_SYNC_REGS),
185	CAP_ENTRY__L(KVM_CAP_PCI_2_3),
186	CAP_ENTRY__L(KVM_CAP_KVMCLOCK_CTRL),
187	CAP_ENTRY__L(KVM_CAP_SIGNAL_MSI),
188	CAP_ENTRY__L(KVM_CAP_PPC_GET_SMMU_INFO),
189	CAP_ENTRY__L(KVM_CAP_S390_COW),
190	CAP_ENTRY__L(KVM_CAP_PPC_ALLOC_HTAB), /* 80 */
191	CAP_ENTRY__L(KVM_CAP_READONLY_MEM),
192	CAP_ENTRY__L(KVM_CAP_IRQFD_RESAMPLE),
193	CAP_ENTRY__L(KVM_CAP_PPC_BOOKE_WATCHDOG),
194	CAP_ENTRY__L(KVM_CAP_PPC_HTAB_FD),
195	CAP_ENTRY__L(KVM_CAP_S390_CSS_SUPPORT),
196	CAP_ENTRY__L(KVM_CAP_PPC_EPR),
197	CAP_ENTRY__L(KVM_CAP_ARM_PSCI),
198	CAP_ENTRY__L(KVM_CAP_ARM_SET_DEVICE_ADDR),
199	CAP_ENTRY__L(KVM_CAP_DEVICE_CTRL),
200	CAP_ENTRY__L(KVM_CAP_IRQ_MPIC), /* 90 */
201	CAP_ENTRY__L(KVM_CAP_PPC_RTAS),
202	CAP_ENTRY__L(KVM_CAP_IRQ_XICS),
203	CAP_ENTRY__L(KVM_CAP_ARM_EL1_32BIT),
204	CAP_ENTRY__L(KVM_CAP_SPAPR_MULTITCE),
205	CAP_ENTRY__L(KVM_CAP_EXT_EMUL_CPUID),
206	CAP_ENTRY__L(KVM_CAP_HYPERV_TIME),
207	CAP_ENTRY__L(KVM_CAP_IOAPIC_POLARITY_IGNORED),
208	CAP_ENTRY__L(KVM_CAP_ENABLE_CAP_VM),
209	CAP_ENTRY__L(KVM_CAP_S390_IRQCHIP),
210	CAP_ENTRY__L(KVM_CAP_IOEVENTFD_NO_LENGTH), /* 100 */
211	CAP_ENTRY__L(KVM_CAP_VM_ATTRIBUTES),
212	CAP_ENTRY__L(KVM_CAP_ARM_PSCI_0_2),
213	CAP_ENTRY__L(KVM_CAP_PPC_FIXUP_HCALL),
214	CAP_ENTRY__L(KVM_CAP_PPC_ENABLE_HCALL),
215	CAP_ENTRY__L(KVM_CAP_CHECK_EXTENSION_VM),
216	CAP_ENTRY__L(KVM_CAP_S390_USER_SIGP),
217	CAP_ENTRY__L(KVM_CAP_S390_VECTOR_REGISTERS),
218	CAP_ENTRY__L(KVM_CAP_S390_MEM_OP),
219	CAP_ENTRY__L(KVM_CAP_S390_USER_STSI),
220	CAP_ENTRY__L(KVM_CAP_S390_SKEYS), /* 110 */
221	CAP_ENTRY__L(KVM_CAP_MIPS_FPU),
222	CAP_ENTRY__L(KVM_CAP_MIPS_MSA),
223	CAP_ENTRY__L(KVM_CAP_S390_INJECT_IRQ),
224	CAP_ENTRY__L(KVM_CAP_S390_IRQ_STATE),
225	CAP_ENTRY__L(KVM_CAP_PPC_HWRNG),
226	CAP_ENTRY__L(KVM_CAP_DISABLE_QUIRKS),
227	CAP_ENTRY__L(KVM_CAP_X86_SMM),
228	CAP_ENTRY__L(KVM_CAP_MULTI_ADDRESS_SPACE),
229	CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_BPS),
230	CAP_ENTRY__L(KVM_CAP_GUEST_DEBUG_HW_WPS), /* 120 */
231	CAP_ENTRY__L(KVM_CAP_SPLIT_IRQCHIP),
232	CAP_ENTRY__L(KVM_CAP_IOEVENTFD_ANY_LENGTH),
233	CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC),
234	CAP_ENTRY__L(KVM_CAP_S390_RI),
235	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_64),
236	CAP_ENTRY__L(KVM_CAP_ARM_PMU_V3),
237	CAP_ENTRY__L(KVM_CAP_VCPU_ATTRIBUTES),
238	CAP_ENTRY__L(KVM_CAP_MAX_VCPU_ID),
239	CAP_ENTRY__L(KVM_CAP_X2APIC_API),
240	CAP_ENTRY__L(KVM_CAP_S390_USER_INSTR0), /* 130 */
241	CAP_ENTRY__L(KVM_CAP_MSI_DEVID),
242	CAP_ENTRY__L(KVM_CAP_PPC_HTM),
243	CAP_ENTRY__L(KVM_CAP_SPAPR_RESIZE_HPT),
244	CAP_ENTRY__L(KVM_CAP_PPC_MMU_RADIX),
245	CAP_ENTRY__L(KVM_CAP_PPC_MMU_HASH_V3),
246	CAP_ENTRY__L(KVM_CAP_IMMEDIATE_EXIT),
247	CAP_ENTRY__L(KVM_CAP_MIPS_VZ),
248	CAP_ENTRY__L(KVM_CAP_MIPS_TE),
249	CAP_ENTRY__L(KVM_CAP_MIPS_64BIT),
250	CAP_ENTRY__L(KVM_CAP_S390_GS), /* 140 */
251	CAP_ENTRY__L(KVM_CAP_S390_AIS),
252	CAP_ENTRY__L(KVM_CAP_SPAPR_TCE_VFIO),
253	CAP_ENTRY__L(KVM_CAP_X86_DISABLE_EXITS),
254	CAP_ENTRY__L(KVM_CAP_ARM_USER_IRQ),
255	CAP_ENTRY__L(KVM_CAP_S390_CMMA_MIGRATION),
256	CAP_ENTRY__L(KVM_CAP_PPC_FWNMI),
257	CAP_ENTRY__L(KVM_CAP_PPC_SMT_POSSIBLE),
258	CAP_ENTRY__L(KVM_CAP_HYPERV_SYNIC2),
259	CAP_ENTRY__L(KVM_CAP_HYPERV_VP_INDEX),
260	CAP_ENTRY__L(KVM_CAP_S390_AIS_MIGRATION), /* 150 */
261	CAP_ENTRY__L(KVM_CAP_PPC_GET_CPU_CHAR),
262	CAP_ENTRY__L(KVM_CAP_S390_BPB),
263	CAP_ENTRY__L(KVM_CAP_GET_MSR_FEATURES),
264	CAP_ENTRY__L(KVM_CAP_HYPERV_EVENTFD),
265	CAP_ENTRY__L(KVM_CAP_HYPERV_TLBFLUSH),
266	CAP_ENTRY__L(KVM_CAP_S390_HPAGE_1M),
267	CAP_ENTRY__L(KVM_CAP_NESTED_STATE),
268	CAP_ENTRY__L(KVM_CAP_ARM_INJECT_SERROR_ESR),
269	CAP_ENTRY__L(KVM_CAP_MSR_PLATFORM_INFO),
270	CAP_ENTRY__L(KVM_CAP_PPC_NESTED_HV), /* 160 */
271	CAP_ENTRY__L(KVM_CAP_HYPERV_SEND_IPI),
272	CAP_ENTRY__L(KVM_CAP_COALESCED_PIO),
273	CAP_ENTRY__L(KVM_CAP_HYPERV_ENLIGHTENED_VMCS),
274	CAP_ENTRY__L(KVM_CAP_EXCEPTION_PAYLOAD),
275	CAP_ENTRY__L(KVM_CAP_ARM_VM_IPA_SIZE),
276	CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT),
277	CAP_ENTRY__L(KVM_CAP_HYPERV_CPUID),
278	CAP_ENTRY__L(KVM_CAP_MANUAL_DIRTY_LOG_PROTECT2),
279	CAP_ENTRY__L(KVM_CAP_PPC_IRQ_XIVE),
280	CAP_ENTRY__L(KVM_CAP_ARM_SVE), /* 170 */
281	CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_ADDRESS),
282	CAP_ENTRY__L(KVM_CAP_ARM_PTRAUTH_GENERIC),
283	CAP_ENTRY__L(KVM_CAP_PMU_EVENT_FILTER),
284	CAP_ENTRY__L(KVM_CAP_ARM_IRQ_LINE_LAYOUT_2),
285	CAP_ENTRY__L(KVM_CAP_HYPERV_DIRECT_TLBFLUSH),
286	CAP_ENTRY__L(KVM_CAP_PPC_GUEST_DEBUG_SSTEP),
287	CAP_ENTRY__L(KVM_CAP_ARM_NISV_TO_USER),
288	CAP_ENTRY__L(KVM_CAP_ARM_INJECT_EXT_DABT),
289	CAP_ENTRY__L(KVM_CAP_S390_VCPU_RESETS),
290	CAP_ENTRY__L(KVM_CAP_S390_PROTECTED), /* 180 */
291	CAP_ENTRY__L(KVM_CAP_PPC_SECURE_GUEST),
292	CAP_ENTRY__L(KVM_CAP_HALT_POLL),
293	CAP_ENTRY__L(KVM_CAP_ASYNC_PF_INT),
294	CAP_ENTRY__L(KVM_CAP_LAST_CPU),
295	CAP_ENTRY__L(KVM_CAP_SMALLER_MAXPHYADDR),
296	CAP_ENTRY__L(KVM_CAP_S390_DIAG318),
297	CAP_ENTRY__L(KVM_CAP_STEAL_TIME),
298	CAP_ENTRY_ML(KVM_CAP_X86_USER_SPACE_MSR), /* (since 5.10) */
299	CAP_ENTRY_ML(KVM_CAP_X86_MSR_FILTER),
300	CAP_ENTRY__L(KVM_CAP_ENFORCE_PV_FEATURE_CPUID), /* 190 */
301	CAP_ENTRY__L(KVM_CAP_SYS_HYPERV_CPUID),
302	CAP_ENTRY__L(KVM_CAP_DIRTY_LOG_RING),
303	CAP_ENTRY__L(KVM_CAP_X86_BUS_LOCK_EXIT),
304	CAP_ENTRY__L(KVM_CAP_PPC_DAWR1),
305	CAP_ENTRY__L(KVM_CAP_SET_GUEST_DEBUG2),
306	CAP_ENTRY__L(KVM_CAP_SGX_ATTRIBUTE),
307	CAP_ENTRY__L(KVM_CAP_VM_COPY_ENC_CONTEXT_FROM),
308	CAP_ENTRY__L(KVM_CAP_PTP_KVM),
309	CAP_ENTRY__U(199),
310	CAP_ENTRY__U(200),
311	CAP_ENTRY__U(201),
312	CAP_ENTRY__U(202),
313	CAP_ENTRY__U(203),
314	CAP_ENTRY__U(204),
315	CAP_ENTRY__U(205),
316	CAP_ENTRY__U(206),
317	CAP_ENTRY__U(207),
318	CAP_ENTRY__U(208),
319	CAP_ENTRY__U(209),
320	CAP_ENTRY__U(210),
321	CAP_ENTRY__U(211),
322	CAP_ENTRY__U(212),
323	CAP_ENTRY__U(213),
324	CAP_ENTRY__U(214),
325	CAP_ENTRY__U(215),
326	CAP_ENTRY__U(216),
327	};
328
329	LogRel(("NEM: KVM capabilities (system):\n"));
330	int rcRet = VINF_SUCCESS;
331	for (unsigned i = 0; i < RT_ELEMENTS(s_aCaps); i++)
332	{
333	int rc = ioctl(pVM->nem.s.fdVm, KVM_CHECK_EXTENSION, s_aCaps[i].iCap);
334	if (rc >= 10)
335	LogRel(("NEM: %36s: %#x (%d)\n", s_aCaps[i].pszName, rc, rc));
336	else if (rc >= 0)
337	LogRel(("NEM: %36s: %d\n", s_aCaps[i].pszName, rc));
338	else
339	LogRel(("NEM: %s failed: %d/%d\n", s_aCaps[i].pszName, rc, errno));
340	switch (s_aCaps[i].cbNem)
341	{
342	case 0:
343	break;
344	case 1:
345	{
346	uint8_t puValue = (uint8_t )&pVM->nem.padding[s_aCaps[i].offNem];
347	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
348	*puValue = (uint8_t)rc;
349	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
350	break;
351	}
352	case 2:
353	{
354	uint16_t puValue = (uint16_t )&pVM->nem.padding[s_aCaps[i].offNem];
355	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
356	*puValue = (uint16_t)rc;
357	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
358	break;
359	}
360	case 4:
361	{
362	uint32_t puValue = (uint32_t )&pVM->nem.padding[s_aCaps[i].offNem];
363	AssertReturn(s_aCaps[i].offNem <= sizeof(NEM) - sizeof(*puValue), VERR_NEM_IPE_0);
364	*puValue = (uint32_t)rc;
365	AssertLogRelMsg((int)*puValue == rc, ("%s: %#x\n", s_aCaps[i].pszName, rc));
366	break;
367	}
368	default:
369	rcRet = RTErrInfoSetF(pErrInfo, VERR_NEM_IPE_0, "s_aCaps[%u] is bad: cbNem=%#x - %s",
370	i, s_aCaps[i].pszName, s_aCaps[i].cbNem);
371	AssertFailedReturn(rcRet);
372	}
373
374	/*
375	* Is a require non-zero entry zero or failing?
376	*/
377	if (s_aCaps[i].fReqNonZero && rc <= 0)
378	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE,
379	"Required capability '%s' is missing!", s_aCaps[i].pszName);
380	}
381
382	/*
383	* Get per VCpu KVM_RUN MMAP area size.
384	*/
385	int rc = ioctl(pVM->nem.s.fdKvm, KVM_GET_VCPU_MMAP_SIZE, 0UL);
386	if ((unsigned)rc < _64M)
387	{
388	pVM->nem.s.cbVCpuMmap = (uint32_t)rc;
389	LogRel(("NEM: %36s: %#x (%d)\n", "KVM_GET_VCPU_MMAP_SIZE", rc, rc));
390	}
391	else if (rc < 0)
392	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_MISSING_FEATURE, "KVM_GET_VCPU_MMAP_SIZE failed: %d", errno);
393	else
394	rcRet = RTERRINFO_LOG_REL_ADD_F(pErrInfo, VERR_NEM_INIT_FAILED, "Odd KVM_GET_VCPU_MMAP_SIZE value: %#x (%d)", rc, rc);
395
396	/*
397	* Init the slot ID bitmap.
398	*/
399	ASMBitSet(&pVM->nem.s.bmSlotIds[0], 0); /* don't use slot 0 */
400	if (pVM->nem.s.cMaxMemSlots < _32K)
401	ASMBitSetRange(&pVM->nem.s.bmSlotIds[0], pVM->nem.s.cMaxMemSlots, _32K);
402	ASMBitSet(&pVM->nem.s.bmSlotIds[0], _32K - 1); /* don't use the last slot */
403
404	return rcRet;
405	}
406
407
408	/**
409	* Does the early setup of a KVM VM.
410	*
411	* @returns VBox status code.
412	* @param pVM The cross context VM structure.
413	* @param pErrInfo Where to always return error info.
414	*/
415	static int nemR3LnxInitSetupVm(PVM pVM, PRTERRINFO pErrInfo)
416	{
417	AssertReturn(pVM->nem.s.fdVm != -1, RTErrInfoSet(pErrInfo, VERR_WRONG_ORDER, "Wrong initalization order"));
418
419	/*
420	* Enable user space MSRs and let us check everything KVM cannot handle.
421	* We will set up filtering later when ring-3 init has completed.
422	*/
423	struct kvm_enable_cap CapEn =
424	{
425	KVM_CAP_X86_USER_SPACE_MSR, 0,
426	{ KVM_MSR_EXIT_REASON_FILTER \| KVM_MSR_EXIT_REASON_UNKNOWN \| KVM_MSR_EXIT_REASON_INVAL, 0, 0, 0}
427	};
428	int rcLnx = ioctl(pVM->nem.s.fdVm, KVM_ENABLE_CAP, &CapEn);
429	if (rcLnx == -1)
430	return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "Failed to enable KVM_CAP_X86_USER_SPACE_MSR failed: %u", errno);
431
432	/*
433	* Create the VCpus.
434	*/
435	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
436	{
437	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
438
439	/* Create it. */
440	pVCpu->nem.s.fdVCpu = ioctl(pVM->nem.s.fdVm, KVM_CREATE_VCPU, (unsigned long)idCpu);
441	if (pVCpu->nem.s.fdVCpu < 0)
442	return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VCPU failed for VCpu #%u: %d", idCpu, errno);
443
444	/* Map the KVM_RUN area. */
445	pVCpu->nem.s.pRun = (struct kvm_run *)mmap(NULL, pVM->nem.s.cbVCpuMmap, PROT_READ \| PROT_WRITE, MAP_SHARED,
446	pVCpu->nem.s.fdVCpu, 0 /offset/);
447	if ((void *)pVCpu->nem.s.pRun == MAP_FAILED)
448	return RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "mmap failed for VCpu #%u: %d", idCpu, errno);
449
450	/* We want all x86 registers and events on each exit. */
451	pVCpu->nem.s.pRun->kvm_valid_regs = KVM_SYNC_X86_REGS \| KVM_SYNC_X86_SREGS \| KVM_SYNC_X86_EVENTS;
452	}
453	return VINF_SUCCESS;
454	}
455
456
457	/** @callback_method_impl{FNVMMEMTRENDEZVOUS} */
458	static DECLCALLBACK(VBOXSTRICTRC) nemR3LnxFixThreadPoke(PVM pVM, PVMCPU pVCpu, void *pvUser)
459	{
460	RT_NOREF(pVM, pvUser);
461	int rc = RTThreadControlPokeSignal(pVCpu->hThread, true /fEnable/);
462	AssertLogRelRC(rc);
463	return VINF_SUCCESS;
464	}
465
466
467	/**
468	* Try initialize the native API.
469	*
470	* This may only do part of the job, more can be done in
471	* nemR3NativeInitAfterCPUM() and nemR3NativeInitCompleted().
472	*
473	* @returns VBox status code.
474	* @param pVM The cross context VM structure.
475	* @param fFallback Whether we're in fallback mode or use-NEM mode. In
476	* the latter we'll fail if we cannot initialize.
477	* @param fForced Whether the HMForced flag is set and we should
478	* fail if we cannot initialize.
479	*/
480	int nemR3NativeInit(PVM pVM, bool fFallback, bool fForced)
481	{
482	RT_NOREF(pVM, fFallback, fForced);
483	/*
484	* Some state init.
485	*/
486	pVM->nem.s.fdKvm = -1;
487	pVM->nem.s.fdVm = -1;
488	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
489	{
490	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
491	pNemCpu->fdVCpu = -1;
492	}
493
494	/*
495	* Error state.
496	* The error message will be non-empty on failure and 'rc' will be set too.
497	*/
498	RTERRINFOSTATIC ErrInfo;
499	PRTERRINFO pErrInfo = RTErrInfoInitStatic(&ErrInfo);
500
501	/*
502	* Open kvm subsystem so we can issue system ioctls.
503	*/
504	int rc;
505	int fdKvm = open("/dev/kvm", O_RDWR \| O_CLOEXEC);
506	if (fdKvm >= 0)
507	{
508	pVM->nem.s.fdKvm = fdKvm;
509
510	/*
511	* Create an empty VM since it is recommended we check capabilities on
512	* the VM rather than the system descriptor.
513	*/
514	int fdVm = ioctl(fdKvm, KVM_CREATE_VM, 0UL /* Type must be zero on x86 */);
515	if (fdVm >= 0)
516	{
517	pVM->nem.s.fdVm = fdVm;
518
519	/*
520	* Check capabilities.
521	*/
522	rc = nemR3LnxInitCheckCapabilities(pVM, pErrInfo);
523	if (RT_SUCCESS(rc))
524	{
525	/*
526	* Set up the VM (more on this later).
527	*/
528	rc = nemR3LnxInitSetupVm(pVM, pErrInfo);
529	if (RT_SUCCESS(rc))
530	{
531	/*
532	* Set ourselves as the execution engine and make config adjustments.
533	*/
534	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_NATIVE_API);
535	Log(("NEM: Marked active!\n"));
536	PGMR3EnableNemMode(pVM);
537
538	/*
539	* Register release statistics
540	*/
541	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
542	{
543	PNEMCPU pNemCpu = &pVM->apCpusR3[idCpu]->nem.s;
544	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnDemand, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of on-demand state imports", "/NEM/CPU%u/ImportOnDemand", idCpu);
545	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of state imports on loop return", "/NEM/CPU%u/ImportOnReturn", idCpu);
546	STAMR3RegisterF(pVM, &pNemCpu->StatImportOnReturnSkipped, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of skipped state imports on loop return", "/NEM/CPU%u/ImportOnReturnSkipped", idCpu);
547	STAMR3RegisterF(pVM, &pNemCpu->StatImportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when importing from KVM", "/NEM/CPU%u/ImportPendingInterrupt", idCpu);
548	STAMR3RegisterF(pVM, &pNemCpu->StatExportPendingInterrupt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times an interrupt was pending when exporting to KVM", "/NEM/CPU%u/ExportPendingInterrupt", idCpu);
549	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn", idCpu);
550	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn1Loop, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-01-loop", idCpu);
551	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn2Loops, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-02-loops", idCpu);
552	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn3Loops, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-03-loops", idCpu);
553	STAMR3RegisterF(pVM, &pNemCpu->StatFlushExitOnReturn4PlusLoops, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of times a KVM_EXIT_IO or KVM_EXIT_MMIO was flushed before returning to EM", "/NEM/CPU%u/FlushExitOnReturn-04-to-7-loops", idCpu);
554	STAMR3RegisterF(pVM, &pNemCpu->StatQueryCpuTick, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Number of TSC queries", "/NEM/CPU%u/QueryCpuTick", idCpu);
555	STAMR3RegisterF(pVM, &pNemCpu->StatExitTotal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "All exits", "/NEM/CPU%u/Exit", idCpu);
556	STAMR3RegisterF(pVM, &pNemCpu->StatExitIo, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IO", "/NEM/CPU%u/Exit/Io", idCpu);
557	STAMR3RegisterF(pVM, &pNemCpu->StatExitMmio, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_MMIO", "/NEM/CPU%u/Exit/Mmio", idCpu);
558	STAMR3RegisterF(pVM, &pNemCpu->StatExitSetTpr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_SET_TRP", "/NEM/CPU%u/Exit/SetTpr", idCpu);
559	STAMR3RegisterF(pVM, &pNemCpu->StatExitTprAccess, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_TPR_ACCESS", "/NEM/CPU%u/Exit/TprAccess", idCpu);
560	STAMR3RegisterF(pVM, &pNemCpu->StatExitRdMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_RDMSR", "/NEM/CPU%u/Exit/RdMsr", idCpu);
561	STAMR3RegisterF(pVM, &pNemCpu->StatExitWrMsr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_WRMSR", "/NEM/CPU%u/Exit/WrMsr", idCpu);
562	STAMR3RegisterF(pVM, &pNemCpu->StatExitIrqWindowOpen, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_IRQ_WINDOWS_OPEN", "/NEM/CPU%u/Exit/IrqWindowOpen", idCpu);
563	STAMR3RegisterF(pVM, &pNemCpu->StatExitHalt, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HLT", "/NEM/CPU%u/Exit/Hlt", idCpu);
564	STAMR3RegisterF(pVM, &pNemCpu->StatExitIntr, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTR", "/NEM/CPU%u/Exit/Intr", idCpu);
565	STAMR3RegisterF(pVM, &pNemCpu->StatExitHypercall, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_HYPERCALL", "/NEM/CPU%u/Exit/Hypercall", idCpu);
566	STAMR3RegisterF(pVM, &pNemCpu->StatExitDebug, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_DEBUG", "/NEM/CPU%u/Exit/Debug", idCpu);
567	STAMR3RegisterF(pVM, &pNemCpu->StatExitBusLock, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_BUS_LOCK", "/NEM/CPU%u/Exit/BusLock", idCpu);
568	STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorEmulation, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/EMULATION", "/NEM/CPU%u/Exit/InternalErrorEmulation", idCpu);
569	STAMR3RegisterF(pVM, &pNemCpu->StatExitInternalErrorFatal, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "KVM_EXIT_INTERNAL_ERROR/*", "/NEM/CPU%u/Exit/InternalErrorFatal", idCpu);
570	}
571
572	/*
573	* Make RTThreadPoke work again (disabled for avoiding unnecessary
574	* critical section issues in ring-0).
575	*/
576	VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ALL_AT_ONCE, nemR3LnxFixThreadPoke, NULL);
577
578	/*
579	* Success.
580	*/
581	return VINF_SUCCESS;
582	}
583
584	/*
585	* Bail out.
586	*/
587	}
588	close(fdVm);
589	pVM->nem.s.fdVm = -1;
590	}
591	else
592	rc = RTErrInfoSetF(pErrInfo, VERR_NEM_VM_CREATE_FAILED, "KVM_CREATE_VM failed: %u", errno);
593	close(fdKvm);
594	pVM->nem.s.fdKvm = -1;
595	}
596	else if (errno == EACCES)
597	rc = RTErrInfoSet(pErrInfo, VERR_ACCESS_DENIED, "Do not have access to open /dev/kvm for reading & writing.");
598	else if (errno == ENOENT)
599	rc = RTErrInfoSet(pErrInfo, VERR_NOT_SUPPORTED, "KVM is not availble (/dev/kvm does not exist)");
600	else
601	rc = RTErrInfoSetF(pErrInfo, RTErrConvertFromErrno(errno), "Failed to open '/dev/kvm': %u", errno);
602
603	/*
604	* We only fail if in forced mode, otherwise just log the complaint and return.
605	*/
606	Assert(RTErrInfoIsSet(pErrInfo));
607	if ( (fForced \|\| !fFallback)
608	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NATIVE_API)
609	return VMSetError(pVM, RT_SUCCESS_NP(rc) ? VERR_NEM_NOT_AVAILABLE : rc, RT_SRC_POS, "%s", pErrInfo->pszMsg);
610	LogRel(("NEM: Not available: %s\n", pErrInfo->pszMsg));
611	return VINF_SUCCESS;
612	}
613
614
615	/**
616	* This is called after CPUMR3Init is done.
617	*
618	* @returns VBox status code.
619	* @param pVM The VM handle..
620	*/
621	int nemR3NativeInitAfterCPUM(PVM pVM)
622	{
623	/*
624	* Validate sanity.
625	*/
626	AssertReturn(pVM->nem.s.fdKvm >= 0, VERR_WRONG_ORDER);
627	AssertReturn(pVM->nem.s.fdVm >= 0, VERR_WRONG_ORDER);
628	AssertReturn(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NATIVE_API, VERR_WRONG_ORDER);
629
630	/** @todo */
631
632	return VINF_SUCCESS;
633	}
634
635
636	/**
637	* Update the CPUID leaves for a VCPU.
638	*
639	* The KVM_SET_CPUID2 call replaces any previous leaves, so we have to redo
640	* everything when there really just are single bit changes. That said, it
641	* looks like KVM update the XCR/XSAVE related stuff as well as the APIC enabled
642	* bit(s), so it should suffice if we do this at startup, I hope.
643	*/
644	static int nemR3LnxUpdateCpuIdsLeaves(PVM pVM, PVMCPU pVCpu)
645	{
646	uint32_t cLeaves = 0;
647	PCCPUMCPUIDLEAF const paLeaves = CPUMR3CpuIdGetPtr(pVM, &cLeaves);
648	struct kvm_cpuid2 pReq = (struct kvm_cpuid2 )alloca(RT_UOFFSETOF_DYN(struct kvm_cpuid2, entries[cLeaves + 2]));
649
650	pReq->nent = cLeaves;
651	pReq->padding = 0;
652
653	for (uint32_t i = 0; i < cLeaves; i++)
654	{
655	CPUMGetGuestCpuId(pVCpu, paLeaves[i].uLeaf, paLeaves[i].uSubLeaf,
656	&pReq->entries[i].eax,
657	&pReq->entries[i].ebx,
658	&pReq->entries[i].ecx,
659	&pReq->entries[i].edx);
660	pReq->entries[i].function = paLeaves[i].uLeaf;
661	pReq->entries[i].index = paLeaves[i].uSubLeaf;
662	pReq->entries[i].flags = !paLeaves[i].fSubLeafMask ? 0 : KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
663	pReq->entries[i].padding[0] = 0;
664	pReq->entries[i].padding[1] = 0;
665	pReq->entries[i].padding[2] = 0;
666	}
667
668	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_CPUID2, pReq);
669	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d cLeaves=%#x\n", rcLnx, errno, cLeaves), RTErrConvertFromErrno(errno));
670
671	return VINF_SUCCESS;
672	}
673
674
675	int nemR3NativeInitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
676	{
677	/*
678	* Configure CPUIDs after ring-3 init has been done.
679	*/
680	if (enmWhat == VMINITCOMPLETED_RING3)
681	{
682	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
683	{
684	int rc = nemR3LnxUpdateCpuIdsLeaves(pVM, pVM->apCpusR3[idCpu]);
685	AssertRCReturn(rc, rc);
686	}
687	}
688
689	/*
690	* Configure MSRs after ring-3 init is done.
691	*
692	* We only need to tell KVM which MSRs it can handle, as we already
693	* requested KVM_MSR_EXIT_REASON_FILTER, KVM_MSR_EXIT_REASON_UNKNOWN
694	* and KVM_MSR_EXIT_REASON_INVAL in nemR3LnxInitSetupVm, and here we
695	* will use KVM_MSR_FILTER_DEFAULT_DENY. So, all MSRs w/o a 1 in the
696	* bitmaps should be deferred to ring-3.
697	*/
698	if (enmWhat == VMINITCOMPLETED_RING3)
699	{
700	struct kvm_msr_filter MsrFilters = {0}; /* Structure with a couple of implicit paddings on 64-bit systems. */
701	MsrFilters.flags = KVM_MSR_FILTER_DEFAULT_DENY;
702
703	unsigned iRange = 0;
704	#define MSR_RANGE_BEGIN(a_uBase, a_uEnd, a_fFlags) \
705	AssertCompile(0x3000 <= KVM_MSR_FILTER_MAX_BITMAP_SIZE * 8); \
706	uint64_t RT_CONCAT(bm, a_uBase)[0x3000 / 64] = {0}; \
707	do { \
708	uint64_t * const pbm = RT_CONCAT(bm, a_uBase); \
709	uint32_t const uBase = UINT32_C(a_uBase); \
710	uint32_t const cMsrs = UINT32_C(a_uEnd) - UINT32_C(a_uBase); \
711	MsrFilters.ranges[iRange].base = UINT32_C(a_uBase); \
712	MsrFilters.ranges[iRange].nmsrs = cMsrs; \
713	MsrFilters.ranges[iRange].flags = (a_fFlags); \
714	MsrFilters.ranges[iRange].bitmap = (uint8_t *)&RT_CONCAT(bm, a_uBase)[0]
715	#define MSR_RANGE_ADD(a_Msr) \
716	do { Assert((uint32_t)(a_Msr) - uBase < cMsrs); ASMBitSet(pbm, (uint32_t)(a_Msr) - uBase); } while (0)
717	#define MSR_RANGE_END(a_cMinMsrs) \
718	/* optimize the range size before closing: */ \
719	uint32_t cBitmap = cMsrs / 64; \
720	while (cBitmap > ((a_cMinMsrs) + 63 / 64) && pbm[cBitmap - 1] == 0) \
721	cBitmap -= 1; \
722	MsrFilters.ranges[iRange].nmsrs = cBitmap * 64; \
723	iRange++; \
724	} while (0)
725
726	/* 1st Intel range: 0000_0000 to 0000_3000. */
727	MSR_RANGE_BEGIN(0x00000000, 0x00003000, KVM_MSR_FILTER_READ \| KVM_MSR_FILTER_WRITE);
728	MSR_RANGE_ADD(MSR_IA32_TSC);
729	MSR_RANGE_ADD(MSR_IA32_SYSENTER_CS);
730	MSR_RANGE_ADD(MSR_IA32_SYSENTER_ESP);
731	MSR_RANGE_ADD(MSR_IA32_SYSENTER_EIP);
732	MSR_RANGE_ADD(MSR_IA32_CR_PAT);
733	/** @todo more? */
734	MSR_RANGE_END(64);
735
736	/* 1st AMD range: c000_0000 to c000_3000 */
737	MSR_RANGE_BEGIN(0xc0000000, 0xc0003000, KVM_MSR_FILTER_READ \| KVM_MSR_FILTER_WRITE);
738	MSR_RANGE_ADD(MSR_K6_EFER);
739	MSR_RANGE_ADD(MSR_K6_STAR);
740	MSR_RANGE_ADD(MSR_K8_GS_BASE);
741	MSR_RANGE_ADD(MSR_K8_KERNEL_GS_BASE);
742	MSR_RANGE_ADD(MSR_K8_LSTAR);
743	MSR_RANGE_ADD(MSR_K8_CSTAR);
744	MSR_RANGE_ADD(MSR_K8_SF_MASK);
745	MSR_RANGE_ADD(MSR_K8_TSC_AUX);
746	/** @todo add more? */
747	MSR_RANGE_END(64);
748
749	/** @todo Specify other ranges too? Like hyper-V and KVM to make sure we get
750	* the MSR requests instead of KVM. */
751
752	int rcLnx = ioctl(pVM->nem.s.fdVm, KVM_X86_SET_MSR_FILTER, &MsrFilters);
753	if (rcLnx == -1)
754	return VMSetError(pVM, VERR_NEM_VM_CREATE_FAILED, RT_SRC_POS,
755	"Failed to enable KVM_X86_SET_MSR_FILTER failed: %u", errno);
756	}
757
758	return VINF_SUCCESS;
759	}
760
761
762	int nemR3NativeTerm(PVM pVM)
763	{
764	/*
765	* Per-cpu data
766	*/
767	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
768	{
769	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
770
771	if (pVCpu->nem.s.fdVCpu != -1)
772	{
773	close(pVCpu->nem.s.fdVCpu);
774	pVCpu->nem.s.fdVCpu = -1;
775	}
776	if (pVCpu->nem.s.pRun)
777	{
778	munmap(pVCpu->nem.s.pRun, pVM->nem.s.cbVCpuMmap);
779	pVCpu->nem.s.pRun = NULL;
780	}
781	}
782
783	/*
784	* Global data.
785	*/
786	if (pVM->nem.s.fdVm != -1)
787	{
788	close(pVM->nem.s.fdVm);
789	pVM->nem.s.fdVm = -1;
790	}
791
792	if (pVM->nem.s.fdKvm != -1)
793	{
794	close(pVM->nem.s.fdKvm);
795	pVM->nem.s.fdKvm = -1;
796	}
797	return VINF_SUCCESS;
798	}
799
800
801	/**
802	* VM reset notification.
803	*
804	* @param pVM The cross context VM structure.
805	*/
806	void nemR3NativeReset(PVM pVM)
807	{
808	RT_NOREF(pVM);
809	}
810
811
812	/**
813	* Reset CPU due to INIT IPI or hot (un)plugging.
814	*
815	* @param pVCpu The cross context virtual CPU structure of the CPU being
816	* reset.
817	* @param fInitIpi Whether this is the INIT IPI or hot (un)plugging case.
818	*/
819	void nemR3NativeResetCpu(PVMCPU pVCpu, bool fInitIpi)
820	{
821	RT_NOREF(pVCpu, fInitIpi);
822	}
823
824
825	/*********************************************************************************************************************************
826	* Memory management *
827	*********************************************************************************************************************************/
828
829
830	/**
831	* Allocates a memory slot ID.
832	*
833	* @returns Slot ID on success, UINT16_MAX on failure.
834	*/
835	static uint16_t nemR3LnxMemSlotIdAlloc(PVM pVM)
836	{
837	/* Use the hint first. */
838	uint16_t idHint = pVM->nem.s.idPrevSlot;
839	if (idHint < _32K - 1)
840	{
841	int32_t idx = ASMBitNextClear(&pVM->nem.s.bmSlotIds, _32K, idHint);
842	Assert(idx < _32K);
843	if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
844	return pVM->nem.s.idPrevSlot = (uint16_t)idx;
845	}
846
847	/*
848	* Search the whole map from the start.
849	*/
850	int32_t idx = ASMBitFirstClear(&pVM->nem.s.bmSlotIds, _32K);
851	Assert(idx < _32K);
852	if (idx > 0 && !ASMAtomicBitTestAndSet(&pVM->nem.s.bmSlotIds, idx))
853	return pVM->nem.s.idPrevSlot = (uint16_t)idx;
854
855	Assert(idx < 0 /shouldn't trigger unless there is a race /);
856	return UINT16_MAX; /* caller is expected to assert. */
857	}
858
859
860	/**
861	* Frees a memory slot ID
862	*/
863	static void nemR3LnxMemSlotIdFree(PVM pVM, uint16_t idSlot)
864	{
865	if (RT_LIKELY(idSlot < _32K && ASMAtomicBitTestAndClear(&pVM->nem.s.bmSlotIds, idSlot)))
866	{ /likely/ }
867	else
868	AssertMsgFailed(("idSlot=%u (%#x)\n", idSlot, idSlot));
869	}
870
871
872
873	VMMR3_INT_DECL(int) NEMR3NotifyPhysRamRegister(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvR3,
874	uint8_t pu2State, uint32_t puNemRange)
875	{
876	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
877	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
878
879	Log5(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p pu2State=%p (%d) puNemRange=%p (%d) - idSlot=%#x\n",
880	GCPhys, cb, pvR3, pu2State, pu2State, puNemRange, *puNemRange, idSlot));
881
882	struct kvm_userspace_memory_region Region;
883	Region.slot = idSlot;
884	Region.flags = 0;
885	Region.guest_phys_addr = GCPhys;
886	Region.memory_size = cb;
887	Region.userspace_addr = (uintptr_t)pvR3;
888
889	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
890	if (rc == 0)
891	{
892	*pu2State = 0;
893	*puNemRange = idSlot;
894	return VINF_SUCCESS;
895	}
896
897	LogRel(("NEMR3NotifyPhysRamRegister: %RGp LB %RGp, pvR3=%p, idSlot=%#x failed: %u/%u\n", GCPhys, cb, pvR3, idSlot, rc, errno));
898	nemR3LnxMemSlotIdFree(pVM, idSlot);
899	return VERR_NEM_MAP_PAGES_FAILED;
900	}
901
902
903	VMMR3_INT_DECL(bool) NEMR3IsMmio2DirtyPageTrackingSupported(PVM pVM)
904	{
905	RT_NOREF(pVM);
906	return true;
907	}
908
909
910	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
911	void pvRam, void pvMmio2, uint8_t pu2State, uint32_t puNemRange)
912	{
913	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p (%d) puNemRange=%p (%#x)\n",
914	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, pu2State, puNemRange, puNemRange ? puNemRange : UINT32_MAX));
915	RT_NOREF(pvRam);
916
917	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
918	{
919	/** @todo implement splitting and whatnot of ranges if we want to be 100%
920	* conforming (just modify RAM registrations in MM.cpp to test). */
921	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
922	VERR_NEM_MAP_PAGES_FAILED);
923	}
924
925	/*
926	* Register MMIO2.
927	*/
928	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
929	{
930	AssertReturn(pvMmio2, VERR_NEM_MAP_PAGES_FAILED);
931	AssertReturn(puNemRange, VERR_NEM_MAP_PAGES_FAILED);
932
933	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
934	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
935
936	struct kvm_userspace_memory_region Region;
937	Region.slot = idSlot;
938	Region.flags = fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_TRACK_DIRTY_PAGES ? KVM_MEM_LOG_DIRTY_PAGES : 0;
939	Region.guest_phys_addr = GCPhys;
940	Region.memory_size = cb;
941	Region.userspace_addr = (uintptr_t)pvMmio2;
942
943	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
944	if (rc == 0)
945	{
946	*pu2State = 0;
947	*puNemRange = idSlot;
948	Log5(("NEMR3NotifyPhysMmioExMapEarly: %RGp LB %RGp fFlags=%#x pvMmio2=%p - idSlot=%#x\n",
949	GCPhys, cb, fFlags, pvMmio2, idSlot));
950	return VINF_SUCCESS;
951	}
952
953	nemR3LnxMemSlotIdFree(pVM, idSlot);
954	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
955	GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
956	VERR_NEM_MAP_PAGES_FAILED);
957	}
958
959	/* MMIO, don't care. */
960	*pu2State = 0;
961	*puNemRange = UINT32_MAX;
962	return VINF_SUCCESS;
963	}
964
965
966	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExMapLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags,
967	void pvRam, void pvMmio2, uint32_t *puNemRange)
968	{
969	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, puNemRange);
970	return VINF_SUCCESS;
971	}
972
973
974	VMMR3_INT_DECL(int) NEMR3NotifyPhysMmioExUnmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t fFlags, void *pvRam,
975	void pvMmio2, uint8_t pu2State, uint32_t *puNemRange)
976	{
977	Log5(("NEMR3NotifyPhysMmioExUnmap: %RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p pu2State=%p puNemRange=%p (%#x)\n",
978	GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State, puNemRange, *puNemRange));
979	RT_NOREF(pVM, GCPhys, cb, fFlags, pvRam, pvMmio2, pu2State);
980
981	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_REPLACE)
982	{
983	/** @todo implement splitting and whatnot of ranges if we want to be 100%
984	* conforming (just modify RAM registrations in MM.cpp to test). */
985	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x pvRam=%p pvMmio2=%p\n", GCPhys, cb, fFlags, pvRam, pvMmio2),
986	VERR_NEM_UNMAP_PAGES_FAILED);
987	}
988
989	if (fFlags & NEM_NOTIFY_PHYS_MMIO_EX_F_MMIO2)
990	{
991	uint32_t const idSlot = *puNemRange;
992	AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
993	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
994
995	struct kvm_userspace_memory_region Region;
996	Region.slot = idSlot;
997	Region.flags = 0;
998	Region.guest_phys_addr = GCPhys;
999	Region.memory_size = 0; /* this deregisters it. */
1000	Region.userspace_addr = (uintptr_t)pvMmio2;
1001
1002	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
1003	if (rc == 0)
1004	{
1005	if (pu2State)
1006	*pu2State = 0;
1007	*puNemRange = UINT32_MAX;
1008	nemR3LnxMemSlotIdFree(pVM, idSlot);
1009	return VINF_SUCCESS;
1010	}
1011
1012	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvMmio2=%p, idSlot=%#x failed: %u/%u\n",
1013	GCPhys, cb, fFlags, pvMmio2, idSlot, errno, rc),
1014	VERR_NEM_UNMAP_PAGES_FAILED);
1015	}
1016
1017	if (pu2State)
1018	*pu2State = UINT8_MAX;
1019	return VINF_SUCCESS;
1020	}
1021
1022
1023	VMMR3_INT_DECL(int) NEMR3PhysMmio2QueryAndResetDirtyBitmap(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, uint32_t uNemRange,
1024	void *pvBitmap, size_t cbBitmap)
1025	{
1026	AssertReturn(uNemRange > 0 && uNemRange < _32K, VERR_NEM_IPE_4);
1027	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, uNemRange), VERR_NEM_IPE_4);
1028
1029	RT_NOREF(GCPhys, cbBitmap);
1030
1031	struct kvm_dirty_log DirtyLog;
1032	DirtyLog.slot = uNemRange;
1033	DirtyLog.padding1 = 0;
1034	DirtyLog.dirty_bitmap = pvBitmap;
1035
1036	int rc = ioctl(pVM->nem.s.fdVm, KVM_GET_DIRTY_LOG, &DirtyLog);
1037	AssertLogRelMsgReturn(rc == 0, ("%RGp LB %RGp idSlot=%#x failed: %u/%u\n", GCPhys, cb, uNemRange, errno, rc),
1038	VERR_NEM_QUERY_DIRTY_BITMAP_FAILED);
1039
1040	return VINF_SUCCESS;
1041	}
1042
1043
1044	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterEarly(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages, uint32_t fFlags,
1045	uint8_t pu2State, uint32_t puNemRange)
1046	{
1047	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp pvPages=%p fFlags=%#x\n", GCPhys, cb, pvPages, fFlags));
1048	*pu2State = UINT8_MAX;
1049
1050	/* Don't support puttint ROM where there is already RAM. For
1051	now just shuffle the registrations till it works... */
1052	AssertLogRelMsgReturn(!(fFlags & NEM_NOTIFY_PHYS_ROM_F_REPLACE), ("%RGp LB %RGp fFlags=%#x\n", GCPhys, cb, fFlags),
1053	VERR_NEM_MAP_PAGES_FAILED);
1054
1055	/** @todo figure out how to do shadow ROMs. */
1056
1057	/*
1058	* We only allocate a slot number here in case we need to use it to
1059	* fend of physical handler fun.
1060	*/
1061	uint16_t idSlot = nemR3LnxMemSlotIdAlloc(pVM);
1062	AssertLogRelReturn(idSlot < _32K, VERR_NEM_MAP_PAGES_FAILED);
1063
1064	*pu2State = 0;
1065	*puNemRange = idSlot;
1066	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
1067	GCPhys, cb, fFlags, pvPages, idSlot));
1068	RT_NOREF(GCPhys, cb, fFlags, pvPages);
1069	return VINF_SUCCESS;
1070	}
1071
1072
1073	VMMR3_INT_DECL(int) NEMR3NotifyPhysRomRegisterLate(PVM pVM, RTGCPHYS GCPhys, RTGCPHYS cb, void *pvPages,
1074	uint32_t fFlags, uint8_t pu2State, uint32_t puNemRange)
1075	{
1076	Log5(("NEMR3NotifyPhysRomRegisterLate: %RGp LB %RGp pvPages=%p fFlags=%#x pu2State=%p (%d) puNemRange=%p (%#x)\n",
1077	GCPhys, cb, pvPages, fFlags, pu2State, pu2State, puNemRange, puNemRange));
1078
1079	AssertPtrReturn(pvPages, VERR_NEM_IPE_5);
1080
1081	uint32_t const idSlot = *puNemRange;
1082	AssertReturn(idSlot > 0 && idSlot < _32K, VERR_NEM_IPE_4);
1083	AssertReturn(ASMBitTest(pVM->nem.s.bmSlotIds, idSlot), VERR_NEM_IPE_4);
1084
1085	*pu2State = UINT8_MAX;
1086
1087	/*
1088	* Do the actual setting of the user pages here now that we've
1089	* got a valid pvPages (typically isn't available during the early
1090	* notification, unless we're replacing RAM).
1091	*/
1092	struct kvm_userspace_memory_region Region;
1093	Region.slot = idSlot;
1094	Region.flags = 0;
1095	Region.guest_phys_addr = GCPhys;
1096	Region.memory_size = cb;
1097	Region.userspace_addr = (uintptr_t)pvPages;
1098
1099	int rc = ioctl(pVM->nem.s.fdVm, KVM_SET_USER_MEMORY_REGION, &Region);
1100	if (rc == 0)
1101	{
1102	*pu2State = 0;
1103	Log5(("NEMR3NotifyPhysRomRegisterEarly: %RGp LB %RGp fFlags=%#x pvPages=%p - idSlot=%#x\n",
1104	GCPhys, cb, fFlags, pvPages, idSlot));
1105	return VINF_SUCCESS;
1106	}
1107	AssertLogRelMsgFailedReturn(("%RGp LB %RGp fFlags=%#x, pvPages=%p, idSlot=%#x failed: %u/%u\n",
1108	GCPhys, cb, fFlags, pvPages, idSlot, errno, rc),
1109	VERR_NEM_MAP_PAGES_FAILED);
1110	}
1111
1112
1113	/**
1114	* Called when the A20 state changes.
1115	*
1116	* @param pVCpu The CPU the A20 state changed on.
1117	* @param fEnabled Whether it was enabled (true) or disabled.
1118	*/
1119	VMMR3_INT_DECL(void) NEMR3NotifySetA20(PVMCPU pVCpu, bool fEnabled)
1120	{
1121	Log(("nemR3NativeNotifySetA20: fEnabled=%RTbool\n", fEnabled));
1122	Assert(VM_IS_NEM_ENABLED(pVCpu->CTX_SUFF(pVM)));
1123	RT_NOREF(pVCpu, fEnabled);
1124	}
1125
1126
1127	VMM_INT_DECL(void) NEMHCNotifyHandlerPhysicalDeregister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb,
1128	RTR3PTR pvMemR3, uint8_t *pu2State)
1129	{
1130	Log5(("NEMHCNotifyHandlerPhysicalDeregister: %RGp LB %RGp enmKind=%d pvMemR3=%p pu2State=%p (%d)\n",
1131	GCPhys, cb, enmKind, pvMemR3, pu2State, *pu2State));
1132
1133	*pu2State = UINT8_MAX;
1134	RT_NOREF(pVM, enmKind, GCPhys, cb, pvMemR3);
1135	}
1136
1137
1138	void nemHCNativeNotifyHandlerPhysicalRegister(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhys, RTGCPHYS cb)
1139	{
1140	Log5(("nemHCNativeNotifyHandlerPhysicalRegister: %RGp LB %RGp enmKind=%d\n", GCPhys, cb, enmKind));
1141	RT_NOREF(pVM, enmKind, GCPhys, cb);
1142	}
1143
1144
1145	void nemHCNativeNotifyHandlerPhysicalModify(PVMCC pVM, PGMPHYSHANDLERKIND enmKind, RTGCPHYS GCPhysOld,
1146	RTGCPHYS GCPhysNew, RTGCPHYS cb, bool fRestoreAsRAM)
1147	{
1148	Log5(("nemHCNativeNotifyHandlerPhysicalModify: %RGp LB %RGp -> %RGp enmKind=%d fRestoreAsRAM=%d\n",
1149	GCPhysOld, cb, GCPhysNew, enmKind, fRestoreAsRAM));
1150	RT_NOREF(pVM, enmKind, GCPhysOld, GCPhysNew, cb, fRestoreAsRAM);
1151	}
1152
1153
1154	int nemHCNativeNotifyPhysPageAllocated(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, uint32_t fPageProt,
1155	PGMPAGETYPE enmType, uint8_t *pu2State)
1156	{
1157	Log5(("nemHCNativeNotifyPhysPageAllocated: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1158	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1159	RT_NOREF(pVM, GCPhys, HCPhys, fPageProt, enmType, pu2State);
1160	return VINF_SUCCESS;
1161	}
1162
1163
1164	VMM_INT_DECL(void) NEMHCNotifyPhysPageProtChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhys, RTR3PTR pvR3, uint32_t fPageProt,
1165	PGMPAGETYPE enmType, uint8_t *pu2State)
1166	{
1167	Log5(("NEMHCNotifyPhysPageProtChanged: %RGp HCPhys=%RHp fPageProt=%#x enmType=%d *pu2State=%d\n",
1168	GCPhys, HCPhys, fPageProt, enmType, *pu2State));
1169	Assert(VM_IS_NEM_ENABLED(pVM));
1170	RT_NOREF(pVM, GCPhys, HCPhys, pvR3, fPageProt, enmType, pu2State);
1171
1172	}
1173
1174
1175	VMM_INT_DECL(void) NEMHCNotifyPhysPageChanged(PVMCC pVM, RTGCPHYS GCPhys, RTHCPHYS HCPhysPrev, RTHCPHYS HCPhysNew,
1176	RTR3PTR pvNewR3, uint32_t fPageProt, PGMPAGETYPE enmType, uint8_t *pu2State)
1177	{
1178	Log5(("nemHCNativeNotifyPhysPageChanged: %RGp HCPhys=%RHp->%RHp pvNewR3=%p fPageProt=%#x enmType=%d *pu2State=%d\n",
1179	GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, *pu2State));
1180	Assert(VM_IS_NEM_ENABLED(pVM));
1181	RT_NOREF(pVM, GCPhys, HCPhysPrev, HCPhysNew, pvNewR3, fPageProt, enmType, pu2State);
1182	}
1183
1184
1185	/*********************************************************************************************************************************
1186	* CPU State *
1187	*********************************************************************************************************************************/
1188
1189	/**
1190	* Worker that imports selected state from KVM.
1191	*/
1192	static int nemHCLnxImportState(PVMCPUCC pVCpu, uint64_t fWhat, PCPUMCTX pCtx, struct kvm_run *pRun)
1193	{
1194	fWhat &= pVCpu->cpum.GstCtx.fExtrn;
1195	if (!fWhat)
1196	return VINF_SUCCESS;
1197
1198	/*
1199	* Stuff that goes into kvm_run::s.regs.regs:
1200	*/
1201	if (fWhat & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK))
1202	{
1203	if (fWhat & CPUMCTX_EXTRN_RIP)
1204	pCtx->rip = pRun->s.regs.regs.rip;
1205	if (fWhat & CPUMCTX_EXTRN_RFLAGS)
1206	pCtx->rflags.u = pRun->s.regs.regs.rflags;
1207
1208	if (fWhat & CPUMCTX_EXTRN_RAX)
1209	pCtx->rax = pRun->s.regs.regs.rax;
1210	if (fWhat & CPUMCTX_EXTRN_RCX)
1211	pCtx->rcx = pRun->s.regs.regs.rcx;
1212	if (fWhat & CPUMCTX_EXTRN_RDX)
1213	pCtx->rdx = pRun->s.regs.regs.rdx;
1214	if (fWhat & CPUMCTX_EXTRN_RBX)
1215	pCtx->rbx = pRun->s.regs.regs.rbx;
1216	if (fWhat & CPUMCTX_EXTRN_RSP)
1217	pCtx->rsp = pRun->s.regs.regs.rsp;
1218	if (fWhat & CPUMCTX_EXTRN_RBP)
1219	pCtx->rbp = pRun->s.regs.regs.rbp;
1220	if (fWhat & CPUMCTX_EXTRN_RSI)
1221	pCtx->rsi = pRun->s.regs.regs.rsi;
1222	if (fWhat & CPUMCTX_EXTRN_RDI)
1223	pCtx->rdi = pRun->s.regs.regs.rdi;
1224	if (fWhat & CPUMCTX_EXTRN_R8_R15)
1225	{
1226	pCtx->r8 = pRun->s.regs.regs.r8;
1227	pCtx->r9 = pRun->s.regs.regs.r9;
1228	pCtx->r10 = pRun->s.regs.regs.r10;
1229	pCtx->r11 = pRun->s.regs.regs.r11;
1230	pCtx->r12 = pRun->s.regs.regs.r12;
1231	pCtx->r13 = pRun->s.regs.regs.r13;
1232	pCtx->r14 = pRun->s.regs.regs.r14;
1233	pCtx->r15 = pRun->s.regs.regs.r15;
1234	}
1235	}
1236
1237	/*
1238	* Stuff that goes into kvm_run::s.regs.sregs.
1239	*
1240	* Note! The apic_base can be ignored because we gets all MSR writes to it
1241	* and VBox always keeps the correct value.
1242	*/
1243	bool fMaybeChangedMode = false;
1244	bool fUpdateCr3 = false;
1245	if (fWhat & ( CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK \| CPUMCTX_EXTRN_CR_MASK
1246	\| CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_APIC_TPR))
1247	{
1248	/** @todo what about Attr.n.u4LimitHigh? */
1249	#define NEM_LNX_IMPORT_SEG(a_CtxSeg, a_KvmSeg) do { \
1250	(a_CtxSeg).u64Base = (a_KvmSeg).base; \
1251	(a_CtxSeg).u32Limit = (a_KvmSeg).limit; \
1252	(a_CtxSeg).ValidSel = (a_CtxSeg).Sel = (a_KvmSeg).selector; \
1253	(a_CtxSeg).Attr.n.u4Type = (a_KvmSeg).type; \
1254	(a_CtxSeg).Attr.n.u1DescType = (a_KvmSeg).s; \
1255	(a_CtxSeg).Attr.n.u2Dpl = (a_KvmSeg).dpl; \
1256	(a_CtxSeg).Attr.n.u1Present = (a_KvmSeg).present; \
1257	(a_CtxSeg).Attr.n.u1Available = (a_KvmSeg).avl; \
1258	(a_CtxSeg).Attr.n.u1Long = (a_KvmSeg).l; \
1259	(a_CtxSeg).Attr.n.u1DefBig = (a_KvmSeg).db; \
1260	(a_CtxSeg).Attr.n.u1Granularity = (a_KvmSeg).g; \
1261	(a_CtxSeg).Attr.n.u1Unusable = (a_KvmSeg).unusable; \
1262	(a_CtxSeg).fFlags = CPUMSELREG_FLAGS_VALID; \
1263	CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &(a_CtxSeg)); \
1264	} while (0)
1265
1266	if (fWhat & CPUMCTX_EXTRN_SREG_MASK)
1267	{
1268	if (fWhat & CPUMCTX_EXTRN_ES)
1269	NEM_LNX_IMPORT_SEG(pCtx->es, pRun->s.regs.sregs.es);
1270	if (fWhat & CPUMCTX_EXTRN_CS)
1271	NEM_LNX_IMPORT_SEG(pCtx->cs, pRun->s.regs.sregs.cs);
1272	if (fWhat & CPUMCTX_EXTRN_SS)
1273	NEM_LNX_IMPORT_SEG(pCtx->ss, pRun->s.regs.sregs.ss);
1274	if (fWhat & CPUMCTX_EXTRN_DS)
1275	NEM_LNX_IMPORT_SEG(pCtx->ds, pRun->s.regs.sregs.ds);
1276	if (fWhat & CPUMCTX_EXTRN_FS)
1277	NEM_LNX_IMPORT_SEG(pCtx->fs, pRun->s.regs.sregs.fs);
1278	if (fWhat & CPUMCTX_EXTRN_GS)
1279	NEM_LNX_IMPORT_SEG(pCtx->gs, pRun->s.regs.sregs.gs);
1280	}
1281	if (fWhat & CPUMCTX_EXTRN_TABLE_MASK)
1282	{
1283	if (fWhat & CPUMCTX_EXTRN_GDTR)
1284	{
1285	pCtx->gdtr.pGdt = pRun->s.regs.sregs.gdt.base;
1286	pCtx->gdtr.cbGdt = pRun->s.regs.sregs.gdt.limit;
1287	}
1288	if (fWhat & CPUMCTX_EXTRN_IDTR)
1289	{
1290	pCtx->idtr.pIdt = pRun->s.regs.sregs.idt.base;
1291	pCtx->idtr.cbIdt = pRun->s.regs.sregs.idt.limit;
1292	}
1293	if (fWhat & CPUMCTX_EXTRN_LDTR)
1294	NEM_LNX_IMPORT_SEG(pCtx->ldtr, pRun->s.regs.sregs.ldt);
1295	if (fWhat & CPUMCTX_EXTRN_TR)
1296	NEM_LNX_IMPORT_SEG(pCtx->tr, pRun->s.regs.sregs.tr);
1297	}
1298	if (fWhat & CPUMCTX_EXTRN_CR_MASK)
1299	{
1300	if (fWhat & CPUMCTX_EXTRN_CR0)
1301	{
1302	if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1303	{
1304	CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1305	fMaybeChangedMode = true;
1306	}
1307	}
1308	if (fWhat & CPUMCTX_EXTRN_CR2)
1309	pCtx->cr2 = pRun->s.regs.sregs.cr2;
1310	if (fWhat & CPUMCTX_EXTRN_CR3)
1311	{
1312	if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1313	{
1314	CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1315	fUpdateCr3 = true;
1316	}
1317	}
1318	if (fWhat & CPUMCTX_EXTRN_CR4)
1319	{
1320	if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1321	{
1322	CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1323	fMaybeChangedMode = true;
1324	}
1325	}
1326	}
1327	if (fWhat & CPUMCTX_EXTRN_APIC_TPR)
1328	APICSetTpr(pVCpu, (uint8_t)pRun->s.regs.sregs.cr8 << 4);
1329	if (fWhat & CPUMCTX_EXTRN_EFER)
1330	{
1331	if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1332	{
1333	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1334	if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1335	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1336	pCtx->msrEFER = pRun->s.regs.sregs.efer;
1337	fMaybeChangedMode = true;
1338	}
1339	}
1340	#undef NEM_LNX_IMPORT_SEG
1341	}
1342
1343	/*
1344	* Debug registers.
1345	*/
1346	if (fWhat & CPUMCTX_EXTRN_DR_MASK)
1347	{
1348	struct kvm_debugregs DbgRegs = {{0}};
1349	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1350	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1351
1352	if (fWhat & CPUMCTX_EXTRN_DR0_DR3)
1353	{
1354	pCtx->dr[0] = DbgRegs.db[0];
1355	pCtx->dr[1] = DbgRegs.db[1];
1356	pCtx->dr[2] = DbgRegs.db[2];
1357	pCtx->dr[3] = DbgRegs.db[3];
1358	}
1359	if (fWhat & CPUMCTX_EXTRN_DR6)
1360	pCtx->dr[6] = DbgRegs.dr6;
1361	if (fWhat & CPUMCTX_EXTRN_DR7)
1362	pCtx->dr[7] = DbgRegs.dr7;
1363	}
1364
1365	/*
1366	* FPU, SSE, AVX, ++.
1367	*/
1368	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE \| CPUMCTX_EXTRN_XCRx))
1369	{
1370	if (fWhat & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1371	{
1372	fWhat \|= CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE; /* we do all or nothing at all */
1373
1374	AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1375	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XSAVE, &pCtx->XState);
1376	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1377	}
1378
1379	if (fWhat & CPUMCTX_EXTRN_XCRx)
1380	{
1381	struct kvm_xcrs Xcrs =
1382	{ /.nr_xcrs = / 2,
1383	/.flags = / 0,
1384	/.xcrs= / {
1385	{ /.xcr =/ 0, /.reserved=/ 0, /.value=/ pCtx->aXcr[0] },
1386	{ /.xcr =/ 1, /.reserved=/ 0, /.value=/ pCtx->aXcr[1] },
1387	}
1388	};
1389
1390	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_XCRS, &Xcrs);
1391	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1392
1393	pCtx->aXcr[0] = Xcrs.xcrs[0].value;
1394	pCtx->aXcr[1] = Xcrs.xcrs[1].value;
1395	}
1396	}
1397
1398	/*
1399	* MSRs.
1400	*/
1401	if (fWhat & ( CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS
1402	\| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
1403	{
1404	union
1405	{
1406	struct kvm_msrs Core;
1407	uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1408	} uBuf;
1409	uint64_t *pauDsts[32];
1410	uint32_t iMsr = 0;
1411	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1412
1413	#define ADD_MSR(a_Msr, a_uValue) do { \
1414	Assert(iMsr < 32); \
1415	uBuf.Core.entries[iMsr].index = (a_Msr); \
1416	uBuf.Core.entries[iMsr].reserved = 0; \
1417	uBuf.Core.entries[iMsr].data = UINT64_MAX; \
1418	pauDsts[iMsr] = &(a_uValue); \
1419	iMsr += 1; \
1420	} while (0)
1421
1422	if (fWhat & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1423	ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1424	if (fWhat & CPUMCTX_EXTRN_SYSCALL_MSRS)
1425	{
1426	ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1427	ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1428	ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1429	ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1430	}
1431	if (fWhat & CPUMCTX_EXTRN_SYSENTER_MSRS)
1432	{
1433	ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1434	ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1435	ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1436	}
1437	if (fWhat & CPUMCTX_EXTRN_TSC_AUX)
1438	ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1439	if (fWhat & CPUMCTX_EXTRN_OTHER_MSRS)
1440	{
1441	ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1442	/** @todo What do we _have_ to add here?
1443	* We also have: Mttr, MiscEnable, FeatureControl. /
1444	}
1445
1446	uBuf.Core.pad = 0;
1447	uBuf.Core.nmsrs = iMsr;
1448	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MSRS, &uBuf);
1449	AssertMsgReturn(rc == (int)iMsr,
1450	("rc=%d iMsr=%d (->%#x) errno=%d\n",
1451	rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1452	VERR_NEM_IPE_3);
1453
1454	while (iMsr-- > 0)
1455	*pauDsts[iMsr] = uBuf.Core.entries[iMsr].data;
1456	#undef ADD_MSR
1457	}
1458
1459	/*
1460	* Interruptibility state and pending interrupts.
1461	*/
1462	if (fWhat & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1463	{
1464	fWhat \|= CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI; /* always do both, see export and interrupt FF handling */
1465
1466	struct kvm_vcpu_events KvmEvents = {0};
1467	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
1468	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1469
1470	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP)
1471	pVCpu->cpum.GstCtx.rip = pRun->s.regs.regs.rip;
1472
1473	if (KvmEvents.interrupt.shadow)
1474	EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip);
1475	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1476	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1477
1478	if (KvmEvents.nmi.masked)
1479	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
1480	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1481	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
1482
1483	if (KvmEvents.interrupt.injected)
1484	{
1485	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportPendingInterrupt);
1486	TRPMAssertTrap(pVCpu, KvmEvents.interrupt.nr, !KvmEvents.interrupt.soft ? TRPM_HARDWARE_INT : TRPM_SOFTWARE_INT);
1487	}
1488
1489	Assert(KvmEvents.nmi.injected == 0);
1490	Assert(KvmEvents.nmi.pending == 0);
1491	}
1492
1493	/*
1494	* Update the external mask.
1495	*/
1496	pCtx->fExtrn &= ~fWhat;
1497	pVCpu->cpum.GstCtx.fExtrn &= ~fWhat;
1498	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1499	pVCpu->cpum.GstCtx.fExtrn = 0;
1500
1501	/*
1502	* We sometimes need to update PGM on the guest status.
1503	*/
1504	if (!fMaybeChangedMode && !fUpdateCr3)
1505	{ /* likely */ }
1506	else
1507	{
1508	/*
1509	* Make sure we got all the state PGM might need.
1510	*/
1511	Log7(("nemHCLnxImportState: fMaybeChangedMode=%d fUpdateCr3=%d fExtrnNeeded=%#RX64\n", fMaybeChangedMode, fUpdateCr3,
1512	pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER) ));
1513	if (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER))
1514	{
1515	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR0)
1516	{
1517	if (pVCpu->cpum.GstCtx.cr0 != pRun->s.regs.sregs.cr0)
1518	{
1519	CPUMSetGuestCR0(pVCpu, pRun->s.regs.sregs.cr0);
1520	fMaybeChangedMode = true;
1521	}
1522	}
1523	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR3)
1524	{
1525	if (pCtx->cr3 != pRun->s.regs.sregs.cr3)
1526	{
1527	CPUMSetGuestCR3(pVCpu, pRun->s.regs.sregs.cr3);
1528	fUpdateCr3 = true;
1529	}
1530	}
1531	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_CR4)
1532	{
1533	if (pCtx->cr4 != pRun->s.regs.sregs.cr4)
1534	{
1535	CPUMSetGuestCR4(pVCpu, pRun->s.regs.sregs.cr4);
1536	fMaybeChangedMode = true;
1537	}
1538	}
1539	if (fWhat & CPUMCTX_EXTRN_EFER)
1540	{
1541	if (pCtx->msrEFER != pRun->s.regs.sregs.efer)
1542	{
1543	Log7(("NEM/%u: MSR EFER changed %RX64 -> %RX64\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.msrEFER, pRun->s.regs.sregs.efer));
1544	if ((pRun->s.regs.sregs.efer ^ pVCpu->cpum.GstCtx.msrEFER) & MSR_K6_EFER_NXE)
1545	PGMNotifyNxeChanged(pVCpu, RT_BOOL(pRun->s.regs.sregs.efer & MSR_K6_EFER_NXE));
1546	pCtx->msrEFER = pRun->s.regs.sregs.efer;
1547	fMaybeChangedMode = true;
1548	}
1549	}
1550
1551	pVCpu->cpum.GstCtx.fExtrn &= ~(CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_CR3 \| CPUMCTX_EXTRN_EFER);
1552	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
1553	pVCpu->cpum.GstCtx.fExtrn = 0;
1554	}
1555
1556	/*
1557	* Notify PGM about the changes.
1558	*/
1559	if (fMaybeChangedMode)
1560	{
1561	int rc = PGMChangeMode(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr4,
1562	pVCpu->cpum.GstCtx.msrEFER, false /fForce/);
1563	AssertMsgReturn(rc == VINF_SUCCESS, ("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_1);
1564	}
1565
1566	if (fUpdateCr3)
1567	{
1568	int rc = PGMUpdateCR3(pVCpu, pVCpu->cpum.GstCtx.cr3);
1569	if (rc == VINF_SUCCESS)
1570	{ /* likely */ }
1571	else
1572	AssertMsgFailedReturn(("rc=%Rrc\n", rc), RT_FAILURE_NP(rc) ? rc : VERR_NEM_IPE_2);
1573	}
1574	}
1575
1576	return VINF_SUCCESS;
1577	}
1578
1579
1580	/**
1581	* Interface for importing state on demand (used by IEM).
1582	*
1583	* @returns VBox status code.
1584	* @param pVCpu The cross context CPU structure.
1585	* @param fWhat What to import, CPUMCTX_EXTRN_XXX.
1586	*/
1587	VMM_INT_DECL(int) NEMImportStateOnDemand(PVMCPUCC pVCpu, uint64_t fWhat)
1588	{
1589	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnDemand);
1590	return nemHCLnxImportState(pVCpu, fWhat, &pVCpu->cpum.GstCtx, pVCpu->nem.s.pRun);
1591	}
1592
1593
1594	/**
1595	* Exports state to KVM.
1596	*/
1597	static int nemHCLnxExportState(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, struct kvm_run *pRun)
1598	{
1599	uint64_t const fExtrn = ~pCtx->fExtrn & CPUMCTX_EXTRN_ALL;
1600	Assert((~fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL);
1601
1602	/*
1603	* Stuff that goes into kvm_run::s.regs.regs:
1604	*/
1605	if (fExtrn & (CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_GPRS_MASK))
1606	{
1607	if (fExtrn & CPUMCTX_EXTRN_RIP)
1608	pRun->s.regs.regs.rip = pCtx->rip;
1609	if (fExtrn & CPUMCTX_EXTRN_RFLAGS)
1610	pRun->s.regs.regs.rflags = pCtx->rflags.u;
1611
1612	if (fExtrn & CPUMCTX_EXTRN_RAX)
1613	pRun->s.regs.regs.rax = pCtx->rax;
1614	if (fExtrn & CPUMCTX_EXTRN_RCX)
1615	pRun->s.regs.regs.rcx = pCtx->rcx;
1616	if (fExtrn & CPUMCTX_EXTRN_RDX)
1617	pRun->s.regs.regs.rdx = pCtx->rdx;
1618	if (fExtrn & CPUMCTX_EXTRN_RBX)
1619	pRun->s.regs.regs.rbx = pCtx->rbx;
1620	if (fExtrn & CPUMCTX_EXTRN_RSP)
1621	pRun->s.regs.regs.rsp = pCtx->rsp;
1622	if (fExtrn & CPUMCTX_EXTRN_RBP)
1623	pRun->s.regs.regs.rbp = pCtx->rbp;
1624	if (fExtrn & CPUMCTX_EXTRN_RSI)
1625	pRun->s.regs.regs.rsi = pCtx->rsi;
1626	if (fExtrn & CPUMCTX_EXTRN_RDI)
1627	pRun->s.regs.regs.rdi = pCtx->rdi;
1628	if (fExtrn & CPUMCTX_EXTRN_R8_R15)
1629	{
1630	pRun->s.regs.regs.r8 = pCtx->r8;
1631	pRun->s.regs.regs.r9 = pCtx->r9;
1632	pRun->s.regs.regs.r10 = pCtx->r10;
1633	pRun->s.regs.regs.r11 = pCtx->r11;
1634	pRun->s.regs.regs.r12 = pCtx->r12;
1635	pRun->s.regs.regs.r13 = pCtx->r13;
1636	pRun->s.regs.regs.r14 = pCtx->r14;
1637	pRun->s.regs.regs.r15 = pCtx->r15;
1638	}
1639	pRun->kvm_dirty_regs \|= KVM_SYNC_X86_REGS;
1640	}
1641
1642	/*
1643	* Stuff that goes into kvm_run::s.regs.sregs:
1644	*
1645	* The APIC base register updating is a little suboptimal... But at least
1646	* VBox always has the right base register value, so it's one directional.
1647	*/
1648	uint64_t const uApicBase = APICGetBaseMsrNoCheck(pVCpu);
1649	if ( (fExtrn & ( CPUMCTX_EXTRN_SREG_MASK \| CPUMCTX_EXTRN_TABLE_MASK \| CPUMCTX_EXTRN_CR_MASK
1650	\| CPUMCTX_EXTRN_EFER \| CPUMCTX_EXTRN_APIC_TPR))
1651	\|\| uApicBase != pVCpu->nem.s.uKvmApicBase)
1652	{
1653	if ((pVCpu->nem.s.uKvmApicBase ^ uApicBase) & MSR_IA32_APICBASE_EN)
1654	Log(("NEM/%u: APICBASE_EN changed %#010RX64 -> %#010RX64\n", pVCpu->idCpu, pVCpu->nem.s.uKvmApicBase, uApicBase));
1655	pRun->s.regs.sregs.apic_base = uApicBase;
1656	pVCpu->nem.s.uKvmApicBase = uApicBase;
1657
1658	if (fExtrn & CPUMCTX_EXTRN_APIC_TPR)
1659	pRun->s.regs.sregs.cr8 = CPUMGetGuestCR8(pVCpu);
1660
1661	#define NEM_LNX_EXPORT_SEG(a_KvmSeg, a_CtxSeg) do { \
1662	(a_KvmSeg).base = (a_CtxSeg).u64Base; \
1663	(a_KvmSeg).limit = (a_CtxSeg).u32Limit; \
1664	(a_KvmSeg).selector = (a_CtxSeg).Sel; \
1665	(a_KvmSeg).type = (a_CtxSeg).Attr.n.u4Type; \
1666	(a_KvmSeg).s = (a_CtxSeg).Attr.n.u1DescType; \
1667	(a_KvmSeg).dpl = (a_CtxSeg).Attr.n.u2Dpl; \
1668	(a_KvmSeg).present = (a_CtxSeg).Attr.n.u1Present; \
1669	(a_KvmSeg).avl = (a_CtxSeg).Attr.n.u1Available; \
1670	(a_KvmSeg).l = (a_CtxSeg).Attr.n.u1Long; \
1671	(a_KvmSeg).db = (a_CtxSeg).Attr.n.u1DefBig; \
1672	(a_KvmSeg).g = (a_CtxSeg).Attr.n.u1Granularity; \
1673	(a_KvmSeg).unusable = (a_CtxSeg).Attr.n.u1Unusable; \
1674	(a_KvmSeg).padding = 0; \
1675	} while (0)
1676
1677	if (fExtrn & CPUMCTX_EXTRN_SREG_MASK)
1678	{
1679	if (fExtrn & CPUMCTX_EXTRN_ES)
1680	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.es, pCtx->es);
1681	if (fExtrn & CPUMCTX_EXTRN_CS)
1682	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.cs, pCtx->cs);
1683	if (fExtrn & CPUMCTX_EXTRN_SS)
1684	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ss, pCtx->ss);
1685	if (fExtrn & CPUMCTX_EXTRN_DS)
1686	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ds, pCtx->ds);
1687	if (fExtrn & CPUMCTX_EXTRN_FS)
1688	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.fs, pCtx->fs);
1689	if (fExtrn & CPUMCTX_EXTRN_GS)
1690	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.gs, pCtx->gs);
1691	}
1692	if (fExtrn & CPUMCTX_EXTRN_TABLE_MASK)
1693	{
1694	if (fExtrn & CPUMCTX_EXTRN_GDTR)
1695	{
1696	pRun->s.regs.sregs.gdt.base = pCtx->gdtr.pGdt;
1697	pRun->s.regs.sregs.gdt.limit = pCtx->gdtr.cbGdt;
1698	pRun->s.regs.sregs.gdt.padding[0] = 0;
1699	pRun->s.regs.sregs.gdt.padding[1] = 0;
1700	pRun->s.regs.sregs.gdt.padding[2] = 0;
1701	}
1702	if (fExtrn & CPUMCTX_EXTRN_IDTR)
1703	{
1704	pRun->s.regs.sregs.idt.base = pCtx->idtr.pIdt;
1705	pRun->s.regs.sregs.idt.limit = pCtx->idtr.cbIdt;
1706	pRun->s.regs.sregs.idt.padding[0] = 0;
1707	pRun->s.regs.sregs.idt.padding[1] = 0;
1708	pRun->s.regs.sregs.idt.padding[2] = 0;
1709	}
1710	if (fExtrn & CPUMCTX_EXTRN_LDTR)
1711	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.ldt, pCtx->ldtr);
1712	if (fExtrn & CPUMCTX_EXTRN_TR)
1713	NEM_LNX_EXPORT_SEG(pRun->s.regs.sregs.tr, pCtx->tr);
1714	}
1715	if (fExtrn & CPUMCTX_EXTRN_CR_MASK)
1716	{
1717	if (fExtrn & CPUMCTX_EXTRN_CR0)
1718	pRun->s.regs.sregs.cr0 = pCtx->cr0;
1719	if (fExtrn & CPUMCTX_EXTRN_CR2)
1720	pRun->s.regs.sregs.cr2 = pCtx->cr2;
1721	if (fExtrn & CPUMCTX_EXTRN_CR3)
1722	pRun->s.regs.sregs.cr3 = pCtx->cr3;
1723	if (fExtrn & CPUMCTX_EXTRN_CR4)
1724	pRun->s.regs.sregs.cr4 = pCtx->cr4;
1725	}
1726	if (fExtrn & CPUMCTX_EXTRN_EFER)
1727	pRun->s.regs.sregs.efer = pCtx->msrEFER;
1728
1729	RT_ZERO(pRun->s.regs.sregs.interrupt_bitmap); /* this is an alternative interrupt injection interface */
1730
1731	pRun->kvm_dirty_regs \|= KVM_SYNC_X86_SREGS;
1732	}
1733
1734	/*
1735	* Debug registers.
1736	*/
1737	if (fExtrn & CPUMCTX_EXTRN_DR_MASK)
1738	{
1739	struct kvm_debugregs DbgRegs = {{0}};
1740
1741	if ((fExtrn & CPUMCTX_EXTRN_DR_MASK) != CPUMCTX_EXTRN_DR_MASK)
1742	{
1743	/* Partial debug state, we must get DbgRegs first so we can merge: */
1744	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_DEBUGREGS, &DbgRegs);
1745	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1746	}
1747
1748	if (fExtrn & CPUMCTX_EXTRN_DR0_DR3)
1749	{
1750	DbgRegs.db[0] = pCtx->dr[0];
1751	DbgRegs.db[1] = pCtx->dr[1];
1752	DbgRegs.db[2] = pCtx->dr[2];
1753	DbgRegs.db[3] = pCtx->dr[3];
1754	}
1755	if (fExtrn & CPUMCTX_EXTRN_DR6)
1756	DbgRegs.dr6 = pCtx->dr[6];
1757	if (fExtrn & CPUMCTX_EXTRN_DR7)
1758	DbgRegs.dr7 = pCtx->dr[7];
1759
1760	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_DEBUGREGS, &DbgRegs);
1761	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1762	}
1763
1764	/*
1765	* FPU, SSE, AVX, ++.
1766	*/
1767	if (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE \| CPUMCTX_EXTRN_XCRx))
1768	{
1769	if (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1770	{
1771	/** @todo could IEM just grab state partial control in some situations? */
1772	Assert( (fExtrn & (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE))
1773	== (CPUMCTX_EXTRN_X87 \| CPUMCTX_EXTRN_SSE_AVX \| CPUMCTX_EXTRN_OTHER_XSAVE)); /* no partial states */
1774
1775	AssertCompile(sizeof(pCtx->XState) >= sizeof(struct kvm_xsave));
1776	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XSAVE, &pCtx->XState);
1777	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1778	}
1779
1780	if (fExtrn & CPUMCTX_EXTRN_XCRx)
1781	{
1782	struct kvm_xcrs Xcrs =
1783	{ /.nr_xcrs = / 2,
1784	/.flags = / 0,
1785	/.xcrs= / {
1786	{ /.xcr =/ 0, /.reserved=/ 0, /.value=/ pCtx->aXcr[0] },
1787	{ /.xcr =/ 1, /.reserved=/ 0, /.value=/ pCtx->aXcr[1] },
1788	}
1789	};
1790
1791	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_XCRS, &Xcrs);
1792	AssertMsgReturn(rc == 0, ("rc=%d errno=%d\n", rc, errno), VERR_NEM_IPE_3);
1793	}
1794	}
1795
1796	/*
1797	* MSRs.
1798	*/
1799	if (fExtrn & ( CPUMCTX_EXTRN_KERNEL_GS_BASE \| CPUMCTX_EXTRN_SYSCALL_MSRS \| CPUMCTX_EXTRN_SYSENTER_MSRS
1800	\| CPUMCTX_EXTRN_TSC_AUX \| CPUMCTX_EXTRN_OTHER_MSRS))
1801	{
1802	union
1803	{
1804	struct kvm_msrs Core;
1805	uint64_t padding[2 + sizeof(struct kvm_msr_entry) * 32];
1806	} uBuf;
1807	uint32_t iMsr = 0;
1808	PCPUMCTXMSRS const pCtxMsrs = CPUMQueryGuestCtxMsrsPtr(pVCpu);
1809
1810	#define ADD_MSR(a_Msr, a_uValue) do { \
1811	Assert(iMsr < 32); \
1812	uBuf.Core.entries[iMsr].index = (a_Msr); \
1813	uBuf.Core.entries[iMsr].reserved = 0; \
1814	uBuf.Core.entries[iMsr].data = (a_uValue); \
1815	iMsr += 1; \
1816	} while (0)
1817
1818	if (fExtrn & CPUMCTX_EXTRN_KERNEL_GS_BASE)
1819	ADD_MSR(MSR_K8_KERNEL_GS_BASE, pCtx->msrKERNELGSBASE);
1820	if (fExtrn & CPUMCTX_EXTRN_SYSCALL_MSRS)
1821	{
1822	ADD_MSR(MSR_K6_STAR, pCtx->msrSTAR);
1823	ADD_MSR(MSR_K8_LSTAR, pCtx->msrLSTAR);
1824	ADD_MSR(MSR_K8_CSTAR, pCtx->msrCSTAR);
1825	ADD_MSR(MSR_K8_SF_MASK, pCtx->msrSFMASK);
1826	}
1827	if (fExtrn & CPUMCTX_EXTRN_SYSENTER_MSRS)
1828	{
1829	ADD_MSR(MSR_IA32_SYSENTER_CS, pCtx->SysEnter.cs);
1830	ADD_MSR(MSR_IA32_SYSENTER_EIP, pCtx->SysEnter.eip);
1831	ADD_MSR(MSR_IA32_SYSENTER_ESP, pCtx->SysEnter.esp);
1832	}
1833	if (fExtrn & CPUMCTX_EXTRN_TSC_AUX)
1834	ADD_MSR(MSR_K8_TSC_AUX, pCtxMsrs->msr.TscAux);
1835	if (fExtrn & CPUMCTX_EXTRN_OTHER_MSRS)
1836	{
1837	ADD_MSR(MSR_IA32_CR_PAT, pCtx->msrPAT);
1838	/** @todo What do we _have_ to add here?
1839	* We also have: Mttr, MiscEnable, FeatureControl. /
1840	}
1841
1842	uBuf.Core.pad = 0;
1843	uBuf.Core.nmsrs = iMsr;
1844	int rc = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_MSRS, &uBuf);
1845	AssertMsgReturn(rc == (int)iMsr,
1846	("rc=%d iMsr=%d (->%#x) errno=%d\n",
1847	rc, iMsr, (uint32_t)rc < iMsr ? uBuf.Core.entries[rc].index : 0, errno),
1848	VERR_NEM_IPE_3);
1849	}
1850
1851	/*
1852	* Interruptibility state.
1853	*
1854	* Note! This I/O control function sets most fields passed in, so when
1855	* raising an interrupt, NMI, SMI or exception, this must be done
1856	* by the code doing the rasing or we'll overwrite it here.
1857	*/
1858	if (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1859	{
1860	Assert( (fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI))
1861	== (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI));
1862
1863	struct kvm_vcpu_events KvmEvents = {0};
1864
1865	KvmEvents.flags = KVM_VCPUEVENT_VALID_SHADOW;
1866	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
1867	{
1868	if (pRun->s.regs.regs.rip == EMGetInhibitInterruptsPC(pVCpu))
1869	KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS \| KVM_X86_SHADOW_INT_STI;
1870	else
1871	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1872	}
1873
1874	/* No flag - this is updated unconditionally. */
1875	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
1876	KvmEvents.nmi.masked = 1;
1877
1878	if (TRPMHasTrap(pVCpu))
1879	{
1880	TRPMEVENT enmType = TRPM_32BIT_HACK;
1881	uint8_t bTrapNo = 0;
1882	TRPMQueryTrap(pVCpu, &bTrapNo, &enmType);
1883	Log(("nemHCLnxExportState: Pending trap: bTrapNo=%#x enmType=%d\n", bTrapNo, enmType));
1884	if ( enmType == TRPM_HARDWARE_INT
1885	\|\| enmType == TRPM_SOFTWARE_INT)
1886	{
1887	KvmEvents.interrupt.soft = enmType == TRPM_SOFTWARE_INT;
1888	KvmEvents.interrupt.nr = bTrapNo;
1889	KvmEvents.interrupt.injected = 1;
1890	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExportPendingInterrupt);
1891	TRPMResetTrap(pVCpu);
1892	}
1893	else
1894	AssertFailed();
1895	}
1896
1897	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
1898	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_3);
1899	}
1900
1901	/*
1902	* KVM now owns all the state.
1903	*/
1904	pCtx->fExtrn = CPUMCTX_EXTRN_KEEPER_NEM \| CPUMCTX_EXTRN_ALL;
1905
1906	RT_NOREF(pVM);
1907	return VINF_SUCCESS;
1908	}
1909
1910
1911	/**
1912	* Query the CPU tick counter and optionally the TSC_AUX MSR value.
1913	*
1914	* @returns VBox status code.
1915	* @param pVCpu The cross context CPU structure.
1916	* @param pcTicks Where to return the CPU tick count.
1917	* @param puAux Where to return the TSC_AUX register value.
1918	*/
1919	VMM_INT_DECL(int) NEMHCQueryCpuTick(PVMCPUCC pVCpu, uint64_t pcTicks, uint32_t puAux)
1920	{
1921	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatQueryCpuTick);
1922	// KVM_GET_CLOCK?
1923	RT_NOREF(pVCpu, pcTicks, puAux);
1924	return VINF_SUCCESS;
1925	}
1926
1927
1928	/**
1929	* Resumes CPU clock (TSC) on all virtual CPUs.
1930	*
1931	* This is called by TM when the VM is started, restored, resumed or similar.
1932	*
1933	* @returns VBox status code.
1934	* @param pVM The cross context VM structure.
1935	* @param pVCpu The cross context CPU structure of the calling EMT.
1936	* @param uPausedTscValue The TSC value at the time of pausing.
1937	*/
1938	VMM_INT_DECL(int) NEMHCResumeCpuTickOnAll(PVMCC pVM, PVMCPUCC pVCpu, uint64_t uPausedTscValue)
1939	{
1940	// KVM_SET_CLOCK?
1941	RT_NOREF(pVM, pVCpu, uPausedTscValue);
1942	return VINF_SUCCESS;
1943	}
1944
1945
1946	VMM_INT_DECL(uint32_t) NEMHCGetFeatures(PVMCC pVM)
1947	{
1948	RT_NOREF(pVM);
1949	return NEM_FEAT_F_NESTED_PAGING
1950	\| NEM_FEAT_F_FULL_GST_EXEC
1951	\| NEM_FEAT_F_XSAVE_XRSTOR;
1952	}
1953
1954
1955
1956	/*********************************************************************************************************************************
1957	* Execution *
1958	*********************************************************************************************************************************/
1959
1960
1961	VMMR3_INT_DECL(bool) NEMR3CanExecuteGuest(PVM pVM, PVMCPU pVCpu)
1962	{
1963	/*
1964	* Only execute when the A20 gate is enabled as I cannot immediately
1965	* spot any A20 support in KVM.
1966	*/
1967	RT_NOREF(pVM);
1968	Assert(VM_IS_NEM_ENABLED(pVM));
1969	return PGMPhysIsA20Enabled(pVCpu);
1970	}
1971
1972
1973	bool nemR3NativeSetSingleInstruction(PVM pVM, PVMCPU pVCpu, bool fEnable)
1974	{
1975	NOREF(pVM); NOREF(pVCpu); NOREF(fEnable);
1976	return false;
1977	}
1978
1979
1980	/**
1981	* Forced flag notification call from VMEmt.cpp.
1982	*
1983	* This is only called when pVCpu is in the VMCPUSTATE_STARTED_EXEC_NEM state.
1984	*
1985	* @param pVM The cross context VM structure.
1986	* @param pVCpu The cross context virtual CPU structure of the CPU
1987	* to be notified.
1988	* @param fFlags Notification flags, VMNOTIFYFF_FLAGS_XXX.
1989	*/
1990	void nemR3NativeNotifyFF(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
1991	{
1992	int rc = RTThreadPoke(pVCpu->hThread);
1993	LogFlow(("nemR3NativeNotifyFF: #%u -> %Rrc\n", pVCpu->idCpu, rc));
1994	AssertRC(rc);
1995	RT_NOREF(pVM, fFlags);
1996	}
1997
1998
1999	/**
2000	* Deals with pending interrupt FFs prior to executing guest code.
2001	*/
2002	static VBOXSTRICTRC nemHCLnxHandleInterruptFF(PVM pVM, PVMCPU pVCpu, struct kvm_run *pRun)
2003	{
2004	RT_NOREF_PV(pVM);
2005
2006	/*
2007	* Do not doing anything if TRPM has something pending already as we can
2008	* only inject one event per KVM_RUN call. This can only happend if we
2009	* can directly from the loop in EM, so the inhibit bits must be internal.
2010	*/
2011	if (!TRPMHasTrap(pVCpu))
2012	{ /* semi likely */ }
2013	else
2014	{
2015	Assert(!(pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI)));
2016	Log8(("nemHCLnxHandleInterruptFF: TRPM has an pending event already\n"));
2017	return VINF_SUCCESS;
2018	}
2019
2020	/*
2021	* First update APIC. We ASSUME this won't need TPR/CR8.
2022	*/
2023	if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
2024	{
2025	APICUpdatePendingInterrupts(pVCpu);
2026	if (!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC
2027	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2028	return VINF_SUCCESS;
2029	}
2030
2031	/*
2032	* We don't currently implement SMIs.
2033	*/
2034	AssertReturn(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI), VERR_NEM_IPE_0);
2035
2036	/*
2037	* In KVM the CPUMCTX_EXTRN_INHIBIT_INT and CPUMCTX_EXTRN_INHIBIT_NMI states
2038	* are tied together with interrupt and NMI delivery, so we must get and
2039	* synchronize these all in one go and set both CPUMCTX_EXTRN_INHIBIT_XXX flags.
2040	* If we don't we may lose the interrupt/NMI we marked pending here when the
2041	* state is exported again before execution.
2042	*/
2043	struct kvm_vcpu_events KvmEvents = {0};
2044	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_VCPU_EVENTS, &KvmEvents);
2045	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2046
2047	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_RIP))
2048	pRun->s.regs.regs.rip = pVCpu->cpum.GstCtx.rip;
2049
2050	KvmEvents.flags \|= KVM_VCPUEVENT_VALID_SHADOW;
2051	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_INT))
2052	{
2053	if (!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2054	KvmEvents.interrupt.shadow = 0;
2055	else if (EMGetInhibitInterruptsPC(pVCpu) == pRun->s.regs.regs.rip)
2056	KvmEvents.interrupt.shadow = KVM_X86_SHADOW_INT_MOV_SS \| KVM_X86_SHADOW_INT_STI;
2057	else
2058	{
2059	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2060	KvmEvents.interrupt.shadow = 0;
2061	}
2062	}
2063	else if (KvmEvents.interrupt.shadow)
2064	EMSetInhibitInterruptsPC(pVCpu, pRun->s.regs.regs.rip);
2065	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
2066	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
2067
2068	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_INHIBIT_NMI))
2069	KvmEvents.nmi.masked = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS) ? 1 : 0;
2070	else if (KvmEvents.nmi.masked)
2071	VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
2072	else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
2073	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
2074
2075	/* KVM will own the INT + NMI inhibit state soon: */
2076	pVCpu->cpum.GstCtx.fExtrn = (pVCpu->cpum.GstCtx.fExtrn & ~CPUMCTX_EXTRN_KEEPER_MASK)
2077	\| CPUMCTX_EXTRN_KEEPER_NEM \| CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI;
2078
2079	/*
2080	* NMI? Try deliver it first.
2081	*/
2082	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI))
2083	{
2084	#if 0
2085	int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_NMI, 0UL);
2086	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2087	#else
2088	KvmEvents.flags \|= KVM_VCPUEVENT_VALID_NMI_PENDING;
2089	KvmEvents.nmi.pending = 1;
2090	#endif
2091	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
2092	Log8(("Queuing NMI on %u\n", pVCpu->idCpu));
2093	}
2094
2095	/*
2096	* APIC or PIC interrupt?
2097	*/
2098	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_INTERRUPT_PIC))
2099	{
2100	if (pRun->s.regs.regs.rflags & X86_EFL_IF)
2101	{
2102	if (KvmEvents.interrupt.shadow == 0)
2103	{
2104	/*
2105	* If CR8 is in KVM, update the VBox copy so PDMGetInterrupt will
2106	* work correctly.
2107	*/
2108	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_APIC_TPR)
2109	APICSetTpr(pVCpu, (uint8_t)pRun->cr8 << 4);
2110
2111	uint8_t bInterrupt;
2112	int rc = PDMGetInterrupt(pVCpu, &bInterrupt);
2113	if (RT_SUCCESS(rc))
2114	{
2115	Assert(KvmEvents.interrupt.injected == false);
2116	#if 0
2117	int rcLnx = ioctl(pVCpu->nem.s.fdVm, KVM_INTERRUPT, (unsigned long)bInterrupt);
2118	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2119	#else
2120	KvmEvents.interrupt.nr = bInterrupt;
2121	KvmEvents.interrupt.soft = false;
2122	KvmEvents.interrupt.injected = true;
2123	#endif
2124	Log8(("Queuing interrupt %#x on %u: %04x:%08RX64 efl=%#x\n", bInterrupt, pVCpu->idCpu,
2125	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.eflags));
2126	}
2127	else if (rc == VERR_APIC_INTR_MASKED_BY_TPR) /** @todo this isn't extremely efficient if we get a lot of exits... */
2128	Log8(("VERR_APIC_INTR_MASKED_BY_TPR\n")); /* We'll get a TRP exit - no interrupt window needed. */
2129	else
2130	Log8(("PDMGetInterrupt failed -> %Rrc\n", rc));
2131	}
2132	else
2133	{
2134	pRun->request_interrupt_window = 1;
2135	Log8(("Interrupt window pending on %u (#2)\n", pVCpu->idCpu));
2136	}
2137	}
2138	else
2139	{
2140	pRun->request_interrupt_window = 1;
2141	Log8(("Interrupt window pending on %u (#1)\n", pVCpu->idCpu));
2142	}
2143	}
2144
2145	/*
2146	* Now, update the state.
2147	*/
2148	/** @todo skip when possible... */
2149	rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_SET_VCPU_EVENTS, &KvmEvents);
2150	AssertLogRelMsgReturn(rcLnx == 0, ("rcLnx=%d errno=%d\n", rcLnx, errno), VERR_NEM_IPE_5);
2151
2152	return VINF_SUCCESS;
2153	}
2154
2155
2156	/**
2157	* Handles KVM_EXIT_INTERNAL_ERROR.
2158	*/
2159	static VBOXSTRICTRC nemR3LnxHandleInternalError(PVMCPU pVCpu, struct kvm_run *pRun)
2160	{
2161	Log(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%d) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror,
2162	pRun->internal.suberror, pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2163
2164	/*
2165	* Deal with each suberror, returning if we don't want IEM to handle it.
2166	*/
2167	switch (pRun->internal.suberror)
2168	{
2169	case KVM_INTERNAL_ERROR_EMULATION:
2170	{
2171	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_EMULATION),
2172	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2173	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorEmulation);
2174	break;
2175	}
2176
2177	case KVM_INTERNAL_ERROR_SIMUL_EX:
2178	case KVM_INTERNAL_ERROR_DELIVERY_EV:
2179	case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON:
2180	default:
2181	{
2182	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERNAL_ERROR_FATAL),
2183	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2184	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitInternalErrorFatal);
2185	const char *pszName;
2186	switch (pRun->internal.suberror)
2187	{
2188	case KVM_INTERNAL_ERROR_EMULATION: pszName = "KVM_INTERNAL_ERROR_EMULATION"; break;
2189	case KVM_INTERNAL_ERROR_SIMUL_EX: pszName = "KVM_INTERNAL_ERROR_SIMUL_EX"; break;
2190	case KVM_INTERNAL_ERROR_DELIVERY_EV: pszName = "KVM_INTERNAL_ERROR_DELIVERY_EV"; break;
2191	case KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON: pszName = "KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON"; break;
2192	default: pszName = "unknown"; break;
2193	}
2194	LogRel(("NEM: KVM_EXIT_INTERNAL_ERROR! suberror=%#x (%s) ndata=%u data=%.*Rhxs\n", pRun->internal.suberror, pszName,
2195	pRun->internal.ndata, sizeof(pRun->internal.data), &pRun->internal.data[0]));
2196	return VERR_NEM_IPE_0;
2197	}
2198	}
2199
2200	/*
2201	* Execute instruction in IEM and try get on with it.
2202	*/
2203	Log2(("nemR3LnxHandleInternalError: Executing instruction at %04x:%08RX64 in IEM\n",
2204	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip));
2205	VBOXSTRICTRC rcStrict = nemHCLnxImportState(pVCpu,
2206	IEM_CPUMCTX_EXTRN_MUST_MASK \| CPUMCTX_EXTRN_INHIBIT_INT
2207	\| CPUMCTX_EXTRN_INHIBIT_NMI,
2208	&pVCpu->cpum.GstCtx, pRun);
2209	if (RT_SUCCESS(rcStrict))
2210	rcStrict = IEMExecOne(pVCpu);
2211	return rcStrict;
2212	}
2213
2214
2215	/**
2216	* Handles KVM_EXIT_IO.
2217	*/
2218	static VBOXSTRICTRC nemHCLnxHandleExitIo(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2219	{
2220	/*
2221	* Input validation.
2222	*/
2223	Assert(pRun->io.count > 0);
2224	Assert(pRun->io.size == 1 \|\| pRun->io.size == 2 \|\| pRun->io.size == 4);
2225	Assert(pRun->io.direction == KVM_EXIT_IO_IN \|\| pRun->io.direction == KVM_EXIT_IO_OUT);
2226	Assert(pRun->io.data_offset < pVM->nem.s.cbVCpuMmap);
2227	Assert(pRun->io.data_offset + pRun->io.size * pRun->io.count <= pVM->nem.s.cbVCpuMmap);
2228
2229	/*
2230	* We cannot easily act on the exit history here, because the I/O port
2231	* exit is stateful and the instruction will be completed in the next
2232	* KVM_RUN call. There seems no way to avoid this.
2233	*/
2234	EMHistoryAddExit(pVCpu,
2235	pRun->io.count == 1
2236	? ( pRun->io.direction == KVM_EXIT_IO_IN
2237	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_READ)
2238	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_WRITE))
2239	: ( pRun->io.direction == KVM_EXIT_IO_IN
2240	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_READ)
2241	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_IO_PORT_STR_WRITE)),
2242	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2243
2244	/*
2245	* Do the requested job.
2246	*/
2247	VBOXSTRICTRC rcStrict;
2248	RTPTRUNION uPtrData;
2249	uPtrData.pu8 = (uint8_t *)pRun + pRun->io.data_offset;
2250	if (pRun->io.count == 1)
2251	{
2252	if (pRun->io.direction == KVM_EXIT_IO_IN)
2253	{
2254	uint32_t uValue = 0;
2255	rcStrict = IOMIOPortRead(pVM, pVCpu, pRun->io.port, &uValue, pRun->io.size);
2256	Log4(("IOExit/%u: %04x:%08RX64: IN %#x LB %u -> %#x, rcStrict=%Rrc\n",
2257	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2258	pRun->io.port, pRun->io.size, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
2259	if (IOM_SUCCESS(rcStrict))
2260	{
2261	if (pRun->io.size == 4)
2262	*uPtrData.pu32 = uValue;
2263	else if (pRun->io.size == 2)
2264	*uPtrData.pu16 = (uint16_t)uValue;
2265	else
2266	*uPtrData.pu8 = (uint8_t)uValue;
2267	}
2268	}
2269	else
2270	{
2271	uint32_t const uValue = pRun->io.size == 4 ? *uPtrData.pu32
2272	: pRun->io.size == 2 ? *uPtrData.pu16
2273	: *uPtrData.pu8;
2274	rcStrict = IOMIOPortWrite(pVM, pVCpu, pRun->io.port, uValue, pRun->io.size);
2275	Log4(("IOExit/%u: %04x:%08RX64: OUT %#x, %#x LB %u rcStrict=%Rrc\n",
2276	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2277	pRun->io.port, uValue, pRun->io.size, VBOXSTRICTRC_VAL(rcStrict) ));
2278	}
2279	}
2280	else
2281	{
2282	uint32_t cTransfers = pRun->io.count;
2283	if (pRun->io.direction == KVM_EXIT_IO_IN)
2284	{
2285	rcStrict = IOMIOPortReadString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2286	Log4(("IOExit/%u: %04x:%08RX64: REP INS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2287	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2288	pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2289	}
2290	else
2291	{
2292	rcStrict = IOMIOPortWriteString(pVM, pVCpu, pRun->io.port, uPtrData.pv, &cTransfers, pRun->io.size);
2293	Log4(("IOExit/%u: %04x:%08RX64: REP OUTS %#x LB %u * %#x times -> rcStrict=%Rrc cTransfers=%d\n",
2294	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2295	pRun->io.port, pRun->io.size, pRun->io.count, VBOXSTRICTRC_VAL(rcStrict), cTransfers ));
2296	}
2297	Assert(cTransfers == 0);
2298	}
2299	return rcStrict;
2300	}
2301
2302
2303	/**
2304	* Handles KVM_EXIT_MMIO.
2305	*/
2306	static VBOXSTRICTRC nemHCLnxHandleExitMmio(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run *pRun)
2307	{
2308	/*
2309	* Input validation.
2310	*/
2311	Assert(pRun->mmio.len <= sizeof(pRun->mmio.data));
2312	Assert(pRun->mmio.is_write <= 1);
2313
2314	/*
2315	* We cannot easily act on the exit history here, because the MMIO port
2316	* exit is stateful and the instruction will be completed in the next
2317	* KVM_RUN call. There seems no way to circumvent this.
2318	*/
2319	EMHistoryAddExit(pVCpu,
2320	pRun->mmio.is_write
2321	? EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_WRITE)
2322	: EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MMIO_READ),
2323	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2324
2325	/*
2326	* Do the requested job.
2327	*/
2328	VBOXSTRICTRC rcStrict;
2329	if (pRun->mmio.is_write)
2330	{
2331	rcStrict = PGMPhysWrite(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2332	Log4(("MmioExit/%u: %04x:%08RX64: WRITE %#x LB %u, %.*Rhxs -> rcStrict=%Rrc\n",
2333	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2334	pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2335	}
2336	else
2337	{
2338	rcStrict = PGMPhysRead(pVM, pRun->mmio.phys_addr, pRun->mmio.data, pRun->mmio.len, PGMACCESSORIGIN_HM);
2339	Log4(("MmioExit/%u: %04x:%08RX64: READ %#x LB %u -> %.*Rhxs rcStrict=%Rrc\n",
2340	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2341	pRun->mmio.phys_addr, pRun->mmio.len, pRun->mmio.len, pRun->mmio.data, VBOXSTRICTRC_VAL(rcStrict) ));
2342	}
2343	return rcStrict;
2344	}
2345
2346
2347	/**
2348	* Handles KVM_EXIT_RDMSR
2349	*/
2350	static VBOXSTRICTRC nemHCLnxHandleExitRdMsr(PVMCPUCC pVCpu, struct kvm_run *pRun)
2351	{
2352	/*
2353	* Input validation.
2354	*/
2355	Assert( pRun->msr.reason == KVM_MSR_EXIT_REASON_INVAL
2356	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_UNKNOWN
2357	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
2358
2359	/*
2360	* We cannot easily act on the exit history here, because the MSR exit is
2361	* stateful and the instruction will be completed in the next KVM_RUN call.
2362	* There seems no way to circumvent this.
2363	*/
2364	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_READ),
2365	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2366
2367	/*
2368	* Do the requested job.
2369	*/
2370	uint64_t uValue = 0;
2371	VBOXSTRICTRC rcStrict = CPUMQueryGuestMsr(pVCpu, pRun->msr.index, &uValue);
2372	pRun->msr.data = uValue;
2373	if (rcStrict != VERR_CPUM_RAISE_GP_0)
2374	{
2375	Log3(("MsrRead/%u: %04x:%08RX64: msr=%#010x (reason=%#x) -> %#RX64 rcStrict=%Rrc\n", pVCpu->idCpu,
2376	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.reason, uValue, VBOXSTRICTRC_VAL(rcStrict) ));
2377	pRun->msr.error = 0;
2378	}
2379	else
2380	{
2381	Log3(("MsrRead/%u: %04x:%08RX64: msr=%#010x (reason%#x)-> %#RX64 rcStrict=#GP!\n", pVCpu->idCpu,
2382	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.reason, uValue));
2383	pRun->msr.error = 1;
2384	rcStrict = VINF_SUCCESS;
2385	}
2386	return rcStrict;
2387	}
2388
2389
2390	/**
2391	* Handles KVM_EXIT_WRMSR
2392	*/
2393	static VBOXSTRICTRC nemHCLnxHandleExitWrMsr(PVMCPUCC pVCpu, struct kvm_run *pRun)
2394	{
2395	/*
2396	* Input validation.
2397	*/
2398	Assert( pRun->msr.reason == KVM_MSR_EXIT_REASON_INVAL
2399	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_UNKNOWN
2400	\|\| pRun->msr.reason == KVM_MSR_EXIT_REASON_FILTER);
2401
2402	/*
2403	* We cannot easily act on the exit history here, because the MSR exit is
2404	* stateful and the instruction will be completed in the next KVM_RUN call.
2405	* There seems no way to circumvent this.
2406	*/
2407	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_EM, EMEXITTYPE_MSR_WRITE),
2408	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2409
2410	/*
2411	* Do the requested job.
2412	*/
2413	VBOXSTRICTRC rcStrict = CPUMSetGuestMsr(pVCpu, pRun->msr.index, pRun->msr.data);
2414	if (rcStrict != VERR_CPUM_RAISE_GP_0)
2415	{
2416	Log3(("MsrWrite/%u: %04x:%08RX64: msr=%#010x := %#RX64 (reason=%#x) -> rcStrict=%Rrc\n", pVCpu->idCpu,
2417	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.data, pRun->msr.reason, VBOXSTRICTRC_VAL(rcStrict) ));
2418	pRun->msr.error = 0;
2419	}
2420	else
2421	{
2422	Log3(("MsrWrite/%u: %04x:%08RX64: msr=%#010x := %#RX64 (reason%#x)-> rcStrict=#GP!\n", pVCpu->idCpu,
2423	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->msr.index, pRun->msr.data, pRun->msr.reason));
2424	pRun->msr.error = 1;
2425	rcStrict = VINF_SUCCESS;
2426	}
2427	return rcStrict;
2428	}
2429
2430
2431
2432	static VBOXSTRICTRC nemHCLnxHandleExit(PVMCC pVM, PVMCPUCC pVCpu, struct kvm_run pRun, bool pfStatefulExit)
2433	{
2434	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTotal);
2435	switch (pRun->exit_reason)
2436	{
2437	case KVM_EXIT_EXCEPTION:
2438	AssertFailed();
2439	break;
2440
2441	case KVM_EXIT_IO:
2442	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIo);
2443	*pfStatefulExit = true;
2444	return nemHCLnxHandleExitIo(pVM, pVCpu, pRun);
2445
2446	case KVM_EXIT_MMIO:
2447	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitMmio);
2448	*pfStatefulExit = true;
2449	return nemHCLnxHandleExitMmio(pVM, pVCpu, pRun);
2450
2451	case KVM_EXIT_IRQ_WINDOW_OPEN:
2452	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTTERRUPT_WINDOW),
2453	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2454	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIrqWindowOpen);
2455	Log5(("IrqWinOpen/%u: %d\n", pVCpu->idCpu, pRun->request_interrupt_window));
2456	pRun->request_interrupt_window = 0;
2457	return VINF_SUCCESS;
2458
2459	case KVM_EXIT_SET_TPR:
2460	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitSetTpr);
2461	AssertFailed();
2462	break;
2463
2464	case KVM_EXIT_TPR_ACCESS:
2465	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitTprAccess);
2466	AssertFailed();
2467	break;
2468
2469	case KVM_EXIT_X86_RDMSR:
2470	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitRdMsr);
2471	*pfStatefulExit = true;
2472	return nemHCLnxHandleExitRdMsr(pVCpu, pRun);
2473
2474	case KVM_EXIT_X86_WRMSR:
2475	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitWrMsr);
2476	*pfStatefulExit = true;
2477	return nemHCLnxHandleExitWrMsr(pVCpu, pRun);
2478
2479	case KVM_EXIT_HLT:
2480	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_HALT),
2481	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2482	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHalt);
2483	Log5(("Halt/%u\n", pVCpu->idCpu));
2484	return VINF_EM_HALT;
2485
2486	case KVM_EXIT_INTR: /* EINTR */
2487	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_INTERRUPTED),
2488	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2489	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitIntr);
2490	Log5(("Intr/%u\n", pVCpu->idCpu));
2491	return VINF_SUCCESS;
2492
2493	case KVM_EXIT_HYPERCALL:
2494	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitHypercall);
2495	AssertFailed();
2496	break;
2497
2498	case KVM_EXIT_DEBUG:
2499	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitDebug);
2500	AssertFailed();
2501	break;
2502
2503	case KVM_EXIT_SYSTEM_EVENT:
2504	AssertFailed();
2505	break;
2506	case KVM_EXIT_IOAPIC_EOI:
2507	AssertFailed();
2508	break;
2509	case KVM_EXIT_HYPERV:
2510	AssertFailed();
2511	break;
2512
2513	case KVM_EXIT_DIRTY_RING_FULL:
2514	AssertFailed();
2515	break;
2516	case KVM_EXIT_AP_RESET_HOLD:
2517	AssertFailed();
2518	break;
2519	case KVM_EXIT_X86_BUS_LOCK:
2520	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatExitBusLock);
2521	AssertFailed();
2522	break;
2523
2524
2525	case KVM_EXIT_SHUTDOWN:
2526	AssertFailed();
2527	break;
2528
2529	case KVM_EXIT_FAIL_ENTRY:
2530	LogRel(("NEM: KVM_EXIT_FAIL_ENTRY! hardware_entry_failure_reason=%#x cpu=%#x\n",
2531	pRun->fail_entry.hardware_entry_failure_reason, pRun->fail_entry.cpu));
2532	EMHistoryAddExit(pVCpu, EMEXIT_MAKE_FT(EMEXIT_F_KIND_NEM, NEMEXITTYPE_FAILED_ENTRY),
2533	pRun->s.regs.regs.rip + pRun->s.regs.sregs.cs.base, ASMReadTSC());
2534	return VERR_NEM_IPE_1;
2535
2536	case KVM_EXIT_INTERNAL_ERROR:
2537	/* we're counting sub-reasons inside the function. */
2538	return nemR3LnxHandleInternalError(pVCpu, pRun);
2539
2540	/*
2541	* Foreign and unknowns.
2542	*/
2543	case KVM_EXIT_NMI:
2544	AssertLogRelMsgFailedReturn(("KVM_EXIT_NMI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2545	case KVM_EXIT_EPR:
2546	AssertLogRelMsgFailedReturn(("KVM_EXIT_EPR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2547	case KVM_EXIT_WATCHDOG:
2548	AssertLogRelMsgFailedReturn(("KVM_EXIT_WATCHDOG on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2549	case KVM_EXIT_ARM_NISV:
2550	AssertLogRelMsgFailedReturn(("KVM_EXIT_ARM_NISV on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2551	case KVM_EXIT_S390_STSI:
2552	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_STSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2553	case KVM_EXIT_S390_TSCH:
2554	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_TSCH on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2555	case KVM_EXIT_OSI:
2556	AssertLogRelMsgFailedReturn(("KVM_EXIT_OSI on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2557	case KVM_EXIT_PAPR_HCALL:
2558	AssertLogRelMsgFailedReturn(("KVM_EXIT_PAPR_HCALL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2559	case KVM_EXIT_S390_UCONTROL:
2560	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_UCONTROL on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2561	case KVM_EXIT_DCR:
2562	AssertLogRelMsgFailedReturn(("KVM_EXIT_DCR on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2563	case KVM_EXIT_S390_SIEIC:
2564	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_SIEIC on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2565	case KVM_EXIT_S390_RESET:
2566	AssertLogRelMsgFailedReturn(("KVM_EXIT_S390_RESET on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2567	case KVM_EXIT_UNKNOWN:
2568	AssertLogRelMsgFailedReturn(("KVM_EXIT_UNKNOWN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2569	case KVM_EXIT_XEN:
2570	AssertLogRelMsgFailedReturn(("KVM_EXIT_XEN on VCpu #%u at %04x:%RX64!\n", pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2571	default:
2572	AssertLogRelMsgFailedReturn(("Unknown exit reason %u on VCpu #%u at %04x:%RX64!\n", pRun->exit_reason, pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip), VERR_NEM_IPE_1);
2573	}
2574
2575	RT_NOREF(pVM, pVCpu, pRun);
2576	return VERR_NOT_IMPLEMENTED;
2577	}
2578
2579
2580	VBOXSTRICTRC nemR3NativeRunGC(PVM pVM, PVMCPU pVCpu)
2581	{
2582	/*
2583	* Try switch to NEM runloop state.
2584	*/
2585	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED))
2586	{ /* likely */ }
2587	else
2588	{
2589	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2590	LogFlow(("NEM/%u: returning immediately because canceled\n", pVCpu->idCpu));
2591	return VINF_SUCCESS;
2592	}
2593
2594	/*
2595	* The run loop.
2596	*/
2597	struct kvm_run * const pRun = pVCpu->nem.s.pRun;
2598	const bool fSingleStepping = DBGFIsStepping(pVCpu);
2599	VBOXSTRICTRC rcStrict = VINF_SUCCESS;
2600	bool fStatefulExit = false; /* For MMIO and IO exits. */
2601	for (unsigned iLoop = 0;; iLoop++)
2602	{
2603	/*
2604	* Pending interrupts or such? Need to check and deal with this prior
2605	* to the state syncing.
2606	*/
2607	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC \| VMCPU_FF_UPDATE_APIC \| VMCPU_FF_INTERRUPT_PIC
2608	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2609	{
2610	/* Try inject interrupt. */
2611	rcStrict = nemHCLnxHandleInterruptFF(pVM, pVCpu, pRun);
2612	if (rcStrict == VINF_SUCCESS)
2613	{ /* likely */ }
2614	else
2615	{
2616	LogFlow(("NEM/%u: breaking: nemHCLnxHandleInterruptFF -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2617	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2618	break;
2619	}
2620	}
2621
2622	/*
2623	* Do not execute in KVM if the A20 isn't enabled.
2624	*/
2625	if (PGMPhysIsA20Enabled(pVCpu))
2626	{ /* likely */ }
2627	else
2628	{
2629	rcStrict = VINF_EM_RESCHEDULE_REM;
2630	LogFlow(("NEM/%u: breaking: A20 disabled\n", pVCpu->idCpu));
2631	break;
2632	}
2633
2634	/*
2635	* Ensure KVM has the whole state.
2636	*/
2637	if ((pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL) != CPUMCTX_EXTRN_ALL)
2638	{
2639	int rc2 = nemHCLnxExportState(pVM, pVCpu, &pVCpu->cpum.GstCtx, pRun);
2640	AssertRCReturn(rc2, rc2);
2641	}
2642
2643	/*
2644	* Poll timers and run for a bit.
2645	*
2646	* With the VID approach (ring-0 or ring-3) we can specify a timeout here,
2647	* so we take the time of the next timer event and uses that as a deadline.
2648	* The rounding heuristics are "tuned" so that rhel5 (1K timer) will boot fine.
2649	*/
2650	/** @todo See if we cannot optimize this TMTimerPollGIP by only redoing
2651	* the whole polling job when timers have changed... */
2652	uint64_t offDeltaIgnored;
2653	uint64_t const nsNextTimerEvt = TMTimerPollGIP(pVM, pVCpu, &offDeltaIgnored); NOREF(nsNextTimerEvt);
2654	if ( !VM_FF_IS_ANY_SET(pVM, VM_FF_EMT_RENDEZVOUS \| VM_FF_TM_VIRTUAL_SYNC)
2655	&& !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HM_TO_R3_MASK))
2656	{
2657	if (VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM_WAIT, VMCPUSTATE_STARTED_EXEC_NEM))
2658	{
2659	LogFlow(("NEM/%u: Entry @ %04x:%08RX64 IF=%d EFL=%#RX64 SS:RSP=%04x:%08RX64 cr0=%RX64\n",
2660	pVCpu->idCpu, pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip,
2661	!!(pRun->s.regs.regs.rflags & X86_EFL_IF), pRun->s.regs.regs.rflags,
2662	pRun->s.regs.sregs.ss.selector, pRun->s.regs.regs.rsp, pRun->s.regs.sregs.cr0));
2663	TMNotifyStartOfExecution(pVM, pVCpu);
2664
2665	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2666
2667	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED_EXEC_NEM, VMCPUSTATE_STARTED_EXEC_NEM_WAIT);
2668	TMNotifyEndOfExecution(pVM, pVCpu, ASMReadTSC());
2669
2670	#ifdef LOG_ENABLED
2671	if (LogIsFlowEnabled())
2672	{
2673	struct kvm_mp_state MpState = {UINT32_MAX};
2674	ioctl(pVCpu->nem.s.fdVCpu, KVM_GET_MP_STATE, &MpState);
2675	LogFlow(("NEM/%u: Exit @ %04x:%08RX64 IF=%d EFL=%#RX64 CR8=%#x Reason=%#x IrqReady=%d Flags=%#x %#lx\n", pVCpu->idCpu,
2676	pRun->s.regs.sregs.cs.selector, pRun->s.regs.regs.rip, pRun->if_flag,
2677	pRun->s.regs.regs.rflags, pRun->s.regs.sregs.cr8, pRun->exit_reason,
2678	pRun->ready_for_interrupt_injection, pRun->flags, MpState.mp_state));
2679	}
2680	#endif
2681	fStatefulExit = false;
2682	if (RT_LIKELY(rcLnx == 0 \|\| errno == EINTR))
2683	{
2684	/*
2685	* Deal with the exit.
2686	*/
2687	rcStrict = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);
2688	if (rcStrict == VINF_SUCCESS)
2689	{ /* hopefully likely */ }
2690	else
2691	{
2692	LogFlow(("NEM/%u: breaking: nemHCLnxHandleExit -> %Rrc\n", pVCpu->idCpu, VBOXSTRICTRC_VAL(rcStrict) ));
2693	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnStatus);
2694	break;
2695	}
2696	}
2697	else
2698	{
2699	int rc2 = RTErrConvertFromErrno(errno);
2700	AssertLogRelMsgFailedReturn(("KVM_RUN failed: rcLnx=%d errno=%u rc=%Rrc\n", rcLnx, errno, rc2), rc2);
2701	}
2702
2703	/*
2704	* If no relevant FFs are pending, loop.
2705	*/
2706	if ( !VM_FF_IS_ANY_SET( pVM, !fSingleStepping ? VM_FF_HP_R0_PRE_HM_MASK : VM_FF_HP_R0_PRE_HM_STEP_MASK)
2707	&& !VMCPU_FF_IS_ANY_SET(pVCpu, !fSingleStepping ? VMCPU_FF_HP_R0_PRE_HM_MASK : VMCPU_FF_HP_R0_PRE_HM_STEP_MASK) )
2708	{ /* likely */ }
2709	else
2710	{
2711
2712	/** @todo Try handle pending flags, not just return to EM loops. Take care
2713	* not to set important RCs here unless we've handled an exit. */
2714	LogFlow(("NEM/%u: breaking: pending FF (%#x / %#RX64)\n",
2715	pVCpu->idCpu, pVM->fGlobalForcedActions, (uint64_t)pVCpu->fLocalForcedActions));
2716	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPost);
2717	break;
2718	}
2719	}
2720	else
2721	{
2722	LogFlow(("NEM/%u: breaking: canceled %d (pre exec)\n", pVCpu->idCpu, VMCPU_GET_STATE(pVCpu) ));
2723	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnCancel);
2724	break;
2725	}
2726	}
2727	else
2728	{
2729	LogFlow(("NEM/%u: breaking: pending FF (pre exec)\n", pVCpu->idCpu));
2730	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatBreakOnFFPre);
2731	break;
2732	}
2733	} /* the run loop */
2734
2735
2736	/*
2737	* If the last exit was stateful, commit the state we provided before
2738	* returning to the EM loop so we have a consistent state and can safely
2739	* be rescheduled and whatnot. This may require us to make multiple runs
2740	* for larger MMIO and I/O operations. Sigh^3.
2741	*
2742	* Note! There is no 'ing way to reset the kernel side completion callback
2743	* for these stateful i/o exits. Very annoying interface.
2744	*/
2745	/** @todo check how this works with string I/O and string MMIO. */
2746	if (fStatefulExit && RT_SUCCESS(rcStrict))
2747	{
2748	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn);
2749	uint32_t const uOrgExit = pRun->exit_reason;
2750	for (uint32_t i = 0; ; i++)
2751	{
2752	pRun->immediate_exit = 1;
2753	int rcLnx = ioctl(pVCpu->nem.s.fdVCpu, KVM_RUN, 0UL);
2754	Log(("NEM/%u: Flushed stateful exit -> %d/%d exit_reason=%d\n", pVCpu->idCpu, rcLnx, errno, pRun->exit_reason));
2755	if (rcLnx == -1 && errno == EINTR)
2756	{
2757	switch (i)
2758	{
2759	case 0: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn1Loop); break;
2760	case 1: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn2Loops); break;
2761	case 2: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn3Loops); break;
2762	default: STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatFlushExitOnReturn4PlusLoops); break;
2763	}
2764	break;
2765	}
2766	AssertLogRelMsgBreakStmt(rcLnx == 0 && pRun->exit_reason == uOrgExit,
2767	("rcLnx=%d errno=%d exit_reason=%d uOrgExit=%d\n", rcLnx, errno, pRun->exit_reason, uOrgExit),
2768	rcStrict = VERR_NEM_IPE_6);
2769	VBOXSTRICTRC rcStrict2 = nemHCLnxHandleExit(pVM, pVCpu, pRun, &fStatefulExit);
2770	if (rcStrict2 == VINF_SUCCESS \|\| rcStrict2 == rcStrict)
2771	{ /* likely */ }
2772	else if (RT_FAILURE(rcStrict2))
2773	{
2774	rcStrict = rcStrict2;
2775	break;
2776	}
2777	else
2778	{
2779	AssertLogRelMsgBreakStmt(rcStrict == VINF_SUCCESS,
2780	("rcStrict=%Rrc rcStrict2=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict), VBOXSTRICTRC_VAL(rcStrict2)),
2781	rcStrict = VERR_NEM_IPE_7);
2782	rcStrict = rcStrict2;
2783	}
2784	}
2785	pRun->immediate_exit = 0;
2786	}
2787
2788	/*
2789	* If the CPU is running, make sure to stop it before we try sync back the
2790	* state and return to EM. We don't sync back the whole state if we can help it.
2791	*/
2792	if (!VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM))
2793	VMCPU_CMPXCHG_STATE(pVCpu, VMCPUSTATE_STARTED, VMCPUSTATE_STARTED_EXEC_NEM_CANCELED);
2794
2795	if (pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL)
2796	{
2797	/* Try anticipate what we might need. */
2798	uint64_t fImport = CPUMCTX_EXTRN_INHIBIT_INT \| CPUMCTX_EXTRN_INHIBIT_NMI /* Required for processing APIC,PIC,NMI & SMI FFs. */
2799	\| IEM_CPUMCTX_EXTRN_MUST_MASK /?/;
2800	if ( (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
2801	\|\| RT_FAILURE(rcStrict))
2802	fImport = CPUMCTX_EXTRN_ALL;
2803	# ifdef IN_RING0 /* Ring-3 I/O port access optimizations: */
2804	else if ( rcStrict == VINF_IOM_R3_IOPORT_COMMIT_WRITE
2805	\|\| rcStrict == VINF_EM_PENDING_R3_IOPORT_WRITE)
2806	fImport = CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS;
2807	else if (rcStrict == VINF_EM_PENDING_R3_IOPORT_READ)
2808	fImport = CPUMCTX_EXTRN_RAX \| CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS;
2809	# endif
2810	else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC \| VMCPU_FF_INTERRUPT_APIC
2811	\| VMCPU_FF_INTERRUPT_NMI \| VMCPU_FF_INTERRUPT_SMI))
2812	fImport \|= IEM_CPUMCTX_EXTRN_XCPT_MASK;
2813
2814	if (pVCpu->cpum.GstCtx.fExtrn & fImport)
2815	{
2816	int rc2 = nemHCLnxImportState(pVCpu, fImport, &pVCpu->cpum.GstCtx, pRun);
2817	if (RT_SUCCESS(rc2))
2818	pVCpu->cpum.GstCtx.fExtrn &= ~fImport;
2819	else if (RT_SUCCESS(rcStrict))
2820	rcStrict = rc2;
2821	if (!(pVCpu->cpum.GstCtx.fExtrn & CPUMCTX_EXTRN_ALL))
2822	pVCpu->cpum.GstCtx.fExtrn = 0;
2823	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturn);
2824	}
2825	else
2826	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2827	}
2828	else
2829	{
2830	pVCpu->cpum.GstCtx.fExtrn = 0;
2831	STAM_REL_COUNTER_INC(&pVCpu->nem.s.StatImportOnReturnSkipped);
2832	}
2833
2834	LogFlow(("NEM/%u: %04x:%08RX64 efl=%#08RX64 => %Rrc\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip,
2835	pVCpu->cpum.GstCtx.rflags, VBOXSTRICTRC_VAL(rcStrict) ));
2836	return rcStrict;
2837	}
2838
2839
2840	/** @page pg_nem_linux NEM/linux - Native Execution Manager, Linux.
2841	*
2842	* This is using KVM.
2843	*
2844	*/
2845

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source: vbox/trunk/src/VBox/VMM/VMMR3/NEMR3Native-linux.cpp@ 92676

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