PDMDevHlp.cpp@ 64551

Last change on this file since 64551 was 64406, checked in by vboxsync, 8 years ago
PDMPCIDEVREG_DEV_NO_SAME_AS_PREV: Extended the search to previous PDM device instances in order to make it easier to do one PCI function per instance.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 172.5 KB

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1	/* $Id: PDMDevHlp.cpp 64406 2016-10-24 19:25:03Z vboxsync $ */
2	/** @file
3	* PDM - Pluggable Device and Driver Manager, Device Helpers.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23	#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24	#include "PDMInternal.h"
25	#include <VBox/vmm/pdm.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/iom.h>
30	#ifdef VBOX_WITH_REM
31	# include <VBox/vmm/rem.h>
32	#endif
33	#include <VBox/vmm/dbgf.h>
34	#include <VBox/vmm/vmapi.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/uvm.h>
37	#include <VBox/vmm/vmm.h>
38
39	#include <VBox/version.h>
40	#include <VBox/log.h>
41	#include <VBox/err.h>
42	#include <iprt/asm.h>
43	#include <iprt/assert.h>
44	#include <iprt/ctype.h>
45	#include <iprt/string.h>
46	#include <iprt/thread.h>
47
48	#include "dtrace/VBoxVMM.h"
49	#include "PDMInline.h"
50
51
52	/*********************************************************************************************************************************
53	* Defined Constants And Macros *
54	*********************************************************************************************************************************/
55	/** @def PDM_DEVHLP_DEADLOCK_DETECTION
56	* Define this to enable the deadlock detection when accessing physical memory.
57	*/
58	#if /defined(DEBUG_bird) \|\|/ defined(DOXYGEN_RUNNING)
59	# define PDM_DEVHLP_DEADLOCK_DETECTION /*< @todo enable DevHlp deadlock detection! /
60	#endif
61
62
63
64	/**
65	* Wrapper around PDMR3LdrGetSymbolRCLazy.
66	*/
67	DECLINLINE(int) pdmR3DevGetSymbolRCLazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTRCPTR ppvValue)
68	{
69	PVM pVM = pDevIns->Internal.s.pVMR3;
70	if (HMIsEnabled(pVM))
71	{
72	*ppvValue = NIL_RTRCPTR;
73	return VINF_SUCCESS;
74	}
75	return PDMR3LdrGetSymbolRCLazy(pVM,
76	pDevIns->Internal.s.pDevR3->pReg->szRCMod,
77	pDevIns->Internal.s.pDevR3->pszRCSearchPath,
78	pszSymbol, ppvValue);
79	}
80
81
82	/**
83	* Wrapper around PDMR3LdrGetSymbolR0Lazy.
84	*/
85	DECLINLINE(int) pdmR3DevGetSymbolR0Lazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTR0PTR ppvValue)
86	{
87	return PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3,
88	pDevIns->Internal.s.pDevR3->pReg->szR0Mod,
89	pDevIns->Internal.s.pDevR3->pszR0SearchPath,
90	pszSymbol, ppvValue);
91	}
92
93
94	/** @name R3 DevHlp
95	* @{
96	*/
97
98
99	/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegister} */
100	static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
101	PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
102	{
103	PDMDEV_ASSERT_DEVINS(pDevIns);
104	LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p p32_tszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
105	Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc, pszDesc));
106	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
107
108	#if 0 /** @todo needs a real string cache for this */
109	if (pDevIns->iInstance > 0)
110	{
111	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
112	if (pszDesc2)
113	pszDesc = pszDesc2;
114	}
115	#endif
116
117	int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser,
118	pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
119
120	LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
121	return rc;
122	}
123
124
125	/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterRC} */
126	static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
127	const char pszOut, const char pszIn,
128	const char pszOutStr, const char pszInStr, const char *pszDesc)
129	{
130	PDMDEV_ASSERT_DEVINS(pDevIns);
131	PVM pVM = pDevIns->Internal.s.pVMR3;
132	VM_ASSERT_EMT(pVM);
133	LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
134	Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
135
136	/*
137	* Resolve the functions (one of the can be NULL).
138	*/
139	int rc = VINF_SUCCESS;
140	if ( pDevIns->pReg->szRCMod[0]
141	&& (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
142	&& !HMIsEnabled(pVM))
143	{
144	RTRCPTR RCPtrIn = NIL_RTRCPTR;
145	if (pszIn)
146	{
147	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszIn, &RCPtrIn);
148	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szRCMod, pszIn));
149	}
150	RTRCPTR RCPtrOut = NIL_RTRCPTR;
151	if (pszOut && RT_SUCCESS(rc))
152	{
153	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOut, &RCPtrOut);
154	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szRCMod, pszOut));
155	}
156	RTRCPTR RCPtrInStr = NIL_RTRCPTR;
157	if (pszInStr && RT_SUCCESS(rc))
158	{
159	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszInStr, &RCPtrInStr);
160	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szRCMod, pszInStr));
161	}
162	RTRCPTR RCPtrOutStr = NIL_RTRCPTR;
163	if (pszOutStr && RT_SUCCESS(rc))
164	{
165	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOutStr, &RCPtrOutStr);
166	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szRCMod, pszOutStr));
167	}
168
169	if (RT_SUCCESS(rc))
170	{
171	#if 0 /** @todo needs a real string cache for this */
172	if (pDevIns->iInstance > 0)
173	{
174	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
175	if (pszDesc2)
176	pszDesc = pszDesc2;
177	}
178	#endif
179
180	rc = IOMR3IOPortRegisterRC(pVM, pDevIns, Port, cPorts, pvUser, RCPtrOut, RCPtrIn, RCPtrOutStr, RCPtrInStr, pszDesc);
181	}
182	}
183	else if (!HMIsEnabled(pVM))
184	{
185	AssertMsgFailed(("No RC module for this driver!\n"));
186	rc = VERR_INVALID_PARAMETER;
187	}
188
189	LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
190	return rc;
191	}
192
193
194	/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterR0} */
195	static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
196	const char pszOut, const char pszIn,
197	const char pszOutStr, const char pszInStr, const char *pszDesc)
198	{
199	PDMDEV_ASSERT_DEVINS(pDevIns);
200	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
201	LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
202	Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
203
204	/*
205	* Resolve the functions (one of the can be NULL).
206	*/
207	int rc = VINF_SUCCESS;
208	if ( pDevIns->pReg->szR0Mod[0]
209	&& (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
210	{
211	R0PTRTYPE(PFNIOMIOPORTIN) pfnR0PtrIn = 0;
212	if (pszIn)
213	{
214	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszIn, &pfnR0PtrIn);
215	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szR0Mod, pszIn));
216	}
217	R0PTRTYPE(PFNIOMIOPORTOUT) pfnR0PtrOut = 0;
218	if (pszOut && RT_SUCCESS(rc))
219	{
220	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOut, &pfnR0PtrOut);
221	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szR0Mod, pszOut));
222	}
223	R0PTRTYPE(PFNIOMIOPORTINSTRING) pfnR0PtrInStr = 0;
224	if (pszInStr && RT_SUCCESS(rc))
225	{
226	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszInStr, &pfnR0PtrInStr);
227	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szR0Mod, pszInStr));
228	}
229	R0PTRTYPE(PFNIOMIOPORTOUTSTRING) pfnR0PtrOutStr = 0;
230	if (pszOutStr && RT_SUCCESS(rc))
231	{
232	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOutStr, &pfnR0PtrOutStr);
233	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szR0Mod, pszOutStr));
234	}
235
236	if (RT_SUCCESS(rc))
237	{
238	#if 0 /** @todo needs a real string cache for this */
239	if (pDevIns->iInstance > 0)
240	{
241	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
242	if (pszDesc2)
243	pszDesc = pszDesc2;
244	}
245	#endif
246
247	rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc);
248	}
249	}
250	else
251	{
252	AssertMsgFailed(("No R0 module for this driver!\n"));
253	rc = VERR_INVALID_PARAMETER;
254	}
255
256	LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
257	return rc;
258	}
259
260
261	/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortDeregister} */
262	static DECLCALLBACK(int) pdmR3DevHlp_IOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
263	{
264	PDMDEV_ASSERT_DEVINS(pDevIns);
265	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
266	LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: Port=%#x cPorts=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance,
267	Port, cPorts));
268
269	int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts);
270
271	LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
272	return rc;
273	}
274
275
276	/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegister} */
277	static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
278	PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
279	uint32_t fFlags, const char *pszDesc)
280	{
281	PDMDEV_ASSERT_DEVINS(pDevIns);
282	PVM pVM = pDevIns->Internal.s.pVMR3;
283	VM_ASSERT_EMT(pVM);
284	LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p fFlags=%#x pszDesc=%p:{%s}\n",
285	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc, fFlags, pszDesc));
286
287	if (pDevIns->iInstance > 0)
288	{
289	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
290	if (pszDesc2)
291	pszDesc = pszDesc2;
292	}
293
294	int rc = IOMR3MmioRegisterR3(pVM, pDevIns, GCPhysStart, cbRange, pvUser,
295	pfnWrite, pfnRead, pfnFill, fFlags, pszDesc);
296
297	LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
298	return rc;
299	}
300
301
302	/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterRC} */
303	static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
304	const char pszWrite, const char pszRead, const char *pszFill)
305	{
306	PDMDEV_ASSERT_DEVINS(pDevIns);
307	PVM pVM = pDevIns->Internal.s.pVMR3;
308	VM_ASSERT_EMT(pVM);
309	LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
310	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
311
312
313	/*
314	* Resolve the functions.
315	* Not all function have to present, leave it to IOM to enforce this.
316	*/
317	int rc = VINF_SUCCESS;
318	if ( pDevIns->pReg->szRCMod[0]
319	&& (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
320	&& !HMIsEnabled(pVM))
321	{
322	RTRCPTR RCPtrWrite = NIL_RTRCPTR;
323	if (pszWrite)
324	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWrite, &RCPtrWrite);
325
326	RTRCPTR RCPtrRead = NIL_RTRCPTR;
327	int rc2 = VINF_SUCCESS;
328	if (pszRead)
329	rc2 = pdmR3DevGetSymbolRCLazy(pDevIns, pszRead, &RCPtrRead);
330
331	RTRCPTR RCPtrFill = NIL_RTRCPTR;
332	int rc3 = VINF_SUCCESS;
333	if (pszFill)
334	rc3 = pdmR3DevGetSymbolRCLazy(pDevIns, pszFill, &RCPtrFill);
335
336	if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
337	rc = IOMR3MmioRegisterRC(pVM, pDevIns, GCPhysStart, cbRange, pvUser, RCPtrWrite, RCPtrRead, RCPtrFill);
338	else
339	{
340	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szRCMod, pszWrite));
341	AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szRCMod, pszRead));
342	AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szRCMod, pszFill));
343	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
344	rc = rc2;
345	if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
346	rc = rc3;
347	}
348	}
349	else if (!HMIsEnabled(pVM))
350	{
351	AssertMsgFailed(("No RC module for this driver!\n"));
352	rc = VERR_INVALID_PARAMETER;
353	}
354
355	LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
356	return rc;
357	}
358
359	/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterR0} */
360	static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
361	const char pszWrite, const char pszRead, const char *pszFill)
362	{
363	PDMDEV_ASSERT_DEVINS(pDevIns);
364	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
365	LogFlow(("pdmR3DevHlp_MMIORegisterHC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
366	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
367
368	/*
369	* Resolve the functions.
370	* Not all function have to present, leave it to IOM to enforce this.
371	*/
372	int rc = VINF_SUCCESS;
373	if ( pDevIns->pReg->szR0Mod[0]
374	&& (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
375	{
376	R0PTRTYPE(PFNIOMMMIOWRITE) pfnR0PtrWrite = 0;
377	if (pszWrite)
378	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWrite, &pfnR0PtrWrite);
379	R0PTRTYPE(PFNIOMMMIOREAD) pfnR0PtrRead = 0;
380	int rc2 = VINF_SUCCESS;
381	if (pszRead)
382	rc2 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszRead, &pfnR0PtrRead);
383	R0PTRTYPE(PFNIOMMMIOFILL) pfnR0PtrFill = 0;
384	int rc3 = VINF_SUCCESS;
385	if (pszFill)
386	rc3 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFill, &pfnR0PtrFill);
387	if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
388	rc = IOMR3MmioRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser,
389	pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill);
390	else
391	{
392	AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szR0Mod, pszWrite));
393	AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szR0Mod, pszRead));
394	AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szR0Mod, pszFill));
395	if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
396	rc = rc2;
397	if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
398	rc = rc3;
399	}
400	}
401	else
402	{
403	AssertMsgFailed(("No R0 module for this driver!\n"));
404	rc = VERR_INVALID_PARAMETER;
405	}
406
407	LogFlow(("pdmR3DevHlp_MMIORegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
408	return rc;
409	}
410
411
412	/** @interface_method_impl{PDMDEVHLPR3,pfnMMIODeregister} */
413	static DECLCALLBACK(int) pdmR3DevHlp_MMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange)
414	{
415	PDMDEV_ASSERT_DEVINS(pDevIns);
416	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
417	LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp\n",
418	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange));
419
420	int rc = IOMR3MmioDeregister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange);
421
422	LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
423	return rc;
424	}
425
426
427	/**
428	* @copydoc PDMDEVHLPR3::pfnMMIO2Register
429	*/
430	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
431	uint32_t fFlags, void *ppv, const char pszDesc)
432	{
433	PDMDEV_ASSERT_DEVINS(pDevIns);
434	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
435	LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: pPciDev=%p (%#x) iRegion=%#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n",
436	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion,
437	cb, fFlags, ppv, pszDesc, pszDesc));
438	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
439
440	/** @todo PGMR3PhysMMIO2Register mangles the description, move it here and
441	* use a real string cache. */
442	int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion,
443	cb, fFlags, ppv, pszDesc);
444
445	LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
446	return rc;
447	}
448
449
450	/**
451	* @interface_method_impl{PDMDEVHLPR3,pfnMMIOExPreRegister}
452	*/
453	static DECLCALLBACK(int)
454	pdmR3DevHlp_MMIOExPreRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion, uint32_t fFlags,
455	const char *pszDesc,
456	RTHCPTR pvUser, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
457	RTR0PTR pvUserR0, const char pszWriteR0, const char pszReadR0, const char *pszFillR0,
458	RTRCPTR pvUserRC, const char pszWriteRC, const char pszReadRC, const char *pszFillRC)
459	{
460	PDMDEV_ASSERT_DEVINS(pDevIns);
461	PVM pVM = pDevIns->Internal.s.pVMR3;
462	VM_ASSERT_EMT(pVM);
463	LogFlow(("pdmR3DevHlp_MMIOExPreRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x cbRegion=%#RGp fFlags=%RX32 pszDesc=%p:{%s}\n"
464	" pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p\n"
465	" pvUserR0=%p pszWriteR0=%s pszReadR0=%s pszFillR0=%s\n"
466	" pvUserRC=%p pszWriteRC=%s pszReadRC=%s pszFillRC=%s\n",
467	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, cbRegion,
468	fFlags, pszDesc, pszDesc,
469	pvUser, pfnWrite, pfnRead, pfnFill,
470	pvUserR0, pszWriteR0, pszReadR0, pszFillR0,
471	pvUserRC, pszWriteRC, pszReadRC, pszFillRC));
472	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
473
474	/*
475	* Resolve the functions.
476	*/
477	AssertLogRelReturn( (!pszWriteR0 && !pszReadR0 && !pszFillR0)
478	\|\| (pDevIns->pReg->szR0Mod[0] && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)),
479	VERR_INVALID_PARAMETER);
480	AssertLogRelReturn( (!pszWriteRC && !pszReadRC && !pszFillRC)
481	\|\| (pDevIns->pReg->szRCMod[0] && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)),
482	VERR_INVALID_PARAMETER);
483
484	/* Ring-0 */
485	int rc;
486	R0PTRTYPE(PFNIOMMMIOWRITE) pfnWriteR0 = 0;
487	if (pszWriteR0)
488	{
489	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWriteR0, &pfnWriteR0);
490	AssertLogRelMsgRCReturn(rc, ("pszWriteR0=%s rc=%Rrc\n", pszWriteR0, rc), rc);
491	}
492
493	R0PTRTYPE(PFNIOMMMIOREAD) pfnReadR0 = 0;
494	if (pszReadR0)
495	{
496	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszReadR0, &pfnReadR0);
497	AssertLogRelMsgRCReturn(rc, ("pszReadR0=%s rc=%Rrc\n", pszReadR0, rc), rc);
498	}
499	R0PTRTYPE(PFNIOMMMIOFILL) pfnFillR0 = 0;
500	if (pszFillR0)
501	{
502	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFillR0, &pfnFillR0);
503	AssertLogRelMsgRCReturn(rc, ("pszFillR0=%s rc=%Rrc\n", pszFillR0, rc), rc);
504	}
505
506	/* Raw-mode */
507	rc = VINF_SUCCESS;
508	RCPTRTYPE(PFNIOMMMIOWRITE) pfnWriteRC = 0;
509	if (pszWriteRC)
510	{
511	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWriteRC, &pfnWriteRC);
512	AssertLogRelMsgRCReturn(rc, ("pszWriteRC=%s rc=%Rrc\n", pszWriteRC, rc), rc);
513	}
514
515	RCPTRTYPE(PFNIOMMMIOREAD) pfnReadRC = 0;
516	if (pszReadRC)
517	{
518	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszReadRC, &pfnReadRC);
519	AssertLogRelMsgRCReturn(rc, ("pszReadRC=%s rc=%Rrc\n", pszReadRC, rc), rc);
520	}
521	RCPTRTYPE(PFNIOMMMIOFILL) pfnFillRC = 0;
522	if (pszFillRC)
523	{
524	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszFillRC, &pfnFillRC);
525	AssertLogRelMsgRCReturn(rc, ("pszFillRC=%s rc=%Rrc\n", pszFillRC, rc), rc);
526	}
527
528	/*
529	* Call IOM to make the registration.
530	*/
531	rc = IOMR3MmioExPreRegister(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, cbRegion, fFlags, pszDesc,
532	pvUser, pfnWrite, pfnRead, pfnFill,
533	pvUserR0, pfnWriteR0, pfnReadR0, pfnFillR0,
534	pvUserRC, pfnWriteRC, pfnReadRC, pfnFillRC);
535
536	LogFlow(("pdmR3DevHlp_MMIOExPreRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
537	return rc;
538	}
539
540
541	/**
542	* @copydoc PDMDEVHLPR3::pfnMMIOExDeregister
543	*/
544	static DECLCALLBACK(int) pdmR3DevHlp_MMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion)
545	{
546	PDMDEV_ASSERT_DEVINS(pDevIns);
547	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
548	LogFlow(("pdmR3DevHlp_MMIOExDeregister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x\n",
549	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion));
550
551	AssertReturn(iRegion <= UINT8_MAX \|\| iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
552	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
553
554	int rc = PGMR3PhysMMIOExDeregister(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion);
555
556	LogFlow(("pdmR3DevHlp_MMIOExDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
557	return rc;
558	}
559
560
561	/**
562	* @copydoc PDMDEVHLPR3::pfnMMIOExMap
563	*/
564	static DECLCALLBACK(int) pdmR3DevHlp_MMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
565	{
566	PDMDEV_ASSERT_DEVINS(pDevIns);
567	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
568	LogFlow(("pdmR3DevHlp_MMIOExMap: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x GCPhys=%#RGp\n",
569	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, GCPhys));
570	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
571
572	int rc = PGMR3PhysMMIOExMap(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, GCPhys);
573
574	LogFlow(("pdmR3DevHlp_MMIOExMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
575	return rc;
576	}
577
578
579	/**
580	* @copydoc PDMDEVHLPR3::pfnMMIOExUnmap
581	*/
582	static DECLCALLBACK(int) pdmR3DevHlp_MMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
583	{
584	PDMDEV_ASSERT_DEVINS(pDevIns);
585	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
586	LogFlow(("pdmR3DevHlp_MMIOExUnmap: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x GCPhys=%#RGp\n",
587	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, GCPhys));
588	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
589
590	int rc = PGMR3PhysMMIOExUnmap(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, GCPhys);
591
592	LogFlow(("pdmR3DevHlp_MMIOExUnmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
593	return rc;
594	}
595
596
597	/**
598	* @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
599	*/
600	static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
601	RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr)
602	{
603	PDMDEV_ASSERT_DEVINS(pDevIns);
604	PVM pVM = pDevIns->Internal.s.pVMR3;
605	VM_ASSERT_EMT(pVM);
606	LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n",
607	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, off, cb, pszDesc, pszDesc, pRCPtr));
608	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
609
610	if (pDevIns->iInstance > 0)
611	{
612	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
613	if (pszDesc2)
614	pszDesc = pszDesc2;
615	}
616
617	int rc = MMR3HyperMapMMIO2(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, off, cb, pszDesc, pRCPtr);
618
619	LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc pRCPtr=%RRv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, pRCPtr));
620	return rc;
621	}
622
623
624	/**
625	* @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
626	*/
627	static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
628	RTGCPHYS cb,const char *pszDesc, PRTR0PTR pR0Ptr)
629	{
630	PDMDEV_ASSERT_DEVINS(pDevIns);
631	PVM pVM = pDevIns->Internal.s.pVMR3;
632	VM_ASSERT_EMT(pVM);
633	LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n",
634	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr));
635	AssertReturn(!pPciDev \|\| pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
636
637	if (pDevIns->iInstance > 0)
638	{
639	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
640	if (pszDesc2)
641	pszDesc = pszDesc2;
642	}
643
644	int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, off, cb, pszDesc, pR0Ptr);
645
646	LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc pR0Ptr=%RHv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, pR0Ptr));
647	return rc;
648	}
649
650
651	/** @interface_method_impl{PDMDEVHLPR3,pfnROMRegister} */
652	static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
653	const void pvBinary, uint32_t cbBinary, uint32_t fFlags, const char pszDesc)
654	{
655	PDMDEV_ASSERT_DEVINS(pDevIns);
656	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
657	LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvBinary=%p cbBinary=%#x fFlags=%#RX32 pszDesc=%p:{%s}\n",
658	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc, pszDesc));
659
660	/** @todo can we mangle pszDesc? */
661	int rc = PGMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
662
663	LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
664	return rc;
665	}
666
667
668	/** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */
669	static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
670	{
671	PDMDEV_ASSERT_DEVINS(pDevIns);
672	LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",
673	pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));
674
675	int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);
676
677	LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
678	return rc;
679	}
680
681
682	/** @interface_method_impl{PDMDEVHLPR3,pfnSSMRegister} */
683	static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
684	PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
685	PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
686	PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
687	{
688	PDMDEV_ASSERT_DEVINS(pDevIns);
689	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
690	LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: uVersion=%#x cbGuess=%#x pszBefore=%p:{%s}\n"
691	" pfnLivePrep=%p pfnLiveExec=%p pfnLiveVote=%p pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pszLoadPrep=%p pfnLoadExec=%p pfnLoadDone=%p\n",
692	pDevIns->pReg->szName, pDevIns->iInstance, uVersion, cbGuess, pszBefore, pszBefore,
693	pfnLivePrep, pfnLiveExec, pfnLiveVote,
694	pfnSavePrep, pfnSaveExec, pfnSaveDone,
695	pfnLoadPrep, pfnLoadExec, pfnLoadDone));
696
697	int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance,
698	uVersion, cbGuess, pszBefore,
699	pfnLivePrep, pfnLiveExec, pfnLiveVote,
700	pfnSavePrep, pfnSaveExec, pfnSaveDone,
701	pfnLoadPrep, pfnLoadExec, pfnLoadDone);
702
703	LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
704	return rc;
705	}
706
707
708	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimerCreate} */
709	static DECLCALLBACK(int) pdmR3DevHlp_TMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void pvUser, uint32_t fFlags, const char pszDesc, PPTMTIMERR3 ppTimer)
710	{
711	PDMDEV_ASSERT_DEVINS(pDevIns);
712	PVM pVM = pDevIns->Internal.s.pVMR3;
713	VM_ASSERT_EMT(pVM);
714	LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pvUser=%p fFlags=%#x pszDesc=%p:{%s} ppTimer=%p\n",
715	pDevIns->pReg->szName, pDevIns->iInstance, enmClock, pfnCallback, pvUser, fFlags, pszDesc, pszDesc, ppTimer));
716
717	if (pDevIns->iInstance > 0) /** @todo use a string cache here later. */
718	{
719	char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
720	if (pszDesc2)
721	pszDesc = pszDesc2;
722	}
723
724	int rc = TMR3TimerCreateDevice(pVM, pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
725
726	LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
727	return rc;
728	}
729
730
731	/** @interface_method_impl{PDMDEVHLPR3,pfnTMUtcNow} */
732	static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_TMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
733	{
734	PDMDEV_ASSERT_DEVINS(pDevIns);
735	LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: pTime=%p\n",
736	pDevIns->pReg->szName, pDevIns->iInstance, pTime));
737
738	pTime = TMR3UtcNow(pDevIns->Internal.s.pVMR3, pTime);
739
740	LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));
741	return pTime;
742	}
743
744
745	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGet} */
746	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
747	{
748	PDMDEV_ASSERT_DEVINS(pDevIns);
749	LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d\n",
750	pDevIns->pReg->szName, pDevIns->iInstance));
751
752	uint64_t u64Time = TMVirtualSyncGet(pDevIns->Internal.s.pVMR3);
753
754	LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Time));
755	return u64Time;
756	}
757
758
759	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetFreq} */
760	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
761	{
762	PDMDEV_ASSERT_DEVINS(pDevIns);
763	LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d\n",
764	pDevIns->pReg->szName, pDevIns->iInstance));
765
766	uint64_t u64Freq = TMVirtualGetFreq(pDevIns->Internal.s.pVMR3);
767
768	LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Freq));
769	return u64Freq;
770	}
771
772
773	/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetNano} */
774	static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
775	{
776	PDMDEV_ASSERT_DEVINS(pDevIns);
777	LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d\n",
778	pDevIns->pReg->szName, pDevIns->iInstance));
779
780	uint64_t u64Time = TMVirtualGet(pDevIns->Internal.s.pVMR3);
781	uint64_t u64Nano = TMVirtualToNano(pDevIns->Internal.s.pVMR3, u64Time);
782
783	LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Nano));
784	return u64Nano;
785	}
786
787
788	/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
789	static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_GetSupDrvSession(PPDMDEVINS pDevIns)
790	{
791	PDMDEV_ASSERT_DEVINS(pDevIns);
792	LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d\n",
793	pDevIns->pReg->szName, pDevIns->iInstance));
794
795	PSUPDRVSESSION pSession = pDevIns->Internal.s.pVMR3->pSession;
796
797	LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d: returns %#p\n", pDevIns->pReg->szName, pDevIns->iInstance, pSession));
798	return pSession;
799	}
800
801
802	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */
803	static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
804	{
805	PDMDEV_ASSERT_DEVINS(pDevIns);
806	PVM pVM = pDevIns->Internal.s.pVMR3;
807	LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
808	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
809
810	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
811	if (!VM_IS_EMT(pVM))
812	{
813	char szNames[128];
814	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
815	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
816	}
817	#endif
818
819	VBOXSTRICTRC rcStrict;
820	if (VM_IS_EMT(pVM))
821	rcStrict = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
822	else
823	rcStrict = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
824	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
825
826	Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
827	return VBOXSTRICTRC_VAL(rcStrict);
828	}
829
830
831	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */
832	static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
833	{
834	PDMDEV_ASSERT_DEVINS(pDevIns);
835	PVM pVM = pDevIns->Internal.s.pVMR3;
836	LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
837	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
838
839	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
840	if (!VM_IS_EMT(pVM))
841	{
842	char szNames[128];
843	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
844	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
845	}
846	#endif
847
848	VBOXSTRICTRC rcStrict;
849	if (VM_IS_EMT(pVM))
850	rcStrict = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
851	else
852	rcStrict = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
853	AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
854
855	Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
856	return VBOXSTRICTRC_VAL(rcStrict);
857	}
858
859
860	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */
861	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
862	{
863	PDMDEV_ASSERT_DEVINS(pDevIns);
864	PVM pVM = pDevIns->Internal.s.pVMR3;
865	LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
866	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
867	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
868
869	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
870	if (!VM_IS_EMT(pVM))
871	{
872	char szNames[128];
873	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
874	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
875	}
876	#endif
877
878	int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock);
879
880	Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
881	return rc;
882	}
883
884
885	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */
886	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
887	{
888	PDMDEV_ASSERT_DEVINS(pDevIns);
889	PVM pVM = pDevIns->Internal.s.pVMR3;
890	LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
891	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
892	AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
893
894	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
895	if (!VM_IS_EMT(pVM))
896	{
897	char szNames[128];
898	uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
899	AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
900	}
901	#endif
902
903	int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock);
904
905	Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
906	return rc;
907	}
908
909
910	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */
911	static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
912	{
913	PDMDEV_ASSERT_DEVINS(pDevIns);
914	PVM pVM = pDevIns->Internal.s.pVMR3;
915	LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n",
916	pDevIns->pReg->szName, pDevIns->iInstance, pLock));
917
918	PGMPhysReleasePageMappingLock(pVM, pLock);
919
920	Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
921	}
922
923
924	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */
925	static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
926	{
927	PDMDEV_ASSERT_DEVINS(pDevIns);
928	PVM pVM = pDevIns->Internal.s.pVMR3;
929	VM_ASSERT_EMT(pVM);
930	LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n",
931	pDevIns->pReg->szName, pDevIns->iInstance, pvDst, GCVirtSrc, cb));
932
933	PVMCPU pVCpu = VMMGetCpu(pVM);
934	if (!pVCpu)
935	return VERR_ACCESS_DENIED;
936	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
937	/** @todo SMP. */
938	#endif
939
940	int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb);
941
942	LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
943
944	return rc;
945	}
946
947
948	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */
949	static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
950	{
951	PDMDEV_ASSERT_DEVINS(pDevIns);
952	PVM pVM = pDevIns->Internal.s.pVMR3;
953	VM_ASSERT_EMT(pVM);
954	LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n",
955	pDevIns->pReg->szName, pDevIns->iInstance, GCVirtDst, pvSrc, cb));
956
957	PVMCPU pVCpu = VMMGetCpu(pVM);
958	if (!pVCpu)
959	return VERR_ACCESS_DENIED;
960	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
961	/** @todo SMP. */
962	#endif
963
964	int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb);
965
966	LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
967
968	return rc;
969	}
970
971
972	/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */
973	static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
974	{
975	PDMDEV_ASSERT_DEVINS(pDevIns);
976	PVM pVM = pDevIns->Internal.s.pVMR3;
977	VM_ASSERT_EMT(pVM);
978	LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n",
979	pDevIns->pReg->szName, pDevIns->iInstance, GCPtr, pGCPhys));
980
981	PVMCPU pVCpu = VMMGetCpu(pVM);
982	if (!pVCpu)
983	return VERR_ACCESS_DENIED;
984	#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
985	/** @todo SMP. */
986	#endif
987
988	int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys);
989
990	LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc pGCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, pGCPhys));
991
992	return rc;
993	}
994
995
996	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */
997	static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
998	{
999	PDMDEV_ASSERT_DEVINS(pDevIns);
1000	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1001
1002	void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1003
1004	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1005	return pv;
1006	}
1007
1008
1009	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */
1010	static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
1011	{
1012	PDMDEV_ASSERT_DEVINS(pDevIns);
1013	LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1014
1015	void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1016
1017	LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1018	return pv;
1019	}
1020
1021
1022	/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */
1023	static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv)
1024	{
1025	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1026	LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1027
1028	MMR3HeapFree(pv);
1029
1030	LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1031	}
1032
1033
1034	/** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */
1035	static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns)
1036	{
1037	PDMDEV_ASSERT_DEVINS(pDevIns);
1038
1039	VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
1040
1041	LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pReg->szName, pDevIns->iInstance,
1042	enmVMState, VMR3GetStateName(enmVMState)));
1043	return enmVMState;
1044	}
1045
1046
1047	/** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */
1048	static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
1049	{
1050	PDMDEV_ASSERT_DEVINS(pDevIns);
1051
1052	bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3);
1053
1054	LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance,
1055	fRc));
1056	return fRc;
1057	}
1058
1059
1060	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetError} */
1061	static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
1062	{
1063	PDMDEV_ASSERT_DEVINS(pDevIns);
1064	va_list args;
1065	va_start(args, pszFormat);
1066	int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
1067	va_end(args);
1068	return rc;
1069	}
1070
1071
1072	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */
1073	static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1074	{
1075	PDMDEV_ASSERT_DEVINS(pDevIns);
1076	int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1077	return rc;
1078	}
1079
1080
1081	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeError} */
1082	static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char pszErrorId, const char pszFormat, ...)
1083	{
1084	PDMDEV_ASSERT_DEVINS(pDevIns);
1085	va_list args;
1086	va_start(args, pszFormat);
1087	int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args);
1088	va_end(args);
1089	return rc;
1090	}
1091
1092
1093	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */
1094	static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char pszErrorId, const char pszFormat, va_list va)
1095	{
1096	PDMDEV_ASSERT_DEVINS(pDevIns);
1097	int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va);
1098	return rc;
1099	}
1100
1101
1102	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */
1103	static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction, const char *pszFormat, va_list args)
1104	{
1105	PDMDEV_ASSERT_DEVINS(pDevIns);
1106	#ifdef LOG_ENABLED
1107	va_list va2;
1108	va_copy(va2, args);
1109	LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",
1110	pDevIns->pReg->szName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));
1111	va_end(va2);
1112	#endif
1113
1114	PVM pVM = pDevIns->Internal.s.pVMR3;
1115	VM_ASSERT_EMT(pVM);
1116	int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);
1117	if (rc == VERR_DBGF_NOT_ATTACHED)
1118	rc = VINF_SUCCESS;
1119
1120	LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1121	return rc;
1122	}
1123
1124
1125	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */
1126	static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char pszName, const char pszDesc, PFNDBGFHANDLERDEV pfnHandler)
1127	{
1128	PDMDEV_ASSERT_DEVINS(pDevIns);
1129	LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1130	pDevIns->pReg->szName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1131
1132	PVM pVM = pDevIns->Internal.s.pVMR3;
1133	VM_ASSERT_EMT(pVM);
1134	int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1135
1136	LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1137	return rc;
1138	}
1139
1140
1141	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegRegister} */
1142	static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
1143	{
1144	PDMDEV_ASSERT_DEVINS(pDevIns);
1145	LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: paRegisters=%p\n",
1146	pDevIns->pReg->szName, pDevIns->iInstance, paRegisters));
1147
1148	PVM pVM = pDevIns->Internal.s.pVMR3;
1149	VM_ASSERT_EMT(pVM);
1150	int rc = DBGFR3RegRegisterDevice(pVM, paRegisters, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance);
1151
1152	LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1153	return rc;
1154	}
1155
1156
1157	/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFTraceBuf} */
1158	static DECLCALLBACK(RTTRACEBUF) pdmR3DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1159	{
1160	PDMDEV_ASSERT_DEVINS(pDevIns);
1161	RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR3->hTraceBufR3;
1162	LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, hTraceBuf));
1163	return hTraceBuf;
1164	}
1165
1166
1167	/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */
1168	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void pvSample, STAMTYPE enmType, const char pszName,
1169	STAMUNIT enmUnit, const char *pszDesc)
1170	{
1171	PDMDEV_ASSERT_DEVINS(pDevIns);
1172	PVM pVM = pDevIns->Internal.s.pVMR3;
1173	VM_ASSERT_EMT(pVM);
1174
1175	STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc);
1176	RT_NOREF_PV(pVM); RT_NOREF6(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
1177	}
1178
1179
1180
1181	/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterF} */
1182	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1183	STAMUNIT enmUnit, const char pszDesc, const char pszName, ...)
1184	{
1185	PDMDEV_ASSERT_DEVINS(pDevIns);
1186	PVM pVM = pDevIns->Internal.s.pVMR3;
1187	VM_ASSERT_EMT(pVM);
1188
1189	va_list args;
1190	va_start(args, pszName);
1191	int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1192	va_end(args);
1193	AssertRC(rc);
1194
1195	NOREF(pVM);
1196	}
1197
1198
1199	/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */
1200	static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1201	STAMUNIT enmUnit, const char pszDesc, const char pszName, va_list args)
1202	{
1203	PDMDEV_ASSERT_DEVINS(pDevIns);
1204	PVM pVM = pDevIns->Internal.s.pVMR3;
1205	VM_ASSERT_EMT(pVM);
1206
1207	int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1208	AssertRC(rc);
1209
1210	NOREF(pVM);
1211	}
1212
1213
1214	/**
1215	* @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister}
1216	*/
1217	static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t idxDevCfg, uint32_t fFlags,
1218	uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
1219	{
1220	PDMDEV_ASSERT_DEVINS(pDevIns);
1221	PVM pVM = pDevIns->Internal.s.pVMR3;
1222	VM_ASSERT_EMT(pVM);
1223	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Rhxs} idxDevCfg=%d fFlags=%#x uPciDevNo=%#x uPciFunNo=%#x pszName=%p:{%s}\n",
1224	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->abConfig, idxDevCfg, fFlags, uPciDevNo, uPciFunNo, pszName, pszName ? pszName : ""));
1225
1226	/*
1227	* Validate input.
1228	*/
1229	AssertLogRelMsgReturn(RT_VALID_PTR(pPciDev),
1230	("'%s'/%d: Invalid pPciDev value: %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1231	VERR_INVALID_POINTER);
1232	AssertLogRelMsgReturn(PDMPciDevGetVendorId(pPciDev),
1233	("'%s'/%d: Vendor ID is not set!\n", pDevIns->pReg->szName, pDevIns->iInstance),
1234	VERR_INVALID_POINTER);
1235	AssertLogRelMsgReturn(idxDevCfg < 256 \|\| idxDevCfg == PDMPCIDEVREG_CFG_NEXT,
1236	("'%s'/%d: Invalid config selector: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1237	VERR_OUT_OF_RANGE);
1238	AssertLogRelMsgReturn( uPciDevNo < 32
1239	\|\| uPciDevNo == PDMPCIDEVREG_DEV_NO_FIRST_UNUSED
1240	\|\| uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV,
1241	("'%s'/%d: Invalid PCI device number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciDevNo),
1242	VERR_INVALID_PARAMETER);
1243	AssertLogRelMsgReturn( uPciFunNo < 8
1244	\|\| uPciFunNo == PDMPCIDEVREG_FUN_NO_FIRST_UNUSED,
1245	("'%s'/%d: Invalid PCI funcion number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciFunNo),
1246	VERR_INVALID_PARAMETER);
1247	AssertLogRelMsgReturn(!(fFlags & ~PDMPCIDEVREG_F_VALID_MASK),
1248	("'%s'/%d: Invalid flags: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, fFlags),
1249	VERR_INVALID_FLAGS);
1250	if (!pszName)
1251	pszName = pDevIns->pReg->szName;
1252	AssertLogRelReturn(RT_VALID_PTR(pszName), VERR_INVALID_POINTER);
1253
1254	/*
1255	* Find the last(/previous) registered PCI device (for linking and more),
1256	* checking for duplicate registration attempts while doing so.
1257	*/
1258	uint32_t idxDevCfgNext = 0;
1259	PPDMPCIDEV pPrevPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1260	while (pPrevPciDev)
1261	{
1262	AssertLogRelMsgReturn(pPrevPciDev != pPciDev,
1263	("'%s'/%d attempted to register the same PCI device (%p) twice\n",
1264	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1265	VERR_DUPLICATE);
1266	AssertLogRelMsgReturn(pPrevPciDev->Int.s.idxDevCfg != idxDevCfg,
1267	("'%s'/%d attempted to use the same device config index (%u) twice\n",
1268	pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1269	VERR_ALREADY_LOADED);
1270	if (pPrevPciDev->Int.s.idxDevCfg >= idxDevCfgNext)
1271	idxDevCfgNext = pPrevPciDev->Int.s.idxDevCfg + 1;
1272
1273	if (!pPrevPciDev->Int.s.pNextR3)
1274	break;
1275	pPrevPciDev = pPrevPciDev->Int.s.pNextR3;
1276	}
1277
1278	/*
1279	* Resolve the PCI configuration node for the device. The default (zero'th)
1280	* is the same as the PDM device, the rest are "PciCfg1..255" CFGM sub-nodes.
1281	*/
1282	if (idxDevCfg == PDMPCIDEVREG_CFG_NEXT)
1283	{
1284	idxDevCfg = idxDevCfgNext;
1285	AssertLogRelMsgReturn(idxDevCfg < 256, ("'%s'/%d: PDMPCIDEVREG_IDX_DEV_CFG_NEXT ran out of valid indexes (ends at 255)\n",
1286	pDevIns->pReg->szName, pDevIns->iInstance),
1287	VERR_OUT_OF_RANGE);
1288	}
1289
1290	PCFGMNODE pCfg = pDevIns->Internal.s.pCfgHandle;
1291	if (idxDevCfg != 0)
1292	pCfg = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "PciCfg%u", idxDevCfg);
1293
1294	/*
1295	* We resolve PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, the PCI bus handles
1296	* PDMPCIDEVREG_DEV_NO_FIRST_UNUSED and PDMPCIDEVREG_FUN_NO_FIRST_UNUSED.
1297	*/
1298	uint8_t const uPciDevNoRaw = uPciDevNo;
1299	if (uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV)
1300	{
1301	if (pPrevPciDev)
1302	uPciDevNo = pPrevPciDev->uDevFn >> 3;
1303	else
1304	{
1305	/* Look for PCI device registered with an earlier device instance so we can more
1306	easily have multiple functions spanning multiple PDM device instances. */
1307	PPDMPCIDEV pOtherPciDev = NULL;
1308	PPDMDEVINS pPrevIns = pDevIns->Internal.s.pDevR3->pInstances;
1309	while (pPrevIns != pDevIns && pPrevIns)
1310	{
1311	pOtherPciDev = pPrevIns->Internal.s.pHeadPciDevR3;
1312	pPrevIns = pPrevIns->Internal.s.pNextR3;
1313	}
1314	Assert(pPrevIns == pDevIns);
1315	AssertLogRelMsgReturn(pOtherPciDev,
1316	("'%s'/%d: Can't use PDMPCIDEVREG_DEV_NO_SAME_AS_PREV without a previously registered PCI device by the same or earlier PDM device instance!\n",
1317	pDevIns->pReg->szName, pDevIns->iInstance),
1318	VERR_WRONG_ORDER);
1319
1320	while (pOtherPciDev->Int.s.pNextR3)
1321	pOtherPciDev = pOtherPciDev->Int.s.pNextR3;
1322	uPciDevNo = pOtherPciDev->uDevFn >> 3;
1323	}
1324	}
1325
1326	/*
1327	* Choose the PCI bus for the device.
1328	*
1329	* This is simple. If the device was configured for a particular bus, the PCIBusNo
1330	* configuration value will be set. If not the default bus is 0.
1331	*/
1332	/** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIBusNo, uint8_t, 0, 7, 0}
1333	* Selects the PCI bus number of a device.
1334	*/
1335	uint8_t u8Bus;
1336	int rc = CFGMR3QueryU8Def(pCfg, "PCIBusNo", &u8Bus, 0);
1337	AssertLogRelMsgRCReturn(rc, ("Configuration error: PCIBusNo query failed with rc=%Rrc (%s/%d)\n",
1338	rc, pDevIns->pReg->szName, pDevIns->iInstance), rc);
1339	AssertLogRelMsgReturn(u8Bus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
1340	("Configuration error: PCIBusNo=%d, max is %d. (%s/%d)\n", u8Bus,
1341	RT_ELEMENTS(pVM->pdm.s.aPciBuses), pDevIns->pReg->szName, pDevIns->iInstance),
1342	VERR_PDM_NO_PCI_BUS);
1343	PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3 = &pVM->pdm.s.aPciBuses[u8Bus];
1344	if (pBus->pDevInsR3)
1345	{
1346	/*
1347	* Check the configuration for PCI device and function assignment.
1348	*/
1349	/** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIDeviceNo, uint8_t, 0, 31}
1350	* Overrides the default PCI device number of a device.
1351	*/
1352	uint8_t uCfgDevice;
1353	rc = CFGMR3QueryU8(pCfg, "PCIDeviceNo", &uCfgDevice);
1354	if (RT_SUCCESS(rc))
1355	{
1356	AssertMsgReturn(uCfgDevice <= 31,
1357	("Configuration error: PCIDeviceNo=%d, max is 31. (%s/%d/%d)\n",
1358	uCfgDevice, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1359	VERR_PDM_BAD_PCI_CONFIG);
1360	uPciDevNo = uCfgDevice;
1361	}
1362	else
1363	AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT,
1364	("Configuration error: PCIDeviceNo query failed with rc=%Rrc (%s/%d/%d)\n",
1365	rc, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1366	rc);
1367
1368	/** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIFunctionNo, uint8_t, 0, 7}
1369	* Overrides the default PCI function number of a device.
1370	*/
1371	uint8_t uCfgFunction;
1372	rc = CFGMR3QueryU8(pCfg, "PCIFunctionNo", &uCfgFunction);
1373	if (RT_SUCCESS(rc))
1374	{
1375	AssertMsgReturn(uCfgFunction <= 7,
1376	("Configuration error: PCIFunctionNo=%#x, max is 7. (%s/%d/%d)\n",
1377	uCfgFunction, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1378	VERR_PDM_BAD_PCI_CONFIG);
1379	uPciFunNo = uCfgFunction;
1380	}
1381	else
1382	AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND \|\| rc == VERR_CFGM_NO_PARENT,
1383	("Configuration error: PCIFunctionNo query failed with rc=%Rrc (%s/%d/%d)\n",
1384	rc, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1385	rc);
1386
1387
1388	/*
1389	* Initialize the internal data. We only do the wipe and the members
1390	* owned by PDM, the PCI bus does the rest in the registration call.
1391	*/
1392	RT_ZERO(pPciDev->Int);
1393
1394	pPciDev->Int.s.idxDevCfg = idxDevCfg;
1395	pPciDev->Int.s.fReassignableDevNo = uPciDevNoRaw >= VBOX_PCI_MAX_DEVICES;
1396	pPciDev->Int.s.fReassignableFunNo = uPciFunNo >= VBOX_PCI_MAX_FUNCTIONS;
1397	pPciDev->Int.s.pDevInsR3 = pDevIns;
1398	pPciDev->Int.s.pPdmBusR3 = pBus;
1399	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1400	{
1401	pPciDev->Int.s.pDevInsR0 = MMHyperR3ToR0(pVM, pDevIns);
1402	pPciDev->Int.s.pPdmBusR0 = MMHyperR3ToR0(pVM, pBus);
1403	}
1404	else
1405	{
1406	pPciDev->Int.s.pDevInsR0 = NIL_RTR0PTR;
1407	pPciDev->Int.s.pPdmBusR0 = NIL_RTR0PTR;
1408	}
1409
1410	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1411	{
1412	pPciDev->Int.s.pDevInsRC = MMHyperR3ToRC(pVM, pDevIns);
1413	pPciDev->Int.s.pPdmBusRC = MMHyperR3ToRC(pVM, pBus);
1414	}
1415	else
1416	{
1417	pPciDev->Int.s.pDevInsRC = NIL_RTRCPTR;
1418	pPciDev->Int.s.pPdmBusRC = NIL_RTRCPTR;
1419	}
1420
1421	/* Set some of the public members too. */
1422	pPciDev->pszNameR3 = pszName;
1423
1424	/*
1425	* Call the pci bus device to do the actual registration.
1426	*/
1427	pdmLock(pVM);
1428	rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
1429	pdmUnlock(pVM);
1430	if (RT_SUCCESS(rc))
1431	{
1432
1433	/*
1434	* Link it.
1435	*/
1436	if (pPrevPciDev)
1437	{
1438	Assert(!pPrevPciDev->Int.s.pNextR3);
1439	pPrevPciDev->Int.s.pNextR3 = pPciDev;
1440	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1441	pPrevPciDev->Int.s.pNextR0 = MMHyperR3ToR0(pVM, pPciDev);
1442	else
1443	pPrevPciDev->Int.s.pNextR0 = NIL_RTR0PTR;
1444	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1445	pPrevPciDev->Int.s.pNextRC = MMHyperR3ToRC(pVM, pPciDev);
1446	else
1447	pPrevPciDev->Int.s.pNextRC = NIL_RTRCPTR;
1448	}
1449	else
1450	{
1451	Assert(!pDevIns->Internal.s.pHeadPciDevR3);
1452	pDevIns->Internal.s.pHeadPciDevR3 = pPciDev;
1453	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1454	pDevIns->Internal.s.pHeadPciDevR0 = MMHyperR3ToR0(pVM, pPciDev);
1455	else
1456	pDevIns->Internal.s.pHeadPciDevR0 = NIL_RTR0PTR;
1457	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1458	pDevIns->Internal.s.pHeadPciDevRC = MMHyperR3ToRC(pVM, pPciDev);
1459	else
1460	pDevIns->Internal.s.pHeadPciDevRC = NIL_RTRCPTR;
1461	}
1462
1463	Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n",
1464	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->uDevFn, pBus->iBus));
1465	}
1466	}
1467	else
1468	{
1469	AssertLogRelMsgFailed(("Configuration error: No PCI bus available. This could be related to init order too!\n"));
1470	rc = VERR_PDM_NO_PCI_BUS;
1471	}
1472
1473	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1474	return rc;
1475	}
1476
1477
1478	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegisterMsi} */
1479	static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
1480	{
1481	PDMDEV_ASSERT_DEVINS(pDevIns);
1482	if (!pPciDev) /* NULL is an alias for the default PCI device. */
1483	pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1484	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1485	LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: pPciDev=%p:{%#x} pMsgReg=%p:{cMsiVectors=%d, cMsixVectors=%d}\n",
1486	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, pMsiReg, pMsiReg->cMsiVectors, pMsiReg->cMsixVectors));
1487
1488	PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3; Assert(pBus);
1489	PVM pVM = pDevIns->Internal.s.pVMR3;
1490	pdmLock(pVM);
1491	int rc;
1492	if (pBus->pfnRegisterMsiR3)
1493	rc = pBus->pfnRegisterMsiR3(pBus->pDevInsR3, pPciDev, pMsiReg);
1494	else
1495	rc = VERR_NOT_IMPLEMENTED;
1496	pdmUnlock(pVM);
1497
1498	LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1499	return rc;
1500	}
1501
1502
1503	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIIORegionRegister} */
1504	static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
1505	RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1506	{
1507	PDMDEV_ASSERT_DEVINS(pDevIns);
1508	PVM pVM = pDevIns->Internal.s.pVMR3;
1509	VM_ASSERT_EMT(pVM);
1510	if (!pPciDev) /* NULL is an alias for the default PCI device. */
1511	pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1512	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1513	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%d cbRegion=%RGp enmType=%d pfnCallback=%p\n",
1514	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iRegion, cbRegion, enmType, pfnCallback));
1515
1516	/*
1517	* Validate input.
1518	*/
1519	if (iRegion >= VBOX_PCI_NUM_REGIONS)
1520	{
1521	Assert(iRegion < VBOX_PCI_NUM_REGIONS);
1522	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (iRegion)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1523	return VERR_INVALID_PARAMETER;
1524	}
1525
1526	switch ((int)enmType)
1527	{
1528	case PCI_ADDRESS_SPACE_IO:
1529	/*
1530	* Sanity check: don't allow to register more than 32K of the PCI I/O space.
1531	*/
1532	AssertLogRelMsgReturn(cbRegion <= _32K,
1533	("caller='%s'/%d: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cbRegion),
1534	VERR_INVALID_PARAMETER);
1535	break;
1536
1537	case PCI_ADDRESS_SPACE_MEM:
1538	case PCI_ADDRESS_SPACE_MEM_PREFETCH:
1539	/*
1540	* Sanity check: Don't allow to register more than 2GB of the PCI MMIO space.
1541	*/
1542	AssertLogRelMsgReturn(cbRegion <= MM_MMIO_32_MAX,
1543	("caller='%s'/%d: %RGp (max %RGp)\n",
1544	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, (RTGCPHYS)MM_MMIO_32_MAX),
1545	VERR_OUT_OF_RANGE);
1546	break;
1547
1548	case PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM:
1549	case PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH:
1550	/*
1551	* Sanity check: Don't allow to register more than 64GB of the 64-bit PCI MMIO space.
1552	*/
1553	AssertLogRelMsgReturn(cbRegion <= MM_MMIO_64_MAX,
1554	("caller='%s'/%d: %RGp (max %RGp)\n",
1555	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, MM_MMIO_64_MAX),
1556	VERR_OUT_OF_RANGE);
1557	break;
1558
1559	default:
1560	AssertMsgFailed(("enmType=%#x is unknown\n", enmType));
1561	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (enmType)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1562	return VERR_INVALID_PARAMETER;
1563	}
1564	if (!pfnCallback)
1565	{
1566	Assert(pfnCallback);
1567	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (callback)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1568	return VERR_INVALID_PARAMETER;
1569	}
1570	AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1571
1572	/*
1573	* We're currently restricted to page aligned MMIO regions.
1574	*/
1575	if ( ((enmType & ~(PCI_ADDRESS_SPACE_BAR64 \| PCI_ADDRESS_SPACE_MEM_PREFETCH)) == PCI_ADDRESS_SPACE_MEM)
1576	&& cbRegion != RT_ALIGN_64(cbRegion, PAGE_SIZE))
1577	{
1578	Log(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: aligning cbRegion %RGp -> %RGp\n",
1579	pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, RT_ALIGN_64(cbRegion, PAGE_SIZE)));
1580	cbRegion = RT_ALIGN_64(cbRegion, PAGE_SIZE);
1581	}
1582
1583	/*
1584	* For registering PCI MMIO memory or PCI I/O memory, the size of the region must be a power of 2!
1585	*/
1586	int iLastSet = ASMBitLastSetU64(cbRegion);
1587	Assert(iLastSet > 0);
1588	uint64_t cbRegionAligned = RT_BIT_64(iLastSet - 1);
1589	if (cbRegion > cbRegionAligned)
1590	cbRegion = cbRegionAligned * 2; /* round up */
1591
1592	PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1593	Assert(pBus);
1594	pdmLock(pVM);
1595	int rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
1596	pdmUnlock(pVM);
1597
1598	LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1599	return rc;
1600	}
1601
1602
1603	/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */
1604	static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1605	PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1606	{
1607	PDMDEV_ASSERT_DEVINS(pDevIns);
1608	PVM pVM = pDevIns->Internal.s.pVMR3;
1609	VM_ASSERT_EMT(pVM);
1610	if (!pPciDev) /* NULL is an alias for the default PCI device. */
1611	pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1612	AssertReturnVoid(pPciDev);
1613	LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
1614	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
1615
1616	/*
1617	* Validate input and resolve defaults.
1618	*/
1619	AssertPtr(pfnRead);
1620	AssertPtr(pfnWrite);
1621	AssertPtrNull(ppfnReadOld);
1622	AssertPtrNull(ppfnWriteOld);
1623	AssertPtrNull(pPciDev);
1624
1625	PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1626	AssertRelease(pBus);
1627	AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1628
1629	/*
1630	* Do the job.
1631	*/
1632	pdmLock(pVM);
1633	pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
1634	pdmUnlock(pVM);
1635
1636	LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1637	}
1638
1639
1640	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */
1641	static DECLCALLBACK(int)
1642	pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
1643	{
1644	PDMDEV_ASSERT_DEVINS(pDevIns);
1645	if (!pPciDev) /* NULL is an alias for the default PCI device. */
1646	pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1647	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1648
1649	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
1650	/*
1651	* Just check the busmaster setting here and forward the request to the generic read helper.
1652	*/
1653	if (PCIDevIsBusmaster(pPciDev))
1654	{ /* likely */ }
1655	else
1656	{
1657	Log(("pdmR3DevHlp_PCIPhysRead: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
1658	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
1659	return VERR_PDM_NOT_PCI_BUS_MASTER;
1660	}
1661	#endif
1662
1663	return pDevIns->pHlpR3->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
1664	}
1665
1666
1667	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysWrite} */
1668	static DECLCALLBACK(int)
1669	pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
1670	{
1671	PDMDEV_ASSERT_DEVINS(pDevIns);
1672	if (!pPciDev) /* NULL is an alias for the default PCI device. */
1673	pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1674	AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1675
1676	#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
1677	/*
1678	* Just check the busmaster setting here and forward the request to the generic read helper.
1679	*/
1680	if (PCIDevIsBusmaster(pPciDev))
1681	{ /* likely */ }
1682	else
1683	{
1684	Log(("pdmR3DevHlp_PCIPhysWrite: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
1685	pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
1686	return VERR_PDM_NOT_PCI_BUS_MASTER;
1687	}
1688	#endif
1689
1690	return pDevIns->pHlpR3->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
1691	}
1692
1693
1694	/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrq} */
1695	static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
1696	{
1697	PDMDEV_ASSERT_DEVINS(pDevIns);
1698	if (!pPciDev) /* NULL is an alias for the default PCI device. */
1699	pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1700	AssertReturnVoid(pPciDev);
1701	LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
1702	pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
1703
1704	/*
1705	* Validate input.
1706	*/
1707	Assert(iIrq == 0);
1708	Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1709
1710	/*
1711	* Must have a PCI device registered!
1712	*/
1713	PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1714	Assert(pBus);
1715	PVM pVM = pDevIns->Internal.s.pVMR3;
1716
1717	pdmLock(pVM);
1718	uint32_t uTagSrc;
1719	if (iLevel & PDM_IRQ_LEVEL_HIGH)
1720	{
1721	pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1722	if (iLevel == PDM_IRQ_LEVEL_HIGH)
1723	VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1724	else
1725	VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1726	}
1727	else
1728	uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1729
1730	pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel, uTagSrc);
1731
1732	if (iLevel == PDM_IRQ_LEVEL_LOW)
1733	VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1734	pdmUnlock(pVM);
1735
1736	LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1737	}
1738
1739
1740	/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrqNoWait} */
1741	static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
1742	{
1743	pdmR3DevHlp_PCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
1744	}
1745
1746
1747	/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrq} */
1748	static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1749	{
1750	PDMDEV_ASSERT_DEVINS(pDevIns);
1751	LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
1752
1753	/*
1754	* Validate input.
1755	*/
1756	Assert(iIrq < 16);
1757	Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1758
1759	PVM pVM = pDevIns->Internal.s.pVMR3;
1760
1761	/*
1762	* Do the job.
1763	*/
1764	pdmLock(pVM);
1765	uint32_t uTagSrc;
1766	if (iLevel & PDM_IRQ_LEVEL_HIGH)
1767	{
1768	pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1769	if (iLevel == PDM_IRQ_LEVEL_HIGH)
1770	VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1771	else
1772	VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1773	}
1774	else
1775	uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1776
1777	PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
1778
1779	if (iLevel == PDM_IRQ_LEVEL_LOW)
1780	VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1781	pdmUnlock(pVM);
1782
1783	LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1784	}
1785
1786
1787	/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrqNoWait} */
1788	static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1789	{
1790	pdmR3DevHlp_ISASetIrq(pDevIns, iIrq, iLevel);
1791	}
1792
1793
1794	/** @interface_method_impl{PDMDEVHLPR3,pfnDriverAttach} */
1795	static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE ppBaseInterface, const char pszDesc)
1796	{
1797	PDMDEV_ASSERT_DEVINS(pDevIns);
1798	PVM pVM = pDevIns->Internal.s.pVMR3;
1799	VM_ASSERT_EMT(pVM);
1800	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n",
1801	pDevIns->pReg->szName, pDevIns->iInstance, iLun, pBaseInterface, ppBaseInterface, pszDesc, pszDesc));
1802
1803	/*
1804	* Lookup the LUN, it might already be registered.
1805	*/
1806	PPDMLUN pLunPrev = NULL;
1807	PPDMLUN pLun = pDevIns->Internal.s.pLunsR3;
1808	for (; pLun; pLunPrev = pLun, pLun = pLun->pNext)
1809	if (pLun->iLun == iLun)
1810	break;
1811
1812	/*
1813	* Create the LUN if if wasn't found, else check if driver is already attached to it.
1814	*/
1815	if (!pLun)
1816	{
1817	if ( !pBaseInterface
1818	\|\| !pszDesc
1819	\|\| !*pszDesc)
1820	{
1821	Assert(pBaseInterface);
1822	Assert(pszDesc \|\| *pszDesc);
1823	return VERR_INVALID_PARAMETER;
1824	}
1825
1826	pLun = (PPDMLUN)MMR3HeapAlloc(pVM, MM_TAG_PDM_LUN, sizeof(*pLun));
1827	if (!pLun)
1828	return VERR_NO_MEMORY;
1829
1830	pLun->iLun = iLun;
1831	pLun->pNext = pLunPrev ? pLunPrev->pNext : NULL;
1832	pLun->pTop = NULL;
1833	pLun->pBottom = NULL;
1834	pLun->pDevIns = pDevIns;
1835	pLun->pUsbIns = NULL;
1836	pLun->pszDesc = pszDesc;
1837	pLun->pBase = pBaseInterface;
1838	if (!pLunPrev)
1839	pDevIns->Internal.s.pLunsR3 = pLun;
1840	else
1841	pLunPrev->pNext = pLun;
1842	Log(("pdmR3DevHlp_DriverAttach: Registered LUN#%d '%s' with device '%s'/%d.\n",
1843	iLun, pszDesc, pDevIns->pReg->szName, pDevIns->iInstance));
1844	}
1845	else if (pLun->pTop)
1846	{
1847	AssertMsgFailed(("Already attached! The device should keep track of such things!\n"));
1848	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_DRIVER_ALREADY_ATTACHED));
1849	return VERR_PDM_DRIVER_ALREADY_ATTACHED;
1850	}
1851	Assert(pLun->pBase == pBaseInterface);
1852
1853
1854	/*
1855	* Get the attached driver configuration.
1856	*/
1857	int rc;
1858	PCFGMNODE pNode = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "LUN#%u", iLun);
1859	if (pNode)
1860	rc = pdmR3DrvInstantiate(pVM, pNode, pBaseInterface, NULL /pDrvAbove/, pLun, ppBaseInterface);
1861	else
1862	rc = VERR_PDM_NO_ATTACHED_DRIVER;
1863
1864	LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1865	return rc;
1866	}
1867
1868
1869	/** @interface_method_impl{PDMDEVHLPR3,pfnDriverDetach} */
1870	static DECLCALLBACK(int) pdmR3DevHlp_DriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
1871	{
1872	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1873	LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: pDrvIns=%p\n",
1874	pDevIns->pReg->szName, pDevIns->iInstance, pDrvIns));
1875
1876	#ifdef VBOX_STRICT
1877	PVM pVM = pDevIns->Internal.s.pVMR3;
1878	VM_ASSERT_EMT(pVM);
1879	#endif
1880
1881	int rc = pdmR3DrvDetach(pDrvIns, fFlags);
1882
1883	LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1884	return rc;
1885	}
1886
1887
1888	/** @interface_method_impl{PDMDEVHLPR3,pfnQueueCreate} */
1889	static DECLCALLBACK(int) pdmR3DevHlp_QueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
1890	PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char pszName, PPDMQUEUE ppQueue)
1891	{
1892	PDMDEV_ASSERT_DEVINS(pDevIns);
1893	LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fRZEnabled=%RTbool pszName=%p:{%s} ppQueue=%p\n",
1894	pDevIns->pReg->szName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, pszName, ppQueue));
1895
1896	PVM pVM = pDevIns->Internal.s.pVMR3;
1897	VM_ASSERT_EMT(pVM);
1898
1899	if (pDevIns->iInstance > 0)
1900	{
1901	pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance);
1902	AssertLogRelReturn(pszName, VERR_NO_MEMORY);
1903	}
1904
1905	int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
1906
1907	LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: returns %Rrc ppQueue=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, ppQueue));
1908	return rc;
1909	}
1910
1911
1912	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */
1913	static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1914	const char *pszNameFmt, va_list va)
1915	{
1916	PDMDEV_ASSERT_DEVINS(pDevIns);
1917	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",
1918	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));
1919
1920	PVM pVM = pDevIns->Internal.s.pVMR3;
1921	VM_ASSERT_EMT(pVM);
1922	int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
1923
1924	LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1925	return rc;
1926	}
1927
1928
1929	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNop} */
1930	static DECLCALLBACK(PPDMCRITSECT) pdmR3DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
1931	{
1932	PDMDEV_ASSERT_DEVINS(pDevIns);
1933	PVM pVM = pDevIns->Internal.s.pVMR3;
1934	VM_ASSERT_EMT(pVM);
1935
1936	PPDMCRITSECT pCritSect = PDMR3CritSectGetNop(pVM);
1937	LogFlow(("pdmR3DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n",
1938	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
1939	return pCritSect;
1940	}
1941
1942
1943	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopR0} */
1944	static DECLCALLBACK(R0PTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopR0(PPDMDEVINS pDevIns)
1945	{
1946	PDMDEV_ASSERT_DEVINS(pDevIns);
1947	PVM pVM = pDevIns->Internal.s.pVMR3;
1948	VM_ASSERT_EMT(pVM);
1949
1950	R0PTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopR0(pVM);
1951	LogFlow(("pdmR3DevHlp_CritSectGetNopR0: caller='%s'/%d: return %RHv\n",
1952	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
1953	return pCritSect;
1954	}
1955
1956
1957	/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopRC} */
1958	static DECLCALLBACK(RCPTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopRC(PPDMDEVINS pDevIns)
1959	{
1960	PDMDEV_ASSERT_DEVINS(pDevIns);
1961	PVM pVM = pDevIns->Internal.s.pVMR3;
1962	VM_ASSERT_EMT(pVM);
1963
1964	RCPTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopRC(pVM);
1965	LogFlow(("pdmR3DevHlp_CritSectGetNopRC: caller='%s'/%d: return %RRv\n",
1966	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
1967	return pCritSect;
1968	}
1969
1970
1971	/** @interface_method_impl{PDMDEVHLPR3,pfnSetDeviceCritSect} */
1972	static DECLCALLBACK(int) pdmR3DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
1973	{
1974	/*
1975	* Validate input.
1976	*
1977	* Note! We only allow the automatically created default critical section
1978	* to be replaced by this API.
1979	*/
1980	PDMDEV_ASSERT_DEVINS(pDevIns);
1981	AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
1982	LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
1983	pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
1984	AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
1985	PVM pVM = pDevIns->Internal.s.pVMR3;
1986	AssertReturn(pCritSect->s.pVMR3 == pVM, VERR_INVALID_PARAMETER);
1987
1988	VM_ASSERT_EMT(pVM);
1989	VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
1990
1991	AssertReturn(pDevIns->pCritSectRoR3, VERR_PDM_DEV_IPE_1);
1992	AssertReturn(pDevIns->pCritSectRoR3->s.fAutomaticDefaultCritsect, VERR_WRONG_ORDER);
1993	AssertReturn(!pDevIns->pCritSectRoR3->s.fUsedByTimerOrSimilar, VERR_WRONG_ORDER);
1994	AssertReturn(pDevIns->pCritSectRoR3 != pCritSect, VERR_INVALID_PARAMETER);
1995
1996	/*
1997	* Replace the critical section and destroy the automatic default section.
1998	*/
1999	PPDMCRITSECT pOldCritSect = pDevIns->pCritSectRoR3;
2000	pDevIns->pCritSectRoR3 = pCritSect;
2001	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2002	pDevIns->pCritSectRoR0 = MMHyperCCToR0(pVM, pDevIns->pCritSectRoR3);
2003	else
2004	Assert(pDevIns->pCritSectRoR0 == NIL_RTRCPTR);
2005
2006	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2007	pDevIns->pCritSectRoRC = MMHyperCCToRC(pVM, pDevIns->pCritSectRoR3);
2008	else
2009	Assert(pDevIns->pCritSectRoRC == NIL_RTRCPTR);
2010
2011	PDMR3CritSectDelete(pOldCritSect);
2012	if (pDevIns->pReg->fFlags & (PDM_DEVREG_FLAGS_RC \| PDM_DEVREG_FLAGS_R0))
2013	MMHyperFree(pVM, pOldCritSect);
2014	else
2015	MMR3HeapFree(pOldCritSect);
2016
2017	LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2018	return VINF_SUCCESS;
2019	}
2020
2021
2022	/** @interface_method_impl{PDMDEVHLPR3,pfnThreadCreate} */
2023	static DECLCALLBACK(int) pdmR3DevHlp_ThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
2024	PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
2025	{
2026	PDMDEV_ASSERT_DEVINS(pDevIns);
2027	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2028	LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",
2029	pDevIns->pReg->szName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));
2030
2031	int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
2032
2033	LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pReg->szName, pDevIns->iInstance,
2034	rc, *ppThread));
2035	return rc;
2036	}
2037
2038
2039	/** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */
2040	static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
2041	{
2042	PDMDEV_ASSERT_DEVINS(pDevIns);
2043	VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3);
2044	LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pfnAsyncNotify));
2045
2046	int rc = VINF_SUCCESS;
2047	AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER);
2048	AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER);
2049	AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED \| PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER);
2050	VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
2051	AssertStmt( enmVMState == VMSTATE_SUSPENDING
2052	\|\| enmVMState == VMSTATE_SUSPENDING_EXT_LS
2053	\|\| enmVMState == VMSTATE_SUSPENDING_LS
2054	\|\| enmVMState == VMSTATE_RESETTING
2055	\|\| enmVMState == VMSTATE_RESETTING_LS
2056	\|\| enmVMState == VMSTATE_POWERING_OFF
2057	\|\| enmVMState == VMSTATE_POWERING_OFF_LS,
2058	rc = VERR_INVALID_STATE);
2059
2060	if (RT_SUCCESS(rc))
2061	pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify;
2062
2063	LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2064	return rc;
2065	}
2066
2067
2068	/** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */
2069	static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns)
2070	{
2071	PDMDEV_ASSERT_DEVINS(pDevIns);
2072	PVM pVM = pDevIns->Internal.s.pVMR3;
2073
2074	VMSTATE enmVMState = VMR3GetState(pVM);
2075	if ( enmVMState == VMSTATE_SUSPENDING
2076	\|\| enmVMState == VMSTATE_SUSPENDING_EXT_LS
2077	\|\| enmVMState == VMSTATE_SUSPENDING_LS
2078	\|\| enmVMState == VMSTATE_RESETTING
2079	\|\| enmVMState == VMSTATE_RESETTING_LS
2080	\|\| enmVMState == VMSTATE_POWERING_OFF
2081	\|\| enmVMState == VMSTATE_POWERING_OFF_LS)
2082	{
2083	LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
2084	VMR3AsyncPdmNotificationWakeupU(pVM->pUVM);
2085	}
2086	else
2087	LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, enmVMState));
2088	}
2089
2090
2091	/** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */
2092	static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
2093	{
2094	PDMDEV_ASSERT_DEVINS(pDevIns);
2095	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2096	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",
2097	pDevIns->pReg->szName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,
2098	pRtcReg->pfnWrite, ppRtcHlp));
2099
2100	/*
2101	* Validate input.
2102	*/
2103	if (pRtcReg->u32Version != PDM_RTCREG_VERSION)
2104	{
2105	AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,
2106	PDM_RTCREG_VERSION));
2107	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",
2108	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2109	return VERR_INVALID_PARAMETER;
2110	}
2111	if ( !pRtcReg->pfnWrite
2112	\|\| !pRtcReg->pfnRead)
2113	{
2114	Assert(pRtcReg->pfnWrite);
2115	Assert(pRtcReg->pfnRead);
2116	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
2117	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2118	return VERR_INVALID_PARAMETER;
2119	}
2120
2121	if (!ppRtcHlp)
2122	{
2123	Assert(ppRtcHlp);
2124	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",
2125	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2126	return VERR_INVALID_PARAMETER;
2127	}
2128
2129	/*
2130	* Only one DMA device.
2131	*/
2132	PVM pVM = pDevIns->Internal.s.pVMR3;
2133	if (pVM->pdm.s.pRtc)
2134	{
2135	AssertMsgFailed(("Only one RTC device is supported!\n"));
2136	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
2137	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2138	return VERR_INVALID_PARAMETER;
2139	}
2140
2141	/*
2142	* Allocate and initialize pci bus structure.
2143	*/
2144	int rc = VINF_SUCCESS;
2145	PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));
2146	if (pRtc)
2147	{
2148	pRtc->pDevIns = pDevIns;
2149	pRtc->Reg = *pRtcReg;
2150	pVM->pdm.s.pRtc = pRtc;
2151
2152	/* set the helper pointer. */
2153	*ppRtcHlp = &g_pdmR3DevRtcHlp;
2154	Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",
2155	pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2156	}
2157	else
2158	rc = VERR_NO_MEMORY;
2159
2160	LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
2161	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2162	return rc;
2163	}
2164
2165
2166	/** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */
2167	static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
2168	{
2169	PDMDEV_ASSERT_DEVINS(pDevIns);
2170	PVM pVM = pDevIns->Internal.s.pVMR3;
2171	VM_ASSERT_EMT(pVM);
2172	LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n",
2173	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser));
2174	int rc = VINF_SUCCESS;
2175	if (pVM->pdm.s.pDmac)
2176	pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser);
2177	else
2178	{
2179	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2180	rc = VERR_PDM_NO_DMAC_INSTANCE;
2181	}
2182	LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n",
2183	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2184	return rc;
2185	}
2186
2187
2188	/** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */
2189	static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbRead)
2190	{
2191	PDMDEV_ASSERT_DEVINS(pDevIns);
2192	PVM pVM = pDevIns->Internal.s.pVMR3;
2193	VM_ASSERT_EMT(pVM);
2194	LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n",
2195	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead));
2196	int rc = VINF_SUCCESS;
2197	if (pVM->pdm.s.pDmac)
2198	{
2199	uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2200	if (pcbRead)
2201	*pcbRead = cb;
2202	}
2203	else
2204	{
2205	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2206	rc = VERR_PDM_NO_DMAC_INSTANCE;
2207	}
2208	LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n",
2209	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2210	return rc;
2211	}
2212
2213
2214	/** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */
2215	static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t pcbWritten)
2216	{
2217	PDMDEV_ASSERT_DEVINS(pDevIns);
2218	PVM pVM = pDevIns->Internal.s.pVMR3;
2219	VM_ASSERT_EMT(pVM);
2220	LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n",
2221	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten));
2222	int rc = VINF_SUCCESS;
2223	if (pVM->pdm.s.pDmac)
2224	{
2225	uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2226	if (pcbWritten)
2227	*pcbWritten = cb;
2228	}
2229	else
2230	{
2231	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2232	rc = VERR_PDM_NO_DMAC_INSTANCE;
2233	}
2234	LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n",
2235	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2236	return rc;
2237	}
2238
2239
2240	/** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */
2241	static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
2242	{
2243	PDMDEV_ASSERT_DEVINS(pDevIns);
2244	PVM pVM = pDevIns->Internal.s.pVMR3;
2245	VM_ASSERT_EMT(pVM);
2246	LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n",
2247	pDevIns->pReg->szName, pDevIns->iInstance, uChannel, uLevel));
2248	int rc = VINF_SUCCESS;
2249	if (pVM->pdm.s.pDmac)
2250	pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel);
2251	else
2252	{
2253	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2254	rc = VERR_PDM_NO_DMAC_INSTANCE;
2255	}
2256	LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n",
2257	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2258	return rc;
2259	}
2260
2261	/** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */
2262	static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
2263	{
2264	PDMDEV_ASSERT_DEVINS(pDevIns);
2265	PVM pVM = pDevIns->Internal.s.pVMR3;
2266	VM_ASSERT_EMT(pVM);
2267	LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n",
2268	pDevIns->pReg->szName, pDevIns->iInstance, uChannel));
2269	uint8_t u8Mode;
2270	if (pVM->pdm.s.pDmac)
2271	u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel);
2272	else
2273	{
2274	AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2275	u8Mode = 3 << 2 /* illegal mode type */;
2276	}
2277	LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n",
2278	pDevIns->pReg->szName, pDevIns->iInstance, u8Mode));
2279	return u8Mode;
2280	}
2281
2282	/** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */
2283	static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns)
2284	{
2285	PDMDEV_ASSERT_DEVINS(pDevIns);
2286	PVM pVM = pDevIns->Internal.s.pVMR3;
2287	VM_ASSERT_EMT(pVM);
2288	LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n",
2289	pDevIns->pReg->szName, pDevIns->iInstance, VM_FF_IS_SET(pVM, VM_FF_PDM_DMA)));
2290
2291	AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2292	VM_FF_SET(pVM, VM_FF_PDM_DMA);
2293	#ifdef VBOX_WITH_REM
2294	REMR3NotifyDmaPending(pVM);
2295	#endif
2296	VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM);
2297	}
2298
2299
2300	/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */
2301	static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
2302	{
2303	PDMDEV_ASSERT_DEVINS(pDevIns);
2304	PVM pVM = pDevIns->Internal.s.pVMR3;
2305	VM_ASSERT_EMT(pVM);
2306
2307	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n",
2308	pDevIns->pReg->szName, pDevIns->iInstance, iReg, u8Value));
2309	int rc;
2310	if (pVM->pdm.s.pRtc)
2311	{
2312	PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2313	rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2314	if (RT_SUCCESS(rc))
2315	{
2316	rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pDevInsRtc, iReg, u8Value);
2317	PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2318	}
2319	}
2320	else
2321	rc = VERR_PDM_NO_RTC_INSTANCE;
2322
2323	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2324	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2325	return rc;
2326	}
2327
2328
2329	/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */
2330	static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
2331	{
2332	PDMDEV_ASSERT_DEVINS(pDevIns);
2333	PVM pVM = pDevIns->Internal.s.pVMR3;
2334	VM_ASSERT_EMT(pVM);
2335
2336	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n",
2337	pDevIns->pReg->szName, pDevIns->iInstance, iReg, pu8Value));
2338	int rc;
2339	if (pVM->pdm.s.pRtc)
2340	{
2341	PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2342	rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2343	if (RT_SUCCESS(rc))
2344	{
2345	rc = pVM->pdm.s.pRtc->Reg.pfnRead(pDevInsRtc, iReg, pu8Value);
2346	PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2347	}
2348	}
2349	else
2350	rc = VERR_PDM_NO_RTC_INSTANCE;
2351
2352	LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2353	pDevIns->pReg->szName, pDevIns->iInstance, rc));
2354	return rc;
2355	}
2356
2357
2358	/** @interface_method_impl{PDMDEVHLPR3,pfnAssertEMT} */
2359	static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction)
2360	{
2361	PDMDEV_ASSERT_DEVINS(pDevIns);
2362	if (VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2363	return true;
2364
2365	char szMsg[100];
2366	RTStrPrintf(szMsg, sizeof(szMsg), "AssertEMT '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2367	RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2368	AssertBreakpoint();
2369	return false;
2370	}
2371
2372
2373	/** @interface_method_impl{PDMDEVHLPR3,pfnAssertOther} */
2374	static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char pszFile, unsigned iLine, const char pszFunction)
2375	{
2376	PDMDEV_ASSERT_DEVINS(pDevIns);
2377	if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2378	return true;
2379
2380	char szMsg[100];
2381	RTStrPrintf(szMsg, sizeof(szMsg), "AssertOther '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2382	RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2383	AssertBreakpoint();
2384	return false;
2385	}
2386
2387
2388	/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetRCInterfaceSymbols} */
2389	static DECLCALLBACK(int) pdmR3DevHlp_LdrGetRCInterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2390	const char pszSymPrefix, const char pszSymList)
2391	{
2392	PDMDEV_ASSERT_DEVINS(pDevIns);
2393	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2394	LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2395	pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2396
2397	int rc;
2398	if ( strncmp(pszSymPrefix, "dev", 3) == 0
2399	&& RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2400	{
2401	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2402	rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2403	pvInterface, cbInterface,
2404	pDevIns->pReg->szRCMod, pDevIns->Internal.s.pDevR3->pszRCSearchPath,
2405	pszSymPrefix, pszSymList,
2406	false /fRing0OrRC/);
2407	else
2408	{
2409	AssertMsgFailed(("Not a raw-mode enabled driver\n"));
2410	rc = VERR_PERMISSION_DENIED;
2411	}
2412	}
2413	else
2414	{
2415	AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2416	pszSymPrefix, pDevIns->pReg->szName));
2417	rc = VERR_INVALID_NAME;
2418	}
2419
2420	LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2421	pDevIns->iInstance, rc));
2422	return rc;
2423	}
2424
2425
2426	/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetR0InterfaceSymbols} */
2427	static DECLCALLBACK(int) pdmR3DevHlp_LdrGetR0InterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2428	const char pszSymPrefix, const char pszSymList)
2429	{
2430	PDMDEV_ASSERT_DEVINS(pDevIns);
2431	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2432	LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2433	pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2434
2435	int rc;
2436	if ( strncmp(pszSymPrefix, "dev", 3) == 0
2437	&& RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2438	{
2439	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2440	rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2441	pvInterface, cbInterface,
2442	pDevIns->pReg->szR0Mod, pDevIns->Internal.s.pDevR3->pszR0SearchPath,
2443	pszSymPrefix, pszSymList,
2444	true /fRing0OrRC/);
2445	else
2446	{
2447	AssertMsgFailed(("Not a ring-0 enabled driver\n"));
2448	rc = VERR_PERMISSION_DENIED;
2449	}
2450	}
2451	else
2452	{
2453	AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2454	pszSymPrefix, pDevIns->pReg->szName));
2455	rc = VERR_INVALID_NAME;
2456	}
2457
2458	LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2459	pDevIns->iInstance, rc));
2460	return rc;
2461	}
2462
2463
2464	/** @interface_method_impl{PDMDEVHLPR3,pfnCallR0} */
2465	static DECLCALLBACK(int) pdmR3DevHlp_CallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
2466	{
2467	PDMDEV_ASSERT_DEVINS(pDevIns);
2468	PVM pVM = pDevIns->Internal.s.pVMR3;
2469	VM_ASSERT_EMT(pVM);
2470	LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: uOperation=%#x u64Arg=%#RX64\n",
2471	pDevIns->pReg->szName, pDevIns->iInstance, uOperation, u64Arg));
2472
2473	/*
2474	* Resolve the ring-0 entry point. There is not need to remember this like
2475	* we do for drivers since this is mainly for construction time hacks and
2476	* other things that aren't performance critical.
2477	*/
2478	int rc;
2479	if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2480	{
2481	char szSymbol[ sizeof("devR0") + sizeof(pDevIns->pReg->szName) + sizeof("ReqHandler")];
2482	strcat(strcat(strcpy(szSymbol, "devR0"), pDevIns->pReg->szName), "ReqHandler");
2483	szSymbol[sizeof("devR0") - 1] = RT_C_TO_UPPER(szSymbol[sizeof("devR0") - 1]);
2484
2485	PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
2486	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, szSymbol, &pfnReqHandlerR0);
2487	if (RT_SUCCESS(rc))
2488	{
2489	/*
2490	* Make the ring-0 call.
2491	*/
2492	PDMDEVICECALLREQHANDLERREQ Req;
2493	Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2494	Req.Hdr.cbReq = sizeof(Req);
2495	Req.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2496	Req.pfnReqHandlerR0 = pfnReqHandlerR0;
2497	Req.uOperation = uOperation;
2498	Req.u32Alignment = 0;
2499	Req.u64Arg = u64Arg;
2500	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_PDM_DEVICE_CALL_REQ_HANDLER, 0, &Req.Hdr);
2501	}
2502	else
2503	pfnReqHandlerR0 = NIL_RTR0PTR;
2504	}
2505	else
2506	rc = VERR_ACCESS_DENIED;
2507	LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2508	pDevIns->iInstance, rc));
2509	return rc;
2510	}
2511
2512
2513	/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetSuspendReason} */
2514	static DECLCALLBACK(VMSUSPENDREASON) pdmR3DevHlp_VMGetSuspendReason(PPDMDEVINS pDevIns)
2515	{
2516	PDMDEV_ASSERT_DEVINS(pDevIns);
2517	PVM pVM = pDevIns->Internal.s.pVMR3;
2518	VM_ASSERT_EMT(pVM);
2519	VMSUSPENDREASON enmReason = VMR3GetSuspendReason(pVM->pUVM);
2520	LogFlow(("pdmR3DevHlp_VMGetSuspendReason: caller='%s'/%d: returns %d\n",
2521	pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
2522	return enmReason;
2523	}
2524
2525
2526	/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetResumeReason} */
2527	static DECLCALLBACK(VMRESUMEREASON) pdmR3DevHlp_VMGetResumeReason(PPDMDEVINS pDevIns)
2528	{
2529	PDMDEV_ASSERT_DEVINS(pDevIns);
2530	PVM pVM = pDevIns->Internal.s.pVMR3;
2531	VM_ASSERT_EMT(pVM);
2532	VMRESUMEREASON enmReason = VMR3GetResumeReason(pVM->pUVM);
2533	LogFlow(("pdmR3DevHlp_VMGetResumeReason: caller='%s'/%d: returns %d\n",
2534	pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
2535	return enmReason;
2536	}
2537
2538
2539	/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
2540	static DECLCALLBACK(PUVM) pdmR3DevHlp_GetUVM(PPDMDEVINS pDevIns)
2541	{
2542	PDMDEV_ASSERT_DEVINS(pDevIns);
2543	LogFlow(("pdmR3DevHlp_GetUVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2544	return pDevIns->Internal.s.pVMR3->pUVM;
2545	}
2546
2547
2548	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
2549	static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns)
2550	{
2551	PDMDEV_ASSERT_DEVINS(pDevIns);
2552	LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2553	return pDevIns->Internal.s.pVMR3;
2554	}
2555
2556
2557	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
2558	static DECLCALLBACK(PVMCPU) pdmR3DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
2559	{
2560	PDMDEV_ASSERT_DEVINS(pDevIns);
2561	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2562	LogFlow(("pdmR3DevHlp_GetVMCPU: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, VMMGetCpuId(pDevIns->Internal.s.pVMR3)));
2563	return VMMGetCpu(pDevIns->Internal.s.pVMR3);
2564	}
2565
2566
2567	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
2568	static DECLCALLBACK(VMCPUID) pdmR3DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
2569	{
2570	PDMDEV_ASSERT_DEVINS(pDevIns);
2571	VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR3);
2572	LogFlow(("pdmR3DevHlp_GetCurrentCpuId: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, idCpu));
2573	return idCpu;
2574	}
2575
2576
2577	/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
2578	static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg, PCPDMPCIHLPR3 *ppPciHlpR3)
2579	{
2580	PDMDEV_ASSERT_DEVINS(pDevIns);
2581	PVM pVM = pDevIns->Internal.s.pVMR3;
2582	VM_ASSERT_EMT(pVM);
2583	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
2584	".pfnSetIrqR3=%p, .pfnFakePCIBIOSR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p\n",
2585	pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
2586	pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pfnFakePCIBIOSR3,
2587	pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3));
2588
2589	/*
2590	* Validate the structure.
2591	*/
2592	if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
2593	{
2594	AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
2595	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2596	return VERR_INVALID_PARAMETER;
2597	}
2598	if ( !pPciBusReg->pfnRegisterR3
2599	\|\| !pPciBusReg->pfnIORegionRegisterR3
2600	\|\| !pPciBusReg->pfnSetIrqR3
2601	\|\| (!pPciBusReg->pfnFakePCIBIOSR3 && !pVM->pdm.s.aPciBuses[0].pDevInsR3)) /* Only the first bus needs to do the BIOS work. */
2602	{
2603	Assert(pPciBusReg->pfnRegisterR3);
2604	Assert(pPciBusReg->pfnIORegionRegisterR3);
2605	Assert(pPciBusReg->pfnSetIrqR3);
2606	Assert(pPciBusReg->pfnFakePCIBIOSR3);
2607	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2608	return VERR_INVALID_PARAMETER;
2609	}
2610	if ( pPciBusReg->pszSetIrqRC
2611	&& !VALID_PTR(pPciBusReg->pszSetIrqRC))
2612	{
2613	Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
2614	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2615	return VERR_INVALID_PARAMETER;
2616	}
2617	if ( pPciBusReg->pszSetIrqR0
2618	&& !VALID_PTR(pPciBusReg->pszSetIrqR0))
2619	{
2620	Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
2621	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2622	return VERR_INVALID_PARAMETER;
2623	}
2624	if (!ppPciHlpR3)
2625	{
2626	Assert(ppPciHlpR3);
2627	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2628	return VERR_INVALID_PARAMETER;
2629	}
2630
2631	/*
2632	* Find free PCI bus entry.
2633	*/
2634	unsigned iBus = 0;
2635	for (iBus = 0; iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses); iBus++)
2636	if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
2637	break;
2638	if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
2639	{
2640	AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
2641	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2642	return VERR_INVALID_PARAMETER;
2643	}
2644	PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
2645
2646	/*
2647	* Resolve and init the RC bits.
2648	*/
2649	if (pPciBusReg->pszSetIrqRC)
2650	{
2651	int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
2652	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPciBusReg->pszSetIrqRC, rc));
2653	if (RT_FAILURE(rc))
2654	{
2655	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2656	return rc;
2657	}
2658	pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2659	}
2660	else
2661	{
2662	pPciBus->pfnSetIrqRC = 0;
2663	pPciBus->pDevInsRC = 0;
2664	}
2665
2666	/*
2667	* Resolve and init the R0 bits.
2668	*/
2669	if (pPciBusReg->pszSetIrqR0)
2670	{
2671	int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
2672	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPciBusReg->pszSetIrqR0, rc));
2673	if (RT_FAILURE(rc))
2674	{
2675	LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2676	return rc;
2677	}
2678	pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2679	}
2680	else
2681	{
2682	pPciBus->pfnSetIrqR0 = 0;
2683	pPciBus->pDevInsR0 = 0;
2684	}
2685
2686	/*
2687	* Init the R3 bits.
2688	*/
2689	pPciBus->iBus = iBus;
2690	pPciBus->pDevInsR3 = pDevIns;
2691	pPciBus->pfnRegisterR3 = pPciBusReg->pfnRegisterR3;
2692	pPciBus->pfnRegisterMsiR3 = pPciBusReg->pfnRegisterMsiR3;
2693	pPciBus->pfnIORegionRegisterR3 = pPciBusReg->pfnIORegionRegisterR3;
2694	pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
2695	pPciBus->pfnSetIrqR3 = pPciBusReg->pfnSetIrqR3;
2696	pPciBus->pfnFakePCIBIOSR3 = pPciBusReg->pfnFakePCIBIOSR3;
2697
2698	Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2699
2700	/* set the helper pointer and return. */
2701	*ppPciHlpR3 = &g_pdmR3DevPciHlp;
2702	LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2703	return VINF_SUCCESS;
2704	}
2705
2706
2707	/** @interface_method_impl{PDMDEVHLPR3,pfnPICRegister} */
2708	static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
2709	{
2710	PDMDEV_ASSERT_DEVINS(pDevIns);
2711	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2712	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pfnGetInterruptR3=%p, .pszGetIrqRC=%p:{%s}, .pszGetInterruptRC=%p:{%s}, .pszGetIrqR0=%p:{%s}, .pszGetInterruptR0=%p:{%s} } ppPicHlpR3=%p\n",
2713	pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrqR3, pPicReg->pfnGetInterruptR3,
2714	pPicReg->pszSetIrqRC, pPicReg->pszSetIrqRC, pPicReg->pszGetInterruptRC, pPicReg->pszGetInterruptRC,
2715	pPicReg->pszSetIrqR0, pPicReg->pszSetIrqR0, pPicReg->pszGetInterruptR0, pPicReg->pszGetInterruptR0,
2716	ppPicHlpR3));
2717
2718	/*
2719	* Validate input.
2720	*/
2721	if (pPicReg->u32Version != PDM_PICREG_VERSION)
2722	{
2723	AssertMsgFailed(("u32Version=%#x expected %#x\n", pPicReg->u32Version, PDM_PICREG_VERSION));
2724	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2725	return VERR_INVALID_PARAMETER;
2726	}
2727	if ( !pPicReg->pfnSetIrqR3
2728	\|\| !pPicReg->pfnGetInterruptR3)
2729	{
2730	Assert(pPicReg->pfnSetIrqR3);
2731	Assert(pPicReg->pfnGetInterruptR3);
2732	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2733	return VERR_INVALID_PARAMETER;
2734	}
2735	if ( ( pPicReg->pszSetIrqRC
2736	\|\| pPicReg->pszGetInterruptRC)
2737	&& ( !VALID_PTR(pPicReg->pszSetIrqRC)
2738	\|\| !VALID_PTR(pPicReg->pszGetInterruptRC))
2739	)
2740	{
2741	Assert(VALID_PTR(pPicReg->pszSetIrqRC));
2742	Assert(VALID_PTR(pPicReg->pszGetInterruptRC));
2743	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2744	return VERR_INVALID_PARAMETER;
2745	}
2746	if ( pPicReg->pszSetIrqRC
2747	&& !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC))
2748	{
2749	Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC);
2750	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2751	return VERR_INVALID_PARAMETER;
2752	}
2753	if ( pPicReg->pszSetIrqR0
2754	&& !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
2755	{
2756	Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0);
2757	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R0 flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2758	return VERR_INVALID_PARAMETER;
2759	}
2760	if (!ppPicHlpR3)
2761	{
2762	Assert(ppPicHlpR3);
2763	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (ppPicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2764	return VERR_INVALID_PARAMETER;
2765	}
2766
2767	/*
2768	* Only one PIC device.
2769	*/
2770	PVM pVM = pDevIns->Internal.s.pVMR3;
2771	if (pVM->pdm.s.Pic.pDevInsR3)
2772	{
2773	AssertMsgFailed(("Only one pic device is supported!\n"));
2774	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2775	return VERR_INVALID_PARAMETER;
2776	}
2777
2778	/*
2779	* RC stuff.
2780	*/
2781	if (pPicReg->pszSetIrqRC)
2782	{
2783	int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszSetIrqRC, &pVM->pdm.s.Pic.pfnSetIrqRC);
2784	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszSetIrqRC, rc));
2785	if (RT_SUCCESS(rc))
2786	{
2787	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszGetInterruptRC, &pVM->pdm.s.Pic.pfnGetInterruptRC);
2788	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszGetInterruptRC, rc));
2789	}
2790	if (RT_FAILURE(rc))
2791	{
2792	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2793	return rc;
2794	}
2795	pVM->pdm.s.Pic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2796	}
2797	else
2798	{
2799	pVM->pdm.s.Pic.pDevInsRC = 0;
2800	pVM->pdm.s.Pic.pfnSetIrqRC = 0;
2801	pVM->pdm.s.Pic.pfnGetInterruptRC = 0;
2802	}
2803
2804	/*
2805	* R0 stuff.
2806	*/
2807	if (pPicReg->pszSetIrqR0)
2808	{
2809	int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszSetIrqR0, &pVM->pdm.s.Pic.pfnSetIrqR0);
2810	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszSetIrqR0, rc));
2811	if (RT_SUCCESS(rc))
2812	{
2813	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszGetInterruptR0, &pVM->pdm.s.Pic.pfnGetInterruptR0);
2814	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszGetInterruptR0, rc));
2815	}
2816	if (RT_FAILURE(rc))
2817	{
2818	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2819	return rc;
2820	}
2821	pVM->pdm.s.Pic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2822	Assert(pVM->pdm.s.Pic.pDevInsR0);
2823	}
2824	else
2825	{
2826	pVM->pdm.s.Pic.pfnSetIrqR0 = 0;
2827	pVM->pdm.s.Pic.pfnGetInterruptR0 = 0;
2828	pVM->pdm.s.Pic.pDevInsR0 = 0;
2829	}
2830
2831	/*
2832	* R3 stuff.
2833	*/
2834	pVM->pdm.s.Pic.pDevInsR3 = pDevIns;
2835	pVM->pdm.s.Pic.pfnSetIrqR3 = pPicReg->pfnSetIrqR3;
2836	pVM->pdm.s.Pic.pfnGetInterruptR3 = pPicReg->pfnGetInterruptR3;
2837	Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2838
2839	/* set the helper pointer and return. */
2840	*ppPicHlpR3 = &g_pdmR3DevPicHlp;
2841	LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2842	return VINF_SUCCESS;
2843	}
2844
2845
2846	/** @interface_method_impl{PDMDEVHLPR3,pfnAPICRegister} */
2847	static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns, PPDMAPICREG pApicReg, PCPDMAPICHLPR3 *ppApicHlpR3)
2848	{
2849	PDMDEV_ASSERT_DEVINS(pDevIns);
2850	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2851	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: pApicReg=%p:{.u32Version=%#x, .pfnGetInterruptR3=%p, .pfnSetBaseMsrR3=%p, .pfnGetBaseMsrR3=%p, "
2852	".pfnSetTprR3=%p, .pfnGetTprR3=%p, .pfnWriteMsr3=%p, .pfnReadMsr3=%p, .pfnBusDeliverR3=%p, .pfnLocalInterruptR3=%p .pfnGetTimerFreqR3=%p, pszGetInterruptRC=%p:{%s}, pszSetBaseMsrRC=%p:{%s}, pszGetBaseMsrRC=%p:{%s}, "
2853	".pszSetTprRC=%p:{%s}, .pszGetTprRC=%p:{%s}, .pszWriteMsrRC=%p:{%s}, .pszReadMsrRC=%p:{%s}, .pszBusDeliverRC=%p:{%s}, .pszLocalInterruptRC=%p:{%s}, .pszGetTimerFreqRC=%p:{%s}} ppApicHlpR3=%p\n",
2854	pDevIns->pReg->szName, pDevIns->iInstance, pApicReg, pApicReg->u32Version, pApicReg->pfnGetInterruptR3, pApicReg->pfnSetBaseMsrR3,
2855	pApicReg->pfnGetBaseMsrR3, pApicReg->pfnSetTprR3, pApicReg->pfnGetTprR3, pApicReg->pfnWriteMsrR3, pApicReg->pfnReadMsrR3, pApicReg->pfnBusDeliverR3, pApicReg->pfnLocalInterruptR3, pApicReg->pfnGetTimerFreqR3, pApicReg->pszGetInterruptRC,
2856	pApicReg->pszGetInterruptRC, pApicReg->pszSetBaseMsrRC, pApicReg->pszSetBaseMsrRC, pApicReg->pszGetBaseMsrRC, pApicReg->pszGetBaseMsrRC,
2857	pApicReg->pszSetTprRC, pApicReg->pszSetTprRC, pApicReg->pszGetTprRC, pApicReg->pszGetTprRC, pApicReg->pszWriteMsrRC, pApicReg->pszWriteMsrRC, pApicReg->pszReadMsrRC, pApicReg->pszReadMsrRC, pApicReg->pszBusDeliverRC,
2858	pApicReg->pszBusDeliverRC, pApicReg->pszLocalInterruptRC, pApicReg->pszLocalInterruptRC, pApicReg->pszGetTimerFreqRC, pApicReg->pszGetTimerFreqRC, ppApicHlpR3));
2859
2860	/*
2861	* Validate input.
2862	*/
2863	if (pApicReg->u32Version != PDM_APICREG_VERSION)
2864	{
2865	AssertMsgFailed(("u32Version=%#x expected %#x\n", pApicReg->u32Version, PDM_APICREG_VERSION));
2866	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2867	return VERR_INVALID_PARAMETER;
2868	}
2869	if ( !pApicReg->pfnGetInterruptR3
2870	\|\| !pApicReg->pfnSetBaseMsrR3
2871	\|\| !pApicReg->pfnGetBaseMsrR3
2872	\|\| !pApicReg->pfnSetTprR3
2873	\|\| !pApicReg->pfnGetTprR3
2874	\|\| !pApicReg->pfnWriteMsrR3
2875	\|\| !pApicReg->pfnReadMsrR3
2876	\|\| !pApicReg->pfnBusDeliverR3
2877	\|\| !pApicReg->pfnLocalInterruptR3
2878	\|\| !pApicReg->pfnGetTimerFreqR3)
2879	{
2880	Assert(pApicReg->pfnGetInterruptR3);
2881	Assert(pApicReg->pfnSetBaseMsrR3);
2882	Assert(pApicReg->pfnGetBaseMsrR3);
2883	Assert(pApicReg->pfnSetTprR3);
2884	Assert(pApicReg->pfnGetTprR3);
2885	Assert(pApicReg->pfnWriteMsrR3);
2886	Assert(pApicReg->pfnReadMsrR3);
2887	Assert(pApicReg->pfnBusDeliverR3);
2888	Assert(pApicReg->pfnLocalInterruptR3);
2889	Assert(pApicReg->pfnGetTimerFreqR3);
2890	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2891	return VERR_INVALID_PARAMETER;
2892	}
2893	if ( ( pApicReg->pszGetInterruptRC
2894	\|\| pApicReg->pszSetBaseMsrRC
2895	\|\| pApicReg->pszGetBaseMsrRC
2896	\|\| pApicReg->pszSetTprRC
2897	\|\| pApicReg->pszGetTprRC
2898	\|\| pApicReg->pszWriteMsrRC
2899	\|\| pApicReg->pszReadMsrRC
2900	\|\| pApicReg->pszBusDeliverRC
2901	\|\| pApicReg->pszLocalInterruptRC
2902	\|\| pApicReg->pszGetTimerFreqRC)
2903	&& ( !VALID_PTR(pApicReg->pszGetInterruptRC)
2904	\|\| !VALID_PTR(pApicReg->pszSetBaseMsrRC)
2905	\|\| !VALID_PTR(pApicReg->pszGetBaseMsrRC)
2906	\|\| !VALID_PTR(pApicReg->pszSetTprRC)
2907	\|\| !VALID_PTR(pApicReg->pszGetTprRC)
2908	\|\| !VALID_PTR(pApicReg->pszWriteMsrRC)
2909	\|\| !VALID_PTR(pApicReg->pszReadMsrRC)
2910	\|\| !VALID_PTR(pApicReg->pszBusDeliverRC)
2911	\|\| !VALID_PTR(pApicReg->pszLocalInterruptRC)
2912	\|\| !VALID_PTR(pApicReg->pszGetTimerFreqRC))
2913	)
2914	{
2915	Assert(VALID_PTR(pApicReg->pszGetInterruptRC));
2916	Assert(VALID_PTR(pApicReg->pszSetBaseMsrRC));
2917	Assert(VALID_PTR(pApicReg->pszGetBaseMsrRC));
2918	Assert(VALID_PTR(pApicReg->pszSetTprRC));
2919	Assert(VALID_PTR(pApicReg->pszGetTprRC));
2920	Assert(VALID_PTR(pApicReg->pszReadMsrRC));
2921	Assert(VALID_PTR(pApicReg->pszWriteMsrRC));
2922	Assert(VALID_PTR(pApicReg->pszBusDeliverRC));
2923	Assert(VALID_PTR(pApicReg->pszLocalInterruptRC));
2924	Assert(VALID_PTR(pApicReg->pszGetTimerFreqRC));
2925	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2926	return VERR_INVALID_PARAMETER;
2927	}
2928	if ( ( pApicReg->pszGetInterruptR0
2929	\|\| pApicReg->pszSetBaseMsrR0
2930	\|\| pApicReg->pszGetBaseMsrR0
2931	\|\| pApicReg->pszSetTprR0
2932	\|\| pApicReg->pszGetTprR0
2933	\|\| pApicReg->pszWriteMsrR0
2934	\|\| pApicReg->pszReadMsrR0
2935	\|\| pApicReg->pszBusDeliverR0
2936	\|\| pApicReg->pszLocalInterruptR0
2937	\|\| pApicReg->pszGetTimerFreqR0)
2938	&& ( !VALID_PTR(pApicReg->pszGetInterruptR0)
2939	\|\| !VALID_PTR(pApicReg->pszSetBaseMsrR0)
2940	\|\| !VALID_PTR(pApicReg->pszGetBaseMsrR0)
2941	\|\| !VALID_PTR(pApicReg->pszSetTprR0)
2942	\|\| !VALID_PTR(pApicReg->pszGetTprR0)
2943	\|\| !VALID_PTR(pApicReg->pszReadMsrR0)
2944	\|\| !VALID_PTR(pApicReg->pszWriteMsrR0)
2945	\|\| !VALID_PTR(pApicReg->pszBusDeliverR0)
2946	\|\| !VALID_PTR(pApicReg->pszLocalInterruptR0)
2947	\|\| !VALID_PTR(pApicReg->pszGetTimerFreqR0))
2948	)
2949	{
2950	Assert(VALID_PTR(pApicReg->pszGetInterruptR0));
2951	Assert(VALID_PTR(pApicReg->pszSetBaseMsrR0));
2952	Assert(VALID_PTR(pApicReg->pszGetBaseMsrR0));
2953	Assert(VALID_PTR(pApicReg->pszSetTprR0));
2954	Assert(VALID_PTR(pApicReg->pszGetTprR0));
2955	Assert(VALID_PTR(pApicReg->pszReadMsrR0));
2956	Assert(VALID_PTR(pApicReg->pszWriteMsrR0));
2957	Assert(VALID_PTR(pApicReg->pszBusDeliverR0));
2958	Assert(VALID_PTR(pApicReg->pszLocalInterruptR0));
2959	Assert(VALID_PTR(pApicReg->pszGetTimerFreqR0));
2960	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (R0 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2961	return VERR_INVALID_PARAMETER;
2962	}
2963	if (!ppApicHlpR3)
2964	{
2965	Assert(ppApicHlpR3);
2966	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2967	return VERR_INVALID_PARAMETER;
2968	}
2969
2970	/*
2971	* Only one APIC device. On SMP we have single logical device covering all LAPICs,
2972	* as they need to communicate and share state easily.
2973	*/
2974	PVM pVM = pDevIns->Internal.s.pVMR3;
2975	if (pVM->pdm.s.Apic.pDevInsR3)
2976	{
2977	AssertMsgFailed(("Only one apic device is supported!\n"));
2978	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2979	return VERR_INVALID_PARAMETER;
2980	}
2981
2982	/*
2983	* Resolve & initialize the RC bits.
2984	*/
2985	if (pApicReg->pszGetInterruptRC)
2986	{
2987	int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetInterruptRC, &pVM->pdm.s.Apic.pfnGetInterruptRC);
2988	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetInterruptRC, rc));
2989	if (RT_SUCCESS(rc))
2990	{
2991	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszSetBaseMsrRC, &pVM->pdm.s.Apic.pfnSetBaseMsrRC);
2992	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszSetBaseMsrRC, rc));
2993	}
2994	if (RT_SUCCESS(rc))
2995	{
2996	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetBaseMsrRC, &pVM->pdm.s.Apic.pfnGetBaseMsrRC);
2997	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetBaseMsrRC, rc));
2998	}
2999	if (RT_SUCCESS(rc))
3000	{
3001	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszSetTprRC, &pVM->pdm.s.Apic.pfnSetTprRC);
3002	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszSetTprRC, rc));
3003	}
3004	if (RT_SUCCESS(rc))
3005	{
3006	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetTprRC, &pVM->pdm.s.Apic.pfnGetTprRC);
3007	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetTprRC, rc));
3008	}
3009	if (RT_SUCCESS(rc))
3010	{
3011	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszWriteMsrRC, &pVM->pdm.s.Apic.pfnWriteMsrRC);
3012	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszWriteMsrRC, rc));
3013	}
3014	if (RT_SUCCESS(rc))
3015	{
3016	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszReadMsrRC, &pVM->pdm.s.Apic.pfnReadMsrRC);
3017	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszReadMsrRC, rc));
3018	}
3019	if (RT_SUCCESS(rc))
3020	{
3021	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszBusDeliverRC, &pVM->pdm.s.Apic.pfnBusDeliverRC);
3022	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszBusDeliverRC, rc));
3023	}
3024	if (RT_SUCCESS(rc))
3025	{
3026	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszLocalInterruptRC, &pVM->pdm.s.Apic.pfnLocalInterruptRC);
3027	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszLocalInterruptRC, rc));
3028	}
3029	if (RT_SUCCESS(rc))
3030	{
3031	rc = pdmR3DevGetSymbolRCLazy(pDevIns, pApicReg->pszGetTimerFreqRC, &pVM->pdm.s.Apic.pfnGetTimerFreqRC);
3032	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pApicReg->pszGetTimerFreqRC, rc));
3033	}
3034	if (RT_FAILURE(rc))
3035	{
3036	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3037	return rc;
3038	}
3039	pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3040	}
3041	else
3042	{
3043	pVM->pdm.s.Apic.pDevInsRC = 0;
3044	pVM->pdm.s.Apic.pfnGetInterruptRC = 0;
3045	pVM->pdm.s.Apic.pfnSetBaseMsrRC = 0;
3046	pVM->pdm.s.Apic.pfnGetBaseMsrRC = 0;
3047	pVM->pdm.s.Apic.pfnSetTprRC = 0;
3048	pVM->pdm.s.Apic.pfnGetTprRC = 0;
3049	pVM->pdm.s.Apic.pfnWriteMsrRC = 0;
3050	pVM->pdm.s.Apic.pfnReadMsrRC = 0;
3051	pVM->pdm.s.Apic.pfnBusDeliverRC = 0;
3052	pVM->pdm.s.Apic.pfnLocalInterruptRC = 0;
3053	pVM->pdm.s.Apic.pfnGetTimerFreqRC = 0;
3054	}
3055
3056	/*
3057	* Resolve & initialize the R0 bits.
3058	*/
3059	if (pApicReg->pszGetInterruptR0)
3060	{
3061	int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetInterruptR0, &pVM->pdm.s.Apic.pfnGetInterruptR0);
3062	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetInterruptR0, rc));
3063	if (RT_SUCCESS(rc))
3064	{
3065	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszSetBaseMsrR0, &pVM->pdm.s.Apic.pfnSetBaseMsrR0);
3066	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszSetBaseMsrR0, rc));
3067	}
3068	if (RT_SUCCESS(rc))
3069	{
3070	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetBaseMsrR0, &pVM->pdm.s.Apic.pfnGetBaseMsrR0);
3071	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetBaseMsrR0, rc));
3072	}
3073	if (RT_SUCCESS(rc))
3074	{
3075	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszSetTprR0, &pVM->pdm.s.Apic.pfnSetTprR0);
3076	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszSetTprR0, rc));
3077	}
3078	if (RT_SUCCESS(rc))
3079	{
3080	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetTprR0, &pVM->pdm.s.Apic.pfnGetTprR0);
3081	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetTprR0, rc));
3082	}
3083	if (RT_SUCCESS(rc))
3084	{
3085	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszWriteMsrR0, &pVM->pdm.s.Apic.pfnWriteMsrR0);
3086	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszWriteMsrR0, rc));
3087	}
3088	if (RT_SUCCESS(rc))
3089	{
3090	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszReadMsrR0, &pVM->pdm.s.Apic.pfnReadMsrR0);
3091	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszReadMsrR0, rc));
3092	}
3093	if (RT_SUCCESS(rc))
3094	{
3095	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszBusDeliverR0, &pVM->pdm.s.Apic.pfnBusDeliverR0);
3096	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszBusDeliverR0, rc));
3097	}
3098	if (RT_SUCCESS(rc))
3099	{
3100	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszLocalInterruptR0, &pVM->pdm.s.Apic.pfnLocalInterruptR0);
3101	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszLocalInterruptR0, rc));
3102	}
3103	if (RT_SUCCESS(rc))
3104	{
3105	rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pApicReg->pszGetTimerFreqR0, &pVM->pdm.s.Apic.pfnGetTimerFreqR0);
3106	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pApicReg->pszGetTimerFreqR0, rc));
3107	}
3108	if (RT_FAILURE(rc))
3109	{
3110	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3111	return rc;
3112	}
3113	pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3114	Assert(pVM->pdm.s.Apic.pDevInsR0);
3115	}
3116	else
3117	{
3118	pVM->pdm.s.Apic.pfnGetInterruptR0 = 0;
3119	pVM->pdm.s.Apic.pfnSetBaseMsrR0 = 0;
3120	pVM->pdm.s.Apic.pfnGetBaseMsrR0 = 0;
3121	pVM->pdm.s.Apic.pfnSetTprR0 = 0;
3122	pVM->pdm.s.Apic.pfnGetTprR0 = 0;
3123	pVM->pdm.s.Apic.pfnWriteMsrR0 = 0;
3124	pVM->pdm.s.Apic.pfnReadMsrR0 = 0;
3125	pVM->pdm.s.Apic.pfnBusDeliverR0 = 0;
3126	pVM->pdm.s.Apic.pfnLocalInterruptR0 = 0;
3127	pVM->pdm.s.Apic.pfnGetTimerFreqR0 = 0;
3128	pVM->pdm.s.Apic.pDevInsR0 = 0;
3129	}
3130
3131	/*
3132	* Initialize the HC bits.
3133	*/
3134	pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
3135	pVM->pdm.s.Apic.pfnGetInterruptR3 = pApicReg->pfnGetInterruptR3;
3136	pVM->pdm.s.Apic.pfnSetBaseMsrR3 = pApicReg->pfnSetBaseMsrR3;
3137	pVM->pdm.s.Apic.pfnGetBaseMsrR3 = pApicReg->pfnGetBaseMsrR3;
3138	pVM->pdm.s.Apic.pfnSetTprR3 = pApicReg->pfnSetTprR3;
3139	pVM->pdm.s.Apic.pfnGetTprR3 = pApicReg->pfnGetTprR3;
3140	pVM->pdm.s.Apic.pfnWriteMsrR3 = pApicReg->pfnWriteMsrR3;
3141	pVM->pdm.s.Apic.pfnReadMsrR3 = pApicReg->pfnReadMsrR3;
3142	pVM->pdm.s.Apic.pfnBusDeliverR3 = pApicReg->pfnBusDeliverR3;
3143	pVM->pdm.s.Apic.pfnLocalInterruptR3 = pApicReg->pfnLocalInterruptR3;
3144	pVM->pdm.s.Apic.pfnGetTimerFreqR3 = pApicReg->pfnGetTimerFreqR3;
3145	Log(("PDM: Registered APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3146
3147	/* set the helper pointer and return. */
3148	*ppApicHlpR3 = &g_pdmR3DevApicHlp;
3149	LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3150	return VINF_SUCCESS;
3151	}
3152
3153
3154	/** @interface_method_impl{PDMDEVHLPR3,pfnIOAPICRegister} */
3155	static DECLCALLBACK(int) pdmR3DevHlp_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
3156	{
3157	PDMDEV_ASSERT_DEVINS(pDevIns);
3158	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3159	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppIoApicHlpR3=%p\n",
3160	pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrqR3,
3161	pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqR0, pIoApicReg->pszSetIrqR0, ppIoApicHlpR3));
3162
3163	/*
3164	* Validate input.
3165	*/
3166	if (pIoApicReg->u32Version != PDM_IOAPICREG_VERSION)
3167	{
3168	AssertMsgFailed(("u32Version=%#x expected %#x\n", pIoApicReg->u32Version, PDM_IOAPICREG_VERSION));
3169	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3170	return VERR_INVALID_PARAMETER;
3171	}
3172	if (!pIoApicReg->pfnSetIrqR3 \|\| !pIoApicReg->pfnSendMsiR3
3173	#ifdef VBOX_WITH_NEW_IOAPIC
3174	\|\| !pIoApicReg->pfnSetEoiR3
3175	#endif
3176	)
3177	{
3178	Assert(pIoApicReg->pfnSetIrqR3);
3179	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3180	return VERR_INVALID_PARAMETER;
3181	}
3182	if ( pIoApicReg->pszSetIrqRC
3183	&& !VALID_PTR(pIoApicReg->pszSetIrqRC))
3184	{
3185	Assert(VALID_PTR(pIoApicReg->pszSetIrqRC));
3186	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3187	return VERR_INVALID_PARAMETER;
3188	}
3189	if ( pIoApicReg->pszSendMsiRC
3190	&& !VALID_PTR(pIoApicReg->pszSendMsiRC))
3191	{
3192	Assert(VALID_PTR(pIoApicReg->pszSendMsiRC));
3193	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3194	return VERR_INVALID_PARAMETER;
3195	}
3196	if ( pIoApicReg->pszSetEoiRC
3197	&& !VALID_PTR(pIoApicReg->pszSetEoiRC))
3198	{
3199	Assert(VALID_PTR(pIoApicReg->pszSetEoiRC));
3200	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3201	return VERR_INVALID_PARAMETER;
3202	}
3203	if ( pIoApicReg->pszSetIrqR0
3204	&& !VALID_PTR(pIoApicReg->pszSetIrqR0))
3205	{
3206	Assert(VALID_PTR(pIoApicReg->pszSetIrqR0));
3207	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3208	return VERR_INVALID_PARAMETER;
3209	}
3210	if ( pIoApicReg->pszSendMsiR0
3211	&& !VALID_PTR(pIoApicReg->pszSendMsiR0))
3212	{
3213	Assert(VALID_PTR(pIoApicReg->pszSendMsiR0));
3214	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3215	return VERR_INVALID_PARAMETER;
3216	}
3217	if ( pIoApicReg->pszSetEoiR0
3218	&& !VALID_PTR(pIoApicReg->pszSetEoiR0))
3219	{
3220	Assert(VALID_PTR(pIoApicReg->pszSetEoiR0));
3221	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3222	return VERR_INVALID_PARAMETER;
3223	}
3224	if (!ppIoApicHlpR3)
3225	{
3226	Assert(ppIoApicHlpR3);
3227	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (ppApicHlp)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3228	return VERR_INVALID_PARAMETER;
3229	}
3230
3231	/*
3232	* The I/O APIC requires the APIC to be present (hacks++).
3233	* If the I/O APIC does GC stuff so must the APIC.
3234	*/
3235	PVM pVM = pDevIns->Internal.s.pVMR3;
3236	if (!pVM->pdm.s.Apic.pDevInsR3)
3237	{
3238	AssertMsgFailed(("Configuration error / Init order error! No APIC!\n"));
3239	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3240	return VERR_INVALID_PARAMETER;
3241	}
3242	if ( pIoApicReg->pszSetIrqRC
3243	&& !pVM->pdm.s.Apic.pDevInsRC)
3244	{
3245	AssertMsgFailed(("Configuration error! APIC doesn't do GC, I/O APIC does!\n"));
3246	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no GC APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3247	return VERR_INVALID_PARAMETER;
3248	}
3249
3250	/*
3251	* Only one I/O APIC device.
3252	*/
3253	if (pVM->pdm.s.IoApic.pDevInsR3)
3254	{
3255	AssertMsgFailed(("Only one ioapic device is supported!\n"));
3256	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (only one)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3257	return VERR_INVALID_PARAMETER;
3258	}
3259
3260	/*
3261	* Resolve & initialize the GC bits.
3262	*/
3263	if (pIoApicReg->pszSetIrqRC)
3264	{
3265	int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetIrqRC, &pVM->pdm.s.IoApic.pfnSetIrqRC);
3266	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetIrqRC, rc));
3267	if (RT_FAILURE(rc))
3268	{
3269	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3270	return rc;
3271	}
3272	pVM->pdm.s.IoApic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3273	}
3274	else
3275	{
3276	pVM->pdm.s.IoApic.pDevInsRC = 0;
3277	pVM->pdm.s.IoApic.pfnSetIrqRC = 0;
3278	}
3279
3280	if (pIoApicReg->pszSendMsiRC)
3281	{
3282	int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSendMsiRC, &pVM->pdm.s.IoApic.pfnSendMsiRC);
3283	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSendMsiRC, rc));
3284	if (RT_FAILURE(rc))
3285	{
3286	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3287	return rc;
3288	}
3289	}
3290	else
3291	{
3292	pVM->pdm.s.IoApic.pfnSendMsiRC = 0;
3293	}
3294
3295	if (pIoApicReg->pszSetEoiRC)
3296	{
3297	int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetEoiRC, &pVM->pdm.s.IoApic.pfnSetEoiRC);
3298	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetEoiRC, rc));
3299	if (RT_FAILURE(rc))
3300	{
3301	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3302	return rc;
3303	}
3304	}
3305	else
3306	{
3307	pVM->pdm.s.IoApic.pfnSetEoiRC = 0;
3308	}
3309
3310	/*
3311	* Resolve & initialize the R0 bits.
3312	*/
3313	if (pIoApicReg->pszSetIrqR0)
3314	{
3315	int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetIrqR0, &pVM->pdm.s.IoApic.pfnSetIrqR0);
3316	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetIrqR0, rc));
3317	if (RT_FAILURE(rc))
3318	{
3319	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3320	return rc;
3321	}
3322	pVM->pdm.s.IoApic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3323	Assert(pVM->pdm.s.IoApic.pDevInsR0);
3324	}
3325	else
3326	{
3327	pVM->pdm.s.IoApic.pfnSetIrqR0 = 0;
3328	pVM->pdm.s.IoApic.pDevInsR0 = 0;
3329	}
3330
3331	if (pIoApicReg->pszSendMsiR0)
3332	{
3333	int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSendMsiR0, &pVM->pdm.s.IoApic.pfnSendMsiR0);
3334	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSendMsiR0, rc));
3335	if (RT_FAILURE(rc))
3336	{
3337	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3338	return rc;
3339	}
3340	}
3341	else
3342	{
3343	pVM->pdm.s.IoApic.pfnSendMsiR0 = 0;
3344	}
3345
3346	if (pIoApicReg->pszSetEoiR0)
3347	{
3348	int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetEoiR0, &pVM->pdm.s.IoApic.pfnSetEoiR0);
3349	AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetEoiR0, rc));
3350	if (RT_FAILURE(rc))
3351	{
3352	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3353	return rc;
3354	}
3355	}
3356	else
3357	{
3358	pVM->pdm.s.IoApic.pfnSetEoiR0 = 0;
3359	}
3360
3361
3362	/*
3363	* Initialize the R3 bits.
3364	*/
3365	pVM->pdm.s.IoApic.pDevInsR3 = pDevIns;
3366	pVM->pdm.s.IoApic.pfnSetIrqR3 = pIoApicReg->pfnSetIrqR3;
3367	pVM->pdm.s.IoApic.pfnSendMsiR3 = pIoApicReg->pfnSendMsiR3;
3368	pVM->pdm.s.IoApic.pfnSetEoiR3 = pIoApicReg->pfnSetEoiR3;
3369	Log(("PDM: Registered I/O APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3370
3371	/* set the helper pointer and return. */
3372	*ppIoApicHlpR3 = &g_pdmR3DevIoApicHlp;
3373	LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3374	return VINF_SUCCESS;
3375	}
3376
3377
3378	/** @interface_method_impl{PDMDEVHLPR3,pfnHPETRegister} */
3379	static DECLCALLBACK(int) pdmR3DevHlp_HPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
3380	{
3381	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
3382	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3383	LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3384
3385	/*
3386	* Validate input.
3387	*/
3388	if (pHpetReg->u32Version != PDM_HPETREG_VERSION)
3389	{
3390	AssertMsgFailed(("u32Version=%#x expected %#x\n", pHpetReg->u32Version, PDM_HPETREG_VERSION));
3391	LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3392	return VERR_INVALID_PARAMETER;
3393	}
3394
3395	if (!ppHpetHlpR3)
3396	{
3397	Assert(ppHpetHlpR3);
3398	LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3399	return VERR_INVALID_PARAMETER;
3400	}
3401
3402	/* set the helper pointer and return. */
3403	*ppHpetHlpR3 = &g_pdmR3DevHpetHlp;
3404	LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3405	return VINF_SUCCESS;
3406	}
3407
3408
3409	/** @interface_method_impl{PDMDEVHLPR3,pfnPciRawRegister} */
3410	static DECLCALLBACK(int) pdmR3DevHlp_PciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
3411	{
3412	PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
3413	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3414	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3415
3416	/*
3417	* Validate input.
3418	*/
3419	if (pPciRawReg->u32Version != PDM_PCIRAWREG_VERSION)
3420	{
3421	AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciRawReg->u32Version, PDM_PCIRAWREG_VERSION));
3422	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3423	return VERR_INVALID_PARAMETER;
3424	}
3425
3426	if (!ppPciRawHlpR3)
3427	{
3428	Assert(ppPciRawHlpR3);
3429	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3430	return VERR_INVALID_PARAMETER;
3431	}
3432
3433	/* set the helper pointer and return. */
3434	*ppPciRawHlpR3 = &g_pdmR3DevPciRawHlp;
3435	LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3436	return VINF_SUCCESS;
3437	}
3438
3439
3440	/** @interface_method_impl{PDMDEVHLPR3,pfnDMACRegister} */
3441	static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
3442	{
3443	PDMDEV_ASSERT_DEVINS(pDevIns);
3444	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3445	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n",
3446	pDevIns->pReg->szName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister,
3447	pDmacReg->pfnReadMemory, pDmacReg->pfnWriteMemory, pDmacReg->pfnSetDREQ, pDmacReg->pfnGetChannelMode, ppDmacHlp));
3448
3449	/*
3450	* Validate input.
3451	*/
3452	if (pDmacReg->u32Version != PDM_DMACREG_VERSION)
3453	{
3454	AssertMsgFailed(("u32Version=%#x expected %#x\n", pDmacReg->u32Version,
3455	PDM_DMACREG_VERSION));
3456	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (version)\n",
3457	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3458	return VERR_INVALID_PARAMETER;
3459	}
3460	if ( !pDmacReg->pfnRun
3461	\|\| !pDmacReg->pfnRegister
3462	\|\| !pDmacReg->pfnReadMemory
3463	\|\| !pDmacReg->pfnWriteMemory
3464	\|\| !pDmacReg->pfnSetDREQ
3465	\|\| !pDmacReg->pfnGetChannelMode)
3466	{
3467	Assert(pDmacReg->pfnRun);
3468	Assert(pDmacReg->pfnRegister);
3469	Assert(pDmacReg->pfnReadMemory);
3470	Assert(pDmacReg->pfnWriteMemory);
3471	Assert(pDmacReg->pfnSetDREQ);
3472	Assert(pDmacReg->pfnGetChannelMode);
3473	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3474	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3475	return VERR_INVALID_PARAMETER;
3476	}
3477
3478	if (!ppDmacHlp)
3479	{
3480	Assert(ppDmacHlp);
3481	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (ppDmacHlp)\n",
3482	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3483	return VERR_INVALID_PARAMETER;
3484	}
3485
3486	/*
3487	* Only one DMA device.
3488	*/
3489	PVM pVM = pDevIns->Internal.s.pVMR3;
3490	if (pVM->pdm.s.pDmac)
3491	{
3492	AssertMsgFailed(("Only one DMA device is supported!\n"));
3493	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3494	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3495	return VERR_INVALID_PARAMETER;
3496	}
3497
3498	/*
3499	* Allocate and initialize pci bus structure.
3500	*/
3501	int rc = VINF_SUCCESS;
3502	PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac));
3503	if (pDmac)
3504	{
3505	pDmac->pDevIns = pDevIns;
3506	pDmac->Reg = *pDmacReg;
3507	pVM->pdm.s.pDmac = pDmac;
3508
3509	/* set the helper pointer. */
3510	*ppDmacHlp = &g_pdmR3DevDmacHlp;
3511	Log(("PDM: Registered DMAC device '%s'/%d pDevIns=%p\n",
3512	pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3513	}
3514	else
3515	rc = VERR_NO_MEMORY;
3516
3517	LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3518	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3519	return rc;
3520	}
3521
3522
3523	/**
3524	* @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
3525	*/
3526	static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
3527	{
3528	PDMDEV_ASSERT_DEVINS(pDevIns);
3529	PVM pVM = pDevIns->Internal.s.pVMR3;
3530	VM_ASSERT_EMT(pVM);
3531	LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: GCPhys=%RGp pvHeap=%p cbHeap=%#x\n",
3532	pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvHeap, cbHeap));
3533
3534	if (pVM->pdm.s.pvVMMDevHeap == NULL)
3535	{
3536	pVM->pdm.s.pvVMMDevHeap = pvHeap;
3537	pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
3538	pVM->pdm.s.cbVMMDevHeap = cbHeap;
3539	pVM->pdm.s.cbVMMDevHeapLeft = cbHeap;
3540	}
3541	else
3542	{
3543	Assert(pVM->pdm.s.pvVMMDevHeap == pvHeap);
3544	Assert(pVM->pdm.s.cbVMMDevHeap == cbHeap);
3545	Assert(pVM->pdm.s.GCPhysVMMDevHeap != GCPhys \|\| GCPhys == NIL_RTGCPHYS);
3546	if (pVM->pdm.s.GCPhysVMMDevHeap != GCPhys)
3547	{
3548	pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
3549	if (pVM->pdm.s.pfnVMMDevHeapNotify)
3550	pVM->pdm.s.pfnVMMDevHeapNotify(pVM, pvHeap, GCPhys);
3551	}
3552	}
3553
3554	LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: returns %Rrc\n",
3555	pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3556	return VINF_SUCCESS;
3557	}
3558
3559
3560	/**
3561	* @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister}
3562	*/
3563	static DECLCALLBACK(int) pdmR3DevHlp_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
3564	{
3565	PDMDEV_ASSERT_DEVINS(pDevIns);
3566	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3567	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: pFWReg=%p:{.u32Version=%#x, .pfnIsHardReset=%p, .u32TheEnd=%#x} ppFwHlp=%p\n",
3568	pDevIns->pReg->szName, pDevIns->iInstance, pFwReg, pFwReg->u32Version, pFwReg->pfnIsHardReset, pFwReg->u32TheEnd, ppFwHlp));
3569
3570	/*
3571	* Validate input.
3572	*/
3573	if (pFwReg->u32Version != PDM_FWREG_VERSION)
3574	{
3575	AssertMsgFailed(("u32Version=%#x expected %#x\n", pFwReg->u32Version, PDM_FWREG_VERSION));
3576	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (version)\n",
3577	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3578	return VERR_INVALID_PARAMETER;
3579	}
3580	if (!pFwReg->pfnIsHardReset)
3581	{
3582	Assert(pFwReg->pfnIsHardReset);
3583	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3584	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3585	return VERR_INVALID_PARAMETER;
3586	}
3587
3588	if (!ppFwHlp)
3589	{
3590	Assert(ppFwHlp);
3591	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (ppFwHlp)\n",
3592	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3593	return VERR_INVALID_PARAMETER;
3594	}
3595
3596	/*
3597	* Only one DMA device.
3598	*/
3599	PVM pVM = pDevIns->Internal.s.pVMR3;
3600	if (pVM->pdm.s.pFirmware)
3601	{
3602	AssertMsgFailed(("Only one firmware device is supported!\n"));
3603	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
3604	pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3605	return VERR_INVALID_PARAMETER;
3606	}
3607
3608	/*
3609	* Allocate and initialize pci bus structure.
3610	*/
3611	int rc = VINF_SUCCESS;
3612	PPDMFW pFirmware = (PPDMFW)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pFirmware));
3613	if (pFirmware)
3614	{
3615	pFirmware->pDevIns = pDevIns;
3616	pFirmware->Reg = *pFwReg;
3617	pVM->pdm.s.pFirmware = pFirmware;
3618
3619	/* set the helper pointer. */
3620	*ppFwHlp = &g_pdmR3DevFirmwareHlp;
3621	Log(("PDM: Registered firmware device '%s'/%d pDevIns=%p\n",
3622	pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3623	}
3624	else
3625	rc = VERR_NO_MEMORY;
3626
3627	LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
3628	pDevIns->pReg->szName, pDevIns->iInstance, rc));
3629	return rc;
3630	}
3631
3632
3633	/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3634	static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
3635	{
3636	PDMDEV_ASSERT_DEVINS(pDevIns);
3637	PVM pVM = pDevIns->Internal.s.pVMR3;
3638	VM_ASSERT_EMT(pVM);
3639	LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: fFlags=%#x VM_FF_RESET %d -> 1\n",
3640	pDevIns->pReg->szName, pDevIns->iInstance, fFlags, VM_FF_IS_SET(pVM, VM_FF_RESET)));
3641
3642	/*
3643	* We postpone this operation because we're likely to be inside a I/O instruction
3644	* and the EIP will be updated when we return.
3645	* We still return VINF_EM_RESET to break out of any execution loops and force FF evaluation.
3646	*/
3647	bool fHaltOnReset;
3648	int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
3649	if (RT_SUCCESS(rc) && fHaltOnReset)
3650	{
3651	Log(("pdmR3DevHlp_VMReset: Halt On Reset!\n"));
3652	rc = VINF_EM_HALT;
3653	}
3654	else
3655	{
3656	pVM->pdm.s.fResetFlags = fFlags;
3657	VM_FF_SET(pVM, VM_FF_RESET);
3658	rc = VINF_EM_RESET;
3659	}
3660
3661	LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3662	return rc;
3663	}
3664
3665
3666	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3667	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns)
3668	{
3669	int rc;
3670	PDMDEV_ASSERT_DEVINS(pDevIns);
3671	PVM pVM = pDevIns->Internal.s.pVMR3;
3672	VM_ASSERT_EMT(pVM);
3673	LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n",
3674	pDevIns->pReg->szName, pDevIns->iInstance));
3675
3676	/** @todo Always take the SMP path - fewer code paths. */
3677	if (pVM->cCpus > 1)
3678	{
3679	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
3680	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3Suspend, 2, pVM->pUVM, VMSUSPENDREASON_VM);
3681	AssertRC(rc);
3682	rc = VINF_EM_SUSPEND;
3683	}
3684	else
3685	rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
3686
3687	LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3688	return rc;
3689	}
3690
3691
3692	/**
3693	* Worker for pdmR3DevHlp_VMSuspendSaveAndPowerOff that is invoked via a queued
3694	* EMT request to avoid deadlocks.
3695	*
3696	* @returns VBox status code fit for scheduling.
3697	* @param pVM The cross context VM structure.
3698	* @param pDevIns The device that triggered this action.
3699	*/
3700	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker(PVM pVM, PPDMDEVINS pDevIns)
3701	{
3702	/*
3703	* Suspend the VM first then do the saving.
3704	*/
3705	int rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
3706	if (RT_SUCCESS(rc))
3707	{
3708	PUVM pUVM = pVM->pUVM;
3709	rc = pUVM->pVmm2UserMethods->pfnSaveState(pVM->pUVM->pVmm2UserMethods, pUVM);
3710
3711	/*
3712	* On success, power off the VM, on failure we'll leave it suspended.
3713	*/
3714	if (RT_SUCCESS(rc))
3715	{
3716	rc = VMR3PowerOff(pVM->pUVM);
3717	if (RT_FAILURE(rc))
3718	LogRel(("%s/SSP: VMR3PowerOff failed: %Rrc\n", pDevIns->pReg->szName, rc));
3719	}
3720	else
3721	LogRel(("%s/SSP: pfnSaveState failed: %Rrc\n", pDevIns->pReg->szName, rc));
3722	}
3723	else
3724	LogRel(("%s/SSP: Suspend failed: %Rrc\n", pDevIns->pReg->szName, rc));
3725	return rc;
3726	}
3727
3728
3729	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3730	static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3731	{
3732	PDMDEV_ASSERT_DEVINS(pDevIns);
3733	PVM pVM = pDevIns->Internal.s.pVMR3;
3734	VM_ASSERT_EMT(pVM);
3735	LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d:\n",
3736	pDevIns->pReg->szName, pDevIns->iInstance));
3737
3738	int rc;
3739	if ( pVM->pUVM->pVmm2UserMethods
3740	&& pVM->pUVM->pVmm2UserMethods->pfnSaveState)
3741	{
3742	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker, 2, pVM, pDevIns);
3743	if (RT_SUCCESS(rc))
3744	{
3745	LogRel(("%s: Suspending, Saving and Powering Off the VM\n", pDevIns->pReg->szName));
3746	rc = VINF_EM_SUSPEND;
3747	}
3748	}
3749	else
3750	rc = VERR_NOT_SUPPORTED;
3751
3752	LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3753	return rc;
3754	}
3755
3756
3757	/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3758	static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns)
3759	{
3760	int rc;
3761	PDMDEV_ASSERT_DEVINS(pDevIns);
3762	PVM pVM = pDevIns->Internal.s.pVMR3;
3763	VM_ASSERT_EMT(pVM);
3764	LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n",
3765	pDevIns->pReg->szName, pDevIns->iInstance));
3766
3767	/** @todo Always take the SMP path - fewer code paths. */
3768	if (pVM->cCpus > 1)
3769	{
3770	/* We might be holding locks here and could cause a deadlock since
3771	VMR3PowerOff rendezvous with the other CPUs. */
3772	rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3PowerOff, 1, pVM->pUVM);
3773	AssertRC(rc);
3774	/* Set the VCPU state to stopped here as well to make sure no
3775	inconsistency with the EM state occurs. */
3776	VMCPU_SET_STATE(VMMGetCpu(pVM), VMCPUSTATE_STOPPED);
3777	rc = VINF_EM_OFF;
3778	}
3779	else
3780	rc = VMR3PowerOff(pVM->pUVM);
3781
3782	LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3783	return rc;
3784	}
3785
3786
3787	/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3788	static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
3789	{
3790	PDMDEV_ASSERT_DEVINS(pDevIns);
3791	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3792
3793	bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));
3794
3795	LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pReg->szName, pDevIns->iInstance, fRc));
3796	return fRc;
3797	}
3798
3799
3800	/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3801	static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3802	{
3803	PDMDEV_ASSERT_DEVINS(pDevIns);
3804	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3805	LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, fEnable));
3806	PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
3807	}
3808
3809
3810	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3811	static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3812	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
3813	{
3814	PDMDEV_ASSERT_DEVINS(pDevIns);
3815	VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3816
3817	LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: iLeaf=%d pEax=%p pEbx=%p pEcx=%p pEdx=%p\n",
3818	pDevIns->pReg->szName, pDevIns->iInstance, iLeaf, pEax, pEbx, pEcx, pEdx));
3819	AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx);
3820
3821	CPUMGetGuestCpuId(VMMGetCpu(pDevIns->Internal.s.pVMR3), iLeaf, 0 /iSubLeaf/, pEax, pEbx, pEcx, pEdx);
3822
3823	LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - pEax=%#x pEbx=%#x pEcx=%#x pEdx=%#x\n",
3824	pDevIns->pReg->szName, pDevIns->iInstance, pEax, pEbx, pEcx, pEdx));
3825	}
3826
3827
3828	/**
3829	* The device helper structure for trusted devices.
3830	*/
3831	const PDMDEVHLPR3 g_pdmR3DevHlpTrusted =
3832	{
3833	PDM_DEVHLPR3_VERSION,
3834	pdmR3DevHlp_IOPortRegister,
3835	pdmR3DevHlp_IOPortRegisterRC,
3836	pdmR3DevHlp_IOPortRegisterR0,
3837	pdmR3DevHlp_IOPortDeregister,
3838	pdmR3DevHlp_MMIORegister,
3839	pdmR3DevHlp_MMIORegisterRC,
3840	pdmR3DevHlp_MMIORegisterR0,
3841	pdmR3DevHlp_MMIODeregister,
3842	pdmR3DevHlp_MMIO2Register,
3843	pdmR3DevHlp_MMIOExPreRegister,
3844	pdmR3DevHlp_MMIOExDeregister,
3845	pdmR3DevHlp_MMIOExMap,
3846	pdmR3DevHlp_MMIOExUnmap,
3847	pdmR3DevHlp_MMHyperMapMMIO2,
3848	pdmR3DevHlp_MMIO2MapKernel,
3849	pdmR3DevHlp_ROMRegister,
3850	pdmR3DevHlp_ROMProtectShadow,
3851	pdmR3DevHlp_SSMRegister,
3852	pdmR3DevHlp_TMTimerCreate,
3853	pdmR3DevHlp_TMUtcNow,
3854	pdmR3DevHlp_PhysRead,
3855	pdmR3DevHlp_PhysWrite,
3856	pdmR3DevHlp_PhysGCPhys2CCPtr,
3857	pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
3858	pdmR3DevHlp_PhysReleasePageMappingLock,
3859	pdmR3DevHlp_PhysReadGCVirt,
3860	pdmR3DevHlp_PhysWriteGCVirt,
3861	pdmR3DevHlp_PhysGCPtr2GCPhys,
3862	pdmR3DevHlp_MMHeapAlloc,
3863	pdmR3DevHlp_MMHeapAllocZ,
3864	pdmR3DevHlp_MMHeapFree,
3865	pdmR3DevHlp_VMState,
3866	pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
3867	pdmR3DevHlp_VMSetError,
3868	pdmR3DevHlp_VMSetErrorV,
3869	pdmR3DevHlp_VMSetRuntimeError,
3870	pdmR3DevHlp_VMSetRuntimeErrorV,
3871	pdmR3DevHlp_DBGFStopV,
3872	pdmR3DevHlp_DBGFInfoRegister,
3873	pdmR3DevHlp_DBGFRegRegister,
3874	pdmR3DevHlp_DBGFTraceBuf,
3875	pdmR3DevHlp_STAMRegister,
3876	pdmR3DevHlp_STAMRegisterF,
3877	pdmR3DevHlp_STAMRegisterV,
3878	pdmR3DevHlp_PCIRegister,
3879	pdmR3DevHlp_PCIRegisterMsi,
3880	pdmR3DevHlp_PCIIORegionRegister,
3881	pdmR3DevHlp_PCISetConfigCallbacks,
3882	pdmR3DevHlp_PCIPhysRead,
3883	pdmR3DevHlp_PCIPhysWrite,
3884	pdmR3DevHlp_PCISetIrq,
3885	pdmR3DevHlp_PCISetIrqNoWait,
3886	pdmR3DevHlp_ISASetIrq,
3887	pdmR3DevHlp_ISASetIrqNoWait,
3888	pdmR3DevHlp_DriverAttach,
3889	pdmR3DevHlp_DriverDetach,
3890	pdmR3DevHlp_QueueCreate,
3891	pdmR3DevHlp_CritSectInit,
3892	pdmR3DevHlp_CritSectGetNop,
3893	pdmR3DevHlp_CritSectGetNopR0,
3894	pdmR3DevHlp_CritSectGetNopRC,
3895	pdmR3DevHlp_SetDeviceCritSect,
3896	pdmR3DevHlp_ThreadCreate,
3897	pdmR3DevHlp_SetAsyncNotification,
3898	pdmR3DevHlp_AsyncNotificationCompleted,
3899	pdmR3DevHlp_RTCRegister,
3900	pdmR3DevHlp_PCIBusRegister,
3901	pdmR3DevHlp_PICRegister,
3902	pdmR3DevHlp_APICRegister,
3903	pdmR3DevHlp_IOAPICRegister,
3904	pdmR3DevHlp_HPETRegister,
3905	pdmR3DevHlp_PciRawRegister,
3906	pdmR3DevHlp_DMACRegister,
3907	pdmR3DevHlp_DMARegister,
3908	pdmR3DevHlp_DMAReadMemory,
3909	pdmR3DevHlp_DMAWriteMemory,
3910	pdmR3DevHlp_DMASetDREQ,
3911	pdmR3DevHlp_DMAGetChannelMode,
3912	pdmR3DevHlp_DMASchedule,
3913	pdmR3DevHlp_CMOSWrite,
3914	pdmR3DevHlp_CMOSRead,
3915	pdmR3DevHlp_AssertEMT,
3916	pdmR3DevHlp_AssertOther,
3917	pdmR3DevHlp_LdrGetRCInterfaceSymbols,
3918	pdmR3DevHlp_LdrGetR0InterfaceSymbols,
3919	pdmR3DevHlp_CallR0,
3920	pdmR3DevHlp_VMGetSuspendReason,
3921	pdmR3DevHlp_VMGetResumeReason,
3922	0,
3923	0,
3924	0,
3925	0,
3926	0,
3927	0,
3928	0,
3929	0,
3930	0,
3931	0,
3932	pdmR3DevHlp_GetUVM,
3933	pdmR3DevHlp_GetVM,
3934	pdmR3DevHlp_GetVMCPU,
3935	pdmR3DevHlp_GetCurrentCpuId,
3936	pdmR3DevHlp_RegisterVMMDevHeap,
3937	pdmR3DevHlp_FirmwareRegister,
3938	pdmR3DevHlp_VMReset,
3939	pdmR3DevHlp_VMSuspend,
3940	pdmR3DevHlp_VMSuspendSaveAndPowerOff,
3941	pdmR3DevHlp_VMPowerOff,
3942	pdmR3DevHlp_A20IsEnabled,
3943	pdmR3DevHlp_A20Set,
3944	pdmR3DevHlp_GetCpuId,
3945	pdmR3DevHlp_TMTimeVirtGet,
3946	pdmR3DevHlp_TMTimeVirtGetFreq,
3947	pdmR3DevHlp_TMTimeVirtGetNano,
3948	pdmR3DevHlp_GetSupDrvSession,
3949	PDM_DEVHLPR3_VERSION /* the end */
3950	};
3951
3952
3953
3954
3955	/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
3956	static DECLCALLBACK(PUVM) pdmR3DevHlp_Untrusted_GetUVM(PPDMDEVINS pDevIns)
3957	{
3958	PDMDEV_ASSERT_DEVINS(pDevIns);
3959	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3960	return NULL;
3961	}
3962
3963
3964	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
3965	static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)
3966	{
3967	PDMDEV_ASSERT_DEVINS(pDevIns);
3968	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3969	return NULL;
3970	}
3971
3972
3973	/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
3974	static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)
3975	{
3976	PDMDEV_ASSERT_DEVINS(pDevIns);
3977	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3978	return NULL;
3979	}
3980
3981
3982	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
3983	static DECLCALLBACK(VMCPUID) pdmR3DevHlp_Untrusted_GetCurrentCpuId(PPDMDEVINS pDevIns)
3984	{
3985	PDMDEV_ASSERT_DEVINS(pDevIns);
3986	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3987	return NIL_VMCPUID;
3988	}
3989
3990
3991	/** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */
3992	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
3993	RTR3PTR pvHeap, unsigned cbHeap)
3994	{
3995	PDMDEV_ASSERT_DEVINS(pDevIns);
3996	NOREF(GCPhys); NOREF(pvHeap); NOREF(cbHeap);
3997	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3998	return VERR_ACCESS_DENIED;
3999	}
4000
4001
4002	/** @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister} */
4003	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
4004	{
4005	PDMDEV_ASSERT_DEVINS(pDevIns);
4006	NOREF(pFwReg); NOREF(ppFwHlp);
4007	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4008	return VERR_ACCESS_DENIED;
4009	}
4010
4011
4012	/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
4013	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
4014	{
4015	PDMDEV_ASSERT_DEVINS(pDevIns); NOREF(fFlags);
4016	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4017	return VERR_ACCESS_DENIED;
4018	}
4019
4020
4021	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
4022	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)
4023	{
4024	PDMDEV_ASSERT_DEVINS(pDevIns);
4025	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4026	return VERR_ACCESS_DENIED;
4027	}
4028
4029
4030	/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
4031	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
4032	{
4033	PDMDEV_ASSERT_DEVINS(pDevIns);
4034	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4035	return VERR_ACCESS_DENIED;
4036	}
4037
4038
4039	/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
4040	static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)
4041	{
4042	PDMDEV_ASSERT_DEVINS(pDevIns);
4043	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4044	return VERR_ACCESS_DENIED;
4045	}
4046
4047
4048	/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
4049	static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)
4050	{
4051	PDMDEV_ASSERT_DEVINS(pDevIns);
4052	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4053	return false;
4054	}
4055
4056
4057	/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
4058	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)
4059	{
4060	PDMDEV_ASSERT_DEVINS(pDevIns);
4061	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4062	NOREF(fEnable);
4063	}
4064
4065
4066	/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
4067	static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
4068	uint32_t pEax, uint32_t pEbx, uint32_t pEcx, uint32_t pEdx)
4069	{
4070	PDMDEV_ASSERT_DEVINS(pDevIns);
4071	NOREF(iLeaf); NOREF(pEax); NOREF(pEbx); NOREF(pEcx); NOREF(pEdx);
4072	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4073	}
4074
4075
4076	/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
4077	static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_Untrusted_GetSupDrvSession(PPDMDEVINS pDevIns)
4078	{
4079	PDMDEV_ASSERT_DEVINS(pDevIns);
4080	AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
4081	return (PSUPDRVSESSION)0;
4082	}
4083
4084
4085	/**
4086	* The device helper structure for non-trusted devices.
4087	*/
4088	const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =
4089	{
4090	PDM_DEVHLPR3_VERSION,
4091	pdmR3DevHlp_IOPortRegister,
4092	pdmR3DevHlp_IOPortRegisterRC,
4093	pdmR3DevHlp_IOPortRegisterR0,
4094	pdmR3DevHlp_IOPortDeregister,
4095	pdmR3DevHlp_MMIORegister,
4096	pdmR3DevHlp_MMIORegisterRC,
4097	pdmR3DevHlp_MMIORegisterR0,
4098	pdmR3DevHlp_MMIODeregister,
4099	pdmR3DevHlp_MMIO2Register,
4100	pdmR3DevHlp_MMIOExPreRegister,
4101	pdmR3DevHlp_MMIOExDeregister,
4102	pdmR3DevHlp_MMIOExMap,
4103	pdmR3DevHlp_MMIOExUnmap,
4104	pdmR3DevHlp_MMHyperMapMMIO2,
4105	pdmR3DevHlp_MMIO2MapKernel,
4106	pdmR3DevHlp_ROMRegister,
4107	pdmR3DevHlp_ROMProtectShadow,
4108	pdmR3DevHlp_SSMRegister,
4109	pdmR3DevHlp_TMTimerCreate,
4110	pdmR3DevHlp_TMUtcNow,
4111	pdmR3DevHlp_PhysRead,
4112	pdmR3DevHlp_PhysWrite,
4113	pdmR3DevHlp_PhysGCPhys2CCPtr,
4114	pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
4115	pdmR3DevHlp_PhysReleasePageMappingLock,
4116	pdmR3DevHlp_PhysReadGCVirt,
4117	pdmR3DevHlp_PhysWriteGCVirt,
4118	pdmR3DevHlp_PhysGCPtr2GCPhys,
4119	pdmR3DevHlp_MMHeapAlloc,
4120	pdmR3DevHlp_MMHeapAllocZ,
4121	pdmR3DevHlp_MMHeapFree,
4122	pdmR3DevHlp_VMState,
4123	pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
4124	pdmR3DevHlp_VMSetError,
4125	pdmR3DevHlp_VMSetErrorV,
4126	pdmR3DevHlp_VMSetRuntimeError,
4127	pdmR3DevHlp_VMSetRuntimeErrorV,
4128	pdmR3DevHlp_DBGFStopV,
4129	pdmR3DevHlp_DBGFInfoRegister,
4130	pdmR3DevHlp_DBGFRegRegister,
4131	pdmR3DevHlp_DBGFTraceBuf,
4132	pdmR3DevHlp_STAMRegister,
4133	pdmR3DevHlp_STAMRegisterF,
4134	pdmR3DevHlp_STAMRegisterV,
4135	pdmR3DevHlp_PCIRegister,
4136	pdmR3DevHlp_PCIRegisterMsi,
4137	pdmR3DevHlp_PCIIORegionRegister,
4138	pdmR3DevHlp_PCISetConfigCallbacks,
4139	pdmR3DevHlp_PCIPhysRead,
4140	pdmR3DevHlp_PCIPhysWrite,
4141	pdmR3DevHlp_PCISetIrq,
4142	pdmR3DevHlp_PCISetIrqNoWait,
4143	pdmR3DevHlp_ISASetIrq,
4144	pdmR3DevHlp_ISASetIrqNoWait,
4145	pdmR3DevHlp_DriverAttach,
4146	pdmR3DevHlp_DriverDetach,
4147	pdmR3DevHlp_QueueCreate,
4148	pdmR3DevHlp_CritSectInit,
4149	pdmR3DevHlp_CritSectGetNop,
4150	pdmR3DevHlp_CritSectGetNopR0,
4151	pdmR3DevHlp_CritSectGetNopRC,
4152	pdmR3DevHlp_SetDeviceCritSect,
4153	pdmR3DevHlp_ThreadCreate,
4154	pdmR3DevHlp_SetAsyncNotification,
4155	pdmR3DevHlp_AsyncNotificationCompleted,
4156	pdmR3DevHlp_RTCRegister,
4157	pdmR3DevHlp_PCIBusRegister,
4158	pdmR3DevHlp_PICRegister,
4159	pdmR3DevHlp_APICRegister,
4160	pdmR3DevHlp_IOAPICRegister,
4161	pdmR3DevHlp_HPETRegister,
4162	pdmR3DevHlp_PciRawRegister,
4163	pdmR3DevHlp_DMACRegister,
4164	pdmR3DevHlp_DMARegister,
4165	pdmR3DevHlp_DMAReadMemory,
4166	pdmR3DevHlp_DMAWriteMemory,
4167	pdmR3DevHlp_DMASetDREQ,
4168	pdmR3DevHlp_DMAGetChannelMode,
4169	pdmR3DevHlp_DMASchedule,
4170	pdmR3DevHlp_CMOSWrite,
4171	pdmR3DevHlp_CMOSRead,
4172	pdmR3DevHlp_AssertEMT,
4173	pdmR3DevHlp_AssertOther,
4174	pdmR3DevHlp_LdrGetRCInterfaceSymbols,
4175	pdmR3DevHlp_LdrGetR0InterfaceSymbols,
4176	pdmR3DevHlp_CallR0,
4177	pdmR3DevHlp_VMGetSuspendReason,
4178	pdmR3DevHlp_VMGetResumeReason,
4179	0,
4180	0,
4181	0,
4182	0,
4183	0,
4184	0,
4185	0,
4186	0,
4187	0,
4188	0,
4189	pdmR3DevHlp_Untrusted_GetUVM,
4190	pdmR3DevHlp_Untrusted_GetVM,
4191	pdmR3DevHlp_Untrusted_GetVMCPU,
4192	pdmR3DevHlp_Untrusted_GetCurrentCpuId,
4193	pdmR3DevHlp_Untrusted_RegisterVMMDevHeap,
4194	pdmR3DevHlp_Untrusted_FirmwareRegister,
4195	pdmR3DevHlp_Untrusted_VMReset,
4196	pdmR3DevHlp_Untrusted_VMSuspend,
4197	pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff,
4198	pdmR3DevHlp_Untrusted_VMPowerOff,
4199	pdmR3DevHlp_Untrusted_A20IsEnabled,
4200	pdmR3DevHlp_Untrusted_A20Set,
4201	pdmR3DevHlp_Untrusted_GetCpuId,
4202	pdmR3DevHlp_TMTimeVirtGet,
4203	pdmR3DevHlp_TMTimeVirtGetFreq,
4204	pdmR3DevHlp_TMTimeVirtGetNano,
4205	pdmR3DevHlp_Untrusted_GetSupDrvSession,
4206	PDM_DEVHLPR3_VERSION /* the end */
4207	};
4208
4209
4210
4211	/**
4212	* Queue consumer callback for internal component.
4213	*
4214	* @returns Success indicator.
4215	* If false the item will not be removed and the flushing will stop.
4216	* @param pVM The cross context VM structure.
4217	* @param pItem The item to consume. Upon return this item will be freed.
4218	*/
4219	DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem)
4220	{
4221	PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)pItem;
4222	LogFlow(("pdmR3DevHlpQueueConsumer: enmOp=%d pDevIns=%p\n", pTask->enmOp, pTask->pDevInsR3));
4223	switch (pTask->enmOp)
4224	{
4225	case PDMDEVHLPTASKOP_ISA_SET_IRQ:
4226	PDMIsaSetIrq(pVM, pTask->u.IsaSetIRQ.iIrq, pTask->u.IsaSetIRQ.iLevel, pTask->u.IsaSetIRQ.uTagSrc);
4227	break;
4228
4229	case PDMDEVHLPTASKOP_PCI_SET_IRQ:
4230	{
4231	/* Same as pdmR3DevHlp_PCISetIrq, except we've got a tag already. */
4232	PPDMPCIDEV pPciDev = pTask->u.PciSetIRQ.pPciDevR3;
4233	if (pPciDev)
4234	{
4235	PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
4236	Assert(pBus);
4237
4238	pdmLock(pVM);
4239	pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, pTask->u.PciSetIRQ.iIrq,
4240	pTask->u.PciSetIRQ.iLevel, pTask->u.PciSetIRQ.uTagSrc);
4241	pdmUnlock(pVM);
4242	}
4243	else
4244	AssertReleaseMsgFailed(("No PCI device registered!\n"));
4245	break;
4246	}
4247
4248	case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ:
4249	PDMIoApicSetIrq(pVM, pTask->u.IoApicSetIRQ.iIrq, pTask->u.IoApicSetIRQ.iLevel, pTask->u.IoApicSetIRQ.uTagSrc);
4250	break;
4251
4252	default:
4253	AssertReleaseMsgFailed(("Invalid operation %d\n", pTask->enmOp));
4254	break;
4255	}
4256	return true;
4257	}
4258
4259	/** @} */
4260

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source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp@ 64551

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