VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevHlp.cpp@ 68993

Last change on this file since 68993 was 68993, checked in by vboxsync, 7 years ago

VMM/PDMDevHlp.cpp: Build fix.
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1/* $Id: PDMDevHlp.cpp 68993 2017-10-05 13:54:29Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#define PDMPCIDEV_INCLUDE_PRIVATE /* Hack to get pdmpcidevint.h included at the right point. */
24#include "PDMInternal.h"
25#include <VBox/vmm/pdm.h>
26#include <VBox/vmm/mm.h>
27#include <VBox/vmm/hm.h>
28#include <VBox/vmm/pgm.h>
29#include <VBox/vmm/iom.h>
30#ifdef VBOX_WITH_REM
31# include <VBox/vmm/rem.h>
32#endif
33#include <VBox/vmm/dbgf.h>
34#include <VBox/vmm/vmapi.h>
35#include <VBox/vmm/vm.h>
36#include <VBox/vmm/uvm.h>
37#include <VBox/vmm/vmm.h>
38
39#include <VBox/version.h>
40#include <VBox/log.h>
41#include <VBox/err.h>
42#include <iprt/asm.h>
43#include <iprt/assert.h>
44#include <iprt/ctype.h>
45#include <iprt/string.h>
46#include <iprt/thread.h>
47
48#include "dtrace/VBoxVMM.h"
49#include "PDMInline.h"
50
51
52/*********************************************************************************************************************************
53* Defined Constants And Macros *
54*********************************************************************************************************************************/
55/** @def PDM_DEVHLP_DEADLOCK_DETECTION
56 * Define this to enable the deadlock detection when accessing physical memory.
57 */
58#if /*defined(DEBUG_bird) ||*/ defined(DOXYGEN_RUNNING)
59# define PDM_DEVHLP_DEADLOCK_DETECTION /**< @todo enable DevHlp deadlock detection! */
60#endif
61
62
63
64/**
65 * Wrapper around PDMR3LdrGetSymbolRCLazy.
66 */
67DECLINLINE(int) pdmR3DevGetSymbolRCLazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTRCPTR ppvValue)
68{
69 PVM pVM = pDevIns->Internal.s.pVMR3;
70 if (HMIsEnabled(pVM))
71 {
72 *ppvValue = NIL_RTRCPTR;
73 return VINF_SUCCESS;
74 }
75 return PDMR3LdrGetSymbolRCLazy(pVM,
76 pDevIns->Internal.s.pDevR3->pReg->szRCMod,
77 pDevIns->Internal.s.pDevR3->pszRCSearchPath,
78 pszSymbol, ppvValue);
79}
80
81
82/**
83 * Wrapper around PDMR3LdrGetSymbolR0Lazy.
84 */
85DECLINLINE(int) pdmR3DevGetSymbolR0Lazy(PPDMDEVINS pDevIns, const char *pszSymbol, PRTR0PTR ppvValue)
86{
87 return PDMR3LdrGetSymbolR0Lazy(pDevIns->Internal.s.pVMR3,
88 pDevIns->Internal.s.pDevR3->pReg->szR0Mod,
89 pDevIns->Internal.s.pDevR3->pszR0SearchPath,
90 pszSymbol, ppvValue);
91}
92
93
94/** @name R3 DevHlp
95 * @{
96 */
97
98
99/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegister} */
100static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTHCPTR pvUser, PFNIOMIOPORTOUT pfnOut, PFNIOMIOPORTIN pfnIn,
101 PFNIOMIOPORTOUTSTRING pfnOutStr, PFNIOMIOPORTINSTRING pfnInStr, const char *pszDesc)
102{
103 PDMDEV_ASSERT_DEVINS(pDevIns);
104 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pfnOut=%p pfnIn=%p pfnOutStr=%p pfnInStr=%p p32_tszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
105 Port, cPorts, pvUser, pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc, pszDesc));
106 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
107
108#if 0 /** @todo needs a real string cache for this */
109 if (pDevIns->iInstance > 0)
110 {
111 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
112 if (pszDesc2)
113 pszDesc = pszDesc2;
114 }
115#endif
116
117 int rc = IOMR3IOPortRegisterR3(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser,
118 pfnOut, pfnIn, pfnOutStr, pfnInStr, pszDesc);
119
120 LogFlow(("pdmR3DevHlp_IOPortRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
121 return rc;
122}
123
124
125/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterRC} */
126static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterRC(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTRCPTR pvUser,
127 const char *pszOut, const char *pszIn,
128 const char *pszOutStr, const char *pszInStr, const char *pszDesc)
129{
130 PDMDEV_ASSERT_DEVINS(pDevIns);
131 PVM pVM = pDevIns->Internal.s.pVMR3;
132 VM_ASSERT_EMT(pVM);
133 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
134 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
135
136 /*
137 * Resolve the functions (one of the can be NULL).
138 */
139 int rc = VINF_SUCCESS;
140 if ( pDevIns->pReg->szRCMod[0]
141 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
142 && !HMIsEnabled(pVM))
143 {
144 RTRCPTR RCPtrIn = NIL_RTRCPTR;
145 if (pszIn)
146 {
147 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszIn, &RCPtrIn);
148 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szRCMod, pszIn));
149 }
150 RTRCPTR RCPtrOut = NIL_RTRCPTR;
151 if (pszOut && RT_SUCCESS(rc))
152 {
153 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOut, &RCPtrOut);
154 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szRCMod, pszOut));
155 }
156 RTRCPTR RCPtrInStr = NIL_RTRCPTR;
157 if (pszInStr && RT_SUCCESS(rc))
158 {
159 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszInStr, &RCPtrInStr);
160 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szRCMod, pszInStr));
161 }
162 RTRCPTR RCPtrOutStr = NIL_RTRCPTR;
163 if (pszOutStr && RT_SUCCESS(rc))
164 {
165 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszOutStr, &RCPtrOutStr);
166 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szRCMod, pszOutStr));
167 }
168
169 if (RT_SUCCESS(rc))
170 {
171#if 0 /** @todo needs a real string cache for this */
172 if (pDevIns->iInstance > 0)
173 {
174 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
175 if (pszDesc2)
176 pszDesc = pszDesc2;
177 }
178#endif
179
180 rc = IOMR3IOPortRegisterRC(pVM, pDevIns, Port, cPorts, pvUser, RCPtrOut, RCPtrIn, RCPtrOutStr, RCPtrInStr, pszDesc);
181 }
182 }
183 else if (!HMIsEnabled(pVM))
184 {
185 AssertMsgFailed(("No RC module for this driver!\n"));
186 rc = VERR_INVALID_PARAMETER;
187 }
188
189 LogFlow(("pdmR3DevHlp_IOPortRegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
190 return rc;
191}
192
193
194/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortRegisterR0} */
195static DECLCALLBACK(int) pdmR3DevHlp_IOPortRegisterR0(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts, RTR0PTR pvUser,
196 const char *pszOut, const char *pszIn,
197 const char *pszOutStr, const char *pszInStr, const char *pszDesc)
198{
199 PDMDEV_ASSERT_DEVINS(pDevIns);
200 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
201 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: Port=%#x cPorts=%#x pvUser=%p pszOut=%p:{%s} pszIn=%p:{%s} pszOutStr=%p:{%s} pszInStr=%p:{%s} pszDesc=%p:{%s}\n", pDevIns->pReg->szName, pDevIns->iInstance,
202 Port, cPorts, pvUser, pszOut, pszOut, pszIn, pszIn, pszOutStr, pszOutStr, pszInStr, pszInStr, pszDesc, pszDesc));
203
204 /*
205 * Resolve the functions (one of the can be NULL).
206 */
207 int rc = VINF_SUCCESS;
208 if ( pDevIns->pReg->szR0Mod[0]
209 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
210 {
211 R0PTRTYPE(PFNIOMIOPORTIN) pfnR0PtrIn = 0;
212 if (pszIn)
213 {
214 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszIn, &pfnR0PtrIn);
215 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszIn)\n", pDevIns->pReg->szR0Mod, pszIn));
216 }
217 R0PTRTYPE(PFNIOMIOPORTOUT) pfnR0PtrOut = 0;
218 if (pszOut && RT_SUCCESS(rc))
219 {
220 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOut, &pfnR0PtrOut);
221 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOut)\n", pDevIns->pReg->szR0Mod, pszOut));
222 }
223 R0PTRTYPE(PFNIOMIOPORTINSTRING) pfnR0PtrInStr = 0;
224 if (pszInStr && RT_SUCCESS(rc))
225 {
226 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszInStr, &pfnR0PtrInStr);
227 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszInStr)\n", pDevIns->pReg->szR0Mod, pszInStr));
228 }
229 R0PTRTYPE(PFNIOMIOPORTOUTSTRING) pfnR0PtrOutStr = 0;
230 if (pszOutStr && RT_SUCCESS(rc))
231 {
232 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszOutStr, &pfnR0PtrOutStr);
233 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszOutStr)\n", pDevIns->pReg->szR0Mod, pszOutStr));
234 }
235
236 if (RT_SUCCESS(rc))
237 {
238#if 0 /** @todo needs a real string cache for this */
239 if (pDevIns->iInstance > 0)
240 {
241 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
242 if (pszDesc2)
243 pszDesc = pszDesc2;
244 }
245#endif
246
247 rc = IOMR3IOPortRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts, pvUser, pfnR0PtrOut, pfnR0PtrIn, pfnR0PtrOutStr, pfnR0PtrInStr, pszDesc);
248 }
249 }
250 else
251 {
252 AssertMsgFailed(("No R0 module for this driver!\n"));
253 rc = VERR_INVALID_PARAMETER;
254 }
255
256 LogFlow(("pdmR3DevHlp_IOPortRegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
257 return rc;
258}
259
260
261/** @interface_method_impl{PDMDEVHLPR3,pfnIOPortDeregister} */
262static DECLCALLBACK(int) pdmR3DevHlp_IOPortDeregister(PPDMDEVINS pDevIns, RTIOPORT Port, RTIOPORT cPorts)
263{
264 PDMDEV_ASSERT_DEVINS(pDevIns);
265 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
266 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: Port=%#x cPorts=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance,
267 Port, cPorts));
268
269 int rc = IOMR3IOPortDeregister(pDevIns->Internal.s.pVMR3, pDevIns, Port, cPorts);
270
271 LogFlow(("pdmR3DevHlp_IOPortDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
272 return rc;
273}
274
275
276/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegister} */
277static DECLCALLBACK(int) pdmR3DevHlp_MMIORegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTHCPTR pvUser,
278 PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
279 uint32_t fFlags, const char *pszDesc)
280{
281 PDMDEV_ASSERT_DEVINS(pDevIns);
282 PVM pVM = pDevIns->Internal.s.pVMR3;
283 VM_ASSERT_EMT(pVM);
284 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p fFlags=%#x pszDesc=%p:{%s}\n",
285 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pfnWrite, pfnRead, pfnFill, pszDesc, fFlags, pszDesc));
286
287 if (pDevIns->iInstance > 0)
288 {
289 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
290 if (pszDesc2)
291 pszDesc = pszDesc2;
292 }
293
294 int rc = IOMR3MmioRegisterR3(pVM, pDevIns, GCPhysStart, cbRange, pvUser,
295 pfnWrite, pfnRead, pfnFill, fFlags, pszDesc);
296
297 LogFlow(("pdmR3DevHlp_MMIORegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
298 return rc;
299}
300
301
302/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterRC} */
303static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterRC(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTRCPTR pvUser,
304 const char *pszWrite, const char *pszRead, const char *pszFill)
305{
306 PDMDEV_ASSERT_DEVINS(pDevIns);
307 PVM pVM = pDevIns->Internal.s.pVMR3;
308 VM_ASSERT_EMT(pVM);
309 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
310 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
311
312
313 /*
314 * Resolve the functions.
315 * Not all function have to present, leave it to IOM to enforce this.
316 */
317 int rc = VINF_SUCCESS;
318 if ( pDevIns->pReg->szRCMod[0]
319 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
320 && !HMIsEnabled(pVM))
321 {
322 RTRCPTR RCPtrWrite = NIL_RTRCPTR;
323 if (pszWrite)
324 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWrite, &RCPtrWrite);
325
326 RTRCPTR RCPtrRead = NIL_RTRCPTR;
327 int rc2 = VINF_SUCCESS;
328 if (pszRead)
329 rc2 = pdmR3DevGetSymbolRCLazy(pDevIns, pszRead, &RCPtrRead);
330
331 RTRCPTR RCPtrFill = NIL_RTRCPTR;
332 int rc3 = VINF_SUCCESS;
333 if (pszFill)
334 rc3 = pdmR3DevGetSymbolRCLazy(pDevIns, pszFill, &RCPtrFill);
335
336 if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
337 rc = IOMR3MmioRegisterRC(pVM, pDevIns, GCPhysStart, cbRange, pvUser, RCPtrWrite, RCPtrRead, RCPtrFill);
338 else
339 {
340 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szRCMod, pszWrite));
341 AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szRCMod, pszRead));
342 AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szRCMod, pszFill));
343 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
344 rc = rc2;
345 if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
346 rc = rc3;
347 }
348 }
349 else if (!HMIsEnabled(pVM))
350 {
351 AssertMsgFailed(("No RC module for this driver!\n"));
352 rc = VERR_INVALID_PARAMETER;
353 }
354
355 LogFlow(("pdmR3DevHlp_MMIORegisterRC: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
356 return rc;
357}
358
359/** @interface_method_impl{PDMDEVHLPR3,pfnMMIORegisterR0} */
360static DECLCALLBACK(int) pdmR3DevHlp_MMIORegisterR0(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange, RTR0PTR pvUser,
361 const char *pszWrite, const char *pszRead, const char *pszFill)
362{
363 PDMDEV_ASSERT_DEVINS(pDevIns);
364 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
365 LogFlow(("pdmR3DevHlp_MMIORegisterHC: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp pvUser=%p pszWrite=%p:{%s} pszRead=%p:{%s} pszFill=%p:{%s}\n",
366 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvUser, pszWrite, pszWrite, pszRead, pszRead, pszFill, pszFill));
367
368 /*
369 * Resolve the functions.
370 * Not all function have to present, leave it to IOM to enforce this.
371 */
372 int rc = VINF_SUCCESS;
373 if ( pDevIns->pReg->szR0Mod[0]
374 && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
375 {
376 R0PTRTYPE(PFNIOMMMIOWRITE) pfnR0PtrWrite = 0;
377 if (pszWrite)
378 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWrite, &pfnR0PtrWrite);
379 R0PTRTYPE(PFNIOMMMIOREAD) pfnR0PtrRead = 0;
380 int rc2 = VINF_SUCCESS;
381 if (pszRead)
382 rc2 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszRead, &pfnR0PtrRead);
383 R0PTRTYPE(PFNIOMMMIOFILL) pfnR0PtrFill = 0;
384 int rc3 = VINF_SUCCESS;
385 if (pszFill)
386 rc3 = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFill, &pfnR0PtrFill);
387 if (RT_SUCCESS(rc) && RT_SUCCESS(rc2) && RT_SUCCESS(rc3))
388 rc = IOMR3MmioRegisterR0(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvUser,
389 pfnR0PtrWrite, pfnR0PtrRead, pfnR0PtrFill);
390 else
391 {
392 AssertMsgRC(rc, ("Failed to resolve %s.%s (pszWrite)\n", pDevIns->pReg->szR0Mod, pszWrite));
393 AssertMsgRC(rc2, ("Failed to resolve %s.%s (pszRead)\n", pDevIns->pReg->szR0Mod, pszRead));
394 AssertMsgRC(rc3, ("Failed to resolve %s.%s (pszFill)\n", pDevIns->pReg->szR0Mod, pszFill));
395 if (RT_FAILURE(rc2) && RT_SUCCESS(rc))
396 rc = rc2;
397 if (RT_FAILURE(rc3) && RT_SUCCESS(rc))
398 rc = rc3;
399 }
400 }
401 else
402 {
403 AssertMsgFailed(("No R0 module for this driver!\n"));
404 rc = VERR_INVALID_PARAMETER;
405 }
406
407 LogFlow(("pdmR3DevHlp_MMIORegisterR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
408 return rc;
409}
410
411
412/** @interface_method_impl{PDMDEVHLPR3,pfnMMIODeregister} */
413static DECLCALLBACK(int) pdmR3DevHlp_MMIODeregister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, RTGCPHYS cbRange)
414{
415 PDMDEV_ASSERT_DEVINS(pDevIns);
416 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
417 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%RGp\n",
418 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange));
419
420 int rc = IOMR3MmioDeregister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange);
421
422 LogFlow(("pdmR3DevHlp_MMIODeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
423 return rc;
424}
425
426
427/**
428 * @copydoc PDMDEVHLPR3::pfnMMIO2Register
429 */
430static DECLCALLBACK(int) pdmR3DevHlp_MMIO2Register(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cb,
431 uint32_t fFlags, void **ppv, const char *pszDesc)
432{
433 PDMDEV_ASSERT_DEVINS(pDevIns);
434 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
435 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: pPciDev=%p (%#x) iRegion=%#x cb=%#RGp fFlags=%RX32 ppv=%p pszDescp=%p:{%s}\n",
436 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion,
437 cb, fFlags, ppv, pszDesc, pszDesc));
438 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
439
440/** @todo PGMR3PhysMMIO2Register mangles the description, move it here and
441 * use a real string cache. */
442 int rc = PGMR3PhysMMIO2Register(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion,
443 cb, fFlags, ppv, pszDesc);
444
445 LogFlow(("pdmR3DevHlp_MMIO2Register: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
446 return rc;
447}
448
449
450/**
451 * @interface_method_impl{PDMDEVHLPR3,pfnMMIOExPreRegister}
452 */
453static DECLCALLBACK(int)
454pdmR3DevHlp_MMIOExPreRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion, uint32_t fFlags,
455 const char *pszDesc,
456 RTHCPTR pvUser, PFNIOMMMIOWRITE pfnWrite, PFNIOMMMIOREAD pfnRead, PFNIOMMMIOFILL pfnFill,
457 RTR0PTR pvUserR0, const char *pszWriteR0, const char *pszReadR0, const char *pszFillR0,
458 RTRCPTR pvUserRC, const char *pszWriteRC, const char *pszReadRC, const char *pszFillRC)
459{
460 PDMDEV_ASSERT_DEVINS(pDevIns);
461 PVM pVM = pDevIns->Internal.s.pVMR3;
462 VM_ASSERT_EMT(pVM);
463 LogFlow(("pdmR3DevHlp_MMIOExPreRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x cbRegion=%#RGp fFlags=%RX32 pszDesc=%p:{%s}\n"
464 " pvUser=%p pfnWrite=%p pfnRead=%p pfnFill=%p\n"
465 " pvUserR0=%p pszWriteR0=%s pszReadR0=%s pszFillR0=%s\n"
466 " pvUserRC=%p pszWriteRC=%s pszReadRC=%s pszFillRC=%s\n",
467 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, cbRegion,
468 fFlags, pszDesc, pszDesc,
469 pvUser, pfnWrite, pfnRead, pfnFill,
470 pvUserR0, pszWriteR0, pszReadR0, pszFillR0,
471 pvUserRC, pszWriteRC, pszReadRC, pszFillRC));
472 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
473
474 /*
475 * Resolve the functions.
476 */
477 AssertLogRelReturn( (!pszWriteR0 && !pszReadR0 && !pszFillR0)
478 || (pDevIns->pReg->szR0Mod[0] && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)),
479 VERR_INVALID_PARAMETER);
480 AssertLogRelReturn( (!pszWriteRC && !pszReadRC && !pszFillRC)
481 || (pDevIns->pReg->szRCMod[0] && (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)),
482 VERR_INVALID_PARAMETER);
483
484 /* Ring-0 */
485 int rc;
486 R0PTRTYPE(PFNIOMMMIOWRITE) pfnWriteR0 = 0;
487 if (pszWriteR0)
488 {
489 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszWriteR0, &pfnWriteR0);
490 AssertLogRelMsgRCReturn(rc, ("pszWriteR0=%s rc=%Rrc\n", pszWriteR0, rc), rc);
491 }
492
493 R0PTRTYPE(PFNIOMMMIOREAD) pfnReadR0 = 0;
494 if (pszReadR0)
495 {
496 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszReadR0, &pfnReadR0);
497 AssertLogRelMsgRCReturn(rc, ("pszReadR0=%s rc=%Rrc\n", pszReadR0, rc), rc);
498 }
499 R0PTRTYPE(PFNIOMMMIOFILL) pfnFillR0 = 0;
500 if (pszFillR0)
501 {
502 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pszFillR0, &pfnFillR0);
503 AssertLogRelMsgRCReturn(rc, ("pszFillR0=%s rc=%Rrc\n", pszFillR0, rc), rc);
504 }
505
506 /* Raw-mode */
507 rc = VINF_SUCCESS;
508 RCPTRTYPE(PFNIOMMMIOWRITE) pfnWriteRC = 0;
509 if (pszWriteRC)
510 {
511 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszWriteRC, &pfnWriteRC);
512 AssertLogRelMsgRCReturn(rc, ("pszWriteRC=%s rc=%Rrc\n", pszWriteRC, rc), rc);
513 }
514
515 RCPTRTYPE(PFNIOMMMIOREAD) pfnReadRC = 0;
516 if (pszReadRC)
517 {
518 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszReadRC, &pfnReadRC);
519 AssertLogRelMsgRCReturn(rc, ("pszReadRC=%s rc=%Rrc\n", pszReadRC, rc), rc);
520 }
521 RCPTRTYPE(PFNIOMMMIOFILL) pfnFillRC = 0;
522 if (pszFillRC)
523 {
524 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pszFillRC, &pfnFillRC);
525 AssertLogRelMsgRCReturn(rc, ("pszFillRC=%s rc=%Rrc\n", pszFillRC, rc), rc);
526 }
527
528 /*
529 * Call IOM to make the registration.
530 */
531 rc = IOMR3MmioExPreRegister(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, cbRegion, fFlags, pszDesc,
532 pvUser, pfnWrite, pfnRead, pfnFill,
533 pvUserR0, pfnWriteR0, pfnReadR0, pfnFillR0,
534 pvUserRC, pfnWriteRC, pfnReadRC, pfnFillRC);
535
536 LogFlow(("pdmR3DevHlp_MMIOExPreRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
537 return rc;
538}
539
540
541/**
542 * @copydoc PDMDEVHLPR3::pfnMMIOExDeregister
543 */
544static DECLCALLBACK(int) pdmR3DevHlp_MMIOExDeregister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion)
545{
546 PDMDEV_ASSERT_DEVINS(pDevIns);
547 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
548 LogFlow(("pdmR3DevHlp_MMIOExDeregister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x\n",
549 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion));
550
551 AssertReturn(iRegion <= UINT8_MAX || iRegion == UINT32_MAX, VERR_INVALID_PARAMETER);
552 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
553
554 int rc = PGMR3PhysMMIOExDeregister(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion);
555
556 LogFlow(("pdmR3DevHlp_MMIOExDeregister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
557 return rc;
558}
559
560
561/**
562 * @copydoc PDMDEVHLPR3::pfnMMIOExMap
563 */
564static DECLCALLBACK(int) pdmR3DevHlp_MMIOExMap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
565{
566 PDMDEV_ASSERT_DEVINS(pDevIns);
567 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
568 LogFlow(("pdmR3DevHlp_MMIOExMap: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x GCPhys=%#RGp\n",
569 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, GCPhys));
570 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
571
572 int rc = PGMR3PhysMMIOExMap(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, GCPhys);
573
574 LogFlow(("pdmR3DevHlp_MMIOExMap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
575 return rc;
576}
577
578
579/**
580 * @copydoc PDMDEVHLPR3::pfnMMIOExUnmap
581 */
582static DECLCALLBACK(int) pdmR3DevHlp_MMIOExUnmap(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS GCPhys)
583{
584 PDMDEV_ASSERT_DEVINS(pDevIns);
585 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
586 LogFlow(("pdmR3DevHlp_MMIOExUnmap: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x GCPhys=%#RGp\n",
587 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, GCPhys));
588 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
589
590 int rc = PGMR3PhysMMIOExUnmap(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, GCPhys);
591
592 LogFlow(("pdmR3DevHlp_MMIOExUnmap: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
593 return rc;
594}
595
596
597/**
598 * @copydoc PDMDEVHLPR3::pfnMMIOExReduce
599 */
600static DECLCALLBACK(int) pdmR3DevHlp_MMIOExReduce(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS cbRegion)
601{
602 PDMDEV_ASSERT_DEVINS(pDevIns);
603 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
604 LogFlow(("pdmR3DevHlp_MMIOExReduce: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x cbRegion=%RGp\n",
605 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, cbRegion));
606 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 != NULL, VERR_INVALID_PARAMETER);
607
608 int rc = PGMR3PhysMMIOExReduce(pDevIns->Internal.s.pVMR3, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, cbRegion);
609
610 LogFlow(("pdmR3DevHlp_MMIOExReduce: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
611 return rc;
612}
613
614
615/**
616 * @copydoc PDMDEVHLPR3::pfnMMHyperMapMMIO2
617 */
618static DECLCALLBACK(int) pdmR3DevHlp_MMHyperMapMMIO2(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
619 RTGCPHYS cb, const char *pszDesc, PRTRCPTR pRCPtr)
620{
621 PDMDEV_ASSERT_DEVINS(pDevIns);
622 PVM pVM = pDevIns->Internal.s.pVMR3;
623 VM_ASSERT_EMT(pVM);
624 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pRCPtr=%p\n",
625 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, off, cb, pszDesc, pszDesc, pRCPtr));
626 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
627
628 if (pDevIns->iInstance > 0)
629 {
630 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
631 if (pszDesc2)
632 pszDesc = pszDesc2;
633 }
634
635 int rc = MMR3HyperMapMMIO2(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, off, cb, pszDesc, pRCPtr);
636
637 LogFlow(("pdmR3DevHlp_MMHyperMapMMIO2: caller='%s'/%d: returns %Rrc *pRCPtr=%RRv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pRCPtr));
638 return rc;
639}
640
641
642/**
643 * @copydoc PDMDEVHLPR3::pfnMMIO2MapKernel
644 */
645static DECLCALLBACK(int) pdmR3DevHlp_MMIO2MapKernel(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion, RTGCPHYS off,
646 RTGCPHYS cb,const char *pszDesc, PRTR0PTR pR0Ptr)
647{
648 PDMDEV_ASSERT_DEVINS(pDevIns);
649 PVM pVM = pDevIns->Internal.s.pVMR3;
650 VM_ASSERT_EMT(pVM);
651 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%#x off=%RGp cb=%RGp pszDesc=%p:{%s} pR0Ptr=%p\n",
652 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev ? pPciDev->uDevFn : UINT32_MAX, iRegion, off, cb, pszDesc, pszDesc, pR0Ptr));
653 AssertReturn(!pPciDev || pPciDev->Int.s.pDevInsR3 == pDevIns, VERR_INVALID_PARAMETER);
654
655 if (pDevIns->iInstance > 0)
656 {
657 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
658 if (pszDesc2)
659 pszDesc = pszDesc2;
660 }
661
662 int rc = PGMR3PhysMMIO2MapKernel(pVM, pDevIns, pPciDev ? pPciDev->Int.s.idxDevCfg : 254, iRegion, off, cb, pszDesc, pR0Ptr);
663
664 LogFlow(("pdmR3DevHlp_MMIO2MapKernel: caller='%s'/%d: returns %Rrc *pR0Ptr=%RHv\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pR0Ptr));
665 return rc;
666}
667
668
669/** @interface_method_impl{PDMDEVHLPR3,pfnROMRegister} */
670static DECLCALLBACK(int) pdmR3DevHlp_ROMRegister(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange,
671 const void *pvBinary, uint32_t cbBinary, uint32_t fFlags, const char *pszDesc)
672{
673 PDMDEV_ASSERT_DEVINS(pDevIns);
674 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
675 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x pvBinary=%p cbBinary=%#x fFlags=%#RX32 pszDesc=%p:{%s}\n",
676 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc, pszDesc));
677
678/** @todo can we mangle pszDesc? */
679 int rc = PGMR3PhysRomRegister(pDevIns->Internal.s.pVMR3, pDevIns, GCPhysStart, cbRange, pvBinary, cbBinary, fFlags, pszDesc);
680
681 LogFlow(("pdmR3DevHlp_ROMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
682 return rc;
683}
684
685
686/** @interface_method_impl{PDMDEVHLPR3,pfnROMProtectShadow} */
687static DECLCALLBACK(int) pdmR3DevHlp_ROMProtectShadow(PPDMDEVINS pDevIns, RTGCPHYS GCPhysStart, uint32_t cbRange, PGMROMPROT enmProt)
688{
689 PDMDEV_ASSERT_DEVINS(pDevIns);
690 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: GCPhysStart=%RGp cbRange=%#x enmProt=%d\n",
691 pDevIns->pReg->szName, pDevIns->iInstance, GCPhysStart, cbRange, enmProt));
692
693 int rc = PGMR3PhysRomProtect(pDevIns->Internal.s.pVMR3, GCPhysStart, cbRange, enmProt);
694
695 LogFlow(("pdmR3DevHlp_ROMProtectShadow: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
696 return rc;
697}
698
699
700/** @interface_method_impl{PDMDEVHLPR3,pfnSSMRegister} */
701static DECLCALLBACK(int) pdmR3DevHlp_SSMRegister(PPDMDEVINS pDevIns, uint32_t uVersion, size_t cbGuess, const char *pszBefore,
702 PFNSSMDEVLIVEPREP pfnLivePrep, PFNSSMDEVLIVEEXEC pfnLiveExec, PFNSSMDEVLIVEVOTE pfnLiveVote,
703 PFNSSMDEVSAVEPREP pfnSavePrep, PFNSSMDEVSAVEEXEC pfnSaveExec, PFNSSMDEVSAVEDONE pfnSaveDone,
704 PFNSSMDEVLOADPREP pfnLoadPrep, PFNSSMDEVLOADEXEC pfnLoadExec, PFNSSMDEVLOADDONE pfnLoadDone)
705{
706 PDMDEV_ASSERT_DEVINS(pDevIns);
707 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
708 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: uVersion=%#x cbGuess=%#x pszBefore=%p:{%s}\n"
709 " pfnLivePrep=%p pfnLiveExec=%p pfnLiveVote=%p pfnSavePrep=%p pfnSaveExec=%p pfnSaveDone=%p pszLoadPrep=%p pfnLoadExec=%p pfnLoadDone=%p\n",
710 pDevIns->pReg->szName, pDevIns->iInstance, uVersion, cbGuess, pszBefore, pszBefore,
711 pfnLivePrep, pfnLiveExec, pfnLiveVote,
712 pfnSavePrep, pfnSaveExec, pfnSaveDone,
713 pfnLoadPrep, pfnLoadExec, pfnLoadDone));
714
715 int rc = SSMR3RegisterDevice(pDevIns->Internal.s.pVMR3, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance,
716 uVersion, cbGuess, pszBefore,
717 pfnLivePrep, pfnLiveExec, pfnLiveVote,
718 pfnSavePrep, pfnSaveExec, pfnSaveDone,
719 pfnLoadPrep, pfnLoadExec, pfnLoadDone);
720
721 LogFlow(("pdmR3DevHlp_SSMRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
722 return rc;
723}
724
725
726/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimerCreate} */
727static DECLCALLBACK(int) pdmR3DevHlp_TMTimerCreate(PPDMDEVINS pDevIns, TMCLOCK enmClock, PFNTMTIMERDEV pfnCallback, void *pvUser, uint32_t fFlags, const char *pszDesc, PPTMTIMERR3 ppTimer)
728{
729 PDMDEV_ASSERT_DEVINS(pDevIns);
730 PVM pVM = pDevIns->Internal.s.pVMR3;
731 VM_ASSERT_EMT(pVM);
732 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: enmClock=%d pfnCallback=%p pvUser=%p fFlags=%#x pszDesc=%p:{%s} ppTimer=%p\n",
733 pDevIns->pReg->szName, pDevIns->iInstance, enmClock, pfnCallback, pvUser, fFlags, pszDesc, pszDesc, ppTimer));
734
735 if (pDevIns->iInstance > 0) /** @todo use a string cache here later. */
736 {
737 char *pszDesc2 = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s [%u]", pszDesc, pDevIns->iInstance);
738 if (pszDesc2)
739 pszDesc = pszDesc2;
740 }
741
742 int rc = TMR3TimerCreateDevice(pVM, pDevIns, enmClock, pfnCallback, pvUser, fFlags, pszDesc, ppTimer);
743
744 LogFlow(("pdmR3DevHlp_TMTimerCreate: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
745 return rc;
746}
747
748
749/** @interface_method_impl{PDMDEVHLPR3,pfnTMUtcNow} */
750static DECLCALLBACK(PRTTIMESPEC) pdmR3DevHlp_TMUtcNow(PPDMDEVINS pDevIns, PRTTIMESPEC pTime)
751{
752 PDMDEV_ASSERT_DEVINS(pDevIns);
753 LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: pTime=%p\n",
754 pDevIns->pReg->szName, pDevIns->iInstance, pTime));
755
756 pTime = TMR3UtcNow(pDevIns->Internal.s.pVMR3, pTime);
757
758 LogFlow(("pdmR3DevHlp_TMUtcNow: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, RTTimeSpecGetNano(pTime)));
759 return pTime;
760}
761
762
763/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGet} */
764static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGet(PPDMDEVINS pDevIns)
765{
766 PDMDEV_ASSERT_DEVINS(pDevIns);
767 LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d\n",
768 pDevIns->pReg->szName, pDevIns->iInstance));
769
770 uint64_t u64Time = TMVirtualSyncGet(pDevIns->Internal.s.pVMR3);
771
772 LogFlow(("pdmR3DevHlp_TMTimeVirtGet: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Time));
773 return u64Time;
774}
775
776
777/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetFreq} */
778static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetFreq(PPDMDEVINS pDevIns)
779{
780 PDMDEV_ASSERT_DEVINS(pDevIns);
781 LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d\n",
782 pDevIns->pReg->szName, pDevIns->iInstance));
783
784 uint64_t u64Freq = TMVirtualGetFreq(pDevIns->Internal.s.pVMR3);
785
786 LogFlow(("pdmR3DevHlp_TMTimeVirtGetFreq: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Freq));
787 return u64Freq;
788}
789
790
791/** @interface_method_impl{PDMDEVHLPR3,pfnTMTimeVirtGetNano} */
792static DECLCALLBACK(uint64_t) pdmR3DevHlp_TMTimeVirtGetNano(PPDMDEVINS pDevIns)
793{
794 PDMDEV_ASSERT_DEVINS(pDevIns);
795 LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d\n",
796 pDevIns->pReg->szName, pDevIns->iInstance));
797
798 uint64_t u64Time = TMVirtualGet(pDevIns->Internal.s.pVMR3);
799 uint64_t u64Nano = TMVirtualToNano(pDevIns->Internal.s.pVMR3, u64Time);
800
801 LogFlow(("pdmR3DevHlp_TMTimeVirtGetNano: caller='%s'/%d: returns %RU64\n", pDevIns->pReg->szName, pDevIns->iInstance, u64Nano));
802 return u64Nano;
803}
804
805
806/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
807static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_GetSupDrvSession(PPDMDEVINS pDevIns)
808{
809 PDMDEV_ASSERT_DEVINS(pDevIns);
810 LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d\n",
811 pDevIns->pReg->szName, pDevIns->iInstance));
812
813 PSUPDRVSESSION pSession = pDevIns->Internal.s.pVMR3->pSession;
814
815 LogFlow(("pdmR3DevHlp_GetSupDrvSession: caller='%s'/%d: returns %#p\n", pDevIns->pReg->szName, pDevIns->iInstance, pSession));
816 return pSession;
817}
818
819
820/** @interface_method_impl{PDMDEVHLPR3,pfnQueryGenericUserObject} */
821static DECLCALLBACK(void *) pdmR3DevHlp_QueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
822{
823 PDMDEV_ASSERT_DEVINS(pDevIns);
824 LogFlow(("pdmR3DevHlp_QueryGenericUserObject: caller='%s'/%d: pUuid=%p:%RTuuid\n",
825 pDevIns->pReg->szName, pDevIns->iInstance, pUuid, pUuid));
826
827#if defined(DEBUG_bird) || defined(DEBUG_ramshankar) || defined(DEBUG_sunlover) || defined(DEBUG_michael) || defined(DEBUG_andy)
828 AssertMsgFailed(("'%s' wants %RTuuid - external only interface!\n", pDevIns->pReg->szName, pUuid));
829#endif
830
831 void *pvRet;
832 PUVM pUVM = pDevIns->Internal.s.pVMR3->pUVM;
833 if (pUVM->pVmm2UserMethods->pfnQueryGenericObject)
834 pvRet = pUVM->pVmm2UserMethods->pfnQueryGenericObject(pUVM->pVmm2UserMethods, pUVM, pUuid);
835 else
836 pvRet = NULL;
837
838 LogRel(("pdmR3DevHlp_QueryGenericUserObject: caller='%s'/%d: returns %#p for %RTuuid\n",
839 pDevIns->pReg->szName, pDevIns->iInstance, pvRet, pUuid));
840 return pvRet;
841}
842
843
844/** @interface_method_impl{PDMDEVHLPR3,pfnPhysRead} */
845static DECLCALLBACK(int) pdmR3DevHlp_PhysRead(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
846{
847 PDMDEV_ASSERT_DEVINS(pDevIns);
848 PVM pVM = pDevIns->Internal.s.pVMR3;
849 LogFlow(("pdmR3DevHlp_PhysRead: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbRead=%#x\n",
850 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbRead));
851
852#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
853 if (!VM_IS_EMT(pVM))
854 {
855 char szNames[128];
856 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
857 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
858 }
859#endif
860
861 VBOXSTRICTRC rcStrict;
862 if (VM_IS_EMT(pVM))
863 rcStrict = PGMPhysRead(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
864 else
865 rcStrict = PGMR3PhysReadExternal(pVM, GCPhys, pvBuf, cbRead, PGMACCESSORIGIN_DEVICE);
866 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
867
868 Log(("pdmR3DevHlp_PhysRead: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
869 return VBOXSTRICTRC_VAL(rcStrict);
870}
871
872
873/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWrite} */
874static DECLCALLBACK(int) pdmR3DevHlp_PhysWrite(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
875{
876 PDMDEV_ASSERT_DEVINS(pDevIns);
877 PVM pVM = pDevIns->Internal.s.pVMR3;
878 LogFlow(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: GCPhys=%RGp pvBuf=%p cbWrite=%#x\n",
879 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvBuf, cbWrite));
880
881#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
882 if (!VM_IS_EMT(pVM))
883 {
884 char szNames[128];
885 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
886 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
887 }
888#endif
889
890 VBOXSTRICTRC rcStrict;
891 if (VM_IS_EMT(pVM))
892 rcStrict = PGMPhysWrite(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
893 else
894 rcStrict = PGMR3PhysWriteExternal(pVM, GCPhys, pvBuf, cbWrite, PGMACCESSORIGIN_DEVICE);
895 AssertMsg(rcStrict == VINF_SUCCESS, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict))); /** @todo track down the users for this bugger. */
896
897 Log(("pdmR3DevHlp_PhysWrite: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VBOXSTRICTRC_VAL(rcStrict) ));
898 return VBOXSTRICTRC_VAL(rcStrict);
899}
900
901
902/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtr} */
903static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtr(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, void **ppv, PPGMPAGEMAPLOCK pLock)
904{
905 PDMDEV_ASSERT_DEVINS(pDevIns);
906 PVM pVM = pDevIns->Internal.s.pVMR3;
907 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
908 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
909 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
910
911#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
912 if (!VM_IS_EMT(pVM))
913 {
914 char szNames[128];
915 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
916 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
917 }
918#endif
919
920 int rc = PGMR3PhysGCPhys2CCPtrExternal(pVM, GCPhys, ppv, pLock);
921
922 Log(("pdmR3DevHlp_PhysGCPhys2CCPtr: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
923 return rc;
924}
925
926
927/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPhys2CCPtrReadOnly} */
928static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t fFlags, const void **ppv, PPGMPAGEMAPLOCK pLock)
929{
930 PDMDEV_ASSERT_DEVINS(pDevIns);
931 PVM pVM = pDevIns->Internal.s.pVMR3;
932 LogFlow(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: GCPhys=%RGp fFlags=%#x ppv=%p pLock=%p\n",
933 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, fFlags, ppv, pLock));
934 AssertReturn(!fFlags, VERR_INVALID_PARAMETER);
935
936#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
937 if (!VM_IS_EMT(pVM))
938 {
939 char szNames[128];
940 uint32_t cLocks = PDMR3CritSectCountOwned(pVM, szNames, sizeof(szNames));
941 AssertMsg(cLocks == 0, ("cLocks=%u %s\n", cLocks, szNames));
942 }
943#endif
944
945 int rc = PGMR3PhysGCPhys2CCPtrReadOnlyExternal(pVM, GCPhys, ppv, pLock);
946
947 Log(("pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
948 return rc;
949}
950
951
952/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReleasePageMappingLock} */
953static DECLCALLBACK(void) pdmR3DevHlp_PhysReleasePageMappingLock(PPDMDEVINS pDevIns, PPGMPAGEMAPLOCK pLock)
954{
955 PDMDEV_ASSERT_DEVINS(pDevIns);
956 PVM pVM = pDevIns->Internal.s.pVMR3;
957 LogFlow(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: pLock=%p\n",
958 pDevIns->pReg->szName, pDevIns->iInstance, pLock));
959
960 PGMPhysReleasePageMappingLock(pVM, pLock);
961
962 Log(("pdmR3DevHlp_PhysReleasePageMappingLock: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
963}
964
965
966/** @interface_method_impl{PDMDEVHLPR3,pfnPhysReadGCVirt} */
967static DECLCALLBACK(int) pdmR3DevHlp_PhysReadGCVirt(PPDMDEVINS pDevIns, void *pvDst, RTGCPTR GCVirtSrc, size_t cb)
968{
969 PDMDEV_ASSERT_DEVINS(pDevIns);
970 PVM pVM = pDevIns->Internal.s.pVMR3;
971 VM_ASSERT_EMT(pVM);
972 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: pvDst=%p GCVirt=%RGv cb=%#x\n",
973 pDevIns->pReg->szName, pDevIns->iInstance, pvDst, GCVirtSrc, cb));
974
975 PVMCPU pVCpu = VMMGetCpu(pVM);
976 if (!pVCpu)
977 return VERR_ACCESS_DENIED;
978#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
979 /** @todo SMP. */
980#endif
981
982 int rc = PGMPhysSimpleReadGCPtr(pVCpu, pvDst, GCVirtSrc, cb);
983
984 LogFlow(("pdmR3DevHlp_PhysReadGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
985
986 return rc;
987}
988
989
990/** @interface_method_impl{PDMDEVHLPR3,pfnPhysWriteGCVirt} */
991static DECLCALLBACK(int) pdmR3DevHlp_PhysWriteGCVirt(PPDMDEVINS pDevIns, RTGCPTR GCVirtDst, const void *pvSrc, size_t cb)
992{
993 PDMDEV_ASSERT_DEVINS(pDevIns);
994 PVM pVM = pDevIns->Internal.s.pVMR3;
995 VM_ASSERT_EMT(pVM);
996 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: GCVirtDst=%RGv pvSrc=%p cb=%#x\n",
997 pDevIns->pReg->szName, pDevIns->iInstance, GCVirtDst, pvSrc, cb));
998
999 PVMCPU pVCpu = VMMGetCpu(pVM);
1000 if (!pVCpu)
1001 return VERR_ACCESS_DENIED;
1002#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1003 /** @todo SMP. */
1004#endif
1005
1006 int rc = PGMPhysSimpleWriteGCPtr(pVCpu, GCVirtDst, pvSrc, cb);
1007
1008 LogFlow(("pdmR3DevHlp_PhysWriteGCVirt: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1009
1010 return rc;
1011}
1012
1013
1014/** @interface_method_impl{PDMDEVHLPR3,pfnPhysGCPtr2GCPhys} */
1015static DECLCALLBACK(int) pdmR3DevHlp_PhysGCPtr2GCPhys(PPDMDEVINS pDevIns, RTGCPTR GCPtr, PRTGCPHYS pGCPhys)
1016{
1017 PDMDEV_ASSERT_DEVINS(pDevIns);
1018 PVM pVM = pDevIns->Internal.s.pVMR3;
1019 VM_ASSERT_EMT(pVM);
1020 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: GCPtr=%RGv pGCPhys=%p\n",
1021 pDevIns->pReg->szName, pDevIns->iInstance, GCPtr, pGCPhys));
1022
1023 PVMCPU pVCpu = VMMGetCpu(pVM);
1024 if (!pVCpu)
1025 return VERR_ACCESS_DENIED;
1026#if defined(VBOX_STRICT) && defined(PDM_DEVHLP_DEADLOCK_DETECTION)
1027 /** @todo SMP. */
1028#endif
1029
1030 int rc = PGMPhysGCPtr2GCPhys(pVCpu, GCPtr, pGCPhys);
1031
1032 LogFlow(("pdmR3DevHlp_PhysGCPtr2GCPhys: caller='%s'/%d: returns %Rrc *pGCPhys=%RGp\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *pGCPhys));
1033
1034 return rc;
1035}
1036
1037
1038/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAlloc} */
1039static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAlloc(PPDMDEVINS pDevIns, size_t cb)
1040{
1041 PDMDEV_ASSERT_DEVINS(pDevIns);
1042 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1043
1044 void *pv = MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1045
1046 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1047 return pv;
1048}
1049
1050
1051/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapAllocZ} */
1052static DECLCALLBACK(void *) pdmR3DevHlp_MMHeapAllocZ(PPDMDEVINS pDevIns, size_t cb)
1053{
1054 PDMDEV_ASSERT_DEVINS(pDevIns);
1055 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: cb=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cb));
1056
1057 void *pv = MMR3HeapAllocZ(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE_USER, cb);
1058
1059 LogFlow(("pdmR3DevHlp_MMHeapAllocZ: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1060 return pv;
1061}
1062
1063
1064/** @interface_method_impl{PDMDEVHLPR3,pfnMMHeapFree} */
1065static DECLCALLBACK(void) pdmR3DevHlp_MMHeapFree(PPDMDEVINS pDevIns, void *pv)
1066{
1067 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1068 LogFlow(("pdmR3DevHlp_MMHeapFree: caller='%s'/%d: pv=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pv));
1069
1070 MMR3HeapFree(pv);
1071
1072 LogFlow(("pdmR3DevHlp_MMHeapAlloc: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1073}
1074
1075
1076/** @interface_method_impl{PDMDEVHLPR3,pfnVMState} */
1077static DECLCALLBACK(VMSTATE) pdmR3DevHlp_VMState(PPDMDEVINS pDevIns)
1078{
1079 PDMDEV_ASSERT_DEVINS(pDevIns);
1080
1081 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
1082
1083 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %d (%s)\n", pDevIns->pReg->szName, pDevIns->iInstance,
1084 enmVMState, VMR3GetStateName(enmVMState)));
1085 return enmVMState;
1086}
1087
1088
1089/** @interface_method_impl{PDMDEVHLPR3,pfnVMTeleportedAndNotFullyResumedYet} */
1090static DECLCALLBACK(bool) pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet(PPDMDEVINS pDevIns)
1091{
1092 PDMDEV_ASSERT_DEVINS(pDevIns);
1093
1094 bool fRc = VMR3TeleportedAndNotFullyResumedYet(pDevIns->Internal.s.pVMR3);
1095
1096 LogFlow(("pdmR3DevHlp_VMState: caller='%s'/%d: returns %RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance,
1097 fRc));
1098 return fRc;
1099}
1100
1101
1102/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetError} */
1103static DECLCALLBACK(int) pdmR3DevHlp_VMSetError(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, ...)
1104{
1105 PDMDEV_ASSERT_DEVINS(pDevIns);
1106 va_list args;
1107 va_start(args, pszFormat);
1108 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, args); Assert(rc2 == rc); NOREF(rc2);
1109 va_end(args);
1110 return rc;
1111}
1112
1113
1114/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetErrorV} */
1115static DECLCALLBACK(int) pdmR3DevHlp_VMSetErrorV(PPDMDEVINS pDevIns, int rc, RT_SRC_POS_DECL, const char *pszFormat, va_list va)
1116{
1117 PDMDEV_ASSERT_DEVINS(pDevIns);
1118 int rc2 = VMSetErrorV(pDevIns->Internal.s.pVMR3, rc, RT_SRC_POS_ARGS, pszFormat, va); Assert(rc2 == rc); NOREF(rc2);
1119 return rc;
1120}
1121
1122
1123/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeError} */
1124static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeError(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, ...)
1125{
1126 PDMDEV_ASSERT_DEVINS(pDevIns);
1127 va_list args;
1128 va_start(args, pszFormat);
1129 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, args);
1130 va_end(args);
1131 return rc;
1132}
1133
1134
1135/** @interface_method_impl{PDMDEVHLPR3,pfnVMSetRuntimeErrorV} */
1136static DECLCALLBACK(int) pdmR3DevHlp_VMSetRuntimeErrorV(PPDMDEVINS pDevIns, uint32_t fFlags, const char *pszErrorId, const char *pszFormat, va_list va)
1137{
1138 PDMDEV_ASSERT_DEVINS(pDevIns);
1139 int rc = VMSetRuntimeErrorV(pDevIns->Internal.s.pVMR3, fFlags, pszErrorId, pszFormat, va);
1140 return rc;
1141}
1142
1143
1144/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFStopV} */
1145static DECLCALLBACK(int) pdmR3DevHlp_DBGFStopV(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction, const char *pszFormat, va_list args)
1146{
1147 PDMDEV_ASSERT_DEVINS(pDevIns);
1148#ifdef LOG_ENABLED
1149 va_list va2;
1150 va_copy(va2, args);
1151 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: pszFile=%p:{%s} iLine=%d pszFunction=%p:{%s} pszFormat=%p:{%s} (%N)\n",
1152 pDevIns->pReg->szName, pDevIns->iInstance, pszFile, pszFile, iLine, pszFunction, pszFunction, pszFormat, pszFormat, pszFormat, &va2));
1153 va_end(va2);
1154#endif
1155
1156 PVM pVM = pDevIns->Internal.s.pVMR3;
1157 VM_ASSERT_EMT(pVM);
1158 int rc = DBGFR3EventSrcV(pVM, DBGFEVENT_DEV_STOP, pszFile, iLine, pszFunction, pszFormat, args);
1159 if (rc == VERR_DBGF_NOT_ATTACHED)
1160 rc = VINF_SUCCESS;
1161
1162 LogFlow(("pdmR3DevHlp_DBGFStopV: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1163 return rc;
1164}
1165
1166
1167/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFInfoRegister} */
1168static DECLCALLBACK(int) pdmR3DevHlp_DBGFInfoRegister(PPDMDEVINS pDevIns, const char *pszName, const char *pszDesc, PFNDBGFHANDLERDEV pfnHandler)
1169{
1170 PDMDEV_ASSERT_DEVINS(pDevIns);
1171 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: pszName=%p:{%s} pszDesc=%p:{%s} pfnHandler=%p\n",
1172 pDevIns->pReg->szName, pDevIns->iInstance, pszName, pszName, pszDesc, pszDesc, pfnHandler));
1173
1174 PVM pVM = pDevIns->Internal.s.pVMR3;
1175 VM_ASSERT_EMT(pVM);
1176 int rc = DBGFR3InfoRegisterDevice(pVM, pszName, pszDesc, pfnHandler, pDevIns);
1177
1178 LogFlow(("pdmR3DevHlp_DBGFInfoRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1179 return rc;
1180}
1181
1182
1183/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFRegRegister} */
1184static DECLCALLBACK(int) pdmR3DevHlp_DBGFRegRegister(PPDMDEVINS pDevIns, PCDBGFREGDESC paRegisters)
1185{
1186 PDMDEV_ASSERT_DEVINS(pDevIns);
1187 LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: paRegisters=%p\n",
1188 pDevIns->pReg->szName, pDevIns->iInstance, paRegisters));
1189
1190 PVM pVM = pDevIns->Internal.s.pVMR3;
1191 VM_ASSERT_EMT(pVM);
1192 int rc = DBGFR3RegRegisterDevice(pVM, paRegisters, pDevIns, pDevIns->pReg->szName, pDevIns->iInstance);
1193
1194 LogFlow(("pdmR3DevHlp_DBGFRegRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1195 return rc;
1196}
1197
1198
1199/** @interface_method_impl{PDMDEVHLPR3,pfnDBGFTraceBuf} */
1200static DECLCALLBACK(RTTRACEBUF) pdmR3DevHlp_DBGFTraceBuf(PPDMDEVINS pDevIns)
1201{
1202 PDMDEV_ASSERT_DEVINS(pDevIns);
1203 RTTRACEBUF hTraceBuf = pDevIns->Internal.s.pVMR3->hTraceBufR3;
1204 LogFlow(("pdmR3DevHlp_DBGFTraceBuf: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, hTraceBuf));
1205 return hTraceBuf;
1206}
1207
1208
1209/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegister} */
1210static DECLCALLBACK(void) pdmR3DevHlp_STAMRegister(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, const char *pszName,
1211 STAMUNIT enmUnit, const char *pszDesc)
1212{
1213 PDMDEV_ASSERT_DEVINS(pDevIns);
1214 PVM pVM = pDevIns->Internal.s.pVMR3;
1215 VM_ASSERT_EMT(pVM);
1216
1217 STAM_REG(pVM, pvSample, enmType, pszName, enmUnit, pszDesc);
1218 RT_NOREF_PV(pVM); RT_NOREF6(pDevIns, pvSample, enmType, pszName, enmUnit, pszDesc);
1219}
1220
1221
1222
1223/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterF} */
1224static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterF(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1225 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, ...)
1226{
1227 PDMDEV_ASSERT_DEVINS(pDevIns);
1228 PVM pVM = pDevIns->Internal.s.pVMR3;
1229 VM_ASSERT_EMT(pVM);
1230
1231 va_list args;
1232 va_start(args, pszName);
1233 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1234 va_end(args);
1235 AssertRC(rc);
1236
1237 NOREF(pVM);
1238}
1239
1240
1241/** @interface_method_impl{PDMDEVHLPR3,pfnSTAMRegisterV} */
1242static DECLCALLBACK(void) pdmR3DevHlp_STAMRegisterV(PPDMDEVINS pDevIns, void *pvSample, STAMTYPE enmType, STAMVISIBILITY enmVisibility,
1243 STAMUNIT enmUnit, const char *pszDesc, const char *pszName, va_list args)
1244{
1245 PDMDEV_ASSERT_DEVINS(pDevIns);
1246 PVM pVM = pDevIns->Internal.s.pVMR3;
1247 VM_ASSERT_EMT(pVM);
1248
1249 int rc = STAMR3RegisterV(pVM, pvSample, enmType, enmVisibility, enmUnit, pszDesc, pszName, args);
1250 AssertRC(rc);
1251
1252 NOREF(pVM);
1253}
1254
1255
1256/**
1257 * @interface_method_impl{PDMDEVHLPR3,pfnPCIRegister}
1258 */
1259static DECLCALLBACK(int) pdmR3DevHlp_PCIRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t idxDevCfg, uint32_t fFlags,
1260 uint8_t uPciDevNo, uint8_t uPciFunNo, const char *pszName)
1261{
1262 PDMDEV_ASSERT_DEVINS(pDevIns);
1263 PVM pVM = pDevIns->Internal.s.pVMR3;
1264 VM_ASSERT_EMT(pVM);
1265 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: pPciDev=%p:{.config={%#.256Rhxs} idxDevCfg=%d fFlags=%#x uPciDevNo=%#x uPciFunNo=%#x pszName=%p:{%s}\n",
1266 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->abConfig, idxDevCfg, fFlags, uPciDevNo, uPciFunNo, pszName, pszName ? pszName : ""));
1267
1268 /*
1269 * Validate input.
1270 */
1271 AssertLogRelMsgReturn(RT_VALID_PTR(pPciDev),
1272 ("'%s'/%d: Invalid pPciDev value: %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1273 VERR_INVALID_POINTER);
1274 AssertLogRelMsgReturn(PDMPciDevGetVendorId(pPciDev),
1275 ("'%s'/%d: Vendor ID is not set!\n", pDevIns->pReg->szName, pDevIns->iInstance),
1276 VERR_INVALID_POINTER);
1277 AssertLogRelMsgReturn(idxDevCfg < 256 || idxDevCfg == PDMPCIDEVREG_CFG_NEXT,
1278 ("'%s'/%d: Invalid config selector: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1279 VERR_OUT_OF_RANGE);
1280 AssertLogRelMsgReturn( uPciDevNo < 32
1281 || uPciDevNo == PDMPCIDEVREG_DEV_NO_FIRST_UNUSED
1282 || uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV,
1283 ("'%s'/%d: Invalid PCI device number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciDevNo),
1284 VERR_INVALID_PARAMETER);
1285 AssertLogRelMsgReturn( uPciFunNo < 8
1286 || uPciFunNo == PDMPCIDEVREG_FUN_NO_FIRST_UNUSED,
1287 ("'%s'/%d: Invalid PCI funcion number: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, uPciFunNo),
1288 VERR_INVALID_PARAMETER);
1289 AssertLogRelMsgReturn(!(fFlags & ~PDMPCIDEVREG_F_VALID_MASK),
1290 ("'%s'/%d: Invalid flags: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, fFlags),
1291 VERR_INVALID_FLAGS);
1292 if (!pszName)
1293 pszName = pDevIns->pReg->szName;
1294 AssertLogRelReturn(RT_VALID_PTR(pszName), VERR_INVALID_POINTER);
1295
1296 /*
1297 * Find the last(/previous) registered PCI device (for linking and more),
1298 * checking for duplicate registration attempts while doing so.
1299 */
1300 uint32_t idxDevCfgNext = 0;
1301 PPDMPCIDEV pPrevPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1302 while (pPrevPciDev)
1303 {
1304 AssertLogRelMsgReturn(pPrevPciDev != pPciDev,
1305 ("'%s'/%d attempted to register the same PCI device (%p) twice\n",
1306 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev),
1307 VERR_DUPLICATE);
1308 AssertLogRelMsgReturn(pPrevPciDev->Int.s.idxDevCfg != idxDevCfg,
1309 ("'%s'/%d attempted to use the same device config index (%u) twice\n",
1310 pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1311 VERR_ALREADY_LOADED);
1312 if (pPrevPciDev->Int.s.idxDevCfg >= idxDevCfgNext)
1313 idxDevCfgNext = pPrevPciDev->Int.s.idxDevCfg + 1;
1314
1315 if (!pPrevPciDev->Int.s.pNextR3)
1316 break;
1317 pPrevPciDev = pPrevPciDev->Int.s.pNextR3;
1318 }
1319
1320 /*
1321 * Resolve the PCI configuration node for the device. The default (zero'th)
1322 * is the same as the PDM device, the rest are "PciCfg1..255" CFGM sub-nodes.
1323 */
1324 if (idxDevCfg == PDMPCIDEVREG_CFG_NEXT)
1325 {
1326 idxDevCfg = idxDevCfgNext;
1327 AssertLogRelMsgReturn(idxDevCfg < 256, ("'%s'/%d: PDMPCIDEVREG_IDX_DEV_CFG_NEXT ran out of valid indexes (ends at 255)\n",
1328 pDevIns->pReg->szName, pDevIns->iInstance),
1329 VERR_OUT_OF_RANGE);
1330 }
1331
1332 PCFGMNODE pCfg = pDevIns->Internal.s.pCfgHandle;
1333 if (idxDevCfg != 0)
1334 pCfg = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "PciCfg%u", idxDevCfg);
1335
1336 /*
1337 * We resolve PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, the PCI bus handles
1338 * PDMPCIDEVREG_DEV_NO_FIRST_UNUSED and PDMPCIDEVREG_FUN_NO_FIRST_UNUSED.
1339 */
1340 uint8_t const uPciDevNoRaw = uPciDevNo;
1341 uint32_t uDefPciBusNo = 0;
1342 if (uPciDevNo == PDMPCIDEVREG_DEV_NO_SAME_AS_PREV)
1343 {
1344 if (pPrevPciDev)
1345 {
1346 uPciDevNo = pPrevPciDev->uDevFn >> 3;
1347 uDefPciBusNo = pPrevPciDev->Int.s.pPdmBusR3->iBus;
1348 }
1349 else
1350 {
1351 /* Look for PCI device registered with an earlier device instance so we can more
1352 easily have multiple functions spanning multiple PDM device instances. */
1353 PPDMPCIDEV pOtherPciDev = NULL;
1354 PPDMDEVINS pPrevIns = pDevIns->Internal.s.pDevR3->pInstances;
1355 while (pPrevIns != pDevIns && pPrevIns)
1356 {
1357 pOtherPciDev = pPrevIns->Internal.s.pHeadPciDevR3;
1358 pPrevIns = pPrevIns->Internal.s.pNextR3;
1359 }
1360 Assert(pPrevIns == pDevIns);
1361 AssertLogRelMsgReturn(pOtherPciDev,
1362 ("'%s'/%d: Can't use PDMPCIDEVREG_DEV_NO_SAME_AS_PREV without a previously registered PCI device by the same or earlier PDM device instance!\n",
1363 pDevIns->pReg->szName, pDevIns->iInstance),
1364 VERR_WRONG_ORDER);
1365
1366 while (pOtherPciDev->Int.s.pNextR3)
1367 pOtherPciDev = pOtherPciDev->Int.s.pNextR3;
1368 uPciDevNo = pOtherPciDev->uDevFn >> 3;
1369 uDefPciBusNo = pOtherPciDev->Int.s.pPdmBusR3->iBus;
1370 }
1371 }
1372
1373 /*
1374 * Choose the PCI bus for the device.
1375 *
1376 * This is simple. If the device was configured for a particular bus, the PCIBusNo
1377 * configuration value will be set. If not the default bus is 0.
1378 */
1379 /** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIBusNo, uint8_t, 0, 7, 0}
1380 * Selects the PCI bus number of a device. The default value isn't necessarily
1381 * zero if the device is registered using PDMPCIDEVREG_DEV_NO_SAME_AS_PREV, it
1382 * will then also inherit the bus number from the previously registered device.
1383 */
1384 uint8_t u8Bus;
1385 int rc = CFGMR3QueryU8Def(pCfg, "PCIBusNo", &u8Bus, (uint8_t)uDefPciBusNo);
1386 AssertLogRelMsgRCReturn(rc, ("Configuration error: PCIBusNo query failed with rc=%Rrc (%s/%d)\n",
1387 rc, pDevIns->pReg->szName, pDevIns->iInstance), rc);
1388 AssertLogRelMsgReturn(u8Bus < RT_ELEMENTS(pVM->pdm.s.aPciBuses),
1389 ("Configuration error: PCIBusNo=%d, max is %d. (%s/%d)\n", u8Bus,
1390 RT_ELEMENTS(pVM->pdm.s.aPciBuses), pDevIns->pReg->szName, pDevIns->iInstance),
1391 VERR_PDM_NO_PCI_BUS);
1392 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3 = &pVM->pdm.s.aPciBuses[u8Bus];
1393 if (pBus->pDevInsR3)
1394 {
1395 /*
1396 * Check the configuration for PCI device and function assignment.
1397 */
1398 /** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIDeviceNo, uint8_t, 0, 31}
1399 * Overrides the default PCI device number of a device.
1400 */
1401 uint8_t uCfgDevice;
1402 rc = CFGMR3QueryU8(pCfg, "PCIDeviceNo", &uCfgDevice);
1403 if (RT_SUCCESS(rc))
1404 {
1405 AssertMsgReturn(uCfgDevice <= 31,
1406 ("Configuration error: PCIDeviceNo=%d, max is 31. (%s/%d/%d)\n",
1407 uCfgDevice, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1408 VERR_PDM_BAD_PCI_CONFIG);
1409 uPciDevNo = uCfgDevice;
1410 }
1411 else
1412 AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT,
1413 ("Configuration error: PCIDeviceNo query failed with rc=%Rrc (%s/%d/%d)\n",
1414 rc, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1415 rc);
1416
1417 /** @cfgm{/Devices/NAME/XX/[PciCfgYY/]PCIFunctionNo, uint8_t, 0, 7}
1418 * Overrides the default PCI function number of a device.
1419 */
1420 uint8_t uCfgFunction;
1421 rc = CFGMR3QueryU8(pCfg, "PCIFunctionNo", &uCfgFunction);
1422 if (RT_SUCCESS(rc))
1423 {
1424 AssertMsgReturn(uCfgFunction <= 7,
1425 ("Configuration error: PCIFunctionNo=%#x, max is 7. (%s/%d/%d)\n",
1426 uCfgFunction, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1427 VERR_PDM_BAD_PCI_CONFIG);
1428 uPciFunNo = uCfgFunction;
1429 }
1430 else
1431 AssertMsgReturn(rc == VERR_CFGM_VALUE_NOT_FOUND || rc == VERR_CFGM_NO_PARENT,
1432 ("Configuration error: PCIFunctionNo query failed with rc=%Rrc (%s/%d/%d)\n",
1433 rc, pDevIns->pReg->szName, pDevIns->iInstance, idxDevCfg),
1434 rc);
1435
1436
1437 /*
1438 * Initialize the internal data. We only do the wipe and the members
1439 * owned by PDM, the PCI bus does the rest in the registration call.
1440 */
1441 RT_ZERO(pPciDev->Int);
1442
1443 pPciDev->Int.s.idxDevCfg = idxDevCfg;
1444 pPciDev->Int.s.fReassignableDevNo = uPciDevNoRaw >= VBOX_PCI_MAX_DEVICES;
1445 pPciDev->Int.s.fReassignableFunNo = uPciFunNo >= VBOX_PCI_MAX_FUNCTIONS;
1446 pPciDev->Int.s.pDevInsR3 = pDevIns;
1447 pPciDev->Int.s.pPdmBusR3 = pBus;
1448 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1449 {
1450 pPciDev->Int.s.pDevInsR0 = MMHyperR3ToR0(pVM, pDevIns);
1451 pPciDev->Int.s.pPdmBusR0 = MMHyperR3ToR0(pVM, pBus);
1452 }
1453 else
1454 {
1455 pPciDev->Int.s.pDevInsR0 = NIL_RTR0PTR;
1456 pPciDev->Int.s.pPdmBusR0 = NIL_RTR0PTR;
1457 }
1458
1459 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1460 {
1461 pPciDev->Int.s.pDevInsRC = MMHyperR3ToRC(pVM, pDevIns);
1462 pPciDev->Int.s.pPdmBusRC = MMHyperR3ToRC(pVM, pBus);
1463 }
1464 else
1465 {
1466 pPciDev->Int.s.pDevInsRC = NIL_RTRCPTR;
1467 pPciDev->Int.s.pPdmBusRC = NIL_RTRCPTR;
1468 }
1469
1470 /* Set some of the public members too. */
1471 pPciDev->pszNameR3 = pszName;
1472
1473 /*
1474 * Call the pci bus device to do the actual registration.
1475 */
1476 pdmLock(pVM);
1477 rc = pBus->pfnRegisterR3(pBus->pDevInsR3, pPciDev, fFlags, uPciDevNo, uPciFunNo, pszName);
1478 pdmUnlock(pVM);
1479 if (RT_SUCCESS(rc))
1480 {
1481
1482 /*
1483 * Link it.
1484 */
1485 if (pPrevPciDev)
1486 {
1487 Assert(!pPrevPciDev->Int.s.pNextR3);
1488 pPrevPciDev->Int.s.pNextR3 = pPciDev;
1489 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1490 pPrevPciDev->Int.s.pNextR0 = MMHyperR3ToR0(pVM, pPciDev);
1491 else
1492 pPrevPciDev->Int.s.pNextR0 = NIL_RTR0PTR;
1493 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1494 pPrevPciDev->Int.s.pNextRC = MMHyperR3ToRC(pVM, pPciDev);
1495 else
1496 pPrevPciDev->Int.s.pNextRC = NIL_RTRCPTR;
1497 }
1498 else
1499 {
1500 Assert(!pDevIns->Internal.s.pHeadPciDevR3);
1501 pDevIns->Internal.s.pHeadPciDevR3 = pPciDev;
1502 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
1503 pDevIns->Internal.s.pHeadPciDevR0 = MMHyperR3ToR0(pVM, pPciDev);
1504 else
1505 pDevIns->Internal.s.pHeadPciDevR0 = NIL_RTR0PTR;
1506 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
1507 pDevIns->Internal.s.pHeadPciDevRC = MMHyperR3ToRC(pVM, pPciDev);
1508 else
1509 pDevIns->Internal.s.pHeadPciDevRC = NIL_RTRCPTR;
1510 }
1511
1512 Log(("PDM: Registered device '%s'/%d as PCI device %d on bus %d\n",
1513 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev->uDevFn, pBus->iBus));
1514 }
1515 }
1516 else
1517 {
1518 AssertLogRelMsgFailed(("Configuration error: No PCI bus available. This could be related to init order too!\n"));
1519 rc = VERR_PDM_NO_PCI_BUS;
1520 }
1521
1522 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1523 return rc;
1524}
1525
1526
1527/** @interface_method_impl{PDMDEVHLPR3,pfnPCIRegisterMsi} */
1528static DECLCALLBACK(int) pdmR3DevHlp_PCIRegisterMsi(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PPDMMSIREG pMsiReg)
1529{
1530 PDMDEV_ASSERT_DEVINS(pDevIns);
1531 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1532 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1533 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1534 LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: pPciDev=%p:{%#x} pMsgReg=%p:{cMsiVectors=%d, cMsixVectors=%d}\n",
1535 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, pMsiReg, pMsiReg->cMsiVectors, pMsiReg->cMsixVectors));
1536
1537 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3; Assert(pBus);
1538 PVM pVM = pDevIns->Internal.s.pVMR3;
1539 pdmLock(pVM);
1540 int rc;
1541 if (pBus->pfnRegisterMsiR3)
1542 rc = pBus->pfnRegisterMsiR3(pBus->pDevInsR3, pPciDev, pMsiReg);
1543 else
1544 rc = VERR_NOT_IMPLEMENTED;
1545 pdmUnlock(pVM);
1546
1547 LogFlow(("pdmR3DevHlp_PCIRegisterMsi: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1548 return rc;
1549}
1550
1551
1552/** @interface_method_impl{PDMDEVHLPR3,pfnPCIIORegionRegister} */
1553static DECLCALLBACK(int) pdmR3DevHlp_PCIIORegionRegister(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, uint32_t iRegion,
1554 RTGCPHYS cbRegion, PCIADDRESSSPACE enmType, PFNPCIIOREGIONMAP pfnCallback)
1555{
1556 PDMDEV_ASSERT_DEVINS(pDevIns);
1557 PVM pVM = pDevIns->Internal.s.pVMR3;
1558 VM_ASSERT_EMT(pVM);
1559 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1560 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1561 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1562 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: pPciDev=%p:{%#x} iRegion=%d cbRegion=%RGp enmType=%d pfnCallback=%p\n",
1563 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iRegion, cbRegion, enmType, pfnCallback));
1564
1565 /*
1566 * Validate input.
1567 */
1568 if (iRegion >= VBOX_PCI_NUM_REGIONS)
1569 {
1570 Assert(iRegion < VBOX_PCI_NUM_REGIONS);
1571 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (iRegion)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1572 return VERR_INVALID_PARAMETER;
1573 }
1574
1575 switch ((int)enmType)
1576 {
1577 case PCI_ADDRESS_SPACE_IO:
1578 /*
1579 * Sanity check: don't allow to register more than 32K of the PCI I/O space.
1580 */
1581 AssertLogRelMsgReturn(cbRegion <= _32K,
1582 ("caller='%s'/%d: %#x\n", pDevIns->pReg->szName, pDevIns->iInstance, cbRegion),
1583 VERR_INVALID_PARAMETER);
1584 break;
1585
1586 case PCI_ADDRESS_SPACE_MEM:
1587 case PCI_ADDRESS_SPACE_MEM_PREFETCH:
1588 /*
1589 * Sanity check: Don't allow to register more than 2GB of the PCI MMIO space.
1590 */
1591 AssertLogRelMsgReturn(cbRegion <= MM_MMIO_32_MAX,
1592 ("caller='%s'/%d: %RGp (max %RGp)\n",
1593 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, (RTGCPHYS)MM_MMIO_32_MAX),
1594 VERR_OUT_OF_RANGE);
1595 break;
1596
1597 case PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM:
1598 case PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM_PREFETCH:
1599 /*
1600 * Sanity check: Don't allow to register more than 64GB of the 64-bit PCI MMIO space.
1601 */
1602 AssertLogRelMsgReturn(cbRegion <= MM_MMIO_64_MAX,
1603 ("caller='%s'/%d: %RGp (max %RGp)\n",
1604 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, MM_MMIO_64_MAX),
1605 VERR_OUT_OF_RANGE);
1606 break;
1607
1608 default:
1609 AssertMsgFailed(("enmType=%#x is unknown\n", enmType));
1610 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (enmType)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1611 return VERR_INVALID_PARAMETER;
1612 }
1613 if (!pfnCallback)
1614 {
1615 Assert(pfnCallback);
1616 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc (callback)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
1617 return VERR_INVALID_PARAMETER;
1618 }
1619 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1620
1621 /*
1622 * We're currently restricted to page aligned MMIO regions.
1623 */
1624 if ( ((enmType & ~(PCI_ADDRESS_SPACE_BAR64 | PCI_ADDRESS_SPACE_MEM_PREFETCH)) == PCI_ADDRESS_SPACE_MEM)
1625 && cbRegion != RT_ALIGN_64(cbRegion, PAGE_SIZE))
1626 {
1627 Log(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: aligning cbRegion %RGp -> %RGp\n",
1628 pDevIns->pReg->szName, pDevIns->iInstance, cbRegion, RT_ALIGN_64(cbRegion, PAGE_SIZE)));
1629 cbRegion = RT_ALIGN_64(cbRegion, PAGE_SIZE);
1630 }
1631
1632 /*
1633 * For registering PCI MMIO memory or PCI I/O memory, the size of the region must be a power of 2!
1634 */
1635 int iLastSet = ASMBitLastSetU64(cbRegion);
1636 Assert(iLastSet > 0);
1637 uint64_t cbRegionAligned = RT_BIT_64(iLastSet - 1);
1638 if (cbRegion > cbRegionAligned)
1639 cbRegion = cbRegionAligned * 2; /* round up */
1640
1641 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1642 Assert(pBus);
1643 pdmLock(pVM);
1644 int rc = pBus->pfnIORegionRegisterR3(pBus->pDevInsR3, pPciDev, iRegion, cbRegion, enmType, pfnCallback);
1645 pdmUnlock(pVM);
1646
1647 LogFlow(("pdmR3DevHlp_PCIIORegionRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1648 return rc;
1649}
1650
1651
1652/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetConfigCallbacks} */
1653static DECLCALLBACK(void) pdmR3DevHlp_PCISetConfigCallbacks(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, PFNPCICONFIGREAD pfnRead, PPFNPCICONFIGREAD ppfnReadOld,
1654 PFNPCICONFIGWRITE pfnWrite, PPFNPCICONFIGWRITE ppfnWriteOld)
1655{
1656 PDMDEV_ASSERT_DEVINS(pDevIns);
1657 PVM pVM = pDevIns->Internal.s.pVMR3;
1658 VM_ASSERT_EMT(pVM);
1659 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1660 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1661 AssertReturnVoid(pPciDev);
1662 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: pPciDev=%p pfnRead=%p ppfnReadOld=%p pfnWrite=%p ppfnWriteOld=%p\n",
1663 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld));
1664
1665 /*
1666 * Validate input and resolve defaults.
1667 */
1668 AssertPtr(pfnRead);
1669 AssertPtr(pfnWrite);
1670 AssertPtrNull(ppfnReadOld);
1671 AssertPtrNull(ppfnWriteOld);
1672 AssertPtrNull(pPciDev);
1673
1674 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1675 AssertRelease(pBus);
1676 AssertRelease(VMR3GetState(pVM) != VMSTATE_RUNNING);
1677
1678 /*
1679 * Do the job.
1680 */
1681 pdmLock(pVM);
1682 pBus->pfnSetConfigCallbacksR3(pBus->pDevInsR3, pPciDev, pfnRead, ppfnReadOld, pfnWrite, ppfnWriteOld);
1683 pdmUnlock(pVM);
1684
1685 LogFlow(("pdmR3DevHlp_PCISetConfigCallbacks: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1686}
1687
1688
1689/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysRead} */
1690static DECLCALLBACK(int)
1691pdmR3DevHlp_PCIPhysRead(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, void *pvBuf, size_t cbRead)
1692{
1693 PDMDEV_ASSERT_DEVINS(pDevIns);
1694 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1695 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1696 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1697
1698#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
1699 /*
1700 * Just check the busmaster setting here and forward the request to the generic read helper.
1701 */
1702 if (PCIDevIsBusmaster(pPciDev))
1703 { /* likely */ }
1704 else
1705 {
1706 Log(("pdmR3DevHlp_PCIPhysRead: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbRead=%#zx\n",
1707 pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbRead));
1708 return VERR_PDM_NOT_PCI_BUS_MASTER;
1709 }
1710#endif
1711
1712 return pDevIns->pHlpR3->pfnPhysRead(pDevIns, GCPhys, pvBuf, cbRead);
1713}
1714
1715
1716/** @interface_method_impl{PDMDEVHLPR3,pfnPCIPhysWrite} */
1717static DECLCALLBACK(int)
1718pdmR3DevHlp_PCIPhysWrite(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, RTGCPHYS GCPhys, const void *pvBuf, size_t cbWrite)
1719{
1720 PDMDEV_ASSERT_DEVINS(pDevIns);
1721 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1722 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1723 AssertReturn(pPciDev, VERR_PDM_NOT_PCI_DEVICE);
1724
1725#ifndef PDM_DO_NOT_RESPECT_PCI_BM_BIT
1726 /*
1727 * Just check the busmaster setting here and forward the request to the generic read helper.
1728 */
1729 if (PCIDevIsBusmaster(pPciDev))
1730 { /* likely */ }
1731 else
1732 {
1733 Log(("pdmR3DevHlp_PCIPhysWrite: caller='%s'/%d: returns %Rrc - Not bus master! GCPhys=%RGp cbWrite=%#zx\n",
1734 pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_NOT_PCI_BUS_MASTER, GCPhys, cbWrite));
1735 return VERR_PDM_NOT_PCI_BUS_MASTER;
1736 }
1737#endif
1738
1739 return pDevIns->pHlpR3->pfnPhysWrite(pDevIns, GCPhys, pvBuf, cbWrite);
1740}
1741
1742
1743/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrq} */
1744static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
1745{
1746 PDMDEV_ASSERT_DEVINS(pDevIns);
1747 if (!pPciDev) /* NULL is an alias for the default PCI device. */
1748 pPciDev = pDevIns->Internal.s.pHeadPciDevR3;
1749 AssertReturnVoid(pPciDev);
1750 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: pPciDev=%p:{%#x} iIrq=%d iLevel=%d\n",
1751 pDevIns->pReg->szName, pDevIns->iInstance, pPciDev, pPciDev->uDevFn, iIrq, iLevel));
1752
1753 /*
1754 * Validate input.
1755 */
1756 Assert(iIrq == 0);
1757 Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1758
1759 /*
1760 * Must have a PCI device registered!
1761 */
1762 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
1763 Assert(pBus);
1764 PVM pVM = pDevIns->Internal.s.pVMR3;
1765
1766 pdmLock(pVM);
1767 uint32_t uTagSrc;
1768 if (iLevel & PDM_IRQ_LEVEL_HIGH)
1769 {
1770 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1771 if (iLevel == PDM_IRQ_LEVEL_HIGH)
1772 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1773 else
1774 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1775 }
1776 else
1777 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1778
1779 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, iIrq, iLevel, uTagSrc);
1780
1781 if (iLevel == PDM_IRQ_LEVEL_LOW)
1782 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1783 pdmUnlock(pVM);
1784
1785 LogFlow(("pdmR3DevHlp_PCISetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1786}
1787
1788
1789/** @interface_method_impl{PDMDEVHLPR3,pfnPCISetIrqNoWait} */
1790static DECLCALLBACK(void) pdmR3DevHlp_PCISetIrqNoWait(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel)
1791{
1792 pdmR3DevHlp_PCISetIrq(pDevIns, pPciDev, iIrq, iLevel);
1793}
1794
1795
1796/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrq} */
1797static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1798{
1799 PDMDEV_ASSERT_DEVINS(pDevIns);
1800 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
1801
1802 /*
1803 * Validate input.
1804 */
1805 Assert(iIrq < 16);
1806 Assert((uint32_t)iLevel <= PDM_IRQ_LEVEL_FLIP_FLOP);
1807
1808 PVM pVM = pDevIns->Internal.s.pVMR3;
1809
1810 /*
1811 * Do the job.
1812 */
1813 pdmLock(pVM);
1814 uint32_t uTagSrc;
1815 if (iLevel & PDM_IRQ_LEVEL_HIGH)
1816 {
1817 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1818 if (iLevel == PDM_IRQ_LEVEL_HIGH)
1819 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1820 else
1821 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1822 }
1823 else
1824 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
1825
1826 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
1827
1828 if (iLevel == PDM_IRQ_LEVEL_LOW)
1829 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1830 pdmUnlock(pVM);
1831
1832 LogFlow(("pdmR3DevHlp_ISASetIrq: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1833}
1834
1835
1836/** @interface_method_impl{PDMDEVHLPR3,pfnISASetIrqNoWait} */
1837static DECLCALLBACK(void) pdmR3DevHlp_ISASetIrqNoWait(PPDMDEVINS pDevIns, int iIrq, int iLevel)
1838{
1839 pdmR3DevHlp_ISASetIrq(pDevIns, iIrq, iLevel);
1840}
1841
1842
1843/** @interface_method_impl{PDMDEVHLPR3,pfnIoApicSendMsi} */
1844static DECLCALLBACK(void) pdmR3DevHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue)
1845{
1846 PDMDEV_ASSERT_DEVINS(pDevIns);
1847 LogFlow(("pdmR3DevHlp_IoApicSendMsi: caller='%s'/%d: GCPhys=%RGp uValue=%#x\n", pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, uValue));
1848
1849 /*
1850 * Validate input.
1851 */
1852 Assert(GCPhys != 0);
1853 Assert(uValue != 0);
1854
1855 PVM pVM = pDevIns->Internal.s.pVMR3;
1856
1857 /*
1858 * Do the job.
1859 */
1860 pdmLock(pVM);
1861 uint32_t uTagSrc;
1862 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
1863 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
1864
1865 PDMIoApicSendMsi(pVM, GCPhys, uValue, uTagSrc); /* (The API takes the lock recursively.) */
1866
1867 pdmUnlock(pVM);
1868
1869 LogFlow(("pdmR3DevHlp_IoApicSendMsi: caller='%s'/%d: returns void\n", pDevIns->pReg->szName, pDevIns->iInstance));
1870}
1871
1872
1873/** @interface_method_impl{PDMDEVHLPR3,pfnDriverAttach} */
1874static DECLCALLBACK(int) pdmR3DevHlp_DriverAttach(PPDMDEVINS pDevIns, uint32_t iLun, PPDMIBASE pBaseInterface, PPDMIBASE *ppBaseInterface, const char *pszDesc)
1875{
1876 PDMDEV_ASSERT_DEVINS(pDevIns);
1877 PVM pVM = pDevIns->Internal.s.pVMR3;
1878 VM_ASSERT_EMT(pVM);
1879 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: iLun=%d pBaseInterface=%p ppBaseInterface=%p pszDesc=%p:{%s}\n",
1880 pDevIns->pReg->szName, pDevIns->iInstance, iLun, pBaseInterface, ppBaseInterface, pszDesc, pszDesc));
1881
1882 /*
1883 * Lookup the LUN, it might already be registered.
1884 */
1885 PPDMLUN pLunPrev = NULL;
1886 PPDMLUN pLun = pDevIns->Internal.s.pLunsR3;
1887 for (; pLun; pLunPrev = pLun, pLun = pLun->pNext)
1888 if (pLun->iLun == iLun)
1889 break;
1890
1891 /*
1892 * Create the LUN if if wasn't found, else check if driver is already attached to it.
1893 */
1894 if (!pLun)
1895 {
1896 if ( !pBaseInterface
1897 || !pszDesc
1898 || !*pszDesc)
1899 {
1900 Assert(pBaseInterface);
1901 Assert(pszDesc || *pszDesc);
1902 return VERR_INVALID_PARAMETER;
1903 }
1904
1905 pLun = (PPDMLUN)MMR3HeapAlloc(pVM, MM_TAG_PDM_LUN, sizeof(*pLun));
1906 if (!pLun)
1907 return VERR_NO_MEMORY;
1908
1909 pLun->iLun = iLun;
1910 pLun->pNext = pLunPrev ? pLunPrev->pNext : NULL;
1911 pLun->pTop = NULL;
1912 pLun->pBottom = NULL;
1913 pLun->pDevIns = pDevIns;
1914 pLun->pUsbIns = NULL;
1915 pLun->pszDesc = pszDesc;
1916 pLun->pBase = pBaseInterface;
1917 if (!pLunPrev)
1918 pDevIns->Internal.s.pLunsR3 = pLun;
1919 else
1920 pLunPrev->pNext = pLun;
1921 Log(("pdmR3DevHlp_DriverAttach: Registered LUN#%d '%s' with device '%s'/%d.\n",
1922 iLun, pszDesc, pDevIns->pReg->szName, pDevIns->iInstance));
1923 }
1924 else if (pLun->pTop)
1925 {
1926 AssertMsgFailed(("Already attached! The device should keep track of such things!\n"));
1927 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_PDM_DRIVER_ALREADY_ATTACHED));
1928 return VERR_PDM_DRIVER_ALREADY_ATTACHED;
1929 }
1930 Assert(pLun->pBase == pBaseInterface);
1931
1932
1933 /*
1934 * Get the attached driver configuration.
1935 */
1936 int rc;
1937 PCFGMNODE pNode = CFGMR3GetChildF(pDevIns->Internal.s.pCfgHandle, "LUN#%u", iLun);
1938 if (pNode)
1939 rc = pdmR3DrvInstantiate(pVM, pNode, pBaseInterface, NULL /*pDrvAbove*/, pLun, ppBaseInterface);
1940 else
1941 rc = VERR_PDM_NO_ATTACHED_DRIVER;
1942
1943 LogFlow(("pdmR3DevHlp_DriverAttach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1944 return rc;
1945}
1946
1947
1948/** @interface_method_impl{PDMDEVHLPR3,pfnDriverDetach} */
1949static DECLCALLBACK(int) pdmR3DevHlp_DriverDetach(PPDMDEVINS pDevIns, PPDMDRVINS pDrvIns, uint32_t fFlags)
1950{
1951 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
1952 LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: pDrvIns=%p\n",
1953 pDevIns->pReg->szName, pDevIns->iInstance, pDrvIns));
1954
1955#ifdef VBOX_STRICT
1956 PVM pVM = pDevIns->Internal.s.pVMR3;
1957 VM_ASSERT_EMT(pVM);
1958#endif
1959
1960 int rc = pdmR3DrvDetach(pDrvIns, fFlags);
1961
1962 LogFlow(("pdmR3DevHlp_DriverDetach: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
1963 return rc;
1964}
1965
1966
1967/** @interface_method_impl{PDMDEVHLPR3,pfnQueueCreate} */
1968static DECLCALLBACK(int) pdmR3DevHlp_QueueCreate(PPDMDEVINS pDevIns, size_t cbItem, uint32_t cItems, uint32_t cMilliesInterval,
1969 PFNPDMQUEUEDEV pfnCallback, bool fRZEnabled, const char *pszName, PPDMQUEUE *ppQueue)
1970{
1971 PDMDEV_ASSERT_DEVINS(pDevIns);
1972 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: cbItem=%#x cItems=%#x cMilliesInterval=%u pfnCallback=%p fRZEnabled=%RTbool pszName=%p:{%s} ppQueue=%p\n",
1973 pDevIns->pReg->szName, pDevIns->iInstance, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, pszName, ppQueue));
1974
1975 PVM pVM = pDevIns->Internal.s.pVMR3;
1976 VM_ASSERT_EMT(pVM);
1977
1978 if (pDevIns->iInstance > 0)
1979 {
1980 pszName = MMR3HeapAPrintf(pVM, MM_TAG_PDM_DEVICE_DESC, "%s_%u", pszName, pDevIns->iInstance);
1981 AssertLogRelReturn(pszName, VERR_NO_MEMORY);
1982 }
1983
1984 int rc = PDMR3QueueCreateDevice(pVM, pDevIns, cbItem, cItems, cMilliesInterval, pfnCallback, fRZEnabled, pszName, ppQueue);
1985
1986 LogFlow(("pdmR3DevHlp_QueueCreate: caller='%s'/%d: returns %Rrc *ppQueue=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, rc, *ppQueue));
1987 return rc;
1988}
1989
1990
1991/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectInit} */
1992static DECLCALLBACK(int) pdmR3DevHlp_CritSectInit(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect, RT_SRC_POS_DECL,
1993 const char *pszNameFmt, va_list va)
1994{
1995 PDMDEV_ASSERT_DEVINS(pDevIns);
1996 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: pCritSect=%p pszNameFmt=%p:{%s}\n",
1997 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pszNameFmt, pszNameFmt));
1998
1999 PVM pVM = pDevIns->Internal.s.pVMR3;
2000 VM_ASSERT_EMT(pVM);
2001 int rc = pdmR3CritSectInitDevice(pVM, pDevIns, pCritSect, RT_SRC_POS_ARGS, pszNameFmt, va);
2002
2003 LogFlow(("pdmR3DevHlp_CritSectInit: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2004 return rc;
2005}
2006
2007
2008/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNop} */
2009static DECLCALLBACK(PPDMCRITSECT) pdmR3DevHlp_CritSectGetNop(PPDMDEVINS pDevIns)
2010{
2011 PDMDEV_ASSERT_DEVINS(pDevIns);
2012 PVM pVM = pDevIns->Internal.s.pVMR3;
2013 VM_ASSERT_EMT(pVM);
2014
2015 PPDMCRITSECT pCritSect = PDMR3CritSectGetNop(pVM);
2016 LogFlow(("pdmR3DevHlp_CritSectGetNop: caller='%s'/%d: return %p\n",
2017 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
2018 return pCritSect;
2019}
2020
2021
2022/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopR0} */
2023static DECLCALLBACK(R0PTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopR0(PPDMDEVINS pDevIns)
2024{
2025 PDMDEV_ASSERT_DEVINS(pDevIns);
2026 PVM pVM = pDevIns->Internal.s.pVMR3;
2027 VM_ASSERT_EMT(pVM);
2028
2029 R0PTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopR0(pVM);
2030 LogFlow(("pdmR3DevHlp_CritSectGetNopR0: caller='%s'/%d: return %RHv\n",
2031 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
2032 return pCritSect;
2033}
2034
2035
2036/** @interface_method_impl{PDMDEVHLPR3,pfnCritSectGetNopRC} */
2037static DECLCALLBACK(RCPTRTYPE(PPDMCRITSECT)) pdmR3DevHlp_CritSectGetNopRC(PPDMDEVINS pDevIns)
2038{
2039 PDMDEV_ASSERT_DEVINS(pDevIns);
2040 PVM pVM = pDevIns->Internal.s.pVMR3;
2041 VM_ASSERT_EMT(pVM);
2042
2043 RCPTRTYPE(PPDMCRITSECT) pCritSect = PDMR3CritSectGetNopRC(pVM);
2044 LogFlow(("pdmR3DevHlp_CritSectGetNopRC: caller='%s'/%d: return %RRv\n",
2045 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect));
2046 return pCritSect;
2047}
2048
2049
2050/** @interface_method_impl{PDMDEVHLPR3,pfnSetDeviceCritSect} */
2051static DECLCALLBACK(int) pdmR3DevHlp_SetDeviceCritSect(PPDMDEVINS pDevIns, PPDMCRITSECT pCritSect)
2052{
2053 /*
2054 * Validate input.
2055 *
2056 * Note! We only allow the automatically created default critical section
2057 * to be replaced by this API.
2058 */
2059 PDMDEV_ASSERT_DEVINS(pDevIns);
2060 AssertPtrReturn(pCritSect, VERR_INVALID_POINTER);
2061 LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: pCritSect=%p (%s)\n",
2062 pDevIns->pReg->szName, pDevIns->iInstance, pCritSect, pCritSect->s.pszName));
2063 AssertReturn(PDMCritSectIsInitialized(pCritSect), VERR_INVALID_PARAMETER);
2064 PVM pVM = pDevIns->Internal.s.pVMR3;
2065 AssertReturn(pCritSect->s.pVMR3 == pVM, VERR_INVALID_PARAMETER);
2066
2067 VM_ASSERT_EMT(pVM);
2068 VM_ASSERT_STATE_RETURN(pVM, VMSTATE_CREATING, VERR_WRONG_ORDER);
2069
2070 AssertReturn(pDevIns->pCritSectRoR3, VERR_PDM_DEV_IPE_1);
2071 AssertReturn(pDevIns->pCritSectRoR3->s.fAutomaticDefaultCritsect, VERR_WRONG_ORDER);
2072 AssertReturn(!pDevIns->pCritSectRoR3->s.fUsedByTimerOrSimilar, VERR_WRONG_ORDER);
2073 AssertReturn(pDevIns->pCritSectRoR3 != pCritSect, VERR_INVALID_PARAMETER);
2074
2075 /*
2076 * Replace the critical section and destroy the automatic default section.
2077 */
2078 PPDMCRITSECT pOldCritSect = pDevIns->pCritSectRoR3;
2079 pDevIns->pCritSectRoR3 = pCritSect;
2080 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2081 pDevIns->pCritSectRoR0 = MMHyperCCToR0(pVM, pDevIns->pCritSectRoR3);
2082 else
2083 Assert(pDevIns->pCritSectRoR0 == NIL_RTRCPTR);
2084
2085 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2086 pDevIns->pCritSectRoRC = MMHyperCCToRC(pVM, pDevIns->pCritSectRoR3);
2087 else
2088 Assert(pDevIns->pCritSectRoRC == NIL_RTRCPTR);
2089
2090 PDMR3CritSectDelete(pOldCritSect);
2091 if (pDevIns->pReg->fFlags & (PDM_DEVREG_FLAGS_RC | PDM_DEVREG_FLAGS_R0))
2092 MMHyperFree(pVM, pOldCritSect);
2093 else
2094 MMR3HeapFree(pOldCritSect);
2095
2096 LogFlow(("pdmR3DevHlp_SetDeviceCritSect: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2097 return VINF_SUCCESS;
2098}
2099
2100
2101/** @interface_method_impl{PDMDEVHLPR3,pfnThreadCreate} */
2102static DECLCALLBACK(int) pdmR3DevHlp_ThreadCreate(PPDMDEVINS pDevIns, PPPDMTHREAD ppThread, void *pvUser, PFNPDMTHREADDEV pfnThread,
2103 PFNPDMTHREADWAKEUPDEV pfnWakeup, size_t cbStack, RTTHREADTYPE enmType, const char *pszName)
2104{
2105 PDMDEV_ASSERT_DEVINS(pDevIns);
2106 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2107 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: ppThread=%p pvUser=%p pfnThread=%p pfnWakeup=%p cbStack=%#zx enmType=%d pszName=%p:{%s}\n",
2108 pDevIns->pReg->szName, pDevIns->iInstance, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName, pszName));
2109
2110 int rc = pdmR3ThreadCreateDevice(pDevIns->Internal.s.pVMR3, pDevIns, ppThread, pvUser, pfnThread, pfnWakeup, cbStack, enmType, pszName);
2111
2112 LogFlow(("pdmR3DevHlp_ThreadCreate: caller='%s'/%d: returns %Rrc *ppThread=%RTthrd\n", pDevIns->pReg->szName, pDevIns->iInstance,
2113 rc, *ppThread));
2114 return rc;
2115}
2116
2117
2118/** @interface_method_impl{PDMDEVHLPR3,pfnSetAsyncNotification} */
2119static DECLCALLBACK(int) pdmR3DevHlp_SetAsyncNotification(PPDMDEVINS pDevIns, PFNPDMDEVASYNCNOTIFY pfnAsyncNotify)
2120{
2121 PDMDEV_ASSERT_DEVINS(pDevIns);
2122 VM_ASSERT_EMT0(pDevIns->Internal.s.pVMR3);
2123 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: pfnAsyncNotify=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pfnAsyncNotify));
2124
2125 int rc = VINF_SUCCESS;
2126 AssertStmt(pfnAsyncNotify, rc = VERR_INVALID_PARAMETER);
2127 AssertStmt(!pDevIns->Internal.s.pfnAsyncNotify, rc = VERR_WRONG_ORDER);
2128 AssertStmt(pDevIns->Internal.s.fIntFlags & (PDMDEVINSINT_FLAGS_SUSPENDED | PDMDEVINSINT_FLAGS_RESET), rc = VERR_WRONG_ORDER);
2129 VMSTATE enmVMState = VMR3GetState(pDevIns->Internal.s.pVMR3);
2130 AssertStmt( enmVMState == VMSTATE_SUSPENDING
2131 || enmVMState == VMSTATE_SUSPENDING_EXT_LS
2132 || enmVMState == VMSTATE_SUSPENDING_LS
2133 || enmVMState == VMSTATE_RESETTING
2134 || enmVMState == VMSTATE_RESETTING_LS
2135 || enmVMState == VMSTATE_POWERING_OFF
2136 || enmVMState == VMSTATE_POWERING_OFF_LS,
2137 rc = VERR_INVALID_STATE);
2138
2139 if (RT_SUCCESS(rc))
2140 pDevIns->Internal.s.pfnAsyncNotify = pfnAsyncNotify;
2141
2142 LogFlow(("pdmR3DevHlp_SetAsyncNotification: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2143 return rc;
2144}
2145
2146
2147/** @interface_method_impl{PDMDEVHLPR3,pfnAsyncNotificationCompleted} */
2148static DECLCALLBACK(void) pdmR3DevHlp_AsyncNotificationCompleted(PPDMDEVINS pDevIns)
2149{
2150 PDMDEV_ASSERT_DEVINS(pDevIns);
2151 PVM pVM = pDevIns->Internal.s.pVMR3;
2152
2153 VMSTATE enmVMState = VMR3GetState(pVM);
2154 if ( enmVMState == VMSTATE_SUSPENDING
2155 || enmVMState == VMSTATE_SUSPENDING_EXT_LS
2156 || enmVMState == VMSTATE_SUSPENDING_LS
2157 || enmVMState == VMSTATE_RESETTING
2158 || enmVMState == VMSTATE_RESETTING_LS
2159 || enmVMState == VMSTATE_POWERING_OFF
2160 || enmVMState == VMSTATE_POWERING_OFF_LS)
2161 {
2162 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
2163 VMR3AsyncPdmNotificationWakeupU(pVM->pUVM);
2164 }
2165 else
2166 LogFlow(("pdmR3DevHlp_AsyncNotificationCompleted: caller='%s'/%d: enmVMState=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, enmVMState));
2167}
2168
2169
2170/** @interface_method_impl{PDMDEVHLPR3,pfnRTCRegister} */
2171static DECLCALLBACK(int) pdmR3DevHlp_RTCRegister(PPDMDEVINS pDevIns, PCPDMRTCREG pRtcReg, PCPDMRTCHLP *ppRtcHlp)
2172{
2173 PDMDEV_ASSERT_DEVINS(pDevIns);
2174 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2175 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: pRtcReg=%p:{.u32Version=%#x, .pfnWrite=%p, .pfnRead=%p} ppRtcHlp=%p\n",
2176 pDevIns->pReg->szName, pDevIns->iInstance, pRtcReg, pRtcReg->u32Version, pRtcReg->pfnWrite,
2177 pRtcReg->pfnWrite, ppRtcHlp));
2178
2179 /*
2180 * Validate input.
2181 */
2182 if (pRtcReg->u32Version != PDM_RTCREG_VERSION)
2183 {
2184 AssertMsgFailed(("u32Version=%#x expected %#x\n", pRtcReg->u32Version,
2185 PDM_RTCREG_VERSION));
2186 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (version)\n",
2187 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2188 return VERR_INVALID_PARAMETER;
2189 }
2190 if ( !pRtcReg->pfnWrite
2191 || !pRtcReg->pfnRead)
2192 {
2193 Assert(pRtcReg->pfnWrite);
2194 Assert(pRtcReg->pfnRead);
2195 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
2196 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2197 return VERR_INVALID_PARAMETER;
2198 }
2199
2200 if (!ppRtcHlp)
2201 {
2202 Assert(ppRtcHlp);
2203 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc (ppRtcHlp)\n",
2204 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2205 return VERR_INVALID_PARAMETER;
2206 }
2207
2208 /*
2209 * Only one DMA device.
2210 */
2211 PVM pVM = pDevIns->Internal.s.pVMR3;
2212 if (pVM->pdm.s.pRtc)
2213 {
2214 AssertMsgFailed(("Only one RTC device is supported!\n"));
2215 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
2216 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2217 return VERR_INVALID_PARAMETER;
2218 }
2219
2220 /*
2221 * Allocate and initialize pci bus structure.
2222 */
2223 int rc = VINF_SUCCESS;
2224 PPDMRTC pRtc = (PPDMRTC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pRtc));
2225 if (pRtc)
2226 {
2227 pRtc->pDevIns = pDevIns;
2228 pRtc->Reg = *pRtcReg;
2229 pVM->pdm.s.pRtc = pRtc;
2230
2231 /* set the helper pointer. */
2232 *ppRtcHlp = &g_pdmR3DevRtcHlp;
2233 Log(("PDM: Registered RTC device '%s'/%d pDevIns=%p\n",
2234 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2235 }
2236 else
2237 rc = VERR_NO_MEMORY;
2238
2239 LogFlow(("pdmR3DevHlp_RTCRegister: caller='%s'/%d: returns %Rrc\n",
2240 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2241 return rc;
2242}
2243
2244
2245/** @interface_method_impl{PDMDEVHLPR3,pfnDMARegister} */
2246static DECLCALLBACK(int) pdmR3DevHlp_DMARegister(PPDMDEVINS pDevIns, unsigned uChannel, PFNDMATRANSFERHANDLER pfnTransferHandler, void *pvUser)
2247{
2248 PDMDEV_ASSERT_DEVINS(pDevIns);
2249 PVM pVM = pDevIns->Internal.s.pVMR3;
2250 VM_ASSERT_EMT(pVM);
2251 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: uChannel=%d pfnTransferHandler=%p pvUser=%p\n",
2252 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pfnTransferHandler, pvUser));
2253 int rc = VINF_SUCCESS;
2254 if (pVM->pdm.s.pDmac)
2255 pVM->pdm.s.pDmac->Reg.pfnRegister(pVM->pdm.s.pDmac->pDevIns, uChannel, pfnTransferHandler, pvUser);
2256 else
2257 {
2258 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2259 rc = VERR_PDM_NO_DMAC_INSTANCE;
2260 }
2261 LogFlow(("pdmR3DevHlp_DMARegister: caller='%s'/%d: returns %Rrc\n",
2262 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2263 return rc;
2264}
2265
2266
2267/** @interface_method_impl{PDMDEVHLPR3,pfnDMAReadMemory} */
2268static DECLCALLBACK(int) pdmR3DevHlp_DMAReadMemory(PPDMDEVINS pDevIns, unsigned uChannel, void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbRead)
2269{
2270 PDMDEV_ASSERT_DEVINS(pDevIns);
2271 PVM pVM = pDevIns->Internal.s.pVMR3;
2272 VM_ASSERT_EMT(pVM);
2273 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbRead=%p\n",
2274 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbRead));
2275 int rc = VINF_SUCCESS;
2276 if (pVM->pdm.s.pDmac)
2277 {
2278 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnReadMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2279 if (pcbRead)
2280 *pcbRead = cb;
2281 }
2282 else
2283 {
2284 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2285 rc = VERR_PDM_NO_DMAC_INSTANCE;
2286 }
2287 LogFlow(("pdmR3DevHlp_DMAReadMemory: caller='%s'/%d: returns %Rrc\n",
2288 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2289 return rc;
2290}
2291
2292
2293/** @interface_method_impl{PDMDEVHLPR3,pfnDMAWriteMemory} */
2294static DECLCALLBACK(int) pdmR3DevHlp_DMAWriteMemory(PPDMDEVINS pDevIns, unsigned uChannel, const void *pvBuffer, uint32_t off, uint32_t cbBlock, uint32_t *pcbWritten)
2295{
2296 PDMDEV_ASSERT_DEVINS(pDevIns);
2297 PVM pVM = pDevIns->Internal.s.pVMR3;
2298 VM_ASSERT_EMT(pVM);
2299 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: uChannel=%d pvBuffer=%p off=%#x cbBlock=%#x pcbWritten=%p\n",
2300 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, pvBuffer, off, cbBlock, pcbWritten));
2301 int rc = VINF_SUCCESS;
2302 if (pVM->pdm.s.pDmac)
2303 {
2304 uint32_t cb = pVM->pdm.s.pDmac->Reg.pfnWriteMemory(pVM->pdm.s.pDmac->pDevIns, uChannel, pvBuffer, off, cbBlock);
2305 if (pcbWritten)
2306 *pcbWritten = cb;
2307 }
2308 else
2309 {
2310 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2311 rc = VERR_PDM_NO_DMAC_INSTANCE;
2312 }
2313 LogFlow(("pdmR3DevHlp_DMAWriteMemory: caller='%s'/%d: returns %Rrc\n",
2314 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2315 return rc;
2316}
2317
2318
2319/** @interface_method_impl{PDMDEVHLPR3,pfnDMASetDREQ} */
2320static DECLCALLBACK(int) pdmR3DevHlp_DMASetDREQ(PPDMDEVINS pDevIns, unsigned uChannel, unsigned uLevel)
2321{
2322 PDMDEV_ASSERT_DEVINS(pDevIns);
2323 PVM pVM = pDevIns->Internal.s.pVMR3;
2324 VM_ASSERT_EMT(pVM);
2325 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: uChannel=%d uLevel=%d\n",
2326 pDevIns->pReg->szName, pDevIns->iInstance, uChannel, uLevel));
2327 int rc = VINF_SUCCESS;
2328 if (pVM->pdm.s.pDmac)
2329 pVM->pdm.s.pDmac->Reg.pfnSetDREQ(pVM->pdm.s.pDmac->pDevIns, uChannel, uLevel);
2330 else
2331 {
2332 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2333 rc = VERR_PDM_NO_DMAC_INSTANCE;
2334 }
2335 LogFlow(("pdmR3DevHlp_DMASetDREQ: caller='%s'/%d: returns %Rrc\n",
2336 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2337 return rc;
2338}
2339
2340/** @interface_method_impl{PDMDEVHLPR3,pfnDMAGetChannelMode} */
2341static DECLCALLBACK(uint8_t) pdmR3DevHlp_DMAGetChannelMode(PPDMDEVINS pDevIns, unsigned uChannel)
2342{
2343 PDMDEV_ASSERT_DEVINS(pDevIns);
2344 PVM pVM = pDevIns->Internal.s.pVMR3;
2345 VM_ASSERT_EMT(pVM);
2346 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: uChannel=%d\n",
2347 pDevIns->pReg->szName, pDevIns->iInstance, uChannel));
2348 uint8_t u8Mode;
2349 if (pVM->pdm.s.pDmac)
2350 u8Mode = pVM->pdm.s.pDmac->Reg.pfnGetChannelMode(pVM->pdm.s.pDmac->pDevIns, uChannel);
2351 else
2352 {
2353 AssertMsgFailed(("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2354 u8Mode = 3 << 2 /* illegal mode type */;
2355 }
2356 LogFlow(("pdmR3DevHlp_DMAGetChannelMode: caller='%s'/%d: returns %#04x\n",
2357 pDevIns->pReg->szName, pDevIns->iInstance, u8Mode));
2358 return u8Mode;
2359}
2360
2361/** @interface_method_impl{PDMDEVHLPR3,pfnDMASchedule} */
2362static DECLCALLBACK(void) pdmR3DevHlp_DMASchedule(PPDMDEVINS pDevIns)
2363{
2364 PDMDEV_ASSERT_DEVINS(pDevIns);
2365 PVM pVM = pDevIns->Internal.s.pVMR3;
2366 VM_ASSERT_EMT(pVM);
2367 LogFlow(("pdmR3DevHlp_DMASchedule: caller='%s'/%d: VM_FF_PDM_DMA %d -> 1\n",
2368 pDevIns->pReg->szName, pDevIns->iInstance, VM_FF_IS_SET(pVM, VM_FF_PDM_DMA)));
2369
2370 AssertMsg(pVM->pdm.s.pDmac, ("Configuration error: No DMAC controller available. This could be related to init order too!\n"));
2371 VM_FF_SET(pVM, VM_FF_PDM_DMA);
2372#ifdef VBOX_WITH_REM
2373 REMR3NotifyDmaPending(pVM);
2374#endif
2375 VMR3NotifyGlobalFFU(pVM->pUVM, VMNOTIFYFF_FLAGS_DONE_REM);
2376}
2377
2378
2379/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSWrite} */
2380static DECLCALLBACK(int) pdmR3DevHlp_CMOSWrite(PPDMDEVINS pDevIns, unsigned iReg, uint8_t u8Value)
2381{
2382 PDMDEV_ASSERT_DEVINS(pDevIns);
2383 PVM pVM = pDevIns->Internal.s.pVMR3;
2384 VM_ASSERT_EMT(pVM);
2385
2386 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x u8Value=%#04x\n",
2387 pDevIns->pReg->szName, pDevIns->iInstance, iReg, u8Value));
2388 int rc;
2389 if (pVM->pdm.s.pRtc)
2390 {
2391 PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2392 rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2393 if (RT_SUCCESS(rc))
2394 {
2395 rc = pVM->pdm.s.pRtc->Reg.pfnWrite(pDevInsRtc, iReg, u8Value);
2396 PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2397 }
2398 }
2399 else
2400 rc = VERR_PDM_NO_RTC_INSTANCE;
2401
2402 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2403 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2404 return rc;
2405}
2406
2407
2408/** @interface_method_impl{PDMDEVHLPR3,pfnCMOSRead} */
2409static DECLCALLBACK(int) pdmR3DevHlp_CMOSRead(PPDMDEVINS pDevIns, unsigned iReg, uint8_t *pu8Value)
2410{
2411 PDMDEV_ASSERT_DEVINS(pDevIns);
2412 PVM pVM = pDevIns->Internal.s.pVMR3;
2413 VM_ASSERT_EMT(pVM);
2414
2415 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: iReg=%#04x pu8Value=%p\n",
2416 pDevIns->pReg->szName, pDevIns->iInstance, iReg, pu8Value));
2417 int rc;
2418 if (pVM->pdm.s.pRtc)
2419 {
2420 PPDMDEVINS pDevInsRtc = pVM->pdm.s.pRtc->pDevIns;
2421 rc = PDMCritSectEnter(pDevInsRtc->pCritSectRoR3, VERR_IGNORED);
2422 if (RT_SUCCESS(rc))
2423 {
2424 rc = pVM->pdm.s.pRtc->Reg.pfnRead(pDevInsRtc, iReg, pu8Value);
2425 PDMCritSectLeave(pDevInsRtc->pCritSectRoR3);
2426 }
2427 }
2428 else
2429 rc = VERR_PDM_NO_RTC_INSTANCE;
2430
2431 LogFlow(("pdmR3DevHlp_CMOSWrite: caller='%s'/%d: return %Rrc\n",
2432 pDevIns->pReg->szName, pDevIns->iInstance, rc));
2433 return rc;
2434}
2435
2436
2437/** @interface_method_impl{PDMDEVHLPR3,pfnAssertEMT} */
2438static DECLCALLBACK(bool) pdmR3DevHlp_AssertEMT(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction)
2439{
2440 PDMDEV_ASSERT_DEVINS(pDevIns);
2441 if (VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2442 return true;
2443
2444 char szMsg[100];
2445 RTStrPrintf(szMsg, sizeof(szMsg), "AssertEMT '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2446 RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2447 AssertBreakpoint();
2448 return false;
2449}
2450
2451
2452/** @interface_method_impl{PDMDEVHLPR3,pfnAssertOther} */
2453static DECLCALLBACK(bool) pdmR3DevHlp_AssertOther(PPDMDEVINS pDevIns, const char *pszFile, unsigned iLine, const char *pszFunction)
2454{
2455 PDMDEV_ASSERT_DEVINS(pDevIns);
2456 if (!VM_IS_EMT(pDevIns->Internal.s.pVMR3))
2457 return true;
2458
2459 char szMsg[100];
2460 RTStrPrintf(szMsg, sizeof(szMsg), "AssertOther '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance);
2461 RTAssertMsg1Weak(szMsg, iLine, pszFile, pszFunction);
2462 AssertBreakpoint();
2463 return false;
2464}
2465
2466
2467/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetRCInterfaceSymbols} */
2468static DECLCALLBACK(int) pdmR3DevHlp_LdrGetRCInterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2469 const char *pszSymPrefix, const char *pszSymList)
2470{
2471 PDMDEV_ASSERT_DEVINS(pDevIns);
2472 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2473 LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2474 pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2475
2476 int rc;
2477 if ( strncmp(pszSymPrefix, "dev", 3) == 0
2478 && RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2479 {
2480 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC)
2481 rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2482 pvInterface, cbInterface,
2483 pDevIns->pReg->szRCMod, pDevIns->Internal.s.pDevR3->pszRCSearchPath,
2484 pszSymPrefix, pszSymList,
2485 false /*fRing0OrRC*/);
2486 else
2487 {
2488 AssertMsgFailed(("Not a raw-mode enabled driver\n"));
2489 rc = VERR_PERMISSION_DENIED;
2490 }
2491 }
2492 else
2493 {
2494 AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2495 pszSymPrefix, pDevIns->pReg->szName));
2496 rc = VERR_INVALID_NAME;
2497 }
2498
2499 LogFlow(("pdmR3DevHlp_PDMLdrGetRCInterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2500 pDevIns->iInstance, rc));
2501 return rc;
2502}
2503
2504
2505/** @interface_method_impl{PDMDEVHLPR3,pfnLdrGetR0InterfaceSymbols} */
2506static DECLCALLBACK(int) pdmR3DevHlp_LdrGetR0InterfaceSymbols(PPDMDEVINS pDevIns, void *pvInterface, size_t cbInterface,
2507 const char *pszSymPrefix, const char *pszSymList)
2508{
2509 PDMDEV_ASSERT_DEVINS(pDevIns);
2510 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2511 LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: pvInterface=%p cbInterface=%zu pszSymPrefix=%p:{%s} pszSymList=%p:{%s}\n",
2512 pDevIns->pReg->szName, pDevIns->iInstance, pvInterface, cbInterface, pszSymPrefix, pszSymPrefix, pszSymList, pszSymList));
2513
2514 int rc;
2515 if ( strncmp(pszSymPrefix, "dev", 3) == 0
2516 && RTStrIStr(pszSymPrefix + 3, pDevIns->pReg->szName) != NULL)
2517 {
2518 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2519 rc = PDMR3LdrGetInterfaceSymbols(pDevIns->Internal.s.pVMR3,
2520 pvInterface, cbInterface,
2521 pDevIns->pReg->szR0Mod, pDevIns->Internal.s.pDevR3->pszR0SearchPath,
2522 pszSymPrefix, pszSymList,
2523 true /*fRing0OrRC*/);
2524 else
2525 {
2526 AssertMsgFailed(("Not a ring-0 enabled driver\n"));
2527 rc = VERR_PERMISSION_DENIED;
2528 }
2529 }
2530 else
2531 {
2532 AssertMsgFailed(("Invalid prefix '%s' for '%s'; must start with 'dev' and contain the driver name!\n",
2533 pszSymPrefix, pDevIns->pReg->szName));
2534 rc = VERR_INVALID_NAME;
2535 }
2536
2537 LogFlow(("pdmR3DevHlp_PDMLdrGetR0InterfaceSymbols: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2538 pDevIns->iInstance, rc));
2539 return rc;
2540}
2541
2542
2543/** @interface_method_impl{PDMDEVHLPR3,pfnCallR0} */
2544static DECLCALLBACK(int) pdmR3DevHlp_CallR0(PPDMDEVINS pDevIns, uint32_t uOperation, uint64_t u64Arg)
2545{
2546 PDMDEV_ASSERT_DEVINS(pDevIns);
2547 PVM pVM = pDevIns->Internal.s.pVMR3;
2548 VM_ASSERT_EMT(pVM);
2549 LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: uOperation=%#x u64Arg=%#RX64\n",
2550 pDevIns->pReg->szName, pDevIns->iInstance, uOperation, u64Arg));
2551
2552 /*
2553 * Resolve the ring-0 entry point. There is not need to remember this like
2554 * we do for drivers since this is mainly for construction time hacks and
2555 * other things that aren't performance critical.
2556 */
2557 int rc;
2558 if (pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0)
2559 {
2560 char szSymbol[ sizeof("devR0") + sizeof(pDevIns->pReg->szName) + sizeof("ReqHandler")];
2561 strcat(strcat(strcpy(szSymbol, "devR0"), pDevIns->pReg->szName), "ReqHandler");
2562 szSymbol[sizeof("devR0") - 1] = RT_C_TO_UPPER(szSymbol[sizeof("devR0") - 1]);
2563
2564 PFNPDMDRVREQHANDLERR0 pfnReqHandlerR0;
2565 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, szSymbol, &pfnReqHandlerR0);
2566 if (RT_SUCCESS(rc))
2567 {
2568 /*
2569 * Make the ring-0 call.
2570 */
2571 PDMDEVICECALLREQHANDLERREQ Req;
2572 Req.Hdr.u32Magic = SUPVMMR0REQHDR_MAGIC;
2573 Req.Hdr.cbReq = sizeof(Req);
2574 Req.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2575 Req.pfnReqHandlerR0 = pfnReqHandlerR0;
2576 Req.uOperation = uOperation;
2577 Req.u32Alignment = 0;
2578 Req.u64Arg = u64Arg;
2579 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, NIL_VMCPUID, VMMR0_DO_PDM_DEVICE_CALL_REQ_HANDLER, 0, &Req.Hdr);
2580 }
2581 else
2582 pfnReqHandlerR0 = NIL_RTR0PTR;
2583 }
2584 else
2585 rc = VERR_ACCESS_DENIED;
2586 LogFlow(("pdmR3DevHlp_CallR0: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName,
2587 pDevIns->iInstance, rc));
2588 return rc;
2589}
2590
2591
2592/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetSuspendReason} */
2593static DECLCALLBACK(VMSUSPENDREASON) pdmR3DevHlp_VMGetSuspendReason(PPDMDEVINS pDevIns)
2594{
2595 PDMDEV_ASSERT_DEVINS(pDevIns);
2596 PVM pVM = pDevIns->Internal.s.pVMR3;
2597 VM_ASSERT_EMT(pVM);
2598 VMSUSPENDREASON enmReason = VMR3GetSuspendReason(pVM->pUVM);
2599 LogFlow(("pdmR3DevHlp_VMGetSuspendReason: caller='%s'/%d: returns %d\n",
2600 pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
2601 return enmReason;
2602}
2603
2604
2605/** @interface_method_impl{PDMDEVHLPR3,pfnVMGetResumeReason} */
2606static DECLCALLBACK(VMRESUMEREASON) pdmR3DevHlp_VMGetResumeReason(PPDMDEVINS pDevIns)
2607{
2608 PDMDEV_ASSERT_DEVINS(pDevIns);
2609 PVM pVM = pDevIns->Internal.s.pVMR3;
2610 VM_ASSERT_EMT(pVM);
2611 VMRESUMEREASON enmReason = VMR3GetResumeReason(pVM->pUVM);
2612 LogFlow(("pdmR3DevHlp_VMGetResumeReason: caller='%s'/%d: returns %d\n",
2613 pDevIns->pReg->szName, pDevIns->iInstance, enmReason));
2614 return enmReason;
2615}
2616
2617
2618/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
2619static DECLCALLBACK(PUVM) pdmR3DevHlp_GetUVM(PPDMDEVINS pDevIns)
2620{
2621 PDMDEV_ASSERT_DEVINS(pDevIns);
2622 LogFlow(("pdmR3DevHlp_GetUVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2623 return pDevIns->Internal.s.pVMR3->pUVM;
2624}
2625
2626
2627/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
2628static DECLCALLBACK(PVM) pdmR3DevHlp_GetVM(PPDMDEVINS pDevIns)
2629{
2630 PDMDEV_ASSERT_DEVINS(pDevIns);
2631 LogFlow(("pdmR3DevHlp_GetVM: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns->Internal.s.pVMR3));
2632 return pDevIns->Internal.s.pVMR3;
2633}
2634
2635
2636/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
2637static DECLCALLBACK(PVMCPU) pdmR3DevHlp_GetVMCPU(PPDMDEVINS pDevIns)
2638{
2639 PDMDEV_ASSERT_DEVINS(pDevIns);
2640 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2641 LogFlow(("pdmR3DevHlp_GetVMCPU: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, VMMGetCpuId(pDevIns->Internal.s.pVMR3)));
2642 return VMMGetCpu(pDevIns->Internal.s.pVMR3);
2643}
2644
2645
2646/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
2647static DECLCALLBACK(VMCPUID) pdmR3DevHlp_GetCurrentCpuId(PPDMDEVINS pDevIns)
2648{
2649 PDMDEV_ASSERT_DEVINS(pDevIns);
2650 VMCPUID idCpu = VMMGetCpuId(pDevIns->Internal.s.pVMR3);
2651 LogFlow(("pdmR3DevHlp_GetCurrentCpuId: caller='%s'/%d for CPU %u\n", pDevIns->pReg->szName, pDevIns->iInstance, idCpu));
2652 return idCpu;
2653}
2654
2655
2656/** @interface_method_impl{PDMDEVHLPR3,pfnPCIBusRegister} */
2657static DECLCALLBACK(int) pdmR3DevHlp_PCIBusRegister(PPDMDEVINS pDevIns, PPDMPCIBUSREG pPciBusReg,
2658 PCPDMPCIHLPR3 *ppPciHlpR3, uint32_t *piBus)
2659{
2660 PDMDEV_ASSERT_DEVINS(pDevIns);
2661 PVM pVM = pDevIns->Internal.s.pVMR3;
2662 VM_ASSERT_EMT(pVM);
2663 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: pPciBusReg=%p:{.u32Version=%#x, .pfnRegisterR3=%p, .pfnIORegionRegisterR3=%p, "
2664 ".pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppPciHlpR3=%p piBus=%p\n",
2665 pDevIns->pReg->szName, pDevIns->iInstance, pPciBusReg, pPciBusReg->u32Version, pPciBusReg->pfnRegisterR3,
2666 pPciBusReg->pfnIORegionRegisterR3, pPciBusReg->pfnSetIrqR3, pPciBusReg->pszSetIrqRC, pPciBusReg->pszSetIrqRC,
2667 pPciBusReg->pszSetIrqR0, pPciBusReg->pszSetIrqR0, ppPciHlpR3, piBus));
2668
2669 /*
2670 * Validate the structure.
2671 */
2672 if (pPciBusReg->u32Version != PDM_PCIBUSREG_VERSION)
2673 {
2674 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciBusReg->u32Version, PDM_PCIBUSREG_VERSION));
2675 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2676 return VERR_INVALID_PARAMETER;
2677 }
2678 if ( !pPciBusReg->pfnRegisterR3
2679 || !pPciBusReg->pfnIORegionRegisterR3
2680 || !pPciBusReg->pfnSetIrqR3)
2681 {
2682 Assert(pPciBusReg->pfnRegisterR3);
2683 Assert(pPciBusReg->pfnIORegionRegisterR3);
2684 Assert(pPciBusReg->pfnSetIrqR3);
2685 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2686 return VERR_INVALID_PARAMETER;
2687 }
2688 if ( pPciBusReg->pszSetIrqRC
2689 && !VALID_PTR(pPciBusReg->pszSetIrqRC))
2690 {
2691 Assert(VALID_PTR(pPciBusReg->pszSetIrqRC));
2692 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2693 return VERR_INVALID_PARAMETER;
2694 }
2695 if ( pPciBusReg->pszSetIrqR0
2696 && !VALID_PTR(pPciBusReg->pszSetIrqR0))
2697 {
2698 Assert(VALID_PTR(pPciBusReg->pszSetIrqR0));
2699 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2700 return VERR_INVALID_PARAMETER;
2701 }
2702 if (!ppPciHlpR3)
2703 {
2704 Assert(ppPciHlpR3);
2705 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (ppPciHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2706 return VERR_INVALID_PARAMETER;
2707 }
2708 AssertLogRelMsgReturn(RT_VALID_PTR(piBus) || !piBus,
2709 ("caller='%s'/%d: piBus=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, piBus),
2710 VERR_INVALID_POINTER);
2711
2712 /*
2713 * Find free PCI bus entry.
2714 */
2715 unsigned iBus = 0;
2716 for (iBus = 0; iBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses); iBus++)
2717 if (!pVM->pdm.s.aPciBuses[iBus].pDevInsR3)
2718 break;
2719 if (iBus >= RT_ELEMENTS(pVM->pdm.s.aPciBuses))
2720 {
2721 AssertMsgFailed(("Too many PCI buses. Max=%u\n", RT_ELEMENTS(pVM->pdm.s.aPciBuses)));
2722 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc (pci bus)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2723 return VERR_INVALID_PARAMETER;
2724 }
2725 PPDMPCIBUS pPciBus = &pVM->pdm.s.aPciBuses[iBus];
2726
2727 /*
2728 * Resolve and init the RC bits.
2729 */
2730 if (pPciBusReg->pszSetIrqRC)
2731 {
2732 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPciBusReg->pszSetIrqRC, &pPciBus->pfnSetIrqRC);
2733 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPciBusReg->pszSetIrqRC, rc));
2734 if (RT_FAILURE(rc))
2735 {
2736 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2737 return rc;
2738 }
2739 pPciBus->pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2740 }
2741 else
2742 {
2743 pPciBus->pfnSetIrqRC = 0;
2744 pPciBus->pDevInsRC = 0;
2745 }
2746
2747 /*
2748 * Resolve and init the R0 bits.
2749 */
2750 if (pPciBusReg->pszSetIrqR0)
2751 {
2752 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPciBusReg->pszSetIrqR0, &pPciBus->pfnSetIrqR0);
2753 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPciBusReg->pszSetIrqR0, rc));
2754 if (RT_FAILURE(rc))
2755 {
2756 LogFlow(("pdmR3DevHlp_PCIRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2757 return rc;
2758 }
2759 pPciBus->pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2760 }
2761 else
2762 {
2763 pPciBus->pfnSetIrqR0 = 0;
2764 pPciBus->pDevInsR0 = 0;
2765 }
2766
2767 /*
2768 * Init the R3 bits.
2769 */
2770 pPciBus->iBus = iBus;
2771 pPciBus->pDevInsR3 = pDevIns;
2772 pPciBus->pfnRegisterR3 = pPciBusReg->pfnRegisterR3;
2773 pPciBus->pfnRegisterMsiR3 = pPciBusReg->pfnRegisterMsiR3;
2774 pPciBus->pfnIORegionRegisterR3 = pPciBusReg->pfnIORegionRegisterR3;
2775 pPciBus->pfnSetConfigCallbacksR3 = pPciBusReg->pfnSetConfigCallbacksR3;
2776 pPciBus->pfnSetIrqR3 = pPciBusReg->pfnSetIrqR3;
2777
2778 Log(("PDM: Registered PCI bus device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2779
2780 /* set the helper pointer and return. */
2781 *ppPciHlpR3 = &g_pdmR3DevPciHlp;
2782 if (piBus)
2783 *piBus = iBus;
2784 LogFlow(("pdmR3DevHlp_PCIBusRegister: caller='%s'/%d: returns %Rrc *piBus=%u\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS, iBus));
2785 return VINF_SUCCESS;
2786}
2787
2788
2789/** @interface_method_impl{PDMDEVHLPR3,pfnPICRegister} */
2790static DECLCALLBACK(int) pdmR3DevHlp_PICRegister(PPDMDEVINS pDevIns, PPDMPICREG pPicReg, PCPDMPICHLPR3 *ppPicHlpR3)
2791{
2792 PDMDEV_ASSERT_DEVINS(pDevIns);
2793 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2794 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: pPicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pfnGetInterruptR3=%p, .pszGetIrqRC=%p:{%s}, .pszGetInterruptRC=%p:{%s}, .pszGetIrqR0=%p:{%s}, .pszGetInterruptR0=%p:{%s} } ppPicHlpR3=%p\n",
2795 pDevIns->pReg->szName, pDevIns->iInstance, pPicReg, pPicReg->u32Version, pPicReg->pfnSetIrqR3, pPicReg->pfnGetInterruptR3,
2796 pPicReg->pszSetIrqRC, pPicReg->pszSetIrqRC, pPicReg->pszGetInterruptRC, pPicReg->pszGetInterruptRC,
2797 pPicReg->pszSetIrqR0, pPicReg->pszSetIrqR0, pPicReg->pszGetInterruptR0, pPicReg->pszGetInterruptR0,
2798 ppPicHlpR3));
2799
2800 /*
2801 * Validate input.
2802 */
2803 if (pPicReg->u32Version != PDM_PICREG_VERSION)
2804 {
2805 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPicReg->u32Version, PDM_PICREG_VERSION));
2806 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2807 return VERR_INVALID_PARAMETER;
2808 }
2809 if ( !pPicReg->pfnSetIrqR3
2810 || !pPicReg->pfnGetInterruptR3)
2811 {
2812 Assert(pPicReg->pfnSetIrqR3);
2813 Assert(pPicReg->pfnGetInterruptR3);
2814 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2815 return VERR_INVALID_PARAMETER;
2816 }
2817 if ( ( pPicReg->pszSetIrqRC
2818 || pPicReg->pszGetInterruptRC)
2819 && ( !VALID_PTR(pPicReg->pszSetIrqRC)
2820 || !VALID_PTR(pPicReg->pszGetInterruptRC))
2821 )
2822 {
2823 Assert(VALID_PTR(pPicReg->pszSetIrqRC));
2824 Assert(VALID_PTR(pPicReg->pszGetInterruptRC));
2825 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2826 return VERR_INVALID_PARAMETER;
2827 }
2828 if ( pPicReg->pszSetIrqRC
2829 && !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC))
2830 {
2831 Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_RC);
2832 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (RC flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2833 return VERR_INVALID_PARAMETER;
2834 }
2835 if ( pPicReg->pszSetIrqR0
2836 && !(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0))
2837 {
2838 Assert(pDevIns->pReg->fFlags & PDM_DEVREG_FLAGS_R0);
2839 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (R0 flag)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2840 return VERR_INVALID_PARAMETER;
2841 }
2842 if (!ppPicHlpR3)
2843 {
2844 Assert(ppPicHlpR3);
2845 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc (ppPicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2846 return VERR_INVALID_PARAMETER;
2847 }
2848
2849 /*
2850 * Only one PIC device.
2851 */
2852 PVM pVM = pDevIns->Internal.s.pVMR3;
2853 if (pVM->pdm.s.Pic.pDevInsR3)
2854 {
2855 AssertMsgFailed(("Only one pic device is supported!\n"));
2856 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2857 return VERR_INVALID_PARAMETER;
2858 }
2859
2860 /*
2861 * RC stuff.
2862 */
2863 if (pPicReg->pszSetIrqRC)
2864 {
2865 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszSetIrqRC, &pVM->pdm.s.Pic.pfnSetIrqRC);
2866 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszSetIrqRC, rc));
2867 if (RT_SUCCESS(rc))
2868 {
2869 rc = pdmR3DevGetSymbolRCLazy(pDevIns, pPicReg->pszGetInterruptRC, &pVM->pdm.s.Pic.pfnGetInterruptRC);
2870 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pPicReg->pszGetInterruptRC, rc));
2871 }
2872 if (RT_FAILURE(rc))
2873 {
2874 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2875 return rc;
2876 }
2877 pVM->pdm.s.Pic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2878 }
2879 else
2880 {
2881 pVM->pdm.s.Pic.pDevInsRC = 0;
2882 pVM->pdm.s.Pic.pfnSetIrqRC = 0;
2883 pVM->pdm.s.Pic.pfnGetInterruptRC = 0;
2884 }
2885
2886 /*
2887 * R0 stuff.
2888 */
2889 if (pPicReg->pszSetIrqR0)
2890 {
2891 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszSetIrqR0, &pVM->pdm.s.Pic.pfnSetIrqR0);
2892 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszSetIrqR0, rc));
2893 if (RT_SUCCESS(rc))
2894 {
2895 rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pPicReg->pszGetInterruptR0, &pVM->pdm.s.Pic.pfnGetInterruptR0);
2896 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pPicReg->pszGetInterruptR0, rc));
2897 }
2898 if (RT_FAILURE(rc))
2899 {
2900 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
2901 return rc;
2902 }
2903 pVM->pdm.s.Pic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2904 Assert(pVM->pdm.s.Pic.pDevInsR0);
2905 }
2906 else
2907 {
2908 pVM->pdm.s.Pic.pfnSetIrqR0 = 0;
2909 pVM->pdm.s.Pic.pfnGetInterruptR0 = 0;
2910 pVM->pdm.s.Pic.pDevInsR0 = 0;
2911 }
2912
2913 /*
2914 * R3 stuff.
2915 */
2916 pVM->pdm.s.Pic.pDevInsR3 = pDevIns;
2917 pVM->pdm.s.Pic.pfnSetIrqR3 = pPicReg->pfnSetIrqR3;
2918 pVM->pdm.s.Pic.pfnGetInterruptR3 = pPicReg->pfnGetInterruptR3;
2919 Log(("PDM: Registered PIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
2920
2921 /* set the helper pointer and return. */
2922 *ppPicHlpR3 = &g_pdmR3DevPicHlp;
2923 LogFlow(("pdmR3DevHlp_PICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2924 return VINF_SUCCESS;
2925}
2926
2927
2928/** @interface_method_impl{PDMDEVHLPR3,pfnAPICRegister} */
2929static DECLCALLBACK(int) pdmR3DevHlp_APICRegister(PPDMDEVINS pDevIns)
2930{
2931 PDMDEV_ASSERT_DEVINS(pDevIns);
2932 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2933
2934 /*
2935 * Only one APIC device. On SMP we have single logical device covering all LAPICs,
2936 * as they need to communicate and share state easily.
2937 */
2938 PVM pVM = pDevIns->Internal.s.pVMR3;
2939 if (pVM->pdm.s.Apic.pDevInsR3)
2940 {
2941 AssertMsgFailed(("Only one APIC device is supported!\n"));
2942 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2943 return VERR_INVALID_PARAMETER;
2944 }
2945
2946 /*
2947 * Initialize the RC, R0 and HC bits.
2948 */
2949 pVM->pdm.s.Apic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
2950 Assert(pVM->pdm.s.Apic.pDevInsRC);
2951
2952 pVM->pdm.s.Apic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
2953 Assert(pVM->pdm.s.Apic.pDevInsR0);
2954
2955 pVM->pdm.s.Apic.pDevInsR3 = pDevIns;
2956 LogFlow(("pdmR3DevHlp_APICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
2957 return VINF_SUCCESS;
2958}
2959
2960
2961/** @interface_method_impl{PDMDEVHLPR3,pfnIOAPICRegister} */
2962static DECLCALLBACK(int) pdmR3DevHlp_IOAPICRegister(PPDMDEVINS pDevIns, PPDMIOAPICREG pIoApicReg, PCPDMIOAPICHLPR3 *ppIoApicHlpR3)
2963{
2964 PDMDEV_ASSERT_DEVINS(pDevIns);
2965 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
2966 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: pIoApicReg=%p:{.u32Version=%#x, .pfnSetIrqR3=%p, .pszSetIrqRC=%p:{%s}, .pszSetIrqR0=%p:{%s}} ppIoApicHlpR3=%p\n",
2967 pDevIns->pReg->szName, pDevIns->iInstance, pIoApicReg, pIoApicReg->u32Version, pIoApicReg->pfnSetIrqR3,
2968 pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqRC, pIoApicReg->pszSetIrqR0, pIoApicReg->pszSetIrqR0, ppIoApicHlpR3));
2969
2970 /*
2971 * Validate input.
2972 */
2973 if (pIoApicReg->u32Version != PDM_IOAPICREG_VERSION)
2974 {
2975 AssertMsgFailed(("u32Version=%#x expected %#x\n", pIoApicReg->u32Version, PDM_IOAPICREG_VERSION));
2976 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2977 return VERR_INVALID_PARAMETER;
2978 }
2979 if (!pIoApicReg->pfnSetIrqR3 || !pIoApicReg->pfnSendMsiR3 || !pIoApicReg->pfnSetEoiR3)
2980 {
2981 Assert(pIoApicReg->pfnSetIrqR3);
2982 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (R3 callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2983 return VERR_INVALID_PARAMETER;
2984 }
2985 if ( pIoApicReg->pszSetIrqRC
2986 && !VALID_PTR(pIoApicReg->pszSetIrqRC))
2987 {
2988 Assert(VALID_PTR(pIoApicReg->pszSetIrqRC));
2989 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2990 return VERR_INVALID_PARAMETER;
2991 }
2992 if ( pIoApicReg->pszSendMsiRC
2993 && !VALID_PTR(pIoApicReg->pszSendMsiRC))
2994 {
2995 Assert(VALID_PTR(pIoApicReg->pszSendMsiRC));
2996 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
2997 return VERR_INVALID_PARAMETER;
2998 }
2999 if ( pIoApicReg->pszSetEoiRC
3000 && !VALID_PTR(pIoApicReg->pszSetEoiRC))
3001 {
3002 Assert(VALID_PTR(pIoApicReg->pszSetEoiRC));
3003 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3004 return VERR_INVALID_PARAMETER;
3005 }
3006 if ( pIoApicReg->pszSetIrqR0
3007 && !VALID_PTR(pIoApicReg->pszSetIrqR0))
3008 {
3009 Assert(VALID_PTR(pIoApicReg->pszSetIrqR0));
3010 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3011 return VERR_INVALID_PARAMETER;
3012 }
3013 if ( pIoApicReg->pszSendMsiR0
3014 && !VALID_PTR(pIoApicReg->pszSendMsiR0))
3015 {
3016 Assert(VALID_PTR(pIoApicReg->pszSendMsiR0));
3017 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3018 return VERR_INVALID_PARAMETER;
3019 }
3020 if ( pIoApicReg->pszSetEoiR0
3021 && !VALID_PTR(pIoApicReg->pszSetEoiR0))
3022 {
3023 Assert(VALID_PTR(pIoApicReg->pszSetEoiR0));
3024 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (GC callbacks)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3025 return VERR_INVALID_PARAMETER;
3026 }
3027 if (!ppIoApicHlpR3)
3028 {
3029 Assert(ppIoApicHlpR3);
3030 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (ppApicHlp)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3031 return VERR_INVALID_PARAMETER;
3032 }
3033
3034 /*
3035 * The I/O APIC requires the APIC to be present (hacks++).
3036 * If the I/O APIC does GC stuff so must the APIC.
3037 */
3038 PVM pVM = pDevIns->Internal.s.pVMR3;
3039 if (!pVM->pdm.s.Apic.pDevInsR3)
3040 {
3041 AssertMsgFailed(("Configuration error / Init order error! No APIC!\n"));
3042 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3043 return VERR_INVALID_PARAMETER;
3044 }
3045 if ( pIoApicReg->pszSetIrqRC
3046 && !pVM->pdm.s.Apic.pDevInsRC)
3047 {
3048 AssertMsgFailed(("Configuration error! APIC doesn't do GC, I/O APIC does!\n"));
3049 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (no GC APIC)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3050 return VERR_INVALID_PARAMETER;
3051 }
3052
3053 /*
3054 * Only one I/O APIC device.
3055 */
3056 if (pVM->pdm.s.IoApic.pDevInsR3)
3057 {
3058 AssertMsgFailed(("Only one ioapic device is supported!\n"));
3059 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc (only one)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3060 return VERR_INVALID_PARAMETER;
3061 }
3062
3063 /*
3064 * Resolve & initialize the GC bits.
3065 */
3066 if (pIoApicReg->pszSetIrqRC)
3067 {
3068 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetIrqRC, &pVM->pdm.s.IoApic.pfnSetIrqRC);
3069 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetIrqRC, rc));
3070 if (RT_FAILURE(rc))
3071 {
3072 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3073 return rc;
3074 }
3075 pVM->pdm.s.IoApic.pDevInsRC = PDMDEVINS_2_RCPTR(pDevIns);
3076 }
3077 else
3078 {
3079 pVM->pdm.s.IoApic.pDevInsRC = 0;
3080 pVM->pdm.s.IoApic.pfnSetIrqRC = 0;
3081 }
3082
3083 if (pIoApicReg->pszSendMsiRC)
3084 {
3085 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSendMsiRC, &pVM->pdm.s.IoApic.pfnSendMsiRC);
3086 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSendMsiRC, rc));
3087 if (RT_FAILURE(rc))
3088 {
3089 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3090 return rc;
3091 }
3092 }
3093 else
3094 {
3095 pVM->pdm.s.IoApic.pfnSendMsiRC = 0;
3096 }
3097
3098 if (pIoApicReg->pszSetEoiRC)
3099 {
3100 int rc = pdmR3DevGetSymbolRCLazy(pDevIns, pIoApicReg->pszSetEoiRC, &pVM->pdm.s.IoApic.pfnSetEoiRC);
3101 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szRCMod, pIoApicReg->pszSetEoiRC, rc));
3102 if (RT_FAILURE(rc))
3103 {
3104 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3105 return rc;
3106 }
3107 }
3108 else
3109 {
3110 pVM->pdm.s.IoApic.pfnSetEoiRC = 0;
3111 }
3112
3113 /*
3114 * Resolve & initialize the R0 bits.
3115 */
3116 if (pIoApicReg->pszSetIrqR0)
3117 {
3118 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetIrqR0, &pVM->pdm.s.IoApic.pfnSetIrqR0);
3119 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetIrqR0, rc));
3120 if (RT_FAILURE(rc))
3121 {
3122 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3123 return rc;
3124 }
3125 pVM->pdm.s.IoApic.pDevInsR0 = PDMDEVINS_2_R0PTR(pDevIns);
3126 Assert(pVM->pdm.s.IoApic.pDevInsR0);
3127 }
3128 else
3129 {
3130 pVM->pdm.s.IoApic.pfnSetIrqR0 = 0;
3131 pVM->pdm.s.IoApic.pDevInsR0 = 0;
3132 }
3133
3134 if (pIoApicReg->pszSendMsiR0)
3135 {
3136 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSendMsiR0, &pVM->pdm.s.IoApic.pfnSendMsiR0);
3137 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSendMsiR0, rc));
3138 if (RT_FAILURE(rc))
3139 {
3140 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3141 return rc;
3142 }
3143 }
3144 else
3145 {
3146 pVM->pdm.s.IoApic.pfnSendMsiR0 = 0;
3147 }
3148
3149 if (pIoApicReg->pszSetEoiR0)
3150 {
3151 int rc = pdmR3DevGetSymbolR0Lazy(pDevIns, pIoApicReg->pszSetEoiR0, &pVM->pdm.s.IoApic.pfnSetEoiR0);
3152 AssertMsgRC(rc, ("%s::%s rc=%Rrc\n", pDevIns->pReg->szR0Mod, pIoApicReg->pszSetEoiR0, rc));
3153 if (RT_FAILURE(rc))
3154 {
3155 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3156 return rc;
3157 }
3158 }
3159 else
3160 {
3161 pVM->pdm.s.IoApic.pfnSetEoiR0 = 0;
3162 }
3163
3164
3165 /*
3166 * Initialize the R3 bits.
3167 */
3168 pVM->pdm.s.IoApic.pDevInsR3 = pDevIns;
3169 pVM->pdm.s.IoApic.pfnSetIrqR3 = pIoApicReg->pfnSetIrqR3;
3170 pVM->pdm.s.IoApic.pfnSendMsiR3 = pIoApicReg->pfnSendMsiR3;
3171 pVM->pdm.s.IoApic.pfnSetEoiR3 = pIoApicReg->pfnSetEoiR3;
3172 Log(("PDM: Registered I/O APIC device '%s'/%d pDevIns=%p\n", pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3173
3174 /* set the helper pointer and return. */
3175 *ppIoApicHlpR3 = &g_pdmR3DevIoApicHlp;
3176 LogFlow(("pdmR3DevHlp_IOAPICRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3177 return VINF_SUCCESS;
3178}
3179
3180
3181/** @interface_method_impl{PDMDEVHLPR3,pfnHPETRegister} */
3182static DECLCALLBACK(int) pdmR3DevHlp_HPETRegister(PPDMDEVINS pDevIns, PPDMHPETREG pHpetReg, PCPDMHPETHLPR3 *ppHpetHlpR3)
3183{
3184 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
3185 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3186 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3187
3188 /*
3189 * Validate input.
3190 */
3191 if (pHpetReg->u32Version != PDM_HPETREG_VERSION)
3192 {
3193 AssertMsgFailed(("u32Version=%#x expected %#x\n", pHpetReg->u32Version, PDM_HPETREG_VERSION));
3194 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3195 return VERR_INVALID_PARAMETER;
3196 }
3197
3198 if (!ppHpetHlpR3)
3199 {
3200 Assert(ppHpetHlpR3);
3201 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc (ppApicHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3202 return VERR_INVALID_PARAMETER;
3203 }
3204
3205 /* set the helper pointer and return. */
3206 *ppHpetHlpR3 = &g_pdmR3DevHpetHlp;
3207 LogFlow(("pdmR3DevHlp_HPETRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3208 return VINF_SUCCESS;
3209}
3210
3211
3212/** @interface_method_impl{PDMDEVHLPR3,pfnPciRawRegister} */
3213static DECLCALLBACK(int) pdmR3DevHlp_PciRawRegister(PPDMDEVINS pDevIns, PPDMPCIRAWREG pPciRawReg, PCPDMPCIRAWHLPR3 *ppPciRawHlpR3)
3214{
3215 PDMDEV_ASSERT_DEVINS(pDevIns); RT_NOREF_PV(pDevIns);
3216 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3217 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
3218
3219 /*
3220 * Validate input.
3221 */
3222 if (pPciRawReg->u32Version != PDM_PCIRAWREG_VERSION)
3223 {
3224 AssertMsgFailed(("u32Version=%#x expected %#x\n", pPciRawReg->u32Version, PDM_PCIRAWREG_VERSION));
3225 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (version)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3226 return VERR_INVALID_PARAMETER;
3227 }
3228
3229 if (!ppPciRawHlpR3)
3230 {
3231 Assert(ppPciRawHlpR3);
3232 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc (ppPciRawHlpR3)\n", pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3233 return VERR_INVALID_PARAMETER;
3234 }
3235
3236 /* set the helper pointer and return. */
3237 *ppPciRawHlpR3 = &g_pdmR3DevPciRawHlp;
3238 LogFlow(("pdmR3DevHlp_PciRawRegister: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3239 return VINF_SUCCESS;
3240}
3241
3242
3243/** @interface_method_impl{PDMDEVHLPR3,pfnDMACRegister} */
3244static DECLCALLBACK(int) pdmR3DevHlp_DMACRegister(PPDMDEVINS pDevIns, PPDMDMACREG pDmacReg, PCPDMDMACHLP *ppDmacHlp)
3245{
3246 PDMDEV_ASSERT_DEVINS(pDevIns);
3247 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3248 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: pDmacReg=%p:{.u32Version=%#x, .pfnRun=%p, .pfnRegister=%p, .pfnReadMemory=%p, .pfnWriteMemory=%p, .pfnSetDREQ=%p, .pfnGetChannelMode=%p} ppDmacHlp=%p\n",
3249 pDevIns->pReg->szName, pDevIns->iInstance, pDmacReg, pDmacReg->u32Version, pDmacReg->pfnRun, pDmacReg->pfnRegister,
3250 pDmacReg->pfnReadMemory, pDmacReg->pfnWriteMemory, pDmacReg->pfnSetDREQ, pDmacReg->pfnGetChannelMode, ppDmacHlp));
3251
3252 /*
3253 * Validate input.
3254 */
3255 if (pDmacReg->u32Version != PDM_DMACREG_VERSION)
3256 {
3257 AssertMsgFailed(("u32Version=%#x expected %#x\n", pDmacReg->u32Version,
3258 PDM_DMACREG_VERSION));
3259 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (version)\n",
3260 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3261 return VERR_INVALID_PARAMETER;
3262 }
3263 if ( !pDmacReg->pfnRun
3264 || !pDmacReg->pfnRegister
3265 || !pDmacReg->pfnReadMemory
3266 || !pDmacReg->pfnWriteMemory
3267 || !pDmacReg->pfnSetDREQ
3268 || !pDmacReg->pfnGetChannelMode)
3269 {
3270 Assert(pDmacReg->pfnRun);
3271 Assert(pDmacReg->pfnRegister);
3272 Assert(pDmacReg->pfnReadMemory);
3273 Assert(pDmacReg->pfnWriteMemory);
3274 Assert(pDmacReg->pfnSetDREQ);
3275 Assert(pDmacReg->pfnGetChannelMode);
3276 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3277 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3278 return VERR_INVALID_PARAMETER;
3279 }
3280
3281 if (!ppDmacHlp)
3282 {
3283 Assert(ppDmacHlp);
3284 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc (ppDmacHlp)\n",
3285 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3286 return VERR_INVALID_PARAMETER;
3287 }
3288
3289 /*
3290 * Only one DMA device.
3291 */
3292 PVM pVM = pDevIns->Internal.s.pVMR3;
3293 if (pVM->pdm.s.pDmac)
3294 {
3295 AssertMsgFailed(("Only one DMA device is supported!\n"));
3296 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3297 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3298 return VERR_INVALID_PARAMETER;
3299 }
3300
3301 /*
3302 * Allocate and initialize pci bus structure.
3303 */
3304 int rc = VINF_SUCCESS;
3305 PPDMDMAC pDmac = (PPDMDMAC)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pDmac));
3306 if (pDmac)
3307 {
3308 pDmac->pDevIns = pDevIns;
3309 pDmac->Reg = *pDmacReg;
3310 pVM->pdm.s.pDmac = pDmac;
3311
3312 /* set the helper pointer. */
3313 *ppDmacHlp = &g_pdmR3DevDmacHlp;
3314 Log(("PDM: Registered DMAC device '%s'/%d pDevIns=%p\n",
3315 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3316 }
3317 else
3318 rc = VERR_NO_MEMORY;
3319
3320 LogFlow(("pdmR3DevHlp_DMACRegister: caller='%s'/%d: returns %Rrc\n",
3321 pDevIns->pReg->szName, pDevIns->iInstance, rc));
3322 return rc;
3323}
3324
3325
3326/**
3327 * @copydoc PDMDEVHLPR3::pfnRegisterVMMDevHeap
3328 */
3329static DECLCALLBACK(int) pdmR3DevHlp_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, RTR3PTR pvHeap, unsigned cbHeap)
3330{
3331 PDMDEV_ASSERT_DEVINS(pDevIns);
3332 PVM pVM = pDevIns->Internal.s.pVMR3;
3333 VM_ASSERT_EMT(pVM);
3334 LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: GCPhys=%RGp pvHeap=%p cbHeap=%#x\n",
3335 pDevIns->pReg->szName, pDevIns->iInstance, GCPhys, pvHeap, cbHeap));
3336
3337 if (pVM->pdm.s.pvVMMDevHeap == NULL)
3338 {
3339 pVM->pdm.s.pvVMMDevHeap = pvHeap;
3340 pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
3341 pVM->pdm.s.cbVMMDevHeap = cbHeap;
3342 pVM->pdm.s.cbVMMDevHeapLeft = cbHeap;
3343 }
3344 else
3345 {
3346 Assert(pVM->pdm.s.pvVMMDevHeap == pvHeap);
3347 Assert(pVM->pdm.s.cbVMMDevHeap == cbHeap);
3348 Assert(pVM->pdm.s.GCPhysVMMDevHeap != GCPhys || GCPhys == NIL_RTGCPHYS);
3349 if (pVM->pdm.s.GCPhysVMMDevHeap != GCPhys)
3350 {
3351 pVM->pdm.s.GCPhysVMMDevHeap = GCPhys;
3352 if (pVM->pdm.s.pfnVMMDevHeapNotify)
3353 pVM->pdm.s.pfnVMMDevHeapNotify(pVM, pvHeap, GCPhys);
3354 }
3355 }
3356
3357 LogFlow(("pdmR3DevHlp_RegisterVMMDevHeap: caller='%s'/%d: returns %Rrc\n",
3358 pDevIns->pReg->szName, pDevIns->iInstance, VINF_SUCCESS));
3359 return VINF_SUCCESS;
3360}
3361
3362
3363/**
3364 * @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister}
3365 */
3366static DECLCALLBACK(int) pdmR3DevHlp_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
3367{
3368 PDMDEV_ASSERT_DEVINS(pDevIns);
3369 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3370 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: pFWReg=%p:{.u32Version=%#x, .pfnIsHardReset=%p, .u32TheEnd=%#x} ppFwHlp=%p\n",
3371 pDevIns->pReg->szName, pDevIns->iInstance, pFwReg, pFwReg->u32Version, pFwReg->pfnIsHardReset, pFwReg->u32TheEnd, ppFwHlp));
3372
3373 /*
3374 * Validate input.
3375 */
3376 if (pFwReg->u32Version != PDM_FWREG_VERSION)
3377 {
3378 AssertMsgFailed(("u32Version=%#x expected %#x\n", pFwReg->u32Version, PDM_FWREG_VERSION));
3379 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (version)\n",
3380 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3381 return VERR_INVALID_PARAMETER;
3382 }
3383 if (!pFwReg->pfnIsHardReset)
3384 {
3385 Assert(pFwReg->pfnIsHardReset);
3386 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (callbacks)\n",
3387 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3388 return VERR_INVALID_PARAMETER;
3389 }
3390
3391 if (!ppFwHlp)
3392 {
3393 Assert(ppFwHlp);
3394 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc (ppFwHlp)\n",
3395 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3396 return VERR_INVALID_PARAMETER;
3397 }
3398
3399 /*
3400 * Only one DMA device.
3401 */
3402 PVM pVM = pDevIns->Internal.s.pVMR3;
3403 if (pVM->pdm.s.pFirmware)
3404 {
3405 AssertMsgFailed(("Only one firmware device is supported!\n"));
3406 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
3407 pDevIns->pReg->szName, pDevIns->iInstance, VERR_INVALID_PARAMETER));
3408 return VERR_INVALID_PARAMETER;
3409 }
3410
3411 /*
3412 * Allocate and initialize pci bus structure.
3413 */
3414 int rc = VINF_SUCCESS;
3415 PPDMFW pFirmware = (PPDMFW)MMR3HeapAlloc(pDevIns->Internal.s.pVMR3, MM_TAG_PDM_DEVICE, sizeof(*pFirmware));
3416 if (pFirmware)
3417 {
3418 pFirmware->pDevIns = pDevIns;
3419 pFirmware->Reg = *pFwReg;
3420 pVM->pdm.s.pFirmware = pFirmware;
3421
3422 /* set the helper pointer. */
3423 *ppFwHlp = &g_pdmR3DevFirmwareHlp;
3424 Log(("PDM: Registered firmware device '%s'/%d pDevIns=%p\n",
3425 pDevIns->pReg->szName, pDevIns->iInstance, pDevIns));
3426 }
3427 else
3428 rc = VERR_NO_MEMORY;
3429
3430 LogFlow(("pdmR3DevHlp_FirmwareRegister: caller='%s'/%d: returns %Rrc\n",
3431 pDevIns->pReg->szName, pDevIns->iInstance, rc));
3432 return rc;
3433}
3434
3435
3436/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3437static DECLCALLBACK(int) pdmR3DevHlp_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
3438{
3439 PDMDEV_ASSERT_DEVINS(pDevIns);
3440 PVM pVM = pDevIns->Internal.s.pVMR3;
3441 VM_ASSERT_EMT(pVM);
3442 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: fFlags=%#x VM_FF_RESET %d -> 1\n",
3443 pDevIns->pReg->szName, pDevIns->iInstance, fFlags, VM_FF_IS_SET(pVM, VM_FF_RESET)));
3444
3445 /*
3446 * We postpone this operation because we're likely to be inside a I/O instruction
3447 * and the EIP will be updated when we return.
3448 * We still return VINF_EM_RESET to break out of any execution loops and force FF evaluation.
3449 */
3450 bool fHaltOnReset;
3451 int rc = CFGMR3QueryBool(CFGMR3GetChild(CFGMR3GetRoot(pVM), "PDM"), "HaltOnReset", &fHaltOnReset);
3452 if (RT_SUCCESS(rc) && fHaltOnReset)
3453 {
3454 Log(("pdmR3DevHlp_VMReset: Halt On Reset!\n"));
3455 rc = VINF_EM_HALT;
3456 }
3457 else
3458 {
3459 pVM->pdm.s.fResetFlags = fFlags;
3460 VM_FF_SET(pVM, VM_FF_RESET);
3461 rc = VINF_EM_RESET;
3462 }
3463
3464 LogFlow(("pdmR3DevHlp_VMReset: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3465 return rc;
3466}
3467
3468
3469/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3470static DECLCALLBACK(int) pdmR3DevHlp_VMSuspend(PPDMDEVINS pDevIns)
3471{
3472 int rc;
3473 PDMDEV_ASSERT_DEVINS(pDevIns);
3474 PVM pVM = pDevIns->Internal.s.pVMR3;
3475 VM_ASSERT_EMT(pVM);
3476 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d:\n",
3477 pDevIns->pReg->szName, pDevIns->iInstance));
3478
3479 /** @todo Always take the SMP path - fewer code paths. */
3480 if (pVM->cCpus > 1)
3481 {
3482 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
3483 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3Suspend, 2, pVM->pUVM, VMSUSPENDREASON_VM);
3484 AssertRC(rc);
3485 rc = VINF_EM_SUSPEND;
3486 }
3487 else
3488 rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
3489
3490 LogFlow(("pdmR3DevHlp_VMSuspend: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3491 return rc;
3492}
3493
3494
3495/**
3496 * Worker for pdmR3DevHlp_VMSuspendSaveAndPowerOff that is invoked via a queued
3497 * EMT request to avoid deadlocks.
3498 *
3499 * @returns VBox status code fit for scheduling.
3500 * @param pVM The cross context VM structure.
3501 * @param pDevIns The device that triggered this action.
3502 */
3503static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker(PVM pVM, PPDMDEVINS pDevIns)
3504{
3505 /*
3506 * Suspend the VM first then do the saving.
3507 */
3508 int rc = VMR3Suspend(pVM->pUVM, VMSUSPENDREASON_VM);
3509 if (RT_SUCCESS(rc))
3510 {
3511 PUVM pUVM = pVM->pUVM;
3512 rc = pUVM->pVmm2UserMethods->pfnSaveState(pVM->pUVM->pVmm2UserMethods, pUVM);
3513
3514 /*
3515 * On success, power off the VM, on failure we'll leave it suspended.
3516 */
3517 if (RT_SUCCESS(rc))
3518 {
3519 rc = VMR3PowerOff(pVM->pUVM);
3520 if (RT_FAILURE(rc))
3521 LogRel(("%s/SSP: VMR3PowerOff failed: %Rrc\n", pDevIns->pReg->szName, rc));
3522 }
3523 else
3524 LogRel(("%s/SSP: pfnSaveState failed: %Rrc\n", pDevIns->pReg->szName, rc));
3525 }
3526 else
3527 LogRel(("%s/SSP: Suspend failed: %Rrc\n", pDevIns->pReg->szName, rc));
3528 return rc;
3529}
3530
3531
3532/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3533static DECLCALLBACK(int) pdmR3DevHlp_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3534{
3535 PDMDEV_ASSERT_DEVINS(pDevIns);
3536 PVM pVM = pDevIns->Internal.s.pVMR3;
3537 VM_ASSERT_EMT(pVM);
3538 LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d:\n",
3539 pDevIns->pReg->szName, pDevIns->iInstance));
3540
3541 int rc;
3542 if ( pVM->pUVM->pVmm2UserMethods
3543 && pVM->pUVM->pVmm2UserMethods->pfnSaveState)
3544 {
3545 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)pdmR3DevHlp_VMSuspendSaveAndPowerOffWorker, 2, pVM, pDevIns);
3546 if (RT_SUCCESS(rc))
3547 {
3548 LogRel(("%s: Suspending, Saving and Powering Off the VM\n", pDevIns->pReg->szName));
3549 rc = VINF_EM_SUSPEND;
3550 }
3551 }
3552 else
3553 rc = VERR_NOT_SUPPORTED;
3554
3555 LogFlow(("pdmR3DevHlp_VMSuspendSaveAndPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3556 return rc;
3557}
3558
3559
3560/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3561static DECLCALLBACK(int) pdmR3DevHlp_VMPowerOff(PPDMDEVINS pDevIns)
3562{
3563 int rc;
3564 PDMDEV_ASSERT_DEVINS(pDevIns);
3565 PVM pVM = pDevIns->Internal.s.pVMR3;
3566 VM_ASSERT_EMT(pVM);
3567 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d:\n",
3568 pDevIns->pReg->szName, pDevIns->iInstance));
3569
3570 /** @todo Always take the SMP path - fewer code paths. */
3571 if (pVM->cCpus > 1)
3572 {
3573 /* We might be holding locks here and could cause a deadlock since
3574 VMR3PowerOff rendezvous with the other CPUs. */
3575 rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE, (PFNRT)VMR3PowerOff, 1, pVM->pUVM);
3576 AssertRC(rc);
3577 /* Set the VCPU state to stopped here as well to make sure no
3578 inconsistency with the EM state occurs. */
3579 VMCPU_SET_STATE(VMMGetCpu(pVM), VMCPUSTATE_STOPPED);
3580 rc = VINF_EM_OFF;
3581 }
3582 else
3583 rc = VMR3PowerOff(pVM->pUVM);
3584
3585 LogFlow(("pdmR3DevHlp_VMPowerOff: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
3586 return rc;
3587}
3588
3589
3590/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3591static DECLCALLBACK(bool) pdmR3DevHlp_A20IsEnabled(PPDMDEVINS pDevIns)
3592{
3593 PDMDEV_ASSERT_DEVINS(pDevIns);
3594 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3595
3596 bool fRc = PGMPhysIsA20Enabled(VMMGetCpu(pDevIns->Internal.s.pVMR3));
3597
3598 LogFlow(("pdmR3DevHlp_A20IsEnabled: caller='%s'/%d: returns %d\n", pDevIns->pReg->szName, pDevIns->iInstance, fRc));
3599 return fRc;
3600}
3601
3602
3603/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3604static DECLCALLBACK(void) pdmR3DevHlp_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3605{
3606 PDMDEV_ASSERT_DEVINS(pDevIns);
3607 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3608 LogFlow(("pdmR3DevHlp_A20Set: caller='%s'/%d: fEnable=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, fEnable));
3609 PGMR3PhysSetA20(VMMGetCpu(pDevIns->Internal.s.pVMR3), fEnable);
3610}
3611
3612
3613/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3614static DECLCALLBACK(void) pdmR3DevHlp_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3615 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
3616{
3617 PDMDEV_ASSERT_DEVINS(pDevIns);
3618 VM_ASSERT_EMT(pDevIns->Internal.s.pVMR3);
3619
3620 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: iLeaf=%d pEax=%p pEbx=%p pEcx=%p pEdx=%p\n",
3621 pDevIns->pReg->szName, pDevIns->iInstance, iLeaf, pEax, pEbx, pEcx, pEdx));
3622 AssertPtr(pEax); AssertPtr(pEbx); AssertPtr(pEcx); AssertPtr(pEdx);
3623
3624 CPUMGetGuestCpuId(VMMGetCpu(pDevIns->Internal.s.pVMR3), iLeaf, 0 /*iSubLeaf*/, pEax, pEbx, pEcx, pEdx);
3625
3626 LogFlow(("pdmR3DevHlp_GetCpuId: caller='%s'/%d: returns void - *pEax=%#x *pEbx=%#x *pEcx=%#x *pEdx=%#x\n",
3627 pDevIns->pReg->szName, pDevIns->iInstance, *pEax, *pEbx, *pEcx, *pEdx));
3628}
3629
3630
3631/**
3632 * The device helper structure for trusted devices.
3633 */
3634const PDMDEVHLPR3 g_pdmR3DevHlpTrusted =
3635{
3636 PDM_DEVHLPR3_VERSION,
3637 pdmR3DevHlp_IOPortRegister,
3638 pdmR3DevHlp_IOPortRegisterRC,
3639 pdmR3DevHlp_IOPortRegisterR0,
3640 pdmR3DevHlp_IOPortDeregister,
3641 pdmR3DevHlp_MMIORegister,
3642 pdmR3DevHlp_MMIORegisterRC,
3643 pdmR3DevHlp_MMIORegisterR0,
3644 pdmR3DevHlp_MMIODeregister,
3645 pdmR3DevHlp_MMIO2Register,
3646 pdmR3DevHlp_MMIOExPreRegister,
3647 pdmR3DevHlp_MMIOExDeregister,
3648 pdmR3DevHlp_MMIOExMap,
3649 pdmR3DevHlp_MMIOExUnmap,
3650 pdmR3DevHlp_MMIOExReduce,
3651 pdmR3DevHlp_MMHyperMapMMIO2,
3652 pdmR3DevHlp_MMIO2MapKernel,
3653 pdmR3DevHlp_ROMRegister,
3654 pdmR3DevHlp_ROMProtectShadow,
3655 pdmR3DevHlp_SSMRegister,
3656 pdmR3DevHlp_TMTimerCreate,
3657 pdmR3DevHlp_TMUtcNow,
3658 pdmR3DevHlp_PhysRead,
3659 pdmR3DevHlp_PhysWrite,
3660 pdmR3DevHlp_PhysGCPhys2CCPtr,
3661 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
3662 pdmR3DevHlp_PhysReleasePageMappingLock,
3663 pdmR3DevHlp_PhysReadGCVirt,
3664 pdmR3DevHlp_PhysWriteGCVirt,
3665 pdmR3DevHlp_PhysGCPtr2GCPhys,
3666 pdmR3DevHlp_MMHeapAlloc,
3667 pdmR3DevHlp_MMHeapAllocZ,
3668 pdmR3DevHlp_MMHeapFree,
3669 pdmR3DevHlp_VMState,
3670 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
3671 pdmR3DevHlp_VMSetError,
3672 pdmR3DevHlp_VMSetErrorV,
3673 pdmR3DevHlp_VMSetRuntimeError,
3674 pdmR3DevHlp_VMSetRuntimeErrorV,
3675 pdmR3DevHlp_DBGFStopV,
3676 pdmR3DevHlp_DBGFInfoRegister,
3677 pdmR3DevHlp_DBGFRegRegister,
3678 pdmR3DevHlp_DBGFTraceBuf,
3679 pdmR3DevHlp_STAMRegister,
3680 pdmR3DevHlp_STAMRegisterF,
3681 pdmR3DevHlp_STAMRegisterV,
3682 pdmR3DevHlp_PCIRegister,
3683 pdmR3DevHlp_PCIRegisterMsi,
3684 pdmR3DevHlp_PCIIORegionRegister,
3685 pdmR3DevHlp_PCISetConfigCallbacks,
3686 pdmR3DevHlp_PCIPhysRead,
3687 pdmR3DevHlp_PCIPhysWrite,
3688 pdmR3DevHlp_PCISetIrq,
3689 pdmR3DevHlp_PCISetIrqNoWait,
3690 pdmR3DevHlp_ISASetIrq,
3691 pdmR3DevHlp_ISASetIrqNoWait,
3692 pdmR3DevHlp_IoApicSendMsi,
3693 pdmR3DevHlp_DriverAttach,
3694 pdmR3DevHlp_DriverDetach,
3695 pdmR3DevHlp_QueueCreate,
3696 pdmR3DevHlp_CritSectInit,
3697 pdmR3DevHlp_CritSectGetNop,
3698 pdmR3DevHlp_CritSectGetNopR0,
3699 pdmR3DevHlp_CritSectGetNopRC,
3700 pdmR3DevHlp_SetDeviceCritSect,
3701 pdmR3DevHlp_ThreadCreate,
3702 pdmR3DevHlp_SetAsyncNotification,
3703 pdmR3DevHlp_AsyncNotificationCompleted,
3704 pdmR3DevHlp_RTCRegister,
3705 pdmR3DevHlp_PCIBusRegister,
3706 pdmR3DevHlp_PICRegister,
3707 pdmR3DevHlp_APICRegister,
3708 pdmR3DevHlp_IOAPICRegister,
3709 pdmR3DevHlp_HPETRegister,
3710 pdmR3DevHlp_PciRawRegister,
3711 pdmR3DevHlp_DMACRegister,
3712 pdmR3DevHlp_DMARegister,
3713 pdmR3DevHlp_DMAReadMemory,
3714 pdmR3DevHlp_DMAWriteMemory,
3715 pdmR3DevHlp_DMASetDREQ,
3716 pdmR3DevHlp_DMAGetChannelMode,
3717 pdmR3DevHlp_DMASchedule,
3718 pdmR3DevHlp_CMOSWrite,
3719 pdmR3DevHlp_CMOSRead,
3720 pdmR3DevHlp_AssertEMT,
3721 pdmR3DevHlp_AssertOther,
3722 pdmR3DevHlp_LdrGetRCInterfaceSymbols,
3723 pdmR3DevHlp_LdrGetR0InterfaceSymbols,
3724 pdmR3DevHlp_CallR0,
3725 pdmR3DevHlp_VMGetSuspendReason,
3726 pdmR3DevHlp_VMGetResumeReason,
3727 0,
3728 0,
3729 0,
3730 0,
3731 0,
3732 0,
3733 0,
3734 0,
3735 0,
3736 0,
3737 pdmR3DevHlp_GetUVM,
3738 pdmR3DevHlp_GetVM,
3739 pdmR3DevHlp_GetVMCPU,
3740 pdmR3DevHlp_GetCurrentCpuId,
3741 pdmR3DevHlp_RegisterVMMDevHeap,
3742 pdmR3DevHlp_FirmwareRegister,
3743 pdmR3DevHlp_VMReset,
3744 pdmR3DevHlp_VMSuspend,
3745 pdmR3DevHlp_VMSuspendSaveAndPowerOff,
3746 pdmR3DevHlp_VMPowerOff,
3747 pdmR3DevHlp_A20IsEnabled,
3748 pdmR3DevHlp_A20Set,
3749 pdmR3DevHlp_GetCpuId,
3750 pdmR3DevHlp_TMTimeVirtGet,
3751 pdmR3DevHlp_TMTimeVirtGetFreq,
3752 pdmR3DevHlp_TMTimeVirtGetNano,
3753 pdmR3DevHlp_GetSupDrvSession,
3754 pdmR3DevHlp_QueryGenericUserObject,
3755 PDM_DEVHLPR3_VERSION /* the end */
3756};
3757
3758
3759
3760
3761/** @interface_method_impl{PDMDEVHLPR3,pfnGetUVM} */
3762static DECLCALLBACK(PUVM) pdmR3DevHlp_Untrusted_GetUVM(PPDMDEVINS pDevIns)
3763{
3764 PDMDEV_ASSERT_DEVINS(pDevIns);
3765 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3766 return NULL;
3767}
3768
3769
3770/** @interface_method_impl{PDMDEVHLPR3,pfnGetVM} */
3771static DECLCALLBACK(PVM) pdmR3DevHlp_Untrusted_GetVM(PPDMDEVINS pDevIns)
3772{
3773 PDMDEV_ASSERT_DEVINS(pDevIns);
3774 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3775 return NULL;
3776}
3777
3778
3779/** @interface_method_impl{PDMDEVHLPR3,pfnGetVMCPU} */
3780static DECLCALLBACK(PVMCPU) pdmR3DevHlp_Untrusted_GetVMCPU(PPDMDEVINS pDevIns)
3781{
3782 PDMDEV_ASSERT_DEVINS(pDevIns);
3783 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3784 return NULL;
3785}
3786
3787
3788/** @interface_method_impl{PDMDEVHLPR3,pfnGetCurrentCpuId} */
3789static DECLCALLBACK(VMCPUID) pdmR3DevHlp_Untrusted_GetCurrentCpuId(PPDMDEVINS pDevIns)
3790{
3791 PDMDEV_ASSERT_DEVINS(pDevIns);
3792 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3793 return NIL_VMCPUID;
3794}
3795
3796
3797/** @interface_method_impl{PDMDEVHLPR3,pfnRegisterVMMDevHeap} */
3798static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_RegisterVMMDevHeap(PPDMDEVINS pDevIns, RTGCPHYS GCPhys,
3799 RTR3PTR pvHeap, unsigned cbHeap)
3800{
3801 PDMDEV_ASSERT_DEVINS(pDevIns);
3802 NOREF(GCPhys); NOREF(pvHeap); NOREF(cbHeap);
3803 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3804 return VERR_ACCESS_DENIED;
3805}
3806
3807
3808/** @interface_method_impl{PDMDEVHLPR3,pfnFirmwareRegister} */
3809static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_FirmwareRegister(PPDMDEVINS pDevIns, PCPDMFWREG pFwReg, PCPDMFWHLPR3 *ppFwHlp)
3810{
3811 PDMDEV_ASSERT_DEVINS(pDevIns);
3812 NOREF(pFwReg); NOREF(ppFwHlp);
3813 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3814 return VERR_ACCESS_DENIED;
3815}
3816
3817
3818/** @interface_method_impl{PDMDEVHLPR3,pfnVMReset} */
3819static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMReset(PPDMDEVINS pDevIns, uint32_t fFlags)
3820{
3821 PDMDEV_ASSERT_DEVINS(pDevIns); NOREF(fFlags);
3822 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3823 return VERR_ACCESS_DENIED;
3824}
3825
3826
3827/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspend} */
3828static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspend(PPDMDEVINS pDevIns)
3829{
3830 PDMDEV_ASSERT_DEVINS(pDevIns);
3831 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3832 return VERR_ACCESS_DENIED;
3833}
3834
3835
3836/** @interface_method_impl{PDMDEVHLPR3,pfnVMSuspendSaveAndPowerOff} */
3837static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff(PPDMDEVINS pDevIns)
3838{
3839 PDMDEV_ASSERT_DEVINS(pDevIns);
3840 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3841 return VERR_ACCESS_DENIED;
3842}
3843
3844
3845/** @interface_method_impl{PDMDEVHLPR3,pfnVMPowerOff} */
3846static DECLCALLBACK(int) pdmR3DevHlp_Untrusted_VMPowerOff(PPDMDEVINS pDevIns)
3847{
3848 PDMDEV_ASSERT_DEVINS(pDevIns);
3849 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3850 return VERR_ACCESS_DENIED;
3851}
3852
3853
3854/** @interface_method_impl{PDMDEVHLPR3,pfnA20IsEnabled} */
3855static DECLCALLBACK(bool) pdmR3DevHlp_Untrusted_A20IsEnabled(PPDMDEVINS pDevIns)
3856{
3857 PDMDEV_ASSERT_DEVINS(pDevIns);
3858 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3859 return false;
3860}
3861
3862
3863/** @interface_method_impl{PDMDEVHLPR3,pfnA20Set} */
3864static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_A20Set(PPDMDEVINS pDevIns, bool fEnable)
3865{
3866 PDMDEV_ASSERT_DEVINS(pDevIns);
3867 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3868 NOREF(fEnable);
3869}
3870
3871
3872/** @interface_method_impl{PDMDEVHLPR3,pfnGetCpuId} */
3873static DECLCALLBACK(void) pdmR3DevHlp_Untrusted_GetCpuId(PPDMDEVINS pDevIns, uint32_t iLeaf,
3874 uint32_t *pEax, uint32_t *pEbx, uint32_t *pEcx, uint32_t *pEdx)
3875{
3876 PDMDEV_ASSERT_DEVINS(pDevIns);
3877 NOREF(iLeaf); NOREF(pEax); NOREF(pEbx); NOREF(pEcx); NOREF(pEdx);
3878 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3879}
3880
3881
3882/** @interface_method_impl{PDMDEVHLPR3,pfnGetSupDrvSession} */
3883static DECLCALLBACK(PSUPDRVSESSION) pdmR3DevHlp_Untrusted_GetSupDrvSession(PPDMDEVINS pDevIns)
3884{
3885 PDMDEV_ASSERT_DEVINS(pDevIns);
3886 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
3887 return (PSUPDRVSESSION)0;
3888}
3889
3890
3891/** @interface_method_impl{PDMDEVHLPR3,pfnQueryGenericUserObject} */
3892static DECLCALLBACK(void *) pdmR3DevHlp_Untrusted_QueryGenericUserObject(PPDMDEVINS pDevIns, PCRTUUID pUuid)
3893{
3894 PDMDEV_ASSERT_DEVINS(pDevIns);
3895 AssertReleaseMsgFailed(("Untrusted device called trusted helper! '%s'/%d %RTuuid\n",
3896 pDevIns->pReg->szName, pDevIns->iInstance, pUuid));
3897 return NULL;
3898}
3899
3900
3901/**
3902 * The device helper structure for non-trusted devices.
3903 */
3904const PDMDEVHLPR3 g_pdmR3DevHlpUnTrusted =
3905{
3906 PDM_DEVHLPR3_VERSION,
3907 pdmR3DevHlp_IOPortRegister,
3908 pdmR3DevHlp_IOPortRegisterRC,
3909 pdmR3DevHlp_IOPortRegisterR0,
3910 pdmR3DevHlp_IOPortDeregister,
3911 pdmR3DevHlp_MMIORegister,
3912 pdmR3DevHlp_MMIORegisterRC,
3913 pdmR3DevHlp_MMIORegisterR0,
3914 pdmR3DevHlp_MMIODeregister,
3915 pdmR3DevHlp_MMIO2Register,
3916 pdmR3DevHlp_MMIOExPreRegister,
3917 pdmR3DevHlp_MMIOExDeregister,
3918 pdmR3DevHlp_MMIOExMap,
3919 pdmR3DevHlp_MMIOExUnmap,
3920 pdmR3DevHlp_MMIOExReduce,
3921 pdmR3DevHlp_MMHyperMapMMIO2,
3922 pdmR3DevHlp_MMIO2MapKernel,
3923 pdmR3DevHlp_ROMRegister,
3924 pdmR3DevHlp_ROMProtectShadow,
3925 pdmR3DevHlp_SSMRegister,
3926 pdmR3DevHlp_TMTimerCreate,
3927 pdmR3DevHlp_TMUtcNow,
3928 pdmR3DevHlp_PhysRead,
3929 pdmR3DevHlp_PhysWrite,
3930 pdmR3DevHlp_PhysGCPhys2CCPtr,
3931 pdmR3DevHlp_PhysGCPhys2CCPtrReadOnly,
3932 pdmR3DevHlp_PhysReleasePageMappingLock,
3933 pdmR3DevHlp_PhysReadGCVirt,
3934 pdmR3DevHlp_PhysWriteGCVirt,
3935 pdmR3DevHlp_PhysGCPtr2GCPhys,
3936 pdmR3DevHlp_MMHeapAlloc,
3937 pdmR3DevHlp_MMHeapAllocZ,
3938 pdmR3DevHlp_MMHeapFree,
3939 pdmR3DevHlp_VMState,
3940 pdmR3DevHlp_VMTeleportedAndNotFullyResumedYet,
3941 pdmR3DevHlp_VMSetError,
3942 pdmR3DevHlp_VMSetErrorV,
3943 pdmR3DevHlp_VMSetRuntimeError,
3944 pdmR3DevHlp_VMSetRuntimeErrorV,
3945 pdmR3DevHlp_DBGFStopV,
3946 pdmR3DevHlp_DBGFInfoRegister,
3947 pdmR3DevHlp_DBGFRegRegister,
3948 pdmR3DevHlp_DBGFTraceBuf,
3949 pdmR3DevHlp_STAMRegister,
3950 pdmR3DevHlp_STAMRegisterF,
3951 pdmR3DevHlp_STAMRegisterV,
3952 pdmR3DevHlp_PCIRegister,
3953 pdmR3DevHlp_PCIRegisterMsi,
3954 pdmR3DevHlp_PCIIORegionRegister,
3955 pdmR3DevHlp_PCISetConfigCallbacks,
3956 pdmR3DevHlp_PCIPhysRead,
3957 pdmR3DevHlp_PCIPhysWrite,
3958 pdmR3DevHlp_PCISetIrq,
3959 pdmR3DevHlp_PCISetIrqNoWait,
3960 pdmR3DevHlp_ISASetIrq,
3961 pdmR3DevHlp_ISASetIrqNoWait,
3962 pdmR3DevHlp_IoApicSendMsi,
3963 pdmR3DevHlp_DriverAttach,
3964 pdmR3DevHlp_DriverDetach,
3965 pdmR3DevHlp_QueueCreate,
3966 pdmR3DevHlp_CritSectInit,
3967 pdmR3DevHlp_CritSectGetNop,
3968 pdmR3DevHlp_CritSectGetNopR0,
3969 pdmR3DevHlp_CritSectGetNopRC,
3970 pdmR3DevHlp_SetDeviceCritSect,
3971 pdmR3DevHlp_ThreadCreate,
3972 pdmR3DevHlp_SetAsyncNotification,
3973 pdmR3DevHlp_AsyncNotificationCompleted,
3974 pdmR3DevHlp_RTCRegister,
3975 pdmR3DevHlp_PCIBusRegister,
3976 pdmR3DevHlp_PICRegister,
3977 pdmR3DevHlp_APICRegister,
3978 pdmR3DevHlp_IOAPICRegister,
3979 pdmR3DevHlp_HPETRegister,
3980 pdmR3DevHlp_PciRawRegister,
3981 pdmR3DevHlp_DMACRegister,
3982 pdmR3DevHlp_DMARegister,
3983 pdmR3DevHlp_DMAReadMemory,
3984 pdmR3DevHlp_DMAWriteMemory,
3985 pdmR3DevHlp_DMASetDREQ,
3986 pdmR3DevHlp_DMAGetChannelMode,
3987 pdmR3DevHlp_DMASchedule,
3988 pdmR3DevHlp_CMOSWrite,
3989 pdmR3DevHlp_CMOSRead,
3990 pdmR3DevHlp_AssertEMT,
3991 pdmR3DevHlp_AssertOther,
3992 pdmR3DevHlp_LdrGetRCInterfaceSymbols,
3993 pdmR3DevHlp_LdrGetR0InterfaceSymbols,
3994 pdmR3DevHlp_CallR0,
3995 pdmR3DevHlp_VMGetSuspendReason,
3996 pdmR3DevHlp_VMGetResumeReason,
3997 0,
3998 0,
3999 0,
4000 0,
4001 0,
4002 0,
4003 0,
4004 0,
4005 0,
4006 0,
4007 pdmR3DevHlp_Untrusted_GetUVM,
4008 pdmR3DevHlp_Untrusted_GetVM,
4009 pdmR3DevHlp_Untrusted_GetVMCPU,
4010 pdmR3DevHlp_Untrusted_GetCurrentCpuId,
4011 pdmR3DevHlp_Untrusted_RegisterVMMDevHeap,
4012 pdmR3DevHlp_Untrusted_FirmwareRegister,
4013 pdmR3DevHlp_Untrusted_VMReset,
4014 pdmR3DevHlp_Untrusted_VMSuspend,
4015 pdmR3DevHlp_Untrusted_VMSuspendSaveAndPowerOff,
4016 pdmR3DevHlp_Untrusted_VMPowerOff,
4017 pdmR3DevHlp_Untrusted_A20IsEnabled,
4018 pdmR3DevHlp_Untrusted_A20Set,
4019 pdmR3DevHlp_Untrusted_GetCpuId,
4020 pdmR3DevHlp_TMTimeVirtGet,
4021 pdmR3DevHlp_TMTimeVirtGetFreq,
4022 pdmR3DevHlp_TMTimeVirtGetNano,
4023 pdmR3DevHlp_Untrusted_GetSupDrvSession,
4024 pdmR3DevHlp_Untrusted_QueryGenericUserObject,
4025 PDM_DEVHLPR3_VERSION /* the end */
4026};
4027
4028
4029
4030/**
4031 * Queue consumer callback for internal component.
4032 *
4033 * @returns Success indicator.
4034 * If false the item will not be removed and the flushing will stop.
4035 * @param pVM The cross context VM structure.
4036 * @param pItem The item to consume. Upon return this item will be freed.
4037 */
4038DECLCALLBACK(bool) pdmR3DevHlpQueueConsumer(PVM pVM, PPDMQUEUEITEMCORE pItem)
4039{
4040 PPDMDEVHLPTASK pTask = (PPDMDEVHLPTASK)pItem;
4041 LogFlow(("pdmR3DevHlpQueueConsumer: enmOp=%d pDevIns=%p\n", pTask->enmOp, pTask->pDevInsR3));
4042 switch (pTask->enmOp)
4043 {
4044 case PDMDEVHLPTASKOP_ISA_SET_IRQ:
4045 PDMIsaSetIrq(pVM, pTask->u.IsaSetIRQ.iIrq, pTask->u.IsaSetIRQ.iLevel, pTask->u.IsaSetIRQ.uTagSrc);
4046 break;
4047
4048 case PDMDEVHLPTASKOP_PCI_SET_IRQ:
4049 {
4050 /* Same as pdmR3DevHlp_PCISetIrq, except we've got a tag already. */
4051 PPDMPCIDEV pPciDev = pTask->u.PciSetIRQ.pPciDevR3;
4052 if (pPciDev)
4053 {
4054 PPDMPCIBUS pBus = pPciDev->Int.s.pPdmBusR3;
4055 Assert(pBus);
4056
4057 pdmLock(pVM);
4058 pBus->pfnSetIrqR3(pBus->pDevInsR3, pPciDev, pTask->u.PciSetIRQ.iIrq,
4059 pTask->u.PciSetIRQ.iLevel, pTask->u.PciSetIRQ.uTagSrc);
4060 pdmUnlock(pVM);
4061 }
4062 else
4063 AssertReleaseMsgFailed(("No PCI device registered!\n"));
4064 break;
4065 }
4066
4067 case PDMDEVHLPTASKOP_IOAPIC_SET_IRQ:
4068 PDMIoApicSetIrq(pVM, pTask->u.IoApicSetIRQ.iIrq, pTask->u.IoApicSetIRQ.iLevel, pTask->u.IoApicSetIRQ.uTagSrc);
4069 break;
4070
4071 default:
4072 AssertReleaseMsgFailed(("Invalid operation %d\n", pTask->enmOp));
4073 break;
4074 }
4075 return true;
4076}
4077
4078/** @} */
4079
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