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source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 83085

Last change on this file since 83085 was 82968, checked in by vboxsync, 5 years ago

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1/* $Id: PDMDevMiscHlp.cpp 82968 2020-02-04 10:35:17Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/apic.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30
31#include <VBox/log.h>
32#include <VBox/err.h>
33#include <iprt/asm.h>
34#include <iprt/assert.h>
35#include <iprt/thread.h>
36
37
38#include "PDMInline.h"
39#include "dtrace/VBoxVMM.h"
40
41
42
43/** @name Ring-3 PIC Helpers
44 * @{
45 */
46
47/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
48static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
49{
50 PDMDEV_ASSERT_DEVINS(pDevIns);
51 PVM pVM = pDevIns->Internal.s.pVMR3;
52 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
53
54 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
55 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
56
57 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
58}
59
60
61/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
62static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
63{
64 PDMDEV_ASSERT_DEVINS(pDevIns);
65 PVM pVM = pDevIns->Internal.s.pVMR3;
66 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
67
68 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
69 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
70
71 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
72}
73
74
75/** @interface_method_impl{PDMPICHLP,pfnLock} */
76static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
77{
78 PDMDEV_ASSERT_DEVINS(pDevIns);
79 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
80}
81
82
83/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
84static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
85{
86 PDMDEV_ASSERT_DEVINS(pDevIns);
87 pdmUnlock(pDevIns->Internal.s.pVMR3);
88}
89
90
91/**
92 * PIC Device Helpers.
93 */
94const PDMPICHLP g_pdmR3DevPicHlp =
95{
96 PDM_PICHLP_VERSION,
97 pdmR3PicHlp_SetInterruptFF,
98 pdmR3PicHlp_ClearInterruptFF,
99 pdmR3PicHlp_Lock,
100 pdmR3PicHlp_Unlock,
101 PDM_PICHLP_VERSION /* the end */
102};
103
104/** @} */
105
106
107/** @name Ring-3 I/O APIC Helpers
108 * @{
109 */
110
111/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
112static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
113 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
114 uint8_t u8TriggerMode, uint32_t uTagSrc)
115{
116 PDMDEV_ASSERT_DEVINS(pDevIns);
117 PVM pVM = pDevIns->Internal.s.pVMR3;
118 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
119 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
120 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
121}
122
123
124/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
125static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
126{
127 PDMDEV_ASSERT_DEVINS(pDevIns);
128 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
129 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
130}
131
132
133/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
134static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
135{
136 PDMDEV_ASSERT_DEVINS(pDevIns);
137 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
138 pdmUnlock(pDevIns->Internal.s.pVMR3);
139}
140
141
142/**
143 * I/O APIC Device Helpers.
144 */
145const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
146{
147 PDM_IOAPICHLP_VERSION,
148 pdmR3IoApicHlp_ApicBusDeliver,
149 pdmR3IoApicHlp_Lock,
150 pdmR3IoApicHlp_Unlock,
151 PDM_IOAPICHLP_VERSION /* the end */
152};
153
154/** @} */
155
156
157
158
159/** @name Ring-3 PCI Bus Helpers
160 * @{
161 */
162
163/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
164static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
165{
166 PDMDEV_ASSERT_DEVINS(pDevIns);
167 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
168 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
169}
170
171
172/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
173static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
174{
175 PDMDEV_ASSERT_DEVINS(pDevIns);
176 Log4(("pdmR3PciHlp_IoApicSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
177 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
178}
179
180
181/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
182static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, RTGCPHYS GCPhys, uint32_t uValue, uint32_t uTagSrc)
183{
184 PDMDEV_ASSERT_DEVINS(pDevIns);
185 Log4(("pdmR3PciHlp_IoApicSendMsi: address=%p value=%x uTagSrc=%#x\n", GCPhys, uValue, uTagSrc));
186 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, GCPhys, uValue, uTagSrc);
187}
188
189
190/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
191static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
192{
193 PDMDEV_ASSERT_DEVINS(pDevIns);
194 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
195 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
196}
197
198
199/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
200static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
201{
202 PDMDEV_ASSERT_DEVINS(pDevIns);
203 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
204 pdmUnlock(pDevIns->Internal.s.pVMR3);
205}
206
207
208/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
209static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
210{
211 PDMDEV_ASSERT_DEVINS(pDevIns);
212 PVM pVM = pDevIns->Internal.s.pVMR3;
213 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
214 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
215 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
216 return pRetDevIns;
217}
218
219
220/**
221 * PCI Bus Device Helpers.
222 */
223const PDMPCIHLPR3 g_pdmR3DevPciHlp =
224{
225 PDM_PCIHLPR3_VERSION,
226 pdmR3PciHlp_IsaSetIrq,
227 pdmR3PciHlp_IoApicSetIrq,
228 pdmR3PciHlp_IoApicSendMsi,
229 pdmR3PciHlp_Lock,
230 pdmR3PciHlp_Unlock,
231 pdmR3PciHlp_GetBusByNo,
232 PDM_PCIHLPR3_VERSION, /* the end */
233};
234
235/** @} */
236
237
238
239
240/** @name Ring-3 HPET Helpers
241 * @{
242 */
243
244/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
245static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
246{
247 PDMDEV_ASSERT_DEVINS(pDevIns);
248 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
249
250 size_t i;
251 int rc = VINF_SUCCESS;
252 static const char * const s_apszDevsToNotify[] =
253 {
254 "i8254",
255 "mc146818"
256 };
257 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
258 {
259 PPDMIBASE pBase;
260 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
261 if (RT_SUCCESS(rc))
262 {
263 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
264 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
265 pPort->pfnModeChanged(pPort, fActivated);
266 }
267 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
268 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
269 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
270 else
271 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
272 }
273
274 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
275
276 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
277 return rc;
278}
279
280
281/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
282static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
283{
284 PDMDEV_ASSERT_DEVINS(pDevIns);
285 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
286 PVM pVM = pDevIns->Internal.s.pVMR3;
287
288 pdmLock(pVM);
289 uint32_t uTagSrc;
290 if (iLevel & PDM_IRQ_LEVEL_HIGH)
291 {
292 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
293 if (iLevel == PDM_IRQ_LEVEL_HIGH)
294 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
295 else
296 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
297 }
298 else
299 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
300
301 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
302
303 if (iLevel == PDM_IRQ_LEVEL_LOW)
304 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
305 pdmUnlock(pVM);
306 return 0;
307}
308
309
310/**
311 * HPET Device Helpers.
312 */
313const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
314{
315 PDM_HPETHLPR3_VERSION,
316 pdmR3HpetHlp_SetLegacyMode,
317 pdmR3HpetHlp_SetIrq,
318 PDM_HPETHLPR3_VERSION, /* the end */
319};
320
321/** @} */
322
323
324/** @name Ring-3 Raw PCI Device Helpers
325 * @{
326 */
327
328/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
329static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
330{
331 PDMDEV_ASSERT_DEVINS(pDevIns);
332 PVM pVM = pDevIns->Internal.s.pVMR3;
333 VM_ASSERT_EMT(pVM);
334
335 RTRCPTR pRCHelpers = NIL_RTRCPTR;
336 if (VM_IS_RAW_MODE_ENABLED(pVM))
337 {
338 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
339 AssertReleaseRC(rc);
340 AssertRelease(pRCHelpers);
341 }
342
343 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
344 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
345 return pRCHelpers;
346}
347
348
349/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
350static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
351{
352 PDMDEV_ASSERT_DEVINS(pDevIns);
353 PVM pVM = pDevIns->Internal.s.pVMR3;
354 VM_ASSERT_EMT(pVM);
355 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
356 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
357 AssertReleaseRC(rc);
358 AssertRelease(pR0Helpers);
359 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
360 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
361 return pR0Helpers;
362}
363
364
365/**
366 * Raw PCI Device Helpers.
367 */
368const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
369{
370 PDM_PCIRAWHLPR3_VERSION,
371 pdmR3PciRawHlp_GetRCHelpers,
372 pdmR3PciRawHlp_GetR0Helpers,
373 PDM_PCIRAWHLPR3_VERSION, /* the end */
374};
375
376/** @} */
377
378
379/* none yet */
380
381/**
382 * Firmware Device Helpers.
383 */
384const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
385{
386 PDM_FWHLPR3_VERSION,
387 PDM_FWHLPR3_VERSION
388};
389
390/**
391 * DMAC Device Helpers.
392 */
393const PDMDMACHLP g_pdmR3DevDmacHlp =
394{
395 PDM_DMACHLP_VERSION
396};
397
398
399
400
401/* none yet */
402
403/**
404 * RTC Device Helpers.
405 */
406const PDMRTCHLP g_pdmR3DevRtcHlp =
407{
408 PDM_RTCHLP_VERSION
409};
410
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