VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 87477

Last change on this file since 87477 was 87477, checked in by vboxsync, 4 years ago

AMD IOMMU: bugref:9654 PDM IOMMU code de-duplication and cleanup.
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1/* $Id: PDMDevMiscHlp.cpp 87477 2021-01-29 11:43:09Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/apic.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30
31#include <VBox/log.h>
32#include <VBox/err.h>
33#include <VBox/msi.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36#include <iprt/thread.h>
37
38
39#include "PDMInline.h"
40#include "dtrace/VBoxVMM.h"
41
42
43
44/** @name Ring-3 PIC Helpers
45 * @{
46 */
47
48/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
49static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
50{
51 PDMDEV_ASSERT_DEVINS(pDevIns);
52 PVM pVM = pDevIns->Internal.s.pVMR3;
53 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
54
55 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
56 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
57
58 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
59}
60
61
62/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
63static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
64{
65 PDMDEV_ASSERT_DEVINS(pDevIns);
66 PVM pVM = pDevIns->Internal.s.pVMR3;
67 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
68
69 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
70 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
71
72 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
73}
74
75
76/** @interface_method_impl{PDMPICHLP,pfnLock} */
77static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
78{
79 PDMDEV_ASSERT_DEVINS(pDevIns);
80 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
81}
82
83
84/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
85static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
86{
87 PDMDEV_ASSERT_DEVINS(pDevIns);
88 pdmUnlock(pDevIns->Internal.s.pVMR3);
89}
90
91
92/**
93 * PIC Device Helpers.
94 */
95const PDMPICHLP g_pdmR3DevPicHlp =
96{
97 PDM_PICHLP_VERSION,
98 pdmR3PicHlp_SetInterruptFF,
99 pdmR3PicHlp_ClearInterruptFF,
100 pdmR3PicHlp_Lock,
101 pdmR3PicHlp_Unlock,
102 PDM_PICHLP_VERSION /* the end */
103};
104
105/** @} */
106
107
108/** @name Ring-3 I/O APIC Helpers
109 * @{
110 */
111
112/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
113static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
114 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
115 uint8_t u8TriggerMode, uint32_t uTagSrc)
116{
117 PDMDEV_ASSERT_DEVINS(pDevIns);
118 PVM pVM = pDevIns->Internal.s.pVMR3;
119 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
120 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
121 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
122}
123
124
125/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
126static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
127{
128 PDMDEV_ASSERT_DEVINS(pDevIns);
129 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
130 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
131}
132
133
134/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
135static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
136{
137 PDMDEV_ASSERT_DEVINS(pDevIns);
138 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
139 pdmUnlock(pDevIns->Internal.s.pVMR3);
140}
141
142
143/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
144static DECLCALLBACK(int) pdmR3IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t uDeviceId, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
145{
146 PDMDEV_ASSERT_DEVINS(pDevIns);
147 LogFlow(("pdmR3IoApicHlp_IommuRemapMsi: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
148 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
149
150#ifdef VBOX_WITH_IOMMU_AMD
151 int rc = pdmIommuMsiRemap(pDevIns, uDeviceId, pMsiIn, pMsiOut);
152 if (RT_SUCCESS(rc) || rc != VERR_IOMMU_NOT_PRESENT)
153 return rc;
154#else
155 RT_NOREF(pDevIns, uDeviceId);
156#endif
157
158 *pMsiOut = *pMsiIn;
159 return VINF_SUCCESS;
160}
161
162
163/**
164 * I/O APIC Device Helpers.
165 */
166const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
167{
168 PDM_IOAPICHLP_VERSION,
169 pdmR3IoApicHlp_ApicBusDeliver,
170 pdmR3IoApicHlp_Lock,
171 pdmR3IoApicHlp_Unlock,
172 pdmR3IoApicHlp_IommuMsiRemap,
173 PDM_IOAPICHLP_VERSION /* the end */
174};
175
176/** @} */
177
178
179
180
181/** @name Ring-3 PCI Bus Helpers
182 * @{
183 */
184
185/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
186static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
187{
188 PDMDEV_ASSERT_DEVINS(pDevIns);
189 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
190 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
191}
192
193
194/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
195static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
196{
197 PDMDEV_ASSERT_DEVINS(pDevIns);
198 Log4(("pdmR3PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
199 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, uBusDevFn, iIrq, iLevel, uTagSrc);
200}
201
202
203/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
204static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
205{
206 PDMDEV_ASSERT_DEVINS(pDevIns);
207 Assert(PCIBDF_IS_VALID(uBusDevFn));
208 Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn,
209 pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
210 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc);
211}
212
213
214/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
215static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
216{
217 PDMDEV_ASSERT_DEVINS(pDevIns);
218 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
219 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
220}
221
222
223/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
224static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
225{
226 PDMDEV_ASSERT_DEVINS(pDevIns);
227 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
228 pdmUnlock(pDevIns->Internal.s.pVMR3);
229}
230
231
232/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
233static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
234{
235 PDMDEV_ASSERT_DEVINS(pDevIns);
236 PVM pVM = pDevIns->Internal.s.pVMR3;
237 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
238 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
239 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
240 return pRetDevIns;
241}
242
243
244/**
245 * PCI Bus Device Helpers.
246 */
247const PDMPCIHLPR3 g_pdmR3DevPciHlp =
248{
249 PDM_PCIHLPR3_VERSION,
250 pdmR3PciHlp_IsaSetIrq,
251 pdmR3PciHlp_IoApicSetIrq,
252 pdmR3PciHlp_IoApicSendMsi,
253 pdmR3PciHlp_Lock,
254 pdmR3PciHlp_Unlock,
255 pdmR3PciHlp_GetBusByNo,
256 PDM_PCIHLPR3_VERSION, /* the end */
257};
258
259/** @} */
260
261
262/**
263 * IOMMU Device Helpers.
264 */
265const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
266{
267 PDM_IOMMUHLPR3_VERSION,
268 PDM_IOMMUHLPR3_VERSION /* the end */
269};
270
271
272/** @name Ring-3 HPET Helpers
273 * @{
274 */
275
276/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
277static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
278{
279 PDMDEV_ASSERT_DEVINS(pDevIns);
280 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
281
282 size_t i;
283 int rc = VINF_SUCCESS;
284 static const char * const s_apszDevsToNotify[] =
285 {
286 "i8254",
287 "mc146818"
288 };
289 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
290 {
291 PPDMIBASE pBase;
292 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
293 if (RT_SUCCESS(rc))
294 {
295 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
296 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
297 pPort->pfnModeChanged(pPort, fActivated);
298 }
299 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
300 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
301 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
302 else
303 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
304 }
305
306 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
307
308 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
309 return rc;
310}
311
312
313/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
314static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
315{
316 PDMDEV_ASSERT_DEVINS(pDevIns);
317 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
318 PVM pVM = pDevIns->Internal.s.pVMR3;
319
320 pdmLock(pVM);
321 uint32_t uTagSrc;
322 if (iLevel & PDM_IRQ_LEVEL_HIGH)
323 {
324 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
325 if (iLevel == PDM_IRQ_LEVEL_HIGH)
326 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
327 else
328 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
329 }
330 else
331 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
332
333 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
334
335 if (iLevel == PDM_IRQ_LEVEL_LOW)
336 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
337 pdmUnlock(pVM);
338 return 0;
339}
340
341
342/**
343 * HPET Device Helpers.
344 */
345const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
346{
347 PDM_HPETHLPR3_VERSION,
348 pdmR3HpetHlp_SetLegacyMode,
349 pdmR3HpetHlp_SetIrq,
350 PDM_HPETHLPR3_VERSION, /* the end */
351};
352
353/** @} */
354
355
356/** @name Ring-3 Raw PCI Device Helpers
357 * @{
358 */
359
360/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
361static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
362{
363 PDMDEV_ASSERT_DEVINS(pDevIns);
364 PVM pVM = pDevIns->Internal.s.pVMR3;
365 VM_ASSERT_EMT(pVM);
366
367 RTRCPTR pRCHelpers = NIL_RTRCPTR;
368 if (VM_IS_RAW_MODE_ENABLED(pVM))
369 {
370 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
371 AssertReleaseRC(rc);
372 AssertRelease(pRCHelpers);
373 }
374
375 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
376 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
377 return pRCHelpers;
378}
379
380
381/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
382static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
383{
384 PDMDEV_ASSERT_DEVINS(pDevIns);
385 PVM pVM = pDevIns->Internal.s.pVMR3;
386 VM_ASSERT_EMT(pVM);
387 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
388 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
389 AssertReleaseRC(rc);
390 AssertRelease(pR0Helpers);
391 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
392 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
393 return pR0Helpers;
394}
395
396
397/**
398 * Raw PCI Device Helpers.
399 */
400const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
401{
402 PDM_PCIRAWHLPR3_VERSION,
403 pdmR3PciRawHlp_GetRCHelpers,
404 pdmR3PciRawHlp_GetR0Helpers,
405 PDM_PCIRAWHLPR3_VERSION, /* the end */
406};
407
408/** @} */
409
410
411/* none yet */
412
413/**
414 * Firmware Device Helpers.
415 */
416const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
417{
418 PDM_FWHLPR3_VERSION,
419 PDM_FWHLPR3_VERSION
420};
421
422/**
423 * DMAC Device Helpers.
424 */
425const PDMDMACHLP g_pdmR3DevDmacHlp =
426{
427 PDM_DMACHLP_VERSION
428};
429
430
431
432
433/* none yet */
434
435/**
436 * RTC Device Helpers.
437 */
438const PDMRTCHLP g_pdmR3DevRtcHlp =
439{
440 PDM_RTCHLP_VERSION
441};
442
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