VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 88811

Last change on this file since 88811 was 88639, checked in by vboxsync, 4 years ago

Intel IOMMU: bugref:9967 PDM: Enable more interfaces for Intel IOMMU and comment nit.
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1/* $Id: PDMDevMiscHlp.cpp 88639 2021-04-22 05:52:42Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2020 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_PDM_DEVICE
23#include "PDMInternal.h"
24#include <VBox/vmm/pdm.h>
25#include <VBox/vmm/pgm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/apic.h>
28#include <VBox/vmm/vm.h>
29#include <VBox/vmm/vmm.h>
30
31#include <VBox/log.h>
32#include <VBox/err.h>
33#include <VBox/msi.h>
34#include <iprt/asm.h>
35#include <iprt/assert.h>
36#include <iprt/thread.h>
37
38
39#include "PDMInline.h"
40#include "dtrace/VBoxVMM.h"
41
42
43
44/** @name Ring-3 PIC Helpers
45 * @{
46 */
47
48/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
49static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
50{
51 PDMDEV_ASSERT_DEVINS(pDevIns);
52 PVM pVM = pDevIns->Internal.s.pVMR3;
53 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
54
55 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
56 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
57
58 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
59}
60
61
62/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
63static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
64{
65 PDMDEV_ASSERT_DEVINS(pDevIns);
66 PVM pVM = pDevIns->Internal.s.pVMR3;
67 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
68
69 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
70 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
71
72 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
73}
74
75
76/** @interface_method_impl{PDMPICHLP,pfnLock} */
77static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
78{
79 PDMDEV_ASSERT_DEVINS(pDevIns);
80 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
81}
82
83
84/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
85static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
86{
87 PDMDEV_ASSERT_DEVINS(pDevIns);
88 pdmUnlock(pDevIns->Internal.s.pVMR3);
89}
90
91
92/**
93 * PIC Device Helpers.
94 */
95const PDMPICHLP g_pdmR3DevPicHlp =
96{
97 PDM_PICHLP_VERSION,
98 pdmR3PicHlp_SetInterruptFF,
99 pdmR3PicHlp_ClearInterruptFF,
100 pdmR3PicHlp_Lock,
101 pdmR3PicHlp_Unlock,
102 PDM_PICHLP_VERSION /* the end */
103};
104
105/** @} */
106
107
108/** @name Ring-3 I/O APIC Helpers
109 * @{
110 */
111
112/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
113static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
114 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
115 uint8_t u8TriggerMode, uint32_t uTagSrc)
116{
117 PDMDEV_ASSERT_DEVINS(pDevIns);
118 PVM pVM = pDevIns->Internal.s.pVMR3;
119 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
120 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
121 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
122}
123
124
125/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
126static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
127{
128 PDMDEV_ASSERT_DEVINS(pDevIns);
129 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
130 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
131}
132
133
134/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
135static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
136{
137 PDMDEV_ASSERT_DEVINS(pDevIns);
138 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
139 pdmUnlock(pDevIns->Internal.s.pVMR3);
140}
141
142
143/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
144static DECLCALLBACK(int) pdmR3IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
145{
146 PDMDEV_ASSERT_DEVINS(pDevIns);
147 LogFlow(("pdmR3IoApicHlp_IommuRemapMsi: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
148 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
149
150#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
151 if (pdmIommuIsPresent(pDevIns))
152 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
153#else
154 RT_NOREF(pDevIns, idDevice);
155#endif
156 return VERR_IOMMU_NOT_PRESENT;
157}
158
159
160/**
161 * I/O APIC Device Helpers.
162 */
163const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
164{
165 PDM_IOAPICHLP_VERSION,
166 pdmR3IoApicHlp_ApicBusDeliver,
167 pdmR3IoApicHlp_Lock,
168 pdmR3IoApicHlp_Unlock,
169 pdmR3IoApicHlp_IommuMsiRemap,
170 PDM_IOAPICHLP_VERSION /* the end */
171};
172
173/** @} */
174
175
176
177
178/** @name Ring-3 PCI Bus Helpers
179 * @{
180 */
181
182/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
183static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
184{
185 PDMDEV_ASSERT_DEVINS(pDevIns);
186 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
187 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
188}
189
190
191/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
192static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
193{
194 PDMDEV_ASSERT_DEVINS(pDevIns);
195 Log4(("pdmR3PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
196 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, uBusDevFn, iIrq, iLevel, uTagSrc);
197}
198
199
200/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
201static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
202{
203 PDMDEV_ASSERT_DEVINS(pDevIns);
204 Assert(PCIBDF_IS_VALID(uBusDevFn));
205 Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn,
206 pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
207 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc);
208}
209
210
211/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
212static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
213{
214 PDMDEV_ASSERT_DEVINS(pDevIns);
215 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
216 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
217}
218
219
220/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
221static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
222{
223 PDMDEV_ASSERT_DEVINS(pDevIns);
224 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
225 pdmUnlock(pDevIns->Internal.s.pVMR3);
226}
227
228
229/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
230static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
231{
232 PDMDEV_ASSERT_DEVINS(pDevIns);
233 PVM pVM = pDevIns->Internal.s.pVMR3;
234 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
235 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
236 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
237 return pRetDevIns;
238}
239
240
241/**
242 * PCI Bus Device Helpers.
243 */
244const PDMPCIHLPR3 g_pdmR3DevPciHlp =
245{
246 PDM_PCIHLPR3_VERSION,
247 pdmR3PciHlp_IsaSetIrq,
248 pdmR3PciHlp_IoApicSetIrq,
249 pdmR3PciHlp_IoApicSendMsi,
250 pdmR3PciHlp_Lock,
251 pdmR3PciHlp_Unlock,
252 pdmR3PciHlp_GetBusByNo,
253 PDM_PCIHLPR3_VERSION, /* the end */
254};
255
256/** @} */
257
258
259/** @name Ring-3 IOMMU Helpers
260 * @{
261 */
262
263/** @interface_method_impl{PDMIOMMUHLPR3,pfnLock} */
264static DECLCALLBACK(int) pdmR3IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
265{
266 PDMDEV_ASSERT_DEVINS(pDevIns);
267 LogFlowFunc(("caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
268 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
269}
270
271
272/** @interface_method_impl{PDMIOMMUHLPR3,pfnUnlock} */
273static DECLCALLBACK(void) pdmR3IommuHlp_Unlock(PPDMDEVINS pDevIns)
274{
275 PDMDEV_ASSERT_DEVINS(pDevIns);
276 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
277 pdmUnlock(pDevIns->Internal.s.pVMR3);
278}
279
280
281/** @interface_method_impl{PDMIOMMUHLPR3,pfnLockIsOwner} */
282static DECLCALLBACK(bool) pdmR3IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
283{
284 PDMDEV_ASSERT_DEVINS(pDevIns);
285 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
286 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
287}
288
289
290/** @interface_method_impl{PDMIOMMUHLPR3,pfnSendMsi} */
291static DECLCALLBACK(int) pdmR3IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
292{
293 PDMDEV_ASSERT_DEVINS(pDevIns);
294 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
295 return PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, NIL_PCIBDF, pMsi, uTagSrc);
296}
297
298
299/**
300 * IOMMU Device Helpers.
301 */
302const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
303{
304 PDM_IOMMUHLPR3_VERSION,
305 pdmR3IommuHlp_Lock,
306 pdmR3IommuHlp_Unlock,
307 pdmR3IommuHlp_LockIsOwner,
308 pdmR3IommuHlp_SendMsi,
309 PDM_IOMMUHLPR3_VERSION /* the end */
310};
311
312/** @} */
313
314
315/** @name Ring-3 HPET Helpers
316 * @{
317 */
318
319/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
320static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
321{
322 PDMDEV_ASSERT_DEVINS(pDevIns);
323 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
324
325 size_t i;
326 int rc = VINF_SUCCESS;
327 static const char * const s_apszDevsToNotify[] =
328 {
329 "i8254",
330 "mc146818"
331 };
332 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
333 {
334 PPDMIBASE pBase;
335 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
336 if (RT_SUCCESS(rc))
337 {
338 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
339 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
340 pPort->pfnModeChanged(pPort, fActivated);
341 }
342 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
343 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
344 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
345 else
346 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
347 }
348
349 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
350
351 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
352 return rc;
353}
354
355
356/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
357static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
358{
359 PDMDEV_ASSERT_DEVINS(pDevIns);
360 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
361 PVM pVM = pDevIns->Internal.s.pVMR3;
362
363 pdmLock(pVM);
364 uint32_t uTagSrc;
365 if (iLevel & PDM_IRQ_LEVEL_HIGH)
366 {
367 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
368 if (iLevel == PDM_IRQ_LEVEL_HIGH)
369 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
370 else
371 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
372 }
373 else
374 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
375
376 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
377
378 if (iLevel == PDM_IRQ_LEVEL_LOW)
379 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
380 pdmUnlock(pVM);
381 return 0;
382}
383
384
385/**
386 * HPET Device Helpers.
387 */
388const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
389{
390 PDM_HPETHLPR3_VERSION,
391 pdmR3HpetHlp_SetLegacyMode,
392 pdmR3HpetHlp_SetIrq,
393 PDM_HPETHLPR3_VERSION, /* the end */
394};
395
396/** @} */
397
398
399/** @name Ring-3 Raw PCI Device Helpers
400 * @{
401 */
402
403/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
404static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
405{
406 PDMDEV_ASSERT_DEVINS(pDevIns);
407 PVM pVM = pDevIns->Internal.s.pVMR3;
408 VM_ASSERT_EMT(pVM);
409
410 RTRCPTR pRCHelpers = NIL_RTRCPTR;
411 if (VM_IS_RAW_MODE_ENABLED(pVM))
412 {
413 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
414 AssertReleaseRC(rc);
415 AssertRelease(pRCHelpers);
416 }
417
418 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
419 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
420 return pRCHelpers;
421}
422
423
424/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
425static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
426{
427 PDMDEV_ASSERT_DEVINS(pDevIns);
428 PVM pVM = pDevIns->Internal.s.pVMR3;
429 VM_ASSERT_EMT(pVM);
430 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
431 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
432 AssertReleaseRC(rc);
433 AssertRelease(pR0Helpers);
434 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
435 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
436 return pR0Helpers;
437}
438
439
440/**
441 * Raw PCI Device Helpers.
442 */
443const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
444{
445 PDM_PCIRAWHLPR3_VERSION,
446 pdmR3PciRawHlp_GetRCHelpers,
447 pdmR3PciRawHlp_GetR0Helpers,
448 PDM_PCIRAWHLPR3_VERSION, /* the end */
449};
450
451/** @} */
452
453
454/* none yet */
455
456/**
457 * Firmware Device Helpers.
458 */
459const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
460{
461 PDM_FWHLPR3_VERSION,
462 PDM_FWHLPR3_VERSION
463};
464
465/**
466 * DMAC Device Helpers.
467 */
468const PDMDMACHLP g_pdmR3DevDmacHlp =
469{
470 PDM_DMACHLP_VERSION
471};
472
473
474
475
476/* none yet */
477
478/**
479 * RTC Device Helpers.
480 */
481const PDMRTCHLP g_pdmR3DevRtcHlp =
482{
483 PDM_RTCHLP_VERSION
484};
485
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