VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/PDMDevMiscHlp.cpp@ 98970

Last change on this file since 98970 was 98103, checked in by vboxsync, 2 years ago

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1/* $Id: PDMDevMiscHlp.cpp 98103 2023-01-17 14:15:46Z vboxsync $ */
2/** @file
3 * PDM - Pluggable Device and Driver Manager, Misc. Device Helpers.
4 */
5
6/*
7 * Copyright (C) 2006-2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_PDM_DEVICE
33#include "PDMInternal.h"
34#include <VBox/vmm/pdm.h>
35#include <VBox/vmm/pgm.h>
36#include <VBox/vmm/hm.h>
37#include <VBox/vmm/apic.h>
38#include <VBox/vmm/vm.h>
39#include <VBox/vmm/vmm.h>
40
41#include <VBox/log.h>
42#include <VBox/err.h>
43#include <VBox/msi.h>
44#include <iprt/asm.h>
45#include <iprt/assert.h>
46#include <iprt/thread.h>
47
48
49#include "PDMInline.h"
50#include "dtrace/VBoxVMM.h"
51
52
53
54/** @name Ring-3 PIC Helpers
55 * @{
56 */
57
58/** @interface_method_impl{PDMPICHLP,pfnSetInterruptFF} */
59static DECLCALLBACK(void) pdmR3PicHlp_SetInterruptFF(PPDMDEVINS pDevIns)
60{
61 PDMDEV_ASSERT_DEVINS(pDevIns);
62 PVM pVM = pDevIns->Internal.s.pVMR3;
63 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
64
65 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
66 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
67
68 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 1 /* u8Level */, VINF_SUCCESS /* rcRZ */);
69}
70
71
72/** @interface_method_impl{PDMPICHLP,pfnClearInterruptFF} */
73static DECLCALLBACK(void) pdmR3PicHlp_ClearInterruptFF(PPDMDEVINS pDevIns)
74{
75 PDMDEV_ASSERT_DEVINS(pDevIns);
76 PVM pVM = pDevIns->Internal.s.pVMR3;
77 PVMCPU pVCpu = pVM->apCpusR3[0]; /* for PIC we always deliver to CPU 0, SMP uses APIC */
78
79 /* IRQ state should be loaded as-is by "LoadExec". Changes can be made from LoadDone. */
80 Assert(pVM->enmVMState != VMSTATE_LOADING || pVM->pdm.s.fStateLoaded);
81
82 APICLocalInterrupt(pVCpu, 0 /* u8Pin */, 0 /* u8Level */, VINF_SUCCESS /* rcRZ */);
83}
84
85
86/** @interface_method_impl{PDMPICHLP,pfnLock} */
87static DECLCALLBACK(int) pdmR3PicHlp_Lock(PPDMDEVINS pDevIns, int rc)
88{
89 PDMDEV_ASSERT_DEVINS(pDevIns);
90 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
91}
92
93
94/** @interface_method_impl{PDMPICHLP,pfnUnlock} */
95static DECLCALLBACK(void) pdmR3PicHlp_Unlock(PPDMDEVINS pDevIns)
96{
97 PDMDEV_ASSERT_DEVINS(pDevIns);
98 pdmUnlock(pDevIns->Internal.s.pVMR3);
99}
100
101
102/**
103 * PIC Device Helpers.
104 */
105const PDMPICHLP g_pdmR3DevPicHlp =
106{
107 PDM_PICHLP_VERSION,
108 pdmR3PicHlp_SetInterruptFF,
109 pdmR3PicHlp_ClearInterruptFF,
110 pdmR3PicHlp_Lock,
111 pdmR3PicHlp_Unlock,
112 PDM_PICHLP_VERSION /* the end */
113};
114
115/** @} */
116
117
118/** @name Ring-3 I/O APIC Helpers
119 * @{
120 */
121
122/** @interface_method_impl{PDMIOAPICHLP,pfnApicBusDeliver} */
123static DECLCALLBACK(int) pdmR3IoApicHlp_ApicBusDeliver(PPDMDEVINS pDevIns, uint8_t u8Dest, uint8_t u8DestMode,
124 uint8_t u8DeliveryMode, uint8_t uVector, uint8_t u8Polarity,
125 uint8_t u8TriggerMode, uint32_t uTagSrc)
126{
127 PDMDEV_ASSERT_DEVINS(pDevIns);
128 PVM pVM = pDevIns->Internal.s.pVMR3;
129 LogFlow(("pdmR3IoApicHlp_ApicBusDeliver: caller='%s'/%d: u8Dest=%RX8 u8DestMode=%RX8 u8DeliveryMode=%RX8 uVector=%RX8 u8Polarity=%RX8 u8TriggerMode=%RX8 uTagSrc=%#x\n",
130 pDevIns->pReg->szName, pDevIns->iInstance, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc));
131 return APICBusDeliver(pVM, u8Dest, u8DestMode, u8DeliveryMode, uVector, u8Polarity, u8TriggerMode, uTagSrc);
132}
133
134
135/** @interface_method_impl{PDMIOAPICHLP,pfnLock} */
136static DECLCALLBACK(int) pdmR3IoApicHlp_Lock(PPDMDEVINS pDevIns, int rc)
137{
138 PDMDEV_ASSERT_DEVINS(pDevIns);
139 LogFlow(("pdmR3IoApicHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
140 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
141}
142
143
144/** @interface_method_impl{PDMIOAPICHLP,pfnUnlock} */
145static DECLCALLBACK(void) pdmR3IoApicHlp_Unlock(PPDMDEVINS pDevIns)
146{
147 PDMDEV_ASSERT_DEVINS(pDevIns);
148 LogFlow(("pdmR3IoApicHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
149 pdmUnlock(pDevIns->Internal.s.pVMR3);
150}
151
152
153/** @interface_method_impl{PDMIOAPICHLP,pfnLockIsOwner} */
154static DECLCALLBACK(bool) pdmR3IoApicHlp_LockIsOwner(PPDMDEVINS pDevIns)
155{
156 PDMDEV_ASSERT_DEVINS(pDevIns);
157 LogFlow(("pdmR3IoApicHlp_LockIsOwner: caller='%s'/%d\n", pDevIns->pReg->szName, pDevIns->iInstance));
158 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
159}
160
161
162/** @interface_method_impl{PDMIOAPICHLP,pfnIommuMsiRemap} */
163static DECLCALLBACK(int) pdmR3IoApicHlp_IommuMsiRemap(PPDMDEVINS pDevIns, uint16_t idDevice, PCMSIMSG pMsiIn, PMSIMSG pMsiOut)
164{
165 PDMDEV_ASSERT_DEVINS(pDevIns);
166 LogFlow(("pdmR3IoApicHlp_IommuRemapMsi: caller='%s'/%d: pMsiIn=(%#RX64, %#RU32)\n", pDevIns->pReg->szName,
167 pDevIns->iInstance, pMsiIn->Addr.u64, pMsiIn->Data.u32));
168
169#if defined(VBOX_WITH_IOMMU_AMD) || defined(VBOX_WITH_IOMMU_INTEL)
170 if (pdmIommuIsPresent(pDevIns))
171 return pdmIommuMsiRemap(pDevIns, idDevice, pMsiIn, pMsiOut);
172#else
173 RT_NOREF(pDevIns, idDevice);
174#endif
175 return VERR_IOMMU_NOT_PRESENT;
176}
177
178
179/**
180 * I/O APIC Device Helpers.
181 */
182const PDMIOAPICHLP g_pdmR3DevIoApicHlp =
183{
184 PDM_IOAPICHLP_VERSION,
185 pdmR3IoApicHlp_ApicBusDeliver,
186 pdmR3IoApicHlp_Lock,
187 pdmR3IoApicHlp_Unlock,
188 pdmR3IoApicHlp_LockIsOwner,
189 pdmR3IoApicHlp_IommuMsiRemap,
190 PDM_IOAPICHLP_VERSION /* the end */
191};
192
193/** @} */
194
195
196
197
198/** @name Ring-3 PCI Bus Helpers
199 * @{
200 */
201
202/** @interface_method_impl{PDMPCIHLPR3,pfnIsaSetIrq} */
203static DECLCALLBACK(void) pdmR3PciHlp_IsaSetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel, uint32_t uTagSrc)
204{
205 PDMDEV_ASSERT_DEVINS(pDevIns);
206 Log4(("pdmR3PciHlp_IsaSetIrq: iIrq=%d iLevel=%d uTagSrc=%#x\n", iIrq, iLevel, uTagSrc));
207 PDMIsaSetIrq(pDevIns->Internal.s.pVMR3, iIrq, iLevel, uTagSrc);
208}
209
210
211/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSetIrq} */
212static DECLCALLBACK(void) pdmR3PciHlp_IoApicSetIrq(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, int iIrq, int iLevel, uint32_t uTagSrc)
213{
214 PDMDEV_ASSERT_DEVINS(pDevIns);
215 Log4(("pdmR3PciHlp_IoApicSetIrq: uBusDevFn=%#x iIrq=%d iLevel=%d uTagSrc=%#x\n", uBusDevFn, iIrq, iLevel, uTagSrc));
216 PDMIoApicSetIrq(pDevIns->Internal.s.pVMR3, uBusDevFn, iIrq, iLevel, uTagSrc);
217}
218
219
220/** @interface_method_impl{PDMPCIHLPR3,pfnIoApicSendMsi} */
221static DECLCALLBACK(void) pdmR3PciHlp_IoApicSendMsi(PPDMDEVINS pDevIns, PCIBDF uBusDevFn, PCMSIMSG pMsi, uint32_t uTagSrc)
222{
223 PDMDEV_ASSERT_DEVINS(pDevIns);
224 Assert(PCIBDF_IS_VALID(uBusDevFn));
225 Log4(("pdmR3PciHlp_IoApicSendMsi: uBusDevFn=%#x Msi (Addr=%#RX64 Data=%#x) uTagSrc=%#x\n", uBusDevFn,
226 pMsi->Addr.u64, pMsi->Data.u32, uTagSrc));
227 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, uBusDevFn, pMsi, uTagSrc);
228}
229
230
231/** @interface_method_impl{PDMPCIHLPR3,pfnLock} */
232static DECLCALLBACK(int) pdmR3PciHlp_Lock(PPDMDEVINS pDevIns, int rc)
233{
234 PDMDEV_ASSERT_DEVINS(pDevIns);
235 LogFlow(("pdmR3PciHlp_Lock: caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
236 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
237}
238
239
240/** @interface_method_impl{PDMPCIHLPR3,pfnUnlock} */
241static DECLCALLBACK(void) pdmR3PciHlp_Unlock(PPDMDEVINS pDevIns)
242{
243 PDMDEV_ASSERT_DEVINS(pDevIns);
244 LogFlow(("pdmR3PciHlp_Unlock: caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
245 pdmUnlock(pDevIns->Internal.s.pVMR3);
246}
247
248
249/** @interface_method_impl{PDMPCIHLPR3,pfnGetBusByNo} */
250static DECLCALLBACK(PPDMDEVINS) pdmR3PciHlp_GetBusByNo(PPDMDEVINS pDevIns, uint32_t idxPdmBus)
251{
252 PDMDEV_ASSERT_DEVINS(pDevIns);
253 PVM pVM = pDevIns->Internal.s.pVMR3;
254 AssertReturn(idxPdmBus < RT_ELEMENTS(pVM->pdm.s.aPciBuses), NULL);
255 PPDMDEVINS pRetDevIns = pVM->pdm.s.aPciBuses[idxPdmBus].pDevInsR3;
256 LogFlow(("pdmR3PciHlp_GetBusByNo: caller='%s'/%d: returns %p\n", pDevIns->pReg->szName, pDevIns->iInstance, pRetDevIns));
257 return pRetDevIns;
258}
259
260
261/**
262 * PCI Bus Device Helpers.
263 */
264const PDMPCIHLPR3 g_pdmR3DevPciHlp =
265{
266 PDM_PCIHLPR3_VERSION,
267 pdmR3PciHlp_IsaSetIrq,
268 pdmR3PciHlp_IoApicSetIrq,
269 pdmR3PciHlp_IoApicSendMsi,
270 pdmR3PciHlp_Lock,
271 pdmR3PciHlp_Unlock,
272 pdmR3PciHlp_GetBusByNo,
273 PDM_PCIHLPR3_VERSION, /* the end */
274};
275
276/** @} */
277
278
279/** @name Ring-3 IOMMU Helpers
280 * @{
281 */
282
283/** @interface_method_impl{PDMIOMMUHLPR3,pfnLock} */
284static DECLCALLBACK(int) pdmR3IommuHlp_Lock(PPDMDEVINS pDevIns, int rc)
285{
286 PDMDEV_ASSERT_DEVINS(pDevIns);
287 LogFlowFunc(("caller='%s'/%d: rc=%Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
288 return pdmLockEx(pDevIns->Internal.s.pVMR3, rc);
289}
290
291
292/** @interface_method_impl{PDMIOMMUHLPR3,pfnUnlock} */
293static DECLCALLBACK(void) pdmR3IommuHlp_Unlock(PPDMDEVINS pDevIns)
294{
295 PDMDEV_ASSERT_DEVINS(pDevIns);
296 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
297 pdmUnlock(pDevIns->Internal.s.pVMR3);
298}
299
300
301/** @interface_method_impl{PDMIOMMUHLPR3,pfnLockIsOwner} */
302static DECLCALLBACK(bool) pdmR3IommuHlp_LockIsOwner(PPDMDEVINS pDevIns)
303{
304 PDMDEV_ASSERT_DEVINS(pDevIns);
305 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
306 return pdmLockIsOwner(pDevIns->Internal.s.pVMR3);
307}
308
309
310/** @interface_method_impl{PDMIOMMUHLPR3,pfnSendMsi} */
311static DECLCALLBACK(void) pdmR3IommuHlp_SendMsi(PPDMDEVINS pDevIns, PCMSIMSG pMsi, uint32_t uTagSrc)
312{
313 PDMDEV_ASSERT_DEVINS(pDevIns);
314 LogFlowFunc(("caller='%s'/%d:\n", pDevIns->pReg->szName, pDevIns->iInstance));
315 PDMIoApicSendMsi(pDevIns->Internal.s.pVMR3, NIL_PCIBDF, pMsi, uTagSrc);
316}
317
318
319/**
320 * IOMMU Device Helpers.
321 */
322const PDMIOMMUHLPR3 g_pdmR3DevIommuHlp =
323{
324 PDM_IOMMUHLPR3_VERSION,
325 pdmR3IommuHlp_Lock,
326 pdmR3IommuHlp_Unlock,
327 pdmR3IommuHlp_LockIsOwner,
328 pdmR3IommuHlp_SendMsi,
329 PDM_IOMMUHLPR3_VERSION /* the end */
330};
331
332/** @} */
333
334
335/** @name Ring-3 HPET Helpers
336 * @{
337 */
338
339/** @interface_method_impl{PDMHPETHLPR3,pfnSetLegacyMode} */
340static DECLCALLBACK(int) pdmR3HpetHlp_SetLegacyMode(PPDMDEVINS pDevIns, bool fActivated)
341{
342 PDMDEV_ASSERT_DEVINS(pDevIns);
343 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: fActivated=%RTbool\n", pDevIns->pReg->szName, pDevIns->iInstance, fActivated));
344
345 size_t i;
346 int rc = VINF_SUCCESS;
347 static const char * const s_apszDevsToNotify[] =
348 {
349 "i8254",
350 "mc146818"
351 };
352 for (i = 0; i < RT_ELEMENTS(s_apszDevsToNotify); i++)
353 {
354 PPDMIBASE pBase;
355 rc = PDMR3QueryDevice(pDevIns->Internal.s.pVMR3->pUVM, "i8254", 0, &pBase);
356 if (RT_SUCCESS(rc))
357 {
358 PPDMIHPETLEGACYNOTIFY pPort = PDMIBASE_QUERY_INTERFACE(pBase, PDMIHPETLEGACYNOTIFY);
359 AssertLogRelMsgBreakStmt(pPort, ("%s\n", s_apszDevsToNotify[i]), rc = VERR_PDM_HPET_LEGACY_NOTIFY_MISSING);
360 pPort->pfnModeChanged(pPort, fActivated);
361 }
362 else if ( rc == VERR_PDM_DEVICE_NOT_FOUND
363 || rc == VERR_PDM_DEVICE_INSTANCE_NOT_FOUND)
364 rc = VINF_SUCCESS; /* the device isn't configured, ignore. */
365 else
366 AssertLogRelMsgFailedBreak(("%s -> %Rrc\n", s_apszDevsToNotify[i], rc));
367 }
368
369 /* Don't bother cleaning up, any failure here will cause a guru meditation. */
370
371 LogFlow(("pdmR3HpetHlp_SetLegacyMode: caller='%s'/%d: returns %Rrc\n", pDevIns->pReg->szName, pDevIns->iInstance, rc));
372 return rc;
373}
374
375
376/** @interface_method_impl{PDMHPETHLPR3,pfnSetIrq} */
377static DECLCALLBACK(int) pdmR3HpetHlp_SetIrq(PPDMDEVINS pDevIns, int iIrq, int iLevel)
378{
379 PDMDEV_ASSERT_DEVINS(pDevIns);
380 LogFlow(("pdmR3HpetHlp_SetIrq: caller='%s'/%d: iIrq=%d iLevel=%d\n", pDevIns->pReg->szName, pDevIns->iInstance, iIrq, iLevel));
381 PVM pVM = pDevIns->Internal.s.pVMR3;
382
383 pdmLock(pVM);
384 uint32_t uTagSrc;
385 if (iLevel & PDM_IRQ_LEVEL_HIGH)
386 {
387 pDevIns->Internal.s.uLastIrqTag = uTagSrc = pdmCalcIrqTag(pVM, pDevIns->idTracing);
388 if (iLevel == PDM_IRQ_LEVEL_HIGH)
389 VBOXVMM_PDM_IRQ_HIGH(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
390 else
391 VBOXVMM_PDM_IRQ_HILO(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
392 }
393 else
394 uTagSrc = pDevIns->Internal.s.uLastIrqTag;
395
396 PDMIsaSetIrq(pVM, iIrq, iLevel, uTagSrc); /* (The API takes the lock recursively.) */
397
398 if (iLevel == PDM_IRQ_LEVEL_LOW)
399 VBOXVMM_PDM_IRQ_LOW(VMMGetCpu(pVM), RT_LOWORD(uTagSrc), RT_HIWORD(uTagSrc));
400 pdmUnlock(pVM);
401 return 0;
402}
403
404
405/**
406 * HPET Device Helpers.
407 */
408const PDMHPETHLPR3 g_pdmR3DevHpetHlp =
409{
410 PDM_HPETHLPR3_VERSION,
411 pdmR3HpetHlp_SetLegacyMode,
412 pdmR3HpetHlp_SetIrq,
413 PDM_HPETHLPR3_VERSION, /* the end */
414};
415
416/** @} */
417
418
419/** @name Ring-3 Raw PCI Device Helpers
420 * @{
421 */
422
423/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetRCHelpers} */
424static DECLCALLBACK(PCPDMPCIRAWHLPRC) pdmR3PciRawHlp_GetRCHelpers(PPDMDEVINS pDevIns)
425{
426 PDMDEV_ASSERT_DEVINS(pDevIns);
427 PVM pVM = pDevIns->Internal.s.pVMR3;
428 VM_ASSERT_EMT(pVM);
429
430 RTRCPTR pRCHelpers = NIL_RTRCPTR;
431#if 0
432 if (VM_IS_RAW_MODE_ENABLED(pVM))
433 {
434 int rc = PDMR3LdrGetSymbolRC(pVM, NULL, "g_pdmRCPciRawHlp", &pRCHelpers);
435 AssertReleaseRC(rc);
436 AssertRelease(pRCHelpers);
437 }
438#else
439 RT_NOREF(pVM, pDevIns);
440#endif
441
442 LogFlow(("pdmR3PciRawHlp_GetGCHelpers: caller='%s'/%d: returns %RRv\n",
443 pDevIns->pReg->szName, pDevIns->iInstance, pRCHelpers));
444 return pRCHelpers;
445}
446
447
448/** @interface_method_impl{PDMPCIRAWHLPR3,pfnGetR0Helpers} */
449static DECLCALLBACK(PCPDMPCIRAWHLPR0) pdmR3PciRawHlp_GetR0Helpers(PPDMDEVINS pDevIns)
450{
451 PDMDEV_ASSERT_DEVINS(pDevIns);
452 PVM pVM = pDevIns->Internal.s.pVMR3;
453 VM_ASSERT_EMT(pVM);
454 PCPDMHPETHLPR0 pR0Helpers = NIL_RTR0PTR;
455 int rc = PDMR3LdrGetSymbolR0(pVM, NULL, "g_pdmR0PciRawHlp", &pR0Helpers);
456 AssertReleaseRC(rc);
457 AssertRelease(pR0Helpers);
458 LogFlow(("pdmR3PciRawHlp_GetR0Helpers: caller='%s'/%d: returns %RHv\n",
459 pDevIns->pReg->szName, pDevIns->iInstance, pR0Helpers));
460 return pR0Helpers;
461}
462
463
464/**
465 * Raw PCI Device Helpers.
466 */
467const PDMPCIRAWHLPR3 g_pdmR3DevPciRawHlp =
468{
469 PDM_PCIRAWHLPR3_VERSION,
470 pdmR3PciRawHlp_GetRCHelpers,
471 pdmR3PciRawHlp_GetR0Helpers,
472 PDM_PCIRAWHLPR3_VERSION, /* the end */
473};
474
475/** @} */
476
477
478/* none yet */
479
480/**
481 * Firmware Device Helpers.
482 */
483const PDMFWHLPR3 g_pdmR3DevFirmwareHlp =
484{
485 PDM_FWHLPR3_VERSION,
486 PDM_FWHLPR3_VERSION
487};
488
489/**
490 * DMAC Device Helpers.
491 */
492const PDMDMACHLP g_pdmR3DevDmacHlp =
493{
494 PDM_DMACHLP_VERSION
495};
496
497
498
499
500/* none yet */
501
502/**
503 * RTC Device Helpers.
504 */
505const PDMRTCHLP g_pdmR3DevRtcHlp =
506{
507 PDM_RTCHLP_VERSION
508};
509
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