PGM.cpp@ 45744

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1	/* $Id: PGM.cpp 45739 2013-04-25 19:44:05Z vboxsync $ */
2	/** @file
3	* PGM - Page Manager and Monitor. (Mixing stuff here, not good?)
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/** @page pg_pgm PGM - The Page Manager and Monitor
20	*
21	* @see grp_pgm,
22	* @ref pg_pgm_pool,
23	* @ref pg_pgm_phys.
24	*
25	*
26	* @section sec_pgm_modes Paging Modes
27	*
28	* There are three memory contexts: Host Context (HC), Guest Context (GC)
29	* and intermediate context. When talking about paging HC can also be referred
30	* to as "host paging", and GC referred to as "shadow paging".
31	*
32	* We define three basic paging modes: 32-bit, PAE and AMD64. The host paging mode
33	* is defined by the host operating system. The mode used in the shadow paging mode
34	* depends on the host paging mode and what the mode the guest is currently in. The
35	* following relation between the two is defined:
36	*
37	* @verbatim
38	Host > 32-bit \| PAE \| AMD64 \|
39	Guest \| \| \| \|
40	==v================================
41	32-bit 32-bit PAE PAE
42	-------\|--------\|--------\|--------\|
43	PAE PAE PAE PAE
44	-------\|--------\|--------\|--------\|
45	AMD64 AMD64 AMD64 AMD64
46	-------\|--------\|--------\|--------\| @endverbatim
47	*
48	* All configuration except those in the diagonal (upper left) are expected to
49	* require special effort from the switcher (i.e. a bit slower).
50	*
51	*
52	*
53	*
54	* @section sec_pgm_shw The Shadow Memory Context
55	*
56	*
57	* [..]
58	*
59	* Because of guest context mappings requires PDPT and PML4 entries to allow
60	* writing on AMD64, the two upper levels will have fixed flags whatever the
61	* guest is thinking of using there. So, when shadowing the PD level we will
62	* calculate the effective flags of PD and all the higher levels. In legacy
63	* PAE mode this only applies to the PWT and PCD bits (the rest are
64	* ignored/reserved/MBZ). We will ignore those bits for the present.
65	*
66	*
67	*
68	* @section sec_pgm_int The Intermediate Memory Context
69	*
70	* The world switch goes thru an intermediate memory context which purpose it is
71	* to provide different mappings of the switcher code. All guest mappings are also
72	* present in this context.
73	*
74	* The switcher code is mapped at the same location as on the host, at an
75	* identity mapped location (physical equals virtual address), and at the
76	* hypervisor location. The identity mapped location is for when the world
77	* switches that involves disabling paging.
78	*
79	* PGM maintain page tables for 32-bit, PAE and AMD64 paging modes. This
80	* simplifies switching guest CPU mode and consistency at the cost of more
81	* code to do the work. All memory use for those page tables is located below
82	* 4GB (this includes page tables for guest context mappings).
83	*
84	*
85	* @subsection subsec_pgm_int_gc Guest Context Mappings
86	*
87	* During assignment and relocation of a guest context mapping the intermediate
88	* memory context is used to verify the new location.
89	*
90	* Guest context mappings are currently restricted to below 4GB, for reasons
91	* of simplicity. This may change when we implement AMD64 support.
92	*
93	*
94	*
95	*
96	* @section sec_pgm_misc Misc
97	*
98	*
99	* @subsection sec_pgm_misc_A20 The A20 Gate
100	*
101	* PGM implements the A20 gate masking when translating a virtual guest address
102	* into a physical address for CPU access, i.e. PGMGstGetPage (and friends) and
103	* the code reading the guest page table entries during shadowing. The masking
104	* is done consistenly for all CPU modes, paged ones included. Large pages are
105	* also masked correctly. (On current CPUs, experiments indicates that AMD does
106	* not apply A20M in paged modes and intel only does it for the 2nd MB of
107	* memory.)
108	*
109	* The A20 gate implementation is per CPU core. It can be configured on a per
110	* core basis via the keyboard device and PC architecture device. This is
111	* probably not exactly how real CPUs do it, but SMP and A20 isn't a place where
112	* guest OSes try pushing things anyway, so who cares. (On current real systems
113	* the A20M signal is probably only sent to the boot CPU and it affects all
114	* thread and probably all cores in that package.)
115	*
116	* The keyboard device and the PC architecture device doesn't OR their A20
117	* config bits together, rather they are currently implemented such that they
118	* mirror the CPU state. So, flipping the bit in either of them will change the
119	* A20 state. (On real hardware the bits of the two devices should probably be
120	* ORed together to indicate enabled, i.e. both needs to be cleared to disable
121	* A20 masking.)
122	*
123	* The A20 state will change immediately, transmeta fashion. There is no delays
124	* due to buses, wiring or other physical stuff. (On real hardware there are
125	* normally delays, the delays differs between the two devices and probably also
126	* between chipsets and CPU generations. Note that it's said that transmeta CPUs
127	* does the change immediately like us, they apparently intercept/handles the
128	* port accesses in microcode. Neat.)
129	*
130	* @sa http://en.wikipedia.org/wiki/A20_line#The_80286_and_the_high_memory_area
131	*
132	*
133	* @subsection subsec_pgm_misc_diff Differences Between Legacy PAE and Long Mode PAE
134	*
135	* The differences between legacy PAE and long mode PAE are:
136	* -# PDPE bits 1, 2, 5 and 6 are defined differently. In leagcy mode they are
137	* all marked down as must-be-zero, while in long mode 1, 2 and 5 have the
138	* usual meanings while 6 is ignored (AMD). This means that upon switching to
139	* legacy PAE mode we'll have to clear these bits and when going to long mode
140	* they must be set. This applies to both intermediate and shadow contexts,
141	* however we don't need to do it for the intermediate one since we're
142	* executing with CR0.WP at that time.
143	* -# CR3 allows a 32-byte aligned address in legacy mode, while in long mode
144	* a page aligned one is required.
145	*
146	*
147	* @section sec_pgm_handlers Access Handlers
148	*
149	* Placeholder.
150	*
151	*
152	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
153	*
154	* Placeholder.
155	*
156	*
157	* @subsection sec_pgm_handlers_virt Virtual Access Handlers
158	*
159	* We currently implement three types of virtual access handlers: ALL, WRITE
160	* and HYPERVISOR (WRITE). See PGMVIRTHANDLERTYPE for some more details.
161	*
162	* The HYPERVISOR access handlers is kept in a separate tree since it doesn't apply
163	* to physical pages (PGMTREES::HyperVirtHandlers) and only needs to be consulted in
164	* a special \#PF case. The ALL and WRITE are in the PGMTREES::VirtHandlers tree, the
165	* rest of this section is going to be about these handlers.
166	*
167	* We'll go thru the life cycle of a handler and try make sense of it all, don't know
168	* how successful this is gonna be...
169	*
170	* 1. A handler is registered thru the PGMR3HandlerVirtualRegister and
171	* PGMHandlerVirtualRegisterEx APIs. We check for conflicting virtual handlers
172	* and create a new node that is inserted into the AVL tree (range key). Then
173	* a full PGM resync is flagged (clear pool, sync cr3, update virtual bit of PGMPAGE).
174	*
175	* 2. The following PGMSyncCR3/SyncCR3 operation will first make invoke HandlerVirtualUpdate.
176	*
177	* 2a. HandlerVirtualUpdate will will lookup all the pages covered by virtual handlers
178	* via the current guest CR3 and update the physical page -> virtual handler
179	* translation. Needless to say, this doesn't exactly scale very well. If any changes
180	* are detected, it will flag a virtual bit update just like we did on registration.
181	* PGMPHYS pages with changes will have their virtual handler state reset to NONE.
182	*
183	* 2b. The virtual bit update process will iterate all the pages covered by all the
184	* virtual handlers and update the PGMPAGE virtual handler state to the max of all
185	* virtual handlers on that page.
186	*
187	* 2c. Back in SyncCR3 we will now flush the entire shadow page cache to make sure
188	* we don't miss any alias mappings of the monitored pages.
189	*
190	* 2d. SyncCR3 will then proceed with syncing the CR3 table.
191	*
192	* 3. \#PF(np,read) on a page in the range. This will cause it to be synced
193	* read-only and resumed if it's a WRITE handler. If it's an ALL handler we
194	* will call the handlers like in the next step. If the physical mapping has
195	* changed we will - some time in the future - perform a handler callback
196	* (optional) and update the physical -> virtual handler cache.
197	*
198	* 4. \#PF(,write) on a page in the range. This will cause the handler to
199	* be invoked.
200	*
201	* 5. The guest invalidates the page and changes the physical backing or
202	* unmaps it. This should cause the invalidation callback to be invoked
203	* (it might not yet be 100% perfect). Exactly what happens next... is
204	* this where we mess up and end up out of sync for a while?
205	*
206	* 6. The handler is deregistered by the client via PGMHandlerVirtualDeregister.
207	* We will then set all PGMPAGEs in the physical -> virtual handler cache for
208	* this handler to NONE and trigger a full PGM resync (basically the same
209	* as int step 1). Which means 2 is executed again.
210	*
211	*
212	* @subsubsection sub_sec_pgm_handler_virt_todo TODOs
213	*
214	* There is a bunch of things that needs to be done to make the virtual handlers
215	* work 100% correctly and work more efficiently.
216	*
217	* The first bit hasn't been implemented yet because it's going to slow the
218	* whole mess down even more, and besides it seems to be working reliably for
219	* our current uses. OTOH, some of the optimizations might end up more or less
220	* implementing the missing bits, so we'll see.
221	*
222	* On the optimization side, the first thing to do is to try avoid unnecessary
223	* cache flushing. Then try team up with the shadowing code to track changes
224	* in mappings by means of access to them (shadow in), updates to shadows pages,
225	* invlpg, and shadow PT discarding (perhaps).
226	*
227	* Some idea that have popped up for optimization for current and new features:
228	* - bitmap indicating where there are virtual handlers installed.
229	* (4KB => 220 pages, page 212 => covers 32-bit address space 1:1!)
230	* - Further optimize this by min/max (needs min/max avl getters).
231	* - Shadow page table entry bit (if any left)?
232	*
233	*/
234
235
236	/** @page pg_pgm_phys PGM Physical Guest Memory Management
237	*
238	*
239	* Objectives:
240	* - Guest RAM over-commitment using memory ballooning,
241	* zero pages and general page sharing.
242	* - Moving or mirroring a VM onto a different physical machine.
243	*
244	*
245	* @subsection subsec_pgmPhys_Definitions Definitions
246	*
247	* Allocation chunk - A RTR0MemObjAllocPhysNC object and the tracking
248	* machinery associated with it.
249	*
250	*
251	*
252	*
253	* @subsection subsec_pgmPhys_AllocPage Allocating a page.
254	*
255	* Initially we map all guest memory to the (per VM) zero page, which
256	* means that none of the read functions will cause pages to be allocated.
257	*
258	* Exception, access bit in page tables that have been shared. This must
259	* be handled, but we must also make sure PGMGst*Modify doesn't make
260	* unnecessary modifications.
261	*
262	* Allocation points:
263	* - PGMPhysSimpleWriteGCPhys and PGMPhysWrite.
264	* - Replacing a zero page mapping at \#PF.
265	* - Replacing a shared page mapping at \#PF.
266	* - ROM registration (currently MMR3RomRegister).
267	* - VM restore (pgmR3Load).
268	*
269	* For the first three it would make sense to keep a few pages handy
270	* until we've reached the max memory commitment for the VM.
271	*
272	* For the ROM registration, we know exactly how many pages we need
273	* and will request these from ring-0. For restore, we will save
274	* the number of non-zero pages in the saved state and allocate
275	* them up front. This would allow the ring-0 component to refuse
276	* the request if the isn't sufficient memory available for VM use.
277	*
278	* Btw. for both ROM and restore allocations we won't be requiring
279	* zeroed pages as they are going to be filled instantly.
280	*
281	*
282	* @subsection subsec_pgmPhys_FreePage Freeing a page
283	*
284	* There are a few points where a page can be freed:
285	* - After being replaced by the zero page.
286	* - After being replaced by a shared page.
287	* - After being ballooned by the guest additions.
288	* - At reset.
289	* - At restore.
290	*
291	* When freeing one or more pages they will be returned to the ring-0
292	* component and replaced by the zero page.
293	*
294	* The reasoning for clearing out all the pages on reset is that it will
295	* return us to the exact same state as on power on, and may thereby help
296	* us reduce the memory load on the system. Further it might have a
297	* (temporary) positive influence on memory fragmentation (@see subsec_pgmPhys_Fragmentation).
298	*
299	* On restore, as mention under the allocation topic, pages should be
300	* freed / allocated depending on how many is actually required by the
301	* new VM state. The simplest approach is to do like on reset, and free
302	* all non-ROM pages and then allocate what we need.
303	*
304	* A measure to prevent some fragmentation, would be to let each allocation
305	* chunk have some affinity towards the VM having allocated the most pages
306	* from it. Also, try make sure to allocate from allocation chunks that
307	* are almost full. Admittedly, both these measures might work counter to
308	* our intentions and its probably not worth putting a lot of effort,
309	* cpu time or memory into this.
310	*
311	*
312	* @subsection subsec_pgmPhys_SharePage Sharing a page
313	*
314	* The basic idea is that there there will be a idle priority kernel
315	* thread walking the non-shared VM pages hashing them and looking for
316	* pages with the same checksum. If such pages are found, it will compare
317	* them byte-by-byte to see if they actually are identical. If found to be
318	* identical it will allocate a shared page, copy the content, check that
319	* the page didn't change while doing this, and finally request both the
320	* VMs to use the shared page instead. If the page is all zeros (special
321	* checksum and byte-by-byte check) it will request the VM that owns it
322	* to replace it with the zero page.
323	*
324	* To make this efficient, we will have to make sure not to try share a page
325	* that will change its contents soon. This part requires the most work.
326	* A simple idea would be to request the VM to write monitor the page for
327	* a while to make sure it isn't modified any time soon. Also, it may
328	* make sense to skip pages that are being write monitored since this
329	* information is readily available to the thread if it works on the
330	* per-VM guest memory structures (presently called PGMRAMRANGE).
331	*
332	*
333	* @subsection subsec_pgmPhys_Fragmentation Fragmentation Concerns and Counter Measures
334	*
335	* The pages are organized in allocation chunks in ring-0, this is a necessity
336	* if we wish to have an OS agnostic approach to this whole thing. (On Linux we
337	* could easily work on a page-by-page basis if we liked. Whether this is possible
338	* or efficient on NT I don't quite know.) Fragmentation within these chunks may
339	* become a problem as part of the idea here is that we wish to return memory to
340	* the host system.
341	*
342	* For instance, starting two VMs at the same time, they will both allocate the
343	* guest memory on-demand and if permitted their page allocations will be
344	* intermixed. Shut down one of the two VMs and it will be difficult to return
345	* any memory to the host system because the page allocation for the two VMs are
346	* mixed up in the same allocation chunks.
347	*
348	* To further complicate matters, when pages are freed because they have been
349	* ballooned or become shared/zero the whole idea is that the page is supposed
350	* to be reused by another VM or returned to the host system. This will cause
351	* allocation chunks to contain pages belonging to different VMs and prevent
352	* returning memory to the host when one of those VM shuts down.
353	*
354	* The only way to really deal with this problem is to move pages. This can
355	* either be done at VM shutdown and or by the idle priority worker thread
356	* that will be responsible for finding sharable/zero pages. The mechanisms
357	* involved for coercing a VM to move a page (or to do it for it) will be
358	* the same as when telling it to share/zero a page.
359	*
360	*
361	* @subsection subsec_pgmPhys_Tracking Tracking Structures And Their Cost
362	*
363	* There's a difficult balance between keeping the per-page tracking structures
364	* (global and guest page) easy to use and keeping them from eating too much
365	* memory. We have limited virtual memory resources available when operating in
366	* 32-bit kernel space (on 64-bit there'll it's quite a different story). The
367	* tracking structures will be attempted designed such that we can deal with up
368	* to 32GB of memory on a 32-bit system and essentially unlimited on 64-bit ones.
369	*
370	*
371	* @subsubsection subsubsec_pgmPhys_Tracking_Kernel Kernel Space
372	*
373	* @see pg_GMM
374	*
375	* @subsubsection subsubsec_pgmPhys_Tracking_PerVM Per-VM
376	*
377	* Fixed info is the physical address of the page (HCPhys) and the page id
378	* (described above). Theoretically we'll need 48(-12) bits for the HCPhys part.
379	* Today we've restricting ourselves to 40(-12) bits because this is the current
380	* restrictions of all AMD64 implementations (I think Barcelona will up this
381	* to 48(-12) bits, not that it really matters) and I needed the bits for
382	* tracking mappings of a page. 48-12 = 36. That leaves 28 bits, which means a
383	* decent range for the page id: 2^(28+12) = 1024TB.
384	*
385	* In additions to these, we'll have to keep maintaining the page flags as we
386	* currently do. Although it wouldn't harm to optimize these quite a bit, like
387	* for instance the ROM shouldn't depend on having a write handler installed
388	* in order for it to become read-only. A RO/RW bit should be considered so
389	* that the page syncing code doesn't have to mess about checking multiple
390	* flag combinations (ROM \|\| RW handler \|\| write monitored) in order to
391	* figure out how to setup a shadow PTE. But this of course, is second
392	* priority at present. Current this requires 12 bits, but could probably
393	* be optimized to ~8.
394	*
395	* Then there's the 24 bits used to track which shadow page tables are
396	* currently mapping a page for the purpose of speeding up physical
397	* access handlers, and thereby the page pool cache. More bit for this
398	* purpose wouldn't hurt IIRC.
399	*
400	* Then there is a new bit in which we need to record what kind of page
401	* this is, shared, zero, normal or write-monitored-normal. This'll
402	* require 2 bits. One bit might be needed for indicating whether a
403	* write monitored page has been written to. And yet another one or
404	* two for tracking migration status. 3-4 bits total then.
405	*
406	* Whatever is left will can be used to record the sharabilitiy of a
407	* page. The page checksum will not be stored in the per-VM table as
408	* the idle thread will not be permitted to do modifications to it.
409	* It will instead have to keep its own working set of potentially
410	* shareable pages and their check sums and stuff.
411	*
412	* For the present we'll keep the current packing of the
413	* PGMRAMRANGE::aHCPhys to keep the changes simple, only of course,
414	* we'll have to change it to a struct with a total of 128-bits at
415	* our disposal.
416	*
417	* The initial layout will be like this:
418	* @verbatim
419	RTHCPHYS HCPhys; The current stuff.
420	63:40 Current shadow PT tracking stuff.
421	39:12 The physical page frame number.
422	11:0 The current flags.
423	uint32_t u28PageId : 28; The page id.
424	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
425	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
426	uint32_t u1Reserved : 1; Reserved for later.
427	uint32_t u32Reserved; Reserved for later, mostly sharing stats.
428	@endverbatim
429	*
430	* The final layout will be something like this:
431	* @verbatim
432	RTHCPHYS HCPhys; The current stuff.
433	63:48 High page id (12+).
434	47:12 The physical page frame number.
435	11:0 Low page id.
436	uint32_t fReadOnly : 1; Whether it's readonly page (rom or monitored in some way).
437	uint32_t u3Type : 3; The page type {RESERVED, MMIO, MMIO2, ROM, shadowed ROM, RAM}.
438	uint32_t u2PhysMon : 2; Physical access handler type {none, read, write, all}.
439	uint32_t u2VirtMon : 2; Virtual access handler type {none, read, write, all}..
440	uint32_t u2State : 2; The page state { zero, shared, normal, write monitored }.
441	uint32_t fWrittenTo : 1; Whether a write monitored page was written to.
442	uint32_t u20Reserved : 20; Reserved for later, mostly sharing stats.
443	uint32_t u32Tracking; The shadow PT tracking stuff, roughly.
444	@endverbatim
445	*
446	* Cost wise, this means we'll double the cost for guest memory. There isn't anyway
447	* around that I'm afraid. It means that the cost of dealing out 32GB of memory
448	* to one or more VMs is: (32GB >> PAGE_SHIFT) * 16 bytes, or 128MBs. Or another
449	* example, the VM heap cost when assigning 1GB to a VM will be: 4MB.
450	*
451	* A couple of cost examples for the total cost per-VM + kernel.
452	* 32-bit Windows and 32-bit linux:
453	* 1GB guest ram, 256K pages: 4MB + 2MB(+) = 6MB
454	* 4GB guest ram, 1M pages: 16MB + 8MB(+) = 24MB
455	* 32GB guest ram, 8M pages: 128MB + 64MB(+) = 192MB
456	* 64-bit Windows and 64-bit linux:
457	* 1GB guest ram, 256K pages: 4MB + 3MB(+) = 7MB
458	* 4GB guest ram, 1M pages: 16MB + 12MB(+) = 28MB
459	* 32GB guest ram, 8M pages: 128MB + 96MB(+) = 224MB
460	*
461	* UPDATE - 2007-09-27:
462	* Will need a ballooned flag/state too because we cannot
463	* trust the guest 100% and reporting the same page as ballooned more
464	* than once will put the GMM off balance.
465	*
466	*
467	* @subsection subsec_pgmPhys_Serializing Serializing Access
468	*
469	* Initially, we'll try a simple scheme:
470	*
471	* - The per-VM RAM tracking structures (PGMRAMRANGE) is only modified
472	* by the EMT thread of that VM while in the pgm critsect.
473	* - Other threads in the VM process that needs to make reliable use of
474	* the per-VM RAM tracking structures will enter the critsect.
475	* - No process external thread or kernel thread will ever try enter
476	* the pgm critical section, as that just won't work.
477	* - The idle thread (and similar threads) doesn't not need 100% reliable
478	* data when performing it tasks as the EMT thread will be the one to
479	* do the actual changes later anyway. So, as long as it only accesses
480	* the main ram range, it can do so by somehow preventing the VM from
481	* being destroyed while it works on it...
482	*
483	* - The over-commitment management, including the allocating/freeing
484	* chunks, is serialized by a ring-0 mutex lock (a fast one since the
485	* more mundane mutex implementation is broken on Linux).
486	* - A separate mutex is protecting the set of allocation chunks so
487	* that pages can be shared or/and freed up while some other VM is
488	* allocating more chunks. This mutex can be take from under the other
489	* one, but not the other way around.
490	*
491	*
492	* @subsection subsec_pgmPhys_Request VM Request interface
493	*
494	* When in ring-0 it will become necessary to send requests to a VM so it can
495	* for instance move a page while defragmenting during VM destroy. The idle
496	* thread will make use of this interface to request VMs to setup shared
497	* pages and to perform write monitoring of pages.
498	*
499	* I would propose an interface similar to the current VMReq interface, similar
500	* in that it doesn't require locking and that the one sending the request may
501	* wait for completion if it wishes to. This shouldn't be very difficult to
502	* realize.
503	*
504	* The requests themselves are also pretty simple. They are basically:
505	* -# Check that some precondition is still true.
506	* -# Do the update.
507	* -# Update all shadow page tables involved with the page.
508	*
509	* The 3rd step is identical to what we're already doing when updating a
510	* physical handler, see pgmHandlerPhysicalSetRamFlagsAndFlushShadowPTs.
511	*
512	*
513	*
514	* @section sec_pgmPhys_MappingCaches Mapping Caches
515	*
516	* In order to be able to map in and out memory and to be able to support
517	* guest with more RAM than we've got virtual address space, we'll employing
518	* a mapping cache. Normally ring-0 and ring-3 can share the same cache,
519	* however on 32-bit darwin the ring-0 code is running in a different memory
520	* context and therefore needs a separate cache. In raw-mode context we also
521	* need a separate cache. The 32-bit darwin mapping cache and the one for
522	* raw-mode context share a lot of code, see PGMRZDYNMAP.
523	*
524	*
525	* @subsection subsec_pgmPhys_MappingCaches_R3 Ring-3
526	*
527	* We've considered implementing the ring-3 mapping cache page based but found
528	* that this was bother some when one had to take into account TLBs+SMP and
529	* portability (missing the necessary APIs on several platforms). There were
530	* also some performance concerns with this approach which hadn't quite been
531	* worked out.
532	*
533	* Instead, we'll be mapping allocation chunks into the VM process. This simplifies
534	* matters greatly quite a bit since we don't need to invent any new ring-0 stuff,
535	* only some minor RTR0MEMOBJ mapping stuff. The main concern here is that mapping
536	* compared to the previous idea is that mapping or unmapping a 1MB chunk is more
537	* costly than a single page, although how much more costly is uncertain. We'll
538	* try address this by using a very big cache, preferably bigger than the actual
539	* VM RAM size if possible. The current VM RAM sizes should give some idea for
540	* 32-bit boxes, while on 64-bit we can probably get away with employing an
541	* unlimited cache.
542	*
543	* The cache have to parts, as already indicated, the ring-3 side and the
544	* ring-0 side.
545	*
546	* The ring-0 will be tied to the page allocator since it will operate on the
547	* memory objects it contains. It will therefore require the first ring-0 mutex
548	* discussed in @ref subsec_pgmPhys_Serializing. We
549	* some double house keeping wrt to who has mapped what I think, since both
550	* VMMR0.r0 and RTR0MemObj will keep track of mapping relations
551	*
552	* The ring-3 part will be protected by the pgm critsect. For simplicity, we'll
553	* require anyone that desires to do changes to the mapping cache to do that
554	* from within this critsect. Alternatively, we could employ a separate critsect
555	* for serializing changes to the mapping cache as this would reduce potential
556	* contention with other threads accessing mappings unrelated to the changes
557	* that are in process. We can see about this later, contention will show
558	* up in the statistics anyway, so it'll be simple to tell.
559	*
560	* The organization of the ring-3 part will be very much like how the allocation
561	* chunks are organized in ring-0, that is in an AVL tree by chunk id. To avoid
562	* having to walk the tree all the time, we'll have a couple of lookaside entries
563	* like in we do for I/O ports and MMIO in IOM.
564	*
565	* The simplified flow of a PGMPhysRead/Write function:
566	* -# Enter the PGM critsect.
567	* -# Lookup GCPhys in the ram ranges and get the Page ID.
568	* -# Calc the Allocation Chunk ID from the Page ID.
569	* -# Check the lookaside entries and then the AVL tree for the Chunk ID.
570	* If not found in cache:
571	* -# Call ring-0 and request it to be mapped and supply
572	* a chunk to be unmapped if the cache is maxed out already.
573	* -# Insert the new mapping into the AVL tree (id + R3 address).
574	* -# Update the relevant lookaside entry and return the mapping address.
575	* -# Do the read/write according to monitoring flags and everything.
576	* -# Leave the critsect.
577	*
578	*
579	* @section sec_pgmPhys_Fallback Fallback
580	*
581	* Current all the "second tier" hosts will not support the RTR0MemObjAllocPhysNC
582	* API and thus require a fallback.
583	*
584	* So, when RTR0MemObjAllocPhysNC returns VERR_NOT_SUPPORTED the page allocator
585	* will return to the ring-3 caller (and later ring-0) and asking it to seed
586	* the page allocator with some fresh pages (VERR_GMM_SEED_ME). Ring-3 will
587	* then perform an SUPR3PageAlloc(cbChunk >> PAGE_SHIFT) call and make a
588	* "SeededAllocPages" call to ring-0.
589	*
590	* The first time ring-0 sees the VERR_NOT_SUPPORTED failure it will disable
591	* all page sharing (zero page detection will continue). It will also force
592	* all allocations to come from the VM which seeded the page. Both these
593	* measures are taken to make sure that there will never be any need for
594	* mapping anything into ring-3 - everything will be mapped already.
595	*
596	* Whether we'll continue to use the current MM locked memory management
597	* for this I don't quite know (I'd prefer not to and just ditch that all
598	* together), we'll see what's simplest to do.
599	*
600	*
601	*
602	* @section sec_pgmPhys_Changes Changes
603	*
604	* Breakdown of the changes involved?
605	*/
606
607	/*******************************************************************************
608	* Header Files *
609	*******************************************************************************/
610	#define LOG_GROUP LOG_GROUP_PGM
611	#include <VBox/vmm/dbgf.h>
612	#include <VBox/vmm/pgm.h>
613	#include <VBox/vmm/cpum.h>
614	#include <VBox/vmm/iom.h>
615	#include <VBox/sup.h>
616	#include <VBox/vmm/mm.h>
617	#include <VBox/vmm/em.h>
618	#include <VBox/vmm/stam.h>
619	#ifdef VBOX_WITH_REM
620	# include <VBox/vmm/rem.h>
621	#endif
622	#include <VBox/vmm/selm.h>
623	#include <VBox/vmm/ssm.h>
624	#include <VBox/vmm/hm.h>
625	#include "PGMInternal.h"
626	#include <VBox/vmm/vm.h>
627	#include <VBox/vmm/uvm.h>
628	#include "PGMInline.h"
629
630	#include <VBox/dbg.h>
631	#include <VBox/param.h>
632	#include <VBox/err.h>
633
634	#include <iprt/asm.h>
635	#include <iprt/asm-amd64-x86.h>
636	#include <iprt/assert.h>
637	#include <iprt/env.h>
638	#include <iprt/mem.h>
639	#include <iprt/file.h>
640	#include <iprt/string.h>
641	#include <iprt/thread.h>
642
643
644	/*******************************************************************************
645	* Internal Functions *
646	*******************************************************************************/
647	static int pgmR3InitPaging(PVM pVM);
648	static int pgmR3InitStats(PVM pVM);
649	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
650	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
651	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
652	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser);
653	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
654	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser);
655	#ifdef VBOX_STRICT
656	static FNVMATSTATE pgmR3ResetNoMorePhysWritesFlag;
657	#endif
658	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0);
659	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst);
660	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher);
661
662	#ifdef VBOX_WITH_DEBUGGER
663	static FNDBGCCMD pgmR3CmdError;
664	static FNDBGCCMD pgmR3CmdSync;
665	static FNDBGCCMD pgmR3CmdSyncAlways;
666	# ifdef VBOX_STRICT
667	static FNDBGCCMD pgmR3CmdAssertCR3;
668	# endif
669	static FNDBGCCMD pgmR3CmdPhysToFile;
670	#endif
671
672
673	/*******************************************************************************
674	* Global Variables *
675	*******************************************************************************/
676	#ifdef VBOX_WITH_DEBUGGER
677	/** Argument descriptors for '.pgmerror' and '.pgmerroroff'. */
678	static const DBGCVARDESC g_aPgmErrorArgs[] =
679	{
680	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
681	{ 0, 1, DBGCVAR_CAT_STRING, 0, "where", "Error injection location." },
682	};
683
684	static const DBGCVARDESC g_aPgmPhysToFileArgs[] =
685	{
686	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
687	{ 1, 1, DBGCVAR_CAT_STRING, 0, "file", "The file name." },
688	{ 0, 1, DBGCVAR_CAT_STRING, 0, "nozero", "If present, zero pages are skipped." },
689	};
690
691	# ifdef DEBUG_sandervl
692	static const DBGCVARDESC g_aPgmCountPhysWritesArgs[] =
693	{
694	/* cTimesMin, cTimesMax, enmCategory, fFlags, pszName, pszDescription */
695	{ 1, 1, DBGCVAR_CAT_STRING, 0, "enabled", "on/off." },
696	{ 1, 1, DBGCVAR_CAT_NUMBER_NO_RANGE, 0, "interval", "Interval in ms." },
697	};
698	# endif
699
700	/** Command descriptors. */
701	static const DBGCCMD g_aCmds[] =
702	{
703	/* pszCmd, cArgsMin, cArgsMax, paArgDesc, cArgDescs, fFlags, pfnHandler pszSyntax, ....pszDescription */
704	{ "pgmsync", 0, 0, NULL, 0, 0, pgmR3CmdSync, "", "Sync the CR3 page." },
705	{ "pgmerror", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Enables inject runtime of errors into parts of PGM." },
706	{ "pgmerroroff", 0, 1, &g_aPgmErrorArgs[0], 1, 0, pgmR3CmdError, "", "Disables inject runtime errors into parts of PGM." },
707	# ifdef VBOX_STRICT
708	{ "pgmassertcr3", 0, 0, NULL, 0, 0, pgmR3CmdAssertCR3, "", "Check the shadow CR3 mapping." },
709	# ifdef VBOX_WITH_PAGE_SHARING
710	{ "pgmcheckduppages", 0, 0, NULL, 0, 0, pgmR3CmdCheckDuplicatePages, "", "Check for duplicate pages in all running VMs." },
711	{ "pgmsharedmodules", 0, 0, NULL, 0, 0, pgmR3CmdShowSharedModules, "", "Print shared modules info." },
712	# endif
713	# endif
714	{ "pgmsyncalways", 0, 0, NULL, 0, 0, pgmR3CmdSyncAlways, "", "Toggle permanent CR3 syncing." },
715	{ "pgmphystofile", 1, 2, &g_aPgmPhysToFileArgs[0], 2, 0, pgmR3CmdPhysToFile, "", "Save the physical memory to file." },
716	};
717	#endif
718
719
720
721
722	/*
723	* Shadow - 32-bit mode
724	*/
725	#define PGM_SHW_TYPE PGM_TYPE_32BIT
726	#define PGM_SHW_NAME(name) PGM_SHW_NAME_32BIT(name)
727	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_32BIT_STR(name)
728	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_32BIT_STR(name)
729	#include "PGMShw.h"
730
731	/* Guest - real mode */
732	#define PGM_GST_TYPE PGM_TYPE_REAL
733	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
734	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
735	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
736	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_REAL(name)
737	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_REAL_STR(name)
738	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_REAL_STR(name)
739	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
740	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
741	#include "PGMBth.h"
742	#include "PGMGstDefs.h"
743	#include "PGMGst.h"
744	#undef BTH_PGMPOOLKIND_PT_FOR_PT
745	#undef BTH_PGMPOOLKIND_ROOT
746	#undef PGM_BTH_NAME
747	#undef PGM_BTH_NAME_RC_STR
748	#undef PGM_BTH_NAME_R0_STR
749	#undef PGM_GST_TYPE
750	#undef PGM_GST_NAME
751	#undef PGM_GST_NAME_RC_STR
752	#undef PGM_GST_NAME_R0_STR
753
754	/* Guest - protected mode */
755	#define PGM_GST_TYPE PGM_TYPE_PROT
756	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
757	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
758	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
759	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_PROT(name)
760	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_PROT_STR(name)
761	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_PROT_STR(name)
762	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_PHYS
763	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD_PHYS
764	#include "PGMBth.h"
765	#include "PGMGstDefs.h"
766	#include "PGMGst.h"
767	#undef BTH_PGMPOOLKIND_PT_FOR_PT
768	#undef BTH_PGMPOOLKIND_ROOT
769	#undef PGM_BTH_NAME
770	#undef PGM_BTH_NAME_RC_STR
771	#undef PGM_BTH_NAME_R0_STR
772	#undef PGM_GST_TYPE
773	#undef PGM_GST_NAME
774	#undef PGM_GST_NAME_RC_STR
775	#undef PGM_GST_NAME_R0_STR
776
777	/* Guest - 32-bit mode */
778	#define PGM_GST_TYPE PGM_TYPE_32BIT
779	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
780	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
781	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
782	#define PGM_BTH_NAME(name) PGM_BTH_NAME_32BIT_32BIT(name)
783	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_32BIT_32BIT_STR(name)
784	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_32BIT_32BIT_STR(name)
785	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_32BIT_PT_FOR_32BIT_PT
786	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_32BIT_PT_FOR_32BIT_4MB
787	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_32BIT_PD
788	#include "PGMBth.h"
789	#include "PGMGstDefs.h"
790	#include "PGMGst.h"
791	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
792	#undef BTH_PGMPOOLKIND_PT_FOR_PT
793	#undef BTH_PGMPOOLKIND_ROOT
794	#undef PGM_BTH_NAME
795	#undef PGM_BTH_NAME_RC_STR
796	#undef PGM_BTH_NAME_R0_STR
797	#undef PGM_GST_TYPE
798	#undef PGM_GST_NAME
799	#undef PGM_GST_NAME_RC_STR
800	#undef PGM_GST_NAME_R0_STR
801
802	#undef PGM_SHW_TYPE
803	#undef PGM_SHW_NAME
804	#undef PGM_SHW_NAME_RC_STR
805	#undef PGM_SHW_NAME_R0_STR
806
807
808	/*
809	* Shadow - PAE mode
810	*/
811	#define PGM_SHW_TYPE PGM_TYPE_PAE
812	#define PGM_SHW_NAME(name) PGM_SHW_NAME_PAE(name)
813	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_PAE_STR(name)
814	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_PAE_STR(name)
815	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
816	#include "PGMShw.h"
817
818	/* Guest - real mode */
819	#define PGM_GST_TYPE PGM_TYPE_REAL
820	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
821	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
822	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
823	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_REAL(name)
824	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_REAL_STR(name)
825	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_REAL_STR(name)
826	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
827	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
828	#include "PGMGstDefs.h"
829	#include "PGMBth.h"
830	#undef BTH_PGMPOOLKIND_PT_FOR_PT
831	#undef BTH_PGMPOOLKIND_ROOT
832	#undef PGM_BTH_NAME
833	#undef PGM_BTH_NAME_RC_STR
834	#undef PGM_BTH_NAME_R0_STR
835	#undef PGM_GST_TYPE
836	#undef PGM_GST_NAME
837	#undef PGM_GST_NAME_RC_STR
838	#undef PGM_GST_NAME_R0_STR
839
840	/* Guest - protected mode */
841	#define PGM_GST_TYPE PGM_TYPE_PROT
842	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
843	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
844	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
845	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PROT(name)
846	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PROT_STR(name)
847	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PROT_STR(name)
848	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
849	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_PHYS
850	#include "PGMGstDefs.h"
851	#include "PGMBth.h"
852	#undef BTH_PGMPOOLKIND_PT_FOR_PT
853	#undef BTH_PGMPOOLKIND_ROOT
854	#undef PGM_BTH_NAME
855	#undef PGM_BTH_NAME_RC_STR
856	#undef PGM_BTH_NAME_R0_STR
857	#undef PGM_GST_TYPE
858	#undef PGM_GST_NAME
859	#undef PGM_GST_NAME_RC_STR
860	#undef PGM_GST_NAME_R0_STR
861
862	/* Guest - 32-bit mode */
863	#define PGM_GST_TYPE PGM_TYPE_32BIT
864	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
865	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
866	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
867	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_32BIT(name)
868	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_32BIT_STR(name)
869	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_32BIT_STR(name)
870	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
871	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
872	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT_FOR_32BIT
873	#include "PGMGstDefs.h"
874	#include "PGMBth.h"
875	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
876	#undef BTH_PGMPOOLKIND_PT_FOR_PT
877	#undef BTH_PGMPOOLKIND_ROOT
878	#undef PGM_BTH_NAME
879	#undef PGM_BTH_NAME_RC_STR
880	#undef PGM_BTH_NAME_R0_STR
881	#undef PGM_GST_TYPE
882	#undef PGM_GST_NAME
883	#undef PGM_GST_NAME_RC_STR
884	#undef PGM_GST_NAME_R0_STR
885
886	/* Guest - PAE mode */
887	#define PGM_GST_TYPE PGM_TYPE_PAE
888	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
889	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
890	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
891	#define PGM_BTH_NAME(name) PGM_BTH_NAME_PAE_PAE(name)
892	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_PAE_PAE_STR(name)
893	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_PAE_PAE_STR(name)
894	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
895	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
896	#define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_PAE_PDPT
897	#include "PGMBth.h"
898	#include "PGMGstDefs.h"
899	#include "PGMGst.h"
900	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
901	#undef BTH_PGMPOOLKIND_PT_FOR_PT
902	#undef BTH_PGMPOOLKIND_ROOT
903	#undef PGM_BTH_NAME
904	#undef PGM_BTH_NAME_RC_STR
905	#undef PGM_BTH_NAME_R0_STR
906	#undef PGM_GST_TYPE
907	#undef PGM_GST_NAME
908	#undef PGM_GST_NAME_RC_STR
909	#undef PGM_GST_NAME_R0_STR
910
911	#undef PGM_SHW_TYPE
912	#undef PGM_SHW_NAME
913	#undef PGM_SHW_NAME_RC_STR
914	#undef PGM_SHW_NAME_R0_STR
915
916
917	/*
918	* Shadow - AMD64 mode
919	*/
920	#define PGM_SHW_TYPE PGM_TYPE_AMD64
921	#define PGM_SHW_NAME(name) PGM_SHW_NAME_AMD64(name)
922	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_AMD64_STR(name)
923	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_AMD64_STR(name)
924	#include "PGMShw.h"
925
926	#ifdef VBOX_WITH_64_BITS_GUESTS
927	/* Guest - AMD64 mode */
928	# define PGM_GST_TYPE PGM_TYPE_AMD64
929	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
930	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
931	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
932	# define PGM_BTH_NAME(name) PGM_BTH_NAME_AMD64_AMD64(name)
933	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_AMD64_AMD64_STR(name)
934	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_AMD64_AMD64_STR(name)
935	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
936	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
937	# define BTH_PGMPOOLKIND_ROOT PGMPOOLKIND_64BIT_PML4
938	# include "PGMBth.h"
939	# include "PGMGstDefs.h"
940	# include "PGMGst.h"
941	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
942	# undef BTH_PGMPOOLKIND_PT_FOR_PT
943	# undef BTH_PGMPOOLKIND_ROOT
944	# undef PGM_BTH_NAME
945	# undef PGM_BTH_NAME_RC_STR
946	# undef PGM_BTH_NAME_R0_STR
947	# undef PGM_GST_TYPE
948	# undef PGM_GST_NAME
949	# undef PGM_GST_NAME_RC_STR
950	# undef PGM_GST_NAME_R0_STR
951	#endif /* VBOX_WITH_64_BITS_GUESTS */
952
953	#undef PGM_SHW_TYPE
954	#undef PGM_SHW_NAME
955	#undef PGM_SHW_NAME_RC_STR
956	#undef PGM_SHW_NAME_R0_STR
957
958
959	/*
960	* Shadow - Nested paging mode
961	*/
962	#define PGM_SHW_TYPE PGM_TYPE_NESTED
963	#define PGM_SHW_NAME(name) PGM_SHW_NAME_NESTED(name)
964	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_NESTED_STR(name)
965	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_NESTED_STR(name)
966	#include "PGMShw.h"
967
968	/* Guest - real mode */
969	#define PGM_GST_TYPE PGM_TYPE_REAL
970	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
971	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
972	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
973	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_REAL(name)
974	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_REAL_STR(name)
975	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_REAL_STR(name)
976	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
977	#include "PGMGstDefs.h"
978	#include "PGMBth.h"
979	#undef BTH_PGMPOOLKIND_PT_FOR_PT
980	#undef PGM_BTH_NAME
981	#undef PGM_BTH_NAME_RC_STR
982	#undef PGM_BTH_NAME_R0_STR
983	#undef PGM_GST_TYPE
984	#undef PGM_GST_NAME
985	#undef PGM_GST_NAME_RC_STR
986	#undef PGM_GST_NAME_R0_STR
987
988	/* Guest - protected mode */
989	#define PGM_GST_TYPE PGM_TYPE_PROT
990	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
991	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
992	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
993	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PROT(name)
994	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PROT_STR(name)
995	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PROT_STR(name)
996	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
997	#include "PGMGstDefs.h"
998	#include "PGMBth.h"
999	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1000	#undef PGM_BTH_NAME
1001	#undef PGM_BTH_NAME_RC_STR
1002	#undef PGM_BTH_NAME_R0_STR
1003	#undef PGM_GST_TYPE
1004	#undef PGM_GST_NAME
1005	#undef PGM_GST_NAME_RC_STR
1006	#undef PGM_GST_NAME_R0_STR
1007
1008	/* Guest - 32-bit mode */
1009	#define PGM_GST_TYPE PGM_TYPE_32BIT
1010	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1011	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1012	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1013	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_32BIT(name)
1014	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_32BIT_STR(name)
1015	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_32BIT_STR(name)
1016	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1017	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1018	#include "PGMGstDefs.h"
1019	#include "PGMBth.h"
1020	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1021	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1022	#undef PGM_BTH_NAME
1023	#undef PGM_BTH_NAME_RC_STR
1024	#undef PGM_BTH_NAME_R0_STR
1025	#undef PGM_GST_TYPE
1026	#undef PGM_GST_NAME
1027	#undef PGM_GST_NAME_RC_STR
1028	#undef PGM_GST_NAME_R0_STR
1029
1030	/* Guest - PAE mode */
1031	#define PGM_GST_TYPE PGM_TYPE_PAE
1032	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1033	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1034	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1035	#define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_PAE(name)
1036	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_PAE_STR(name)
1037	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_PAE_STR(name)
1038	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1039	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1040	#include "PGMGstDefs.h"
1041	#include "PGMBth.h"
1042	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1043	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1044	#undef PGM_BTH_NAME
1045	#undef PGM_BTH_NAME_RC_STR
1046	#undef PGM_BTH_NAME_R0_STR
1047	#undef PGM_GST_TYPE
1048	#undef PGM_GST_NAME
1049	#undef PGM_GST_NAME_RC_STR
1050	#undef PGM_GST_NAME_R0_STR
1051
1052	#ifdef VBOX_WITH_64_BITS_GUESTS
1053	/* Guest - AMD64 mode */
1054	# define PGM_GST_TYPE PGM_TYPE_AMD64
1055	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1056	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1057	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1058	# define PGM_BTH_NAME(name) PGM_BTH_NAME_NESTED_AMD64(name)
1059	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_NESTED_AMD64_STR(name)
1060	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_NESTED_AMD64_STR(name)
1061	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1062	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1063	# include "PGMGstDefs.h"
1064	# include "PGMBth.h"
1065	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1066	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1067	# undef PGM_BTH_NAME
1068	# undef PGM_BTH_NAME_RC_STR
1069	# undef PGM_BTH_NAME_R0_STR
1070	# undef PGM_GST_TYPE
1071	# undef PGM_GST_NAME
1072	# undef PGM_GST_NAME_RC_STR
1073	# undef PGM_GST_NAME_R0_STR
1074	#endif /* VBOX_WITH_64_BITS_GUESTS */
1075
1076	#undef PGM_SHW_TYPE
1077	#undef PGM_SHW_NAME
1078	#undef PGM_SHW_NAME_RC_STR
1079	#undef PGM_SHW_NAME_R0_STR
1080
1081
1082	/*
1083	* Shadow - EPT
1084	*/
1085	#define PGM_SHW_TYPE PGM_TYPE_EPT
1086	#define PGM_SHW_NAME(name) PGM_SHW_NAME_EPT(name)
1087	#define PGM_SHW_NAME_RC_STR(name) PGM_SHW_NAME_RC_EPT_STR(name)
1088	#define PGM_SHW_NAME_R0_STR(name) PGM_SHW_NAME_R0_EPT_STR(name)
1089	#include "PGMShw.h"
1090
1091	/* Guest - real mode */
1092	#define PGM_GST_TYPE PGM_TYPE_REAL
1093	#define PGM_GST_NAME(name) PGM_GST_NAME_REAL(name)
1094	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_REAL_STR(name)
1095	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_REAL_STR(name)
1096	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_REAL(name)
1097	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_REAL_STR(name)
1098	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_REAL_STR(name)
1099	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1100	#include "PGMGstDefs.h"
1101	#include "PGMBth.h"
1102	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1103	#undef PGM_BTH_NAME
1104	#undef PGM_BTH_NAME_RC_STR
1105	#undef PGM_BTH_NAME_R0_STR
1106	#undef PGM_GST_TYPE
1107	#undef PGM_GST_NAME
1108	#undef PGM_GST_NAME_RC_STR
1109	#undef PGM_GST_NAME_R0_STR
1110
1111	/* Guest - protected mode */
1112	#define PGM_GST_TYPE PGM_TYPE_PROT
1113	#define PGM_GST_NAME(name) PGM_GST_NAME_PROT(name)
1114	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PROT_STR(name)
1115	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PROT_STR(name)
1116	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PROT(name)
1117	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PROT_STR(name)
1118	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PROT_STR(name)
1119	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PHYS
1120	#include "PGMGstDefs.h"
1121	#include "PGMBth.h"
1122	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1123	#undef PGM_BTH_NAME
1124	#undef PGM_BTH_NAME_RC_STR
1125	#undef PGM_BTH_NAME_R0_STR
1126	#undef PGM_GST_TYPE
1127	#undef PGM_GST_NAME
1128	#undef PGM_GST_NAME_RC_STR
1129	#undef PGM_GST_NAME_R0_STR
1130
1131	/* Guest - 32-bit mode */
1132	#define PGM_GST_TYPE PGM_TYPE_32BIT
1133	#define PGM_GST_NAME(name) PGM_GST_NAME_32BIT(name)
1134	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_32BIT_STR(name)
1135	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_32BIT_STR(name)
1136	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_32BIT(name)
1137	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_32BIT_STR(name)
1138	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_32BIT_STR(name)
1139	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_32BIT_PT
1140	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_32BIT_4MB
1141	#include "PGMGstDefs.h"
1142	#include "PGMBth.h"
1143	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1144	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1145	#undef PGM_BTH_NAME
1146	#undef PGM_BTH_NAME_RC_STR
1147	#undef PGM_BTH_NAME_R0_STR
1148	#undef PGM_GST_TYPE
1149	#undef PGM_GST_NAME
1150	#undef PGM_GST_NAME_RC_STR
1151	#undef PGM_GST_NAME_R0_STR
1152
1153	/* Guest - PAE mode */
1154	#define PGM_GST_TYPE PGM_TYPE_PAE
1155	#define PGM_GST_NAME(name) PGM_GST_NAME_PAE(name)
1156	#define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_PAE_STR(name)
1157	#define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_PAE_STR(name)
1158	#define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_PAE(name)
1159	#define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_PAE_STR(name)
1160	#define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_PAE_STR(name)
1161	#define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1162	#define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1163	#include "PGMGstDefs.h"
1164	#include "PGMBth.h"
1165	#undef BTH_PGMPOOLKIND_PT_FOR_BIG
1166	#undef BTH_PGMPOOLKIND_PT_FOR_PT
1167	#undef PGM_BTH_NAME
1168	#undef PGM_BTH_NAME_RC_STR
1169	#undef PGM_BTH_NAME_R0_STR
1170	#undef PGM_GST_TYPE
1171	#undef PGM_GST_NAME
1172	#undef PGM_GST_NAME_RC_STR
1173	#undef PGM_GST_NAME_R0_STR
1174
1175	#ifdef VBOX_WITH_64_BITS_GUESTS
1176	/* Guest - AMD64 mode */
1177	# define PGM_GST_TYPE PGM_TYPE_AMD64
1178	# define PGM_GST_NAME(name) PGM_GST_NAME_AMD64(name)
1179	# define PGM_GST_NAME_RC_STR(name) PGM_GST_NAME_RC_AMD64_STR(name)
1180	# define PGM_GST_NAME_R0_STR(name) PGM_GST_NAME_R0_AMD64_STR(name)
1181	# define PGM_BTH_NAME(name) PGM_BTH_NAME_EPT_AMD64(name)
1182	# define PGM_BTH_NAME_RC_STR(name) PGM_BTH_NAME_RC_EPT_AMD64_STR(name)
1183	# define PGM_BTH_NAME_R0_STR(name) PGM_BTH_NAME_R0_EPT_AMD64_STR(name)
1184	# define BTH_PGMPOOLKIND_PT_FOR_PT PGMPOOLKIND_PAE_PT_FOR_PAE_PT
1185	# define BTH_PGMPOOLKIND_PT_FOR_BIG PGMPOOLKIND_PAE_PT_FOR_PAE_2MB
1186	# include "PGMGstDefs.h"
1187	# include "PGMBth.h"
1188	# undef BTH_PGMPOOLKIND_PT_FOR_BIG
1189	# undef BTH_PGMPOOLKIND_PT_FOR_PT
1190	# undef PGM_BTH_NAME
1191	# undef PGM_BTH_NAME_RC_STR
1192	# undef PGM_BTH_NAME_R0_STR
1193	# undef PGM_GST_TYPE
1194	# undef PGM_GST_NAME
1195	# undef PGM_GST_NAME_RC_STR
1196	# undef PGM_GST_NAME_R0_STR
1197	#endif /* VBOX_WITH_64_BITS_GUESTS */
1198
1199	#undef PGM_SHW_TYPE
1200	#undef PGM_SHW_NAME
1201	#undef PGM_SHW_NAME_RC_STR
1202	#undef PGM_SHW_NAME_R0_STR
1203
1204
1205
1206	/**
1207	* Initiates the paging of VM.
1208	*
1209	* @returns VBox status code.
1210	* @param pVM Pointer to VM structure.
1211	*/
1212	VMMR3DECL(int) PGMR3Init(PVM pVM)
1213	{
1214	LogFlow(("PGMR3Init:\n"));
1215	PCFGMNODE pCfgPGM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "/PGM");
1216	int rc;
1217
1218	/*
1219	* Assert alignment and sizes.
1220	*/
1221	AssertCompile(sizeof(pVM->pgm.s) <= sizeof(pVM->pgm.padding));
1222	AssertCompile(sizeof(pVM->aCpus[0].pgm.s) <= sizeof(pVM->aCpus[0].pgm.padding));
1223	AssertCompileMemberAlignment(PGM, CritSectX, sizeof(uintptr_t));
1224
1225	/*
1226	* Init the structure.
1227	*/
1228	pVM->pgm.s.offVM = RT_OFFSETOF(VM, pgm.s);
1229	pVM->pgm.s.offVCpuPGM = RT_OFFSETOF(VMCPU, pgm.s);
1230
1231	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aHandyPages); i++)
1232	{
1233	pVM->pgm.s.aHandyPages[i].HCPhysGCPhys = NIL_RTHCPHYS;
1234	pVM->pgm.s.aHandyPages[i].idPage = NIL_GMM_PAGEID;
1235	pVM->pgm.s.aHandyPages[i].idSharedPage = NIL_GMM_PAGEID;
1236	}
1237
1238	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.aLargeHandyPage); i++)
1239	{
1240	pVM->pgm.s.aLargeHandyPage[i].HCPhysGCPhys = NIL_RTHCPHYS;
1241	pVM->pgm.s.aLargeHandyPage[i].idPage = NIL_GMM_PAGEID;
1242	pVM->pgm.s.aLargeHandyPage[i].idSharedPage = NIL_GMM_PAGEID;
1243	}
1244
1245	/* Init the per-CPU part. */
1246	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1247	{
1248	PVMCPU pVCpu = &pVM->aCpus[idCpu];
1249	PPGMCPU pPGM = &pVCpu->pgm.s;
1250
1251	pPGM->offVM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)pVM;
1252	pPGM->offVCpu = RT_OFFSETOF(VMCPU, pgm.s);
1253	pPGM->offPGM = (uintptr_t)&pVCpu->pgm.s - (uintptr_t)&pVM->pgm.s;
1254
1255	pPGM->enmShadowMode = PGMMODE_INVALID;
1256	pPGM->enmGuestMode = PGMMODE_INVALID;
1257
1258	pPGM->GCPhysCR3 = NIL_RTGCPHYS;
1259
1260	pPGM->pGst32BitPdR3 = NULL;
1261	pPGM->pGstPaePdptR3 = NULL;
1262	pPGM->pGstAmd64Pml4R3 = NULL;
1263	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1264	pPGM->pGst32BitPdR0 = NIL_RTR0PTR;
1265	pPGM->pGstPaePdptR0 = NIL_RTR0PTR;
1266	pPGM->pGstAmd64Pml4R0 = NIL_RTR0PTR;
1267	#endif
1268	pPGM->pGst32BitPdRC = NIL_RTRCPTR;
1269	pPGM->pGstPaePdptRC = NIL_RTRCPTR;
1270	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->pgm.s.apGstPaePDsR3); i++)
1271	{
1272	pPGM->apGstPaePDsR3[i] = NULL;
1273	#ifndef VBOX_WITH_2X_4GB_ADDR_SPACE
1274	pPGM->apGstPaePDsR0[i] = NIL_RTR0PTR;
1275	#endif
1276	pPGM->apGstPaePDsRC[i] = NIL_RTRCPTR;
1277	pPGM->aGCPhysGstPaePDs[i] = NIL_RTGCPHYS;
1278	pPGM->aGstPaePdpeRegs[i].u = UINT64_MAX;
1279	pPGM->aGCPhysGstPaePDsMonitored[i] = NIL_RTGCPHYS;
1280	}
1281
1282	pPGM->fA20Enabled = true;
1283	pPGM->GCPhysA20Mask = ~((RTGCPHYS)!pPGM->fA20Enabled << 20);
1284	}
1285
1286	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1287	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1; /* default; checked later */
1288	pVM->pgm.s.GCPtrPrevRamRangeMapping = MM_HYPER_AREA_ADDRESS;
1289
1290	rc = CFGMR3QueryBoolDef(CFGMR3GetRoot(pVM), "RamPreAlloc", &pVM->pgm.s.fRamPreAlloc,
1291	#ifdef VBOX_WITH_PREALLOC_RAM_BY_DEFAULT
1292	true
1293	#else
1294	false
1295	#endif
1296	);
1297	AssertLogRelRCReturn(rc, rc);
1298
1299	#if HC_ARCH_BITS == 32
1300	# ifdef RT_OS_DARWIN
1301	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE * 3);
1302	# else
1303	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, _1G / GMM_CHUNK_SIZE);
1304	# endif
1305	#else
1306	rc = CFGMR3QueryU32Def(pCfgPGM, "MaxRing3Chunks", &pVM->pgm.s.ChunkR3Map.cMax, UINT32_MAX);
1307	#endif
1308	AssertLogRelRCReturn(rc, rc);
1309	for (uint32_t i = 0; i < RT_ELEMENTS(pVM->pgm.s.ChunkR3Map.Tlb.aEntries); i++)
1310	pVM->pgm.s.ChunkR3Map.Tlb.aEntries[i].idChunk = NIL_GMM_CHUNKID;
1311
1312	/*
1313	* Get the configured RAM size - to estimate saved state size.
1314	*/
1315	uint64_t cbRam;
1316	rc = CFGMR3QueryU64(CFGMR3GetRoot(pVM), "RamSize", &cbRam);
1317	if (rc == VERR_CFGM_VALUE_NOT_FOUND)
1318	cbRam = 0;
1319	else if (RT_SUCCESS(rc))
1320	{
1321	if (cbRam < PAGE_SIZE)
1322	cbRam = 0;
1323	cbRam = RT_ALIGN_64(cbRam, PAGE_SIZE);
1324	}
1325	else
1326	{
1327	AssertMsgFailed(("Configuration error: Failed to query integer \"RamSize\", rc=%Rrc.\n", rc));
1328	return rc;
1329	}
1330
1331	/*
1332	* Check for PCI pass-through.
1333	*/
1334	rc = CFGMR3QueryBoolDef(pCfgPGM, "PciPassThrough", &pVM->pgm.s.fPciPassthrough, false);
1335	AssertMsgRCReturn(rc, ("Configuration error: Failed to query integer \"PciPassThrough\", rc=%Rrc.\n", rc), rc);
1336	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough \|\| pVM->pgm.s.fRamPreAlloc, VERR_INVALID_PARAMETER);
1337
1338	#ifdef VBOX_WITH_STATISTICS
1339	/*
1340	* Allocate memory for the statistics before someone tries to use them.
1341	*/
1342	size_t cbTotalStats = RT_ALIGN_Z(sizeof(PGMSTATS), 64) + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64) * pVM->cCpus;
1343	void *pv;
1344	rc = MMHyperAlloc(pVM, RT_ALIGN_Z(cbTotalStats, PAGE_SIZE), PAGE_SIZE, MM_TAG_PGM, &pv);
1345	AssertRCReturn(rc, rc);
1346
1347	pVM->pgm.s.pStatsR3 = (PGMSTATS *)pv;
1348	pVM->pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1349	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1350	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMSTATS), 64);
1351
1352	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1353	{
1354	pVM->aCpus[iCpu].pgm.s.pStatsR3 = (PGMCPUSTATS *)pv;
1355	pVM->aCpus[iCpu].pgm.s.pStatsR0 = MMHyperCCToR0(pVM, pv);
1356	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pv);
1357
1358	pv = (uint8_t *)pv + RT_ALIGN_Z(sizeof(PGMCPUSTATS), 64);
1359	}
1360	#endif /* VBOX_WITH_STATISTICS */
1361
1362	/*
1363	* Register callbacks, string formatters and the saved state data unit.
1364	*/
1365	#ifdef VBOX_STRICT
1366	VMR3AtStateRegister(pVM->pUVM, pgmR3ResetNoMorePhysWritesFlag, NULL);
1367	#endif
1368	PGMRegisterStringFormatTypes();
1369
1370	rc = pgmR3InitSavedState(pVM, cbRam);
1371	if (RT_FAILURE(rc))
1372	return rc;
1373
1374	/*
1375	* Initialize the PGM critical section and flush the phys TLBs
1376	*/
1377	rc = PDMR3CritSectInit(pVM, &pVM->pgm.s.CritSectX, RT_SRC_POS, "PGM");
1378	AssertRCReturn(rc, rc);
1379
1380	PGMR3PhysChunkInvalidateTLB(pVM);
1381	pgmPhysInvalidatePageMapTLB(pVM);
1382
1383	/*
1384	* For the time being we sport a full set of handy pages in addition to the base
1385	* memory to simplify things.
1386	*/
1387	rc = MMR3ReserveHandyPages(pVM, RT_ELEMENTS(pVM->pgm.s.aHandyPages)); /** @todo this should be changed to PGM_HANDY_PAGES_MIN but this needs proper testing... */
1388	AssertRCReturn(rc, rc);
1389
1390	/*
1391	* Trees
1392	*/
1393	rc = MMHyperAlloc(pVM, sizeof(PGMTREES), 0, MM_TAG_PGM, (void **)&pVM->pgm.s.pTreesR3);
1394	if (RT_SUCCESS(rc))
1395	{
1396	pVM->pgm.s.pTreesR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pTreesR3);
1397	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
1398
1399	/*
1400	* Allocate the zero page.
1401	*/
1402	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvZeroPgR3);
1403	}
1404	if (RT_SUCCESS(rc))
1405	{
1406	pVM->pgm.s.pvZeroPgRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pvZeroPgR3);
1407	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
1408	pVM->pgm.s.HCPhysZeroPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvZeroPgR3);
1409	AssertRelease(pVM->pgm.s.HCPhysZeroPg != NIL_RTHCPHYS);
1410
1411	/*
1412	* Allocate the invalid MMIO page.
1413	* (The invalid bits in HCPhysInvMmioPg are set later on init complete.)
1414	*/
1415	rc = MMHyperAlloc(pVM, PAGE_SIZE, PAGE_SIZE, MM_TAG_PGM, &pVM->pgm.s.pvMmioPgR3);
1416	}
1417	if (RT_SUCCESS(rc))
1418	{
1419	ASMMemFill32(pVM->pgm.s.pvMmioPgR3, PAGE_SIZE, 0xfeedface);
1420	pVM->pgm.s.HCPhysMmioPg = MMR3HyperHCVirt2HCPhys(pVM, pVM->pgm.s.pvMmioPgR3);
1421	AssertRelease(pVM->pgm.s.HCPhysMmioPg != NIL_RTHCPHYS);
1422	pVM->pgm.s.HCPhysInvMmioPg = pVM->pgm.s.HCPhysMmioPg;
1423
1424	/*
1425	* Init the paging.
1426	*/
1427	rc = pgmR3InitPaging(pVM);
1428	}
1429	if (RT_SUCCESS(rc))
1430	{
1431	/*
1432	* Init the page pool.
1433	*/
1434	rc = pgmR3PoolInit(pVM);
1435	}
1436	if (RT_SUCCESS(rc))
1437	{
1438	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1439	{
1440	PVMCPU pVCpu = &pVM->aCpus[i];
1441	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1442	if (RT_FAILURE(rc))
1443	break;
1444	}
1445	}
1446
1447	if (RT_SUCCESS(rc))
1448	{
1449	/*
1450	* Info & statistics
1451	*/
1452	DBGFR3InfoRegisterInternal(pVM, "mode",
1453	"Shows the current paging mode. "
1454	"Recognizes 'all', 'guest', 'shadow' and 'host' as arguments, defaulting to 'all' if nothing is given.",
1455	pgmR3InfoMode);
1456	DBGFR3InfoRegisterInternal(pVM, "pgmcr3",
1457	"Dumps all the entries in the top level paging table. No arguments.",
1458	pgmR3InfoCr3);
1459	DBGFR3InfoRegisterInternal(pVM, "phys",
1460	"Dumps all the physical address ranges. No arguments.",
1461	pgmR3PhysInfo);
1462	DBGFR3InfoRegisterInternal(pVM, "handlers",
1463	"Dumps physical, virtual and hyper virtual handlers. "
1464	"Pass 'phys', 'virt', 'hyper' as argument if only one kind is wanted."
1465	"Add 'nost' if the statistics are unwanted, use together with 'all' or explicit selection.",
1466	pgmR3InfoHandlers);
1467	DBGFR3InfoRegisterInternal(pVM, "mappings",
1468	"Dumps guest mappings.",
1469	pgmR3MapInfo);
1470
1471	pgmR3InitStats(pVM);
1472
1473	#ifdef VBOX_WITH_DEBUGGER
1474	/*
1475	* Debugger commands.
1476	*/
1477	static bool s_fRegisteredCmds = false;
1478	if (!s_fRegisteredCmds)
1479	{
1480	int rc2 = DBGCRegisterCommands(&g_aCmds[0], RT_ELEMENTS(g_aCmds));
1481	if (RT_SUCCESS(rc2))
1482	s_fRegisteredCmds = true;
1483	}
1484	#endif
1485	return VINF_SUCCESS;
1486	}
1487
1488	/* Almost no cleanup necessary, MM frees all memory. */
1489	PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
1490
1491	return rc;
1492	}
1493
1494
1495	/**
1496	* Init paging.
1497	*
1498	* Since we need to check what mode the host is operating in before we can choose
1499	* the right paging functions for the host we have to delay this until R0 has
1500	* been initialized.
1501	*
1502	* @returns VBox status code.
1503	* @param pVM Pointer to the VM.
1504	*/
1505	static int pgmR3InitPaging(PVM pVM)
1506	{
1507	/*
1508	* Force a recalculation of modes and switcher so everyone gets notified.
1509	*/
1510	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1511	{
1512	PVMCPU pVCpu = &pVM->aCpus[i];
1513
1514	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
1515	pVCpu->pgm.s.enmGuestMode = PGMMODE_INVALID;
1516	}
1517
1518	pVM->pgm.s.enmHostMode = SUPPAGINGMODE_INVALID;
1519
1520	/*
1521	* Allocate static mapping space for whatever the cr3 register
1522	* points to and in the case of PAE mode to the 4 PDs.
1523	*/
1524	int rc = MMR3HyperReserve(pVM, PAGE_SIZE * 5, "CR3 mapping", &pVM->pgm.s.GCPtrCR3Mapping);
1525	if (RT_FAILURE(rc))
1526	{
1527	AssertMsgFailed(("Failed to reserve two pages for cr mapping in HMA, rc=%Rrc\n", rc));
1528	return rc;
1529	}
1530	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
1531
1532	/*
1533	* Allocate pages for the three possible intermediate contexts
1534	* (AMD64, PAE and plain 32-Bit). We maintain all three contexts
1535	* for the sake of simplicity. The AMD64 uses the PAE for the
1536	* lower levels, making the total number of pages 11 (3 + 7 + 1).
1537	*
1538	* We assume that two page tables will be enought for the core code
1539	* mappings (HC virtual and identity).
1540	*/
1541	pVM->pgm.s.pInterPD = (PX86PD)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPD, VERR_NO_PAGE_MEMORY);
1542	pVM->pgm.s.apInterPTs[0] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[0], VERR_NO_PAGE_MEMORY);
1543	pVM->pgm.s.apInterPTs[1] = (PX86PT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.apInterPTs[1], VERR_NO_PAGE_MEMORY);
1544	pVM->pgm.s.apInterPaePTs[0] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[0], VERR_NO_PAGE_MEMORY);
1545	pVM->pgm.s.apInterPaePTs[1] = (PX86PTPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePTs[1], VERR_NO_PAGE_MEMORY);
1546	pVM->pgm.s.apInterPaePDs[0] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[0], VERR_NO_PAGE_MEMORY);
1547	pVM->pgm.s.apInterPaePDs[1] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[1], VERR_NO_PAGE_MEMORY);
1548	pVM->pgm.s.apInterPaePDs[2] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[2], VERR_NO_PAGE_MEMORY);
1549	pVM->pgm.s.apInterPaePDs[3] = (PX86PDPAE)MMR3PageAlloc(pVM); AssertReturn(pVM->pgm.s.apInterPaePDs[3], VERR_NO_PAGE_MEMORY);
1550	pVM->pgm.s.pInterPaePDPT = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT, VERR_NO_PAGE_MEMORY);
1551	pVM->pgm.s.pInterPaePDPT64 = (PX86PDPT)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePDPT64, VERR_NO_PAGE_MEMORY);
1552	pVM->pgm.s.pInterPaePML4 = (PX86PML4)MMR3PageAllocLow(pVM); AssertReturn(pVM->pgm.s.pInterPaePML4, VERR_NO_PAGE_MEMORY);
1553
1554	pVM->pgm.s.HCPhysInterPD = MMPage2Phys(pVM, pVM->pgm.s.pInterPD);
1555	AssertRelease(pVM->pgm.s.HCPhysInterPD != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPD & PAGE_OFFSET_MASK));
1556	pVM->pgm.s.HCPhysInterPaePDPT = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT);
1557	AssertRelease(pVM->pgm.s.HCPhysInterPaePDPT != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePDPT & PAGE_OFFSET_MASK));
1558	pVM->pgm.s.HCPhysInterPaePML4 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePML4);
1559	AssertRelease(pVM->pgm.s.HCPhysInterPaePML4 != NIL_RTHCPHYS && !(pVM->pgm.s.HCPhysInterPaePML4 & PAGE_OFFSET_MASK) && pVM->pgm.s.HCPhysInterPaePML4 < 0xffffffff);
1560
1561	/*
1562	* Initialize the pages, setting up the PML4 and PDPT for repetitive 4GB action.
1563	*/
1564	ASMMemZeroPage(pVM->pgm.s.pInterPD);
1565	ASMMemZeroPage(pVM->pgm.s.apInterPTs[0]);
1566	ASMMemZeroPage(pVM->pgm.s.apInterPTs[1]);
1567
1568	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[0]);
1569	ASMMemZeroPage(pVM->pgm.s.apInterPaePTs[1]);
1570
1571	ASMMemZeroPage(pVM->pgm.s.pInterPaePDPT);
1572	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.apInterPaePDs); i++)
1573	{
1574	ASMMemZeroPage(pVM->pgm.s.apInterPaePDs[i]);
1575	pVM->pgm.s.pInterPaePDPT->a[i].u = X86_PDPE_P \| PGM_PLXFLAGS_PERMANENT
1576	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[i]);
1577	}
1578
1579	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePDPT64->a); i++)
1580	{
1581	const unsigned iPD = i % RT_ELEMENTS(pVM->pgm.s.apInterPaePDs);
1582	pVM->pgm.s.pInterPaePDPT64->a[i].u = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A \| PGM_PLXFLAGS_PERMANENT
1583	\| MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[iPD]);
1584	}
1585
1586	RTHCPHYS HCPhysInterPaePDPT64 = MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64);
1587	for (unsigned i = 0; i < RT_ELEMENTS(pVM->pgm.s.pInterPaePML4->a); i++)
1588	pVM->pgm.s.pInterPaePML4->a[i].u = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A \| PGM_PLXFLAGS_PERMANENT
1589	\| HCPhysInterPaePDPT64;
1590
1591	/*
1592	* Initialize paging workers and mode from current host mode
1593	* and the guest running in real mode.
1594	*/
1595	pVM->pgm.s.enmHostMode = SUPR3GetPagingMode();
1596	switch (pVM->pgm.s.enmHostMode)
1597	{
1598	case SUPPAGINGMODE_32_BIT:
1599	case SUPPAGINGMODE_32_BIT_GLOBAL:
1600	case SUPPAGINGMODE_PAE:
1601	case SUPPAGINGMODE_PAE_GLOBAL:
1602	case SUPPAGINGMODE_PAE_NX:
1603	case SUPPAGINGMODE_PAE_GLOBAL_NX:
1604	break;
1605
1606	case SUPPAGINGMODE_AMD64:
1607	case SUPPAGINGMODE_AMD64_GLOBAL:
1608	case SUPPAGINGMODE_AMD64_NX:
1609	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
1610	#ifndef VBOX_WITH_HYBRID_32BIT_KERNEL
1611	if (ARCH_BITS != 64)
1612	{
1613	AssertMsgFailed(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1614	LogRel(("Host mode %d (64-bit) is not supported by non-64bit builds\n", pVM->pgm.s.enmHostMode));
1615	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1616	}
1617	#endif
1618	break;
1619	default:
1620	AssertMsgFailed(("Host mode %d is not supported\n", pVM->pgm.s.enmHostMode));
1621	return VERR_PGM_UNSUPPORTED_HOST_PAGING_MODE;
1622	}
1623	rc = pgmR3ModeDataInit(pVM, false /* don't resolve GC and R0 syms yet */);
1624	if (RT_SUCCESS(rc))
1625	{
1626	LogFlow(("pgmR3InitPaging: returns successfully\n"));
1627	#if HC_ARCH_BITS == 64
1628	LogRel(("Debug: HCPhysInterPD=%RHp HCPhysInterPaePDPT=%RHp HCPhysInterPaePML4=%RHp\n",
1629	pVM->pgm.s.HCPhysInterPD, pVM->pgm.s.HCPhysInterPaePDPT, pVM->pgm.s.HCPhysInterPaePML4));
1630	LogRel(("Debug: apInterPTs={%RHp,%RHp} apInterPaePTs={%RHp,%RHp} apInterPaePDs={%RHp,%RHp,%RHp,%RHp} pInterPaePDPT64=%RHp\n",
1631	MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPTs[1]),
1632	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePTs[1]),
1633	MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[0]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[1]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[2]), MMPage2Phys(pVM, pVM->pgm.s.apInterPaePDs[3]),
1634	MMPage2Phys(pVM, pVM->pgm.s.pInterPaePDPT64)));
1635	#endif
1636
1637	/*
1638	* Log the host paging mode. It may come in handy.
1639	*/
1640	const char *pszHostMode;
1641	switch (pVM->pgm.s.enmHostMode)
1642	{
1643	case SUPPAGINGMODE_32_BIT: pszHostMode = "32-bit"; break;
1644	case SUPPAGINGMODE_32_BIT_GLOBAL: pszHostMode = "32-bit+PGE"; break;
1645	case SUPPAGINGMODE_PAE: pszHostMode = "PAE"; break;
1646	case SUPPAGINGMODE_PAE_GLOBAL: pszHostMode = "PAE+PGE"; break;
1647	case SUPPAGINGMODE_PAE_NX: pszHostMode = "PAE+NXE"; break;
1648	case SUPPAGINGMODE_PAE_GLOBAL_NX: pszHostMode = "PAE+PGE+NXE"; break;
1649	case SUPPAGINGMODE_AMD64: pszHostMode = "AMD64"; break;
1650	case SUPPAGINGMODE_AMD64_GLOBAL: pszHostMode = "AMD64+PGE"; break;
1651	case SUPPAGINGMODE_AMD64_NX: pszHostMode = "AMD64+NX"; break;
1652	case SUPPAGINGMODE_AMD64_GLOBAL_NX: pszHostMode = "AMD64+PGE+NX"; break;
1653	default: pszHostMode = "???"; break;
1654	}
1655	LogRel(("Host paging mode: %s\n", pszHostMode));
1656
1657	return VINF_SUCCESS;
1658	}
1659
1660	LogFlow(("pgmR3InitPaging: returns %Rrc\n", rc));
1661	return rc;
1662	}
1663
1664
1665	/**
1666	* Init statistics
1667	* @returns VBox status code.
1668	*/
1669	static int pgmR3InitStats(PVM pVM)
1670	{
1671	PPGM pPGM = &pVM->pgm.s;
1672	int rc;
1673
1674	/*
1675	* Release statistics.
1676	*/
1677	/* Common - misc variables */
1678	STAM_REL_REG(pVM, &pPGM->cAllPages, STAMTYPE_U32, "/PGM/Page/cAllPages", STAMUNIT_COUNT, "The total number of pages.");
1679	STAM_REL_REG(pVM, &pPGM->cPrivatePages, STAMTYPE_U32, "/PGM/Page/cPrivatePages", STAMUNIT_COUNT, "The number of private pages.");
1680	STAM_REL_REG(pVM, &pPGM->cSharedPages, STAMTYPE_U32, "/PGM/Page/cSharedPages", STAMUNIT_COUNT, "The number of shared pages.");
1681	STAM_REL_REG(pVM, &pPGM->cReusedSharedPages, STAMTYPE_U32, "/PGM/Page/cReusedSharedPages", STAMUNIT_COUNT, "The number of reused shared pages.");
1682	STAM_REL_REG(pVM, &pPGM->cZeroPages, STAMTYPE_U32, "/PGM/Page/cZeroPages", STAMUNIT_COUNT, "The number of zero backed pages.");
1683	STAM_REL_REG(pVM, &pPGM->cPureMmioPages, STAMTYPE_U32, "/PGM/Page/cPureMmioPages", STAMUNIT_COUNT, "The number of pure MMIO pages.");
1684	STAM_REL_REG(pVM, &pPGM->cMonitoredPages, STAMTYPE_U32, "/PGM/Page/cMonitoredPages", STAMUNIT_COUNT, "The number of write monitored pages.");
1685	STAM_REL_REG(pVM, &pPGM->cWrittenToPages, STAMTYPE_U32, "/PGM/Page/cWrittenToPages", STAMUNIT_COUNT, "The number of previously write monitored pages that have been written to.");
1686	STAM_REL_REG(pVM, &pPGM->cWriteLockedPages, STAMTYPE_U32, "/PGM/Page/cWriteLockedPages", STAMUNIT_COUNT, "The number of write(/read) locked pages.");
1687	STAM_REL_REG(pVM, &pPGM->cReadLockedPages, STAMTYPE_U32, "/PGM/Page/cReadLockedPages", STAMUNIT_COUNT, "The number of read (only) locked pages.");
1688	STAM_REL_REG(pVM, &pPGM->cBalloonedPages, STAMTYPE_U32, "/PGM/Page/cBalloonedPages", STAMUNIT_COUNT, "The number of ballooned pages.");
1689	STAM_REL_REG(pVM, &pPGM->cHandyPages, STAMTYPE_U32, "/PGM/Page/cHandyPages", STAMUNIT_COUNT, "The number of handy pages (not included in cAllPages).");
1690	STAM_REL_REG(pVM, &pPGM->cLargePages, STAMTYPE_U32, "/PGM/Page/cLargePages", STAMUNIT_COUNT, "The number of large pages allocated (includes disabled).");
1691	STAM_REL_REG(pVM, &pPGM->cLargePagesDisabled, STAMTYPE_U32, "/PGM/Page/cLargePagesDisabled", STAMUNIT_COUNT, "The number of disabled large pages.");
1692	STAM_REL_REG(pVM, &pPGM->cRelocations, STAMTYPE_COUNTER, "/PGM/cRelocations", STAMUNIT_OCCURENCES,"Number of hypervisor relocations.");
1693	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.c, STAMTYPE_U32, "/PGM/ChunkR3Map/c", STAMUNIT_COUNT, "Number of mapped chunks.");
1694	STAM_REL_REG(pVM, &pPGM->ChunkR3Map.cMax, STAMTYPE_U32, "/PGM/ChunkR3Map/cMax", STAMUNIT_COUNT, "Maximum number of mapped chunks.");
1695	STAM_REL_REG(pVM, &pPGM->cMappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Mapped", STAMUNIT_COUNT, "Number of times we mapped a chunk.");
1696	STAM_REL_REG(pVM, &pPGM->cUnmappedChunks, STAMTYPE_U32, "/PGM/ChunkR3Map/Unmapped", STAMUNIT_COUNT, "Number of times we unmapped a chunk.");
1697
1698	STAM_REL_REG(pVM, &pPGM->StatLargePageReused, STAMTYPE_COUNTER, "/PGM/LargePage/Reused", STAMUNIT_OCCURENCES, "The number of times we've reused a large page.");
1699	STAM_REL_REG(pVM, &pPGM->StatLargePageRefused, STAMTYPE_COUNTER, "/PGM/LargePage/Refused", STAMUNIT_OCCURENCES, "The number of times we couldn't use a large page.");
1700	STAM_REL_REG(pVM, &pPGM->StatLargePageRecheck, STAMTYPE_COUNTER, "/PGM/LargePage/Recheck", STAMUNIT_OCCURENCES, "The number of times we've rechecked a disabled large page.");
1701
1702	STAM_REL_REG(pVM, &pPGM->StatShModCheck, STAMTYPE_PROFILE, "/PGM/ShMod/Check", STAMUNIT_TICKS_PER_CALL, "Profiles the shared module checking.");
1703
1704	/* Live save */
1705	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.fActive, STAMTYPE_U8, "/PGM/LiveSave/fActive", STAMUNIT_COUNT, "Active or not.");
1706	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cIgnoredPages, STAMTYPE_U32, "/PGM/LiveSave/cIgnoredPages", STAMUNIT_COUNT, "The number of ignored pages in the RAM ranges (i.e. MMIO, MMIO2 and ROM).");
1707	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesLong, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesLong", STAMUNIT_COUNT, "Longer term dirty page average.");
1708	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cDirtyPagesShort, STAMTYPE_U32, "/PGM/LiveSave/cDirtyPagesShort", STAMUNIT_COUNT, "Short term dirty page average.");
1709	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cPagesPerSecond, STAMTYPE_U32, "/PGM/LiveSave/cPagesPerSecond", STAMUNIT_COUNT, "Pages per second.");
1710	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.cSavedPages, STAMTYPE_U64, "/PGM/LiveSave/cSavedPages", STAMUNIT_COUNT, "The total number of saved pages.");
1711	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cReadPages", STAMUNIT_COUNT, "RAM: Ready pages.");
1712	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cDirtyPages", STAMUNIT_COUNT, "RAM: Dirty pages.");
1713	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cZeroPages", STAMUNIT_COUNT, "RAM: Ready zero pages.");
1714	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Ram.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Ram/cMonitoredPages", STAMUNIT_COUNT, "RAM: Write monitored pages.");
1715	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cReadPages", STAMUNIT_COUNT, "ROM: Ready pages.");
1716	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cDirtyPages", STAMUNIT_COUNT, "ROM: Dirty pages.");
1717	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cZeroPages", STAMUNIT_COUNT, "ROM: Ready zero pages.");
1718	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Rom.cMonitoredPages, STAMTYPE_U32, "/PGM/LiveSave/Rom/cMonitoredPages", STAMUNIT_COUNT, "ROM: Write monitored pages.");
1719	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cReadyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cReadPages", STAMUNIT_COUNT, "MMIO2: Ready pages.");
1720	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cDirtyPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cDirtyPages", STAMUNIT_COUNT, "MMIO2: Dirty pages.");
1721	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cZeroPages, STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cZeroPages", STAMUNIT_COUNT, "MMIO2: Ready zero pages.");
1722	STAM_REL_REG_USED(pVM, &pPGM->LiveSave.Mmio2.cMonitoredPages,STAMTYPE_U32, "/PGM/LiveSave/Mmio2/cMonitoredPages",STAMUNIT_COUNT, "MMIO2: Write monitored pages.");
1723
1724	#ifdef VBOX_WITH_STATISTICS
1725
1726	# define PGM_REG_COUNTER(a, b, c) \
1727	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b); \
1728	AssertRC(rc);
1729
1730	# define PGM_REG_COUNTER_BYTES(a, b, c) \
1731	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_BYTES, c, b); \
1732	AssertRC(rc);
1733
1734	# define PGM_REG_PROFILE(a, b, c) \
1735	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b); \
1736	AssertRC(rc);
1737
1738	PGMSTATS *pStats = pVM->pgm.s.pStatsR3;
1739
1740	PGM_REG_PROFILE(&pStats->StatAllocLargePage, "/PGM/LargePage/Prof/Alloc", "Time spent by the host OS for large page allocation.");
1741	PGM_REG_PROFILE(&pStats->StatClearLargePage, "/PGM/LargePage/Prof/Clear", "Time spent clearing the newly allocated large pages.");
1742	PGM_REG_COUNTER(&pStats->StatLargePageOverflow, "/PGM/LargePage/Overflow", "The number of times allocating a large page took too long.");
1743	PGM_REG_PROFILE(&pStats->StatR3IsValidLargePage, "/PGM/LargePage/Prof/R3/IsValid", "pgmPhysIsValidLargePage profiling - R3.");
1744	PGM_REG_PROFILE(&pStats->StatRZIsValidLargePage, "/PGM/LargePage/Prof/RZ/IsValid", "pgmPhysIsValidLargePage profiling - RZ.");
1745
1746	PGM_REG_COUNTER(&pStats->StatR3DetectedConflicts, "/PGM/R3/DetectedConflicts", "The number of times PGMR3CheckMappingConflicts() detected a conflict.");
1747	PGM_REG_PROFILE(&pStats->StatR3ResolveConflict, "/PGM/R3/ResolveConflict", "pgmR3SyncPTResolveConflict() profiling (includes the entire relocation).");
1748	PGM_REG_COUNTER(&pStats->StatR3PhysRead, "/PGM/R3/Phys/Read", "The number of times PGMPhysRead was called.");
1749	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysReadBytes, "/PGM/R3/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1750	PGM_REG_COUNTER(&pStats->StatR3PhysWrite, "/PGM/R3/Phys/Write", "The number of times PGMPhysWrite was called.");
1751	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysWriteBytes, "/PGM/R3/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1752	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleRead, "/PGM/R3/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1753	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleReadBytes, "/PGM/R3/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1754	PGM_REG_COUNTER(&pStats->StatR3PhysSimpleWrite, "/PGM/R3/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1755	PGM_REG_COUNTER_BYTES(&pStats->StatR3PhysSimpleWriteBytes, "/PGM/R3/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1756
1757	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsRZ", "TLB hits.");
1758	PGM_REG_COUNTER(&pStats->StatRZChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesRZ", "TLB misses.");
1759	PGM_REG_PROFILE(&pStats->StatChunkAging, "/PGM/ChunkR3Map/Map/Aging", "Chunk aging profiling.");
1760	PGM_REG_PROFILE(&pStats->StatChunkFindCandidate, "/PGM/ChunkR3Map/Map/Find", "Chunk unmap find profiling.");
1761	PGM_REG_PROFILE(&pStats->StatChunkUnmap, "/PGM/ChunkR3Map/Map/Unmap", "Chunk unmap of address space profiling.");
1762	PGM_REG_PROFILE(&pStats->StatChunkMap, "/PGM/ChunkR3Map/Map/Map", "Chunk map of address space profiling.");
1763
1764	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbHits, "/PGM/RZ/Page/MapTlbHits", "TLB hits.");
1765	PGM_REG_COUNTER(&pStats->StatRZPageMapTlbMisses, "/PGM/RZ/Page/MapTlbMisses", "TLB misses.");
1766	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbHits, "/PGM/ChunkR3Map/TlbHitsR3", "TLB hits.");
1767	PGM_REG_COUNTER(&pStats->StatR3ChunkR3MapTlbMisses, "/PGM/ChunkR3Map/TlbMissesR3", "TLB misses.");
1768	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbHits, "/PGM/R3/Page/MapTlbHits", "TLB hits.");
1769	PGM_REG_COUNTER(&pStats->StatR3PageMapTlbMisses, "/PGM/R3/Page/MapTlbMisses", "TLB misses.");
1770	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushes, "/PGM/R3/Page/MapTlbFlushes", "TLB flushes (all contexts).");
1771	PGM_REG_COUNTER(&pStats->StatPageMapTlbFlushEntry, "/PGM/R3/Page/MapTlbFlushEntry", "TLB entry flushes (all contexts).");
1772
1773	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbHits, "/PGM/RZ/RamRange/TlbHits", "TLB hits.");
1774	PGM_REG_COUNTER(&pStats->StatRZRamRangeTlbMisses, "/PGM/RZ/RamRange/TlbMisses", "TLB misses.");
1775	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbHits, "/PGM/R3/RamRange/TlbHits", "TLB hits.");
1776	PGM_REG_COUNTER(&pStats->StatR3RamRangeTlbMisses, "/PGM/R3/RamRange/TlbMisses", "TLB misses.");
1777
1778	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualUpdate, "/PGM/RZ/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1779	PGM_REG_PROFILE(&pStats->StatRZSyncCR3HandlerVirtualReset, "/PGM/RZ/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1780	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualUpdate, "/PGM/R3/SyncCR3/Handlers/VirtualUpdate", "Profiling of the virtual handler updates.");
1781	PGM_REG_PROFILE(&pStats->StatR3SyncCR3HandlerVirtualReset, "/PGM/R3/SyncCR3/Handlers/VirtualReset", "Profiling of the virtual handler resets.");
1782
1783	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerReset, "/PGM/RZ/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1784	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerReset, "/PGM/R3/PhysHandlerReset", "The number of times PGMHandlerPhysicalReset is called.");
1785	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupHits, "/PGM/RZ/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1786	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupHits, "/PGM/R3/PhysHandlerLookupHits", "The number of cache hits when looking up physical handlers.");
1787	PGM_REG_COUNTER(&pStats->StatRZPhysHandlerLookupMisses, "/PGM/RZ/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1788	PGM_REG_COUNTER(&pStats->StatR3PhysHandlerLookupMisses, "/PGM/R3/PhysHandlerLookupMisses", "The number of cache misses when looking up physical handlers.");
1789	PGM_REG_PROFILE(&pStats->StatRZVirtHandlerSearchByPhys, "/PGM/RZ/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1790	PGM_REG_PROFILE(&pStats->StatR3VirtHandlerSearchByPhys, "/PGM/R3/VirtHandlerSearchByPhys", "Profiling of pgmHandlerVirtualFindByPhysAddr.");
1791
1792	PGM_REG_COUNTER(&pStats->StatRZPageReplaceShared, "/PGM/RZ/Page/ReplacedShared", "Times a shared page was replaced.");
1793	PGM_REG_COUNTER(&pStats->StatRZPageReplaceZero, "/PGM/RZ/Page/ReplacedZero", "Times the zero page was replaced.");
1794	/// @todo PGM_REG_COUNTER(&pStats->StatRZPageHandyAllocs, "/PGM/RZ/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1795	PGM_REG_COUNTER(&pStats->StatR3PageReplaceShared, "/PGM/R3/Page/ReplacedShared", "Times a shared page was replaced.");
1796	PGM_REG_COUNTER(&pStats->StatR3PageReplaceZero, "/PGM/R3/Page/ReplacedZero", "Times the zero page was replaced.");
1797	/// @todo PGM_REG_COUNTER(&pStats->StatR3PageHandyAllocs, "/PGM/R3/Page/HandyAllocs", "Number of times we've allocated more handy pages.");
1798
1799	PGM_REG_COUNTER(&pStats->StatRZPhysRead, "/PGM/RZ/Phys/Read", "The number of times PGMPhysRead was called.");
1800	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysReadBytes, "/PGM/RZ/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1801	PGM_REG_COUNTER(&pStats->StatRZPhysWrite, "/PGM/RZ/Phys/Write", "The number of times PGMPhysWrite was called.");
1802	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysWriteBytes, "/PGM/RZ/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1803	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleRead, "/PGM/RZ/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1804	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleReadBytes, "/PGM/RZ/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1805	PGM_REG_COUNTER(&pStats->StatRZPhysSimpleWrite, "/PGM/RZ/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1806	PGM_REG_COUNTER_BYTES(&pStats->StatRZPhysSimpleWriteBytes, "/PGM/RZ/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1807
1808	/* GC only: */
1809	PGM_REG_COUNTER(&pStats->StatRCInvlPgConflict, "/PGM/RC/InvlPgConflict", "Number of times PGMInvalidatePage() detected a mapping conflict.");
1810	PGM_REG_COUNTER(&pStats->StatRCInvlPgSyncMonCR3, "/PGM/RC/InvlPgSyncMonitorCR3", "Number of times PGMInvalidatePage() ran into PGM_SYNC_MONITOR_CR3.");
1811
1812	PGM_REG_COUNTER(&pStats->StatRCPhysRead, "/PGM/RC/Phys/Read", "The number of times PGMPhysRead was called.");
1813	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysReadBytes, "/PGM/RC/Phys/Read/Bytes", "The number of bytes read by PGMPhysRead.");
1814	PGM_REG_COUNTER(&pStats->StatRCPhysWrite, "/PGM/RC/Phys/Write", "The number of times PGMPhysWrite was called.");
1815	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysWriteBytes, "/PGM/RC/Phys/Write/Bytes", "The number of bytes written by PGMPhysWrite.");
1816	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleRead, "/PGM/RC/Phys/Simple/Read", "The number of times PGMPhysSimpleReadGCPtr was called.");
1817	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleReadBytes, "/PGM/RC/Phys/Simple/Read/Bytes", "The number of bytes read by PGMPhysSimpleReadGCPtr.");
1818	PGM_REG_COUNTER(&pStats->StatRCPhysSimpleWrite, "/PGM/RC/Phys/Simple/Write", "The number of times PGMPhysSimpleWriteGCPtr was called.");
1819	PGM_REG_COUNTER_BYTES(&pStats->StatRCPhysSimpleWriteBytes, "/PGM/RC/Phys/Simple/Write/Bytes", "The number of bytes written by PGMPhysSimpleWriteGCPtr.");
1820
1821	PGM_REG_COUNTER(&pStats->StatTrackVirgin, "/PGM/Track/Virgin", "The number of first time shadowings");
1822	PGM_REG_COUNTER(&pStats->StatTrackAliased, "/PGM/Track/Aliased", "The number of times switching to cRef2, i.e. the page is being shadowed by two PTs.");
1823	PGM_REG_COUNTER(&pStats->StatTrackAliasedMany, "/PGM/Track/AliasedMany", "The number of times we're tracking using cRef2.");
1824	PGM_REG_COUNTER(&pStats->StatTrackAliasedLots, "/PGM/Track/AliasedLots", "The number of times we're hitting pages which has overflowed cRef2");
1825	PGM_REG_COUNTER(&pStats->StatTrackOverflows, "/PGM/Track/Overflows", "The number of times the extent list grows too long.");
1826	PGM_REG_COUNTER(&pStats->StatTrackNoExtentsLeft, "/PGM/Track/NoExtentLeft", "The number of times the extent list was exhausted.");
1827	PGM_REG_PROFILE(&pStats->StatTrackDeref, "/PGM/Track/Deref", "Profiling of SyncPageWorkerTrackDeref (expensive).");
1828
1829	# undef PGM_REG_COUNTER
1830	# undef PGM_REG_PROFILE
1831	#endif
1832
1833	/*
1834	* Note! The layout below matches the member layout exactly!
1835	*/
1836
1837	/*
1838	* Common - stats
1839	*/
1840	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1841	{
1842	PPGMCPU pPgmCpu = &pVM->aCpus[idCpu].pgm.s;
1843
1844	#define PGM_REG_COUNTER(a, b, c) \
1845	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, idCpu); \
1846	AssertRC(rc);
1847	#define PGM_REG_PROFILE(a, b, c) \
1848	rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, idCpu); \
1849	AssertRC(rc);
1850
1851	PGM_REG_COUNTER(&pPgmCpu->cGuestModeChanges, "/PGM/CPU%u/cGuestModeChanges", "Number of guest mode changes.");
1852	PGM_REG_COUNTER(&pPgmCpu->cA20Changes, "/PGM/CPU%u/cA20Changes", "Number of A20 gate changes.");
1853
1854	#ifdef VBOX_WITH_STATISTICS
1855	PGMCPUSTATS *pCpuStats = pVM->aCpus[idCpu].pgm.s.pStatsR3;
1856
1857	# if 0 /* rarely useful; leave for debugging. */
1858	for (unsigned j = 0; j < RT_ELEMENTS(pPgmCpu->StatSyncPtPD); j++)
1859	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPtPD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1860	"The number of SyncPT per PD n.", "/PGM/CPU%u/PDSyncPT/%04X", i, j);
1861	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatSyncPagePD); j++)
1862	STAMR3RegisterF(pVM, &pCpuStats->StatSyncPagePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1863	"The number of SyncPage per PD n.", "/PGM/CPU%u/PDSyncPage/%04X", i, j);
1864	# endif
1865	/* R0 only: */
1866	PGM_REG_PROFILE(&pCpuStats->StatR0NpMiscfg, "/PGM/CPU%u/R0/NpMiscfg", "PGMR0Trap0eHandlerNPMisconfig() profiling.");
1867	PGM_REG_COUNTER(&pCpuStats->StatR0NpMiscfgSyncPage, "/PGM/CPU%u/R0/NpMiscfgSyncPage", "SyncPage calls from PGMR0Trap0eHandlerNPMisconfig().");
1868
1869	/* RZ only: */
1870	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0e, "/PGM/CPU%u/RZ/Trap0e", "Profiling of the PGMTrap0eHandler() body.");
1871	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Ballooned, "/PGM/CPU%u/RZ/Trap0e/Time2/Ballooned", "Profiling of the Trap0eHandler body when the cause is read access to a ballooned page.");
1872	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2CSAM, "/PGM/CPU%u/RZ/Trap0e/Time2/CSAM", "Profiling of the Trap0eHandler body when the cause is CSAM.");
1873	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2DirtyAndAccessed, "/PGM/CPU%u/RZ/Trap0e/Time2/DirtyAndAccessedBits", "Profiling of the Trap0eHandler body when the cause is dirty and/or accessed bit emulation.");
1874	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2GuestTrap, "/PGM/CPU%u/RZ/Trap0e/Time2/GuestTrap", "Profiling of the Trap0eHandler body when the cause is a guest trap.");
1875	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerPhysical", "Profiling of the Trap0eHandler body when the cause is a physical handler.");
1876	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerVirtual", "Profiling of the Trap0eHandler body when the cause is a virtual handler.");
1877	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2HndUnhandled, "/PGM/CPU%u/RZ/Trap0e/Time2/HandlerUnhandled", "Profiling of the Trap0eHandler body when the cause is access outside the monitored areas of a monitored page.");
1878	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2InvalidPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/InvalidPhys", "Profiling of the Trap0eHandler body when the cause is access to an invalid physical guest address.");
1879	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2MakeWritable, "/PGM/CPU%u/RZ/Trap0e/Time2/MakeWritable", "Profiling of the Trap0eHandler body when the cause is that a page needed to be made writeable.");
1880	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Mapping, "/PGM/CPU%u/RZ/Trap0e/Time2/Mapping", "Profiling of the Trap0eHandler body when the cause is related to the guest mappings.");
1881	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2Misc, "/PGM/CPU%u/RZ/Trap0e/Time2/Misc", "Profiling of the Trap0eHandler body when the cause is not known.");
1882	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSync, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSync", "Profiling of the Trap0eHandler body when the cause is an out-of-sync page.");
1883	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndPhys, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndPhys", "Profiling of the Trap0eHandler body when the cause is an out-of-sync physical handler page.");
1884	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndVirt, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncHndVirt", "Profiling of the Trap0eHandler body when the cause is an out-of-sync virtual handler page.");
1885	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2OutOfSyncHndObs, "/PGM/CPU%u/RZ/Trap0e/Time2/OutOfSyncObsHnd", "Profiling of the Trap0eHandler body when the cause is an obsolete handler page.");
1886	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2SyncPT, "/PGM/CPU%u/RZ/Trap0e/Time2/SyncPT", "Profiling of the Trap0eHandler body when the cause is lazy syncing of a PT.");
1887	PGM_REG_PROFILE(&pCpuStats->StatRZTrap0eTime2WPEmulation, "/PGM/CPU%u/RZ/Trap0e/Time2/WPEmulation", "Profiling of the Trap0eHandler body when the cause is CR0.WP emulation.");
1888	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eConflicts, "/PGM/CPU%u/RZ/Trap0e/Conflicts", "The number of times #PF was caused by an undetected conflict.");
1889	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersMapping, "/PGM/CPU%u/RZ/Trap0e/Handlers/Mapping", "Number of traps due to access handlers in mappings.");
1890	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersOutOfSync, "/PGM/CPU%u/RZ/Trap0e/Handlers/OutOfSync", "Number of traps due to out-of-sync handled pages.");
1891	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAll, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAll", "Number of traps due to physical all-access handlers.");
1892	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysAllOpt, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysAllOpt", "Number of the physical all-access handler traps using the optimization.");
1893	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersPhysWrite, "/PGM/CPU%u/RZ/Trap0e/Handlers/PhysWrite", "Number of traps due to physical write-access handlers.");
1894	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtual, "/PGM/CPU%u/RZ/Trap0e/Handlers/Virtual", "Number of traps due to virtual access handlers.");
1895	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualByPhys, "/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualByPhys", "Number of traps due to virtual access handlers by physical address.");
1896	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersVirtualUnmarked,"/PGM/CPU%u/RZ/Trap0e/Handlers/VirtualUnmarked","Number of traps due to virtual access handlers by virtual address (without proper physical flags).");
1897	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersUnhandled, "/PGM/CPU%u/RZ/Trap0e/Handlers/Unhandled", "Number of traps due to access outside range of monitored page(s).");
1898	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eHandlersInvalid, "/PGM/CPU%u/RZ/Trap0e/Handlers/Invalid", "Number of traps due to access to invalid physical memory.");
1899	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPRead", "Number of user mode not present read page faults.");
1900	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/NPWrite", "Number of user mode not present write page faults.");
1901	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSWrite, "/PGM/CPU%u/RZ/Trap0e/Err/User/Write", "Number of user mode write page faults.");
1902	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSReserved, "/PGM/CPU%u/RZ/Trap0e/Err/User/Reserved", "Number of user mode reserved bit page faults.");
1903	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/User/NXE", "Number of user mode NXE page faults.");
1904	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eUSRead, "/PGM/CPU%u/RZ/Trap0e/Err/User/Read", "Number of user mode read page faults.");
1905	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentRead, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPRead", "Number of supervisor mode not present read page faults.");
1906	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVNotPresentWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NPWrite", "Number of supervisor mode not present write page faults.");
1907	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVWrite, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Write", "Number of supervisor mode write page faults.");
1908	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSVReserved, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/Reserved", "Number of supervisor mode reserved bit page faults.");
1909	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eSNXE, "/PGM/CPU%u/RZ/Trap0e/Err/Supervisor/NXE", "Number of supervisor mode NXE page faults.");
1910	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPF, "/PGM/CPU%u/RZ/Trap0e/GuestPF", "Number of real guest page faults.");
1911	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eGuestPFMapping, "/PGM/CPU%u/RZ/Trap0e/GuestPF/InMapping", "Number of real guest page faults in a mapping.");
1912	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulInRZ, "/PGM/CPU%u/RZ/Trap0e/WP/InRZ", "Number of guest page faults due to X86_CR0_WP emulation.");
1913	PGM_REG_COUNTER(&pCpuStats->StatRZTrap0eWPEmulToR3, "/PGM/CPU%u/RZ/Trap0e/WP/ToR3", "Number of guest page faults due to X86_CR0_WP emulation (forward to R3 for emulation).");
1914	#if 0 /* rarely useful; leave for debugging. */
1915	for (unsigned j = 0; j < RT_ELEMENTS(pCpuStats->StatRZTrap0ePD); j++)
1916	STAMR3RegisterF(pVM, &pCpuStats->StatRZTrap0ePD[i], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1917	"The number of traps in page directory n.", "/PGM/CPU%u/RZ/Trap0e/PD/%04X", i, j);
1918	#endif
1919	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteHandled, "/PGM/CPU%u/RZ/CR3WriteHandled", "The number of times the Guest CR3 change was successfully handled.");
1920	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteUnhandled, "/PGM/CPU%u/RZ/CR3WriteUnhandled", "The number of times the Guest CR3 change was passed back to the recompiler.");
1921	PGM_REG_COUNTER(&pCpuStats->StatRZGuestCR3WriteConflict, "/PGM/CPU%u/RZ/CR3WriteConflict", "The number of times the Guest CR3 monitoring detected a conflict.");
1922	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteHandled, "/PGM/CPU%u/RZ/ROMWriteHandled", "The number of times the Guest ROM change was successfully handled.");
1923	PGM_REG_COUNTER(&pCpuStats->StatRZGuestROMWriteUnhandled, "/PGM/CPU%u/RZ/ROMWriteUnhandled", "The number of times the Guest ROM change was passed back to the recompiler.");
1924
1925	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapMigrateInvlPg, "/PGM/CPU%u/RZ/DynMap/MigrateInvlPg", "invlpg count in PGMR0DynMapMigrateAutoSet.");
1926	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapGCPageInl, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl", "Calls to pgmR0DynMapGCPageInlined.");
1927	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Hits", "Hash table lookup hits.");
1928	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/Misses", "Misses that falls back to the code common.");
1929	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamHits, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamHits", "1st ram range hits.");
1930	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapGCPageInlRamMisses, "/PGM/CPU%u/RZ/DynMap/PageGCPageInl/RamMisses", "1st ram range misses, takes slow path.");
1931	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPageInl, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl", "Calls to pgmRZDynMapHCPageInlined.");
1932	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlHits, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Hits", "Hash table lookup hits.");
1933	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapHCPageInlMisses, "/PGM/CPU%u/RZ/DynMap/PageHCPageInl/Misses", "Misses that falls back to the code common.");
1934	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPage, "/PGM/CPU%u/RZ/DynMap/Page", "Calls to pgmR0DynMapPage");
1935	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetOptimize, "/PGM/CPU%u/RZ/DynMap/Page/SetOptimize", "Calls to pgmRZDynMapOptimizeAutoSet.");
1936	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchFlushes, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchFlushes", "Set search restoring to subset flushes.");
1937	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchHits, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchHits", "Set search hits.");
1938	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSetSearchMisses, "/PGM/CPU%u/RZ/DynMap/Page/SetSearchMisses", "Set search misses.");
1939	PGM_REG_PROFILE(&pCpuStats->StatRZDynMapHCPage, "/PGM/CPU%u/RZ/DynMap/Page/HCPage", "Calls to pgmRZDynMapHCPageCommon (ring-0).");
1940	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits0, "/PGM/CPU%u/RZ/DynMap/Page/Hits0", "Hits at iPage+0");
1941	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits1, "/PGM/CPU%u/RZ/DynMap/Page/Hits1", "Hits at iPage+1");
1942	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageHits2, "/PGM/CPU%u/RZ/DynMap/Page/Hits2", "Hits at iPage+2");
1943	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageInvlPg, "/PGM/CPU%u/RZ/DynMap/Page/InvlPg", "invlpg count in pgmR0DynMapPageSlow.");
1944	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlow, "/PGM/CPU%u/RZ/DynMap/Page/Slow", "Calls to pgmR0DynMapPageSlow - subtract this from pgmR0DynMapPage to get 1st level hits.");
1945	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopHits, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopHits" , "Hits in the loop path.");
1946	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLoopMisses, "/PGM/CPU%u/RZ/DynMap/Page/SlowLoopMisses", "Misses in the loop path. NonLoopMisses = Slow - SlowLoopHit - SlowLoopMisses");
1947	//PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPageSlowLostHits, "/PGM/CPU%u/R0/DynMap/Page/SlowLostHits", "Lost hits.");
1948	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapSubsets, "/PGM/CPU%u/RZ/DynMap/Subsets", "Times PGMRZDynMapPushAutoSubset was called.");
1949	PGM_REG_COUNTER(&pCpuStats->StatRZDynMapPopFlushes, "/PGM/CPU%u/RZ/DynMap/SubsetPopFlushes", "Times PGMRZDynMapPopAutoSubset flushes the subset.");
1950	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[0], "/PGM/CPU%u/RZ/DynMap/SetFilledPct000..09", "00-09% filled (RC: min(set-size, dynmap-size))");
1951	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[1], "/PGM/CPU%u/RZ/DynMap/SetFilledPct010..19", "10-19% filled (RC: min(set-size, dynmap-size))");
1952	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[2], "/PGM/CPU%u/RZ/DynMap/SetFilledPct020..29", "20-29% filled (RC: min(set-size, dynmap-size))");
1953	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[3], "/PGM/CPU%u/RZ/DynMap/SetFilledPct030..39", "30-39% filled (RC: min(set-size, dynmap-size))");
1954	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[4], "/PGM/CPU%u/RZ/DynMap/SetFilledPct040..49", "40-49% filled (RC: min(set-size, dynmap-size))");
1955	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[5], "/PGM/CPU%u/RZ/DynMap/SetFilledPct050..59", "50-59% filled (RC: min(set-size, dynmap-size))");
1956	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[6], "/PGM/CPU%u/RZ/DynMap/SetFilledPct060..69", "60-69% filled (RC: min(set-size, dynmap-size))");
1957	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[7], "/PGM/CPU%u/RZ/DynMap/SetFilledPct070..79", "70-79% filled (RC: min(set-size, dynmap-size))");
1958	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[8], "/PGM/CPU%u/RZ/DynMap/SetFilledPct080..89", "80-89% filled (RC: min(set-size, dynmap-size))");
1959	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[9], "/PGM/CPU%u/RZ/DynMap/SetFilledPct090..99", "90-99% filled (RC: min(set-size, dynmap-size))");
1960	PGM_REG_COUNTER(&pCpuStats->aStatRZDynMapSetFilledPct[10], "/PGM/CPU%u/RZ/DynMap/SetFilledPct100", "100% filled (RC: min(set-size, dynmap-size))");
1961
1962	/* HC only: */
1963
1964	/* RZ & R3: */
1965	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3, "/PGM/CPU%u/RZ/SyncCR3", "Profiling of the PGMSyncCR3() body.");
1966	PGM_REG_PROFILE(&pCpuStats->StatRZSyncCR3Handlers, "/PGM/CPU%u/RZ/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
1967	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3Global, "/PGM/CPU%u/RZ/SyncCR3/Global", "The number of global CR3 syncs.");
1968	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3NotGlobal, "/PGM/CPU%u/RZ/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
1969	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstCacheHit, "/PGM/CPU%u/RZ/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
1970	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreed, "/PGM/CPU%u/RZ/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
1971	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstFreedSrcNP, "/PGM/CPU%u/RZ/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
1972	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstNotPresent, "/PGM/CPU%u/RZ/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
1973	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
1974	PGM_REG_COUNTER(&pCpuStats->StatRZSyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/RZ/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
1975	PGM_REG_PROFILE(&pCpuStats->StatRZSyncPT, "/PGM/CPU%u/RZ/SyncPT", "Profiling of the pfnSyncPT() body.");
1976	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPTFailed, "/PGM/CPU%u/RZ/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
1977	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4K, "/PGM/CPU%u/RZ/SyncPT/4K", "Nr of 4K PT syncs");
1978	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPT4M, "/PGM/CPU%u/RZ/SyncPT/4M", "Nr of 4M PT syncs");
1979	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDNAs, "/PGM/CPU%u/RZ/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
1980	PGM_REG_COUNTER(&pCpuStats->StatRZSyncPagePDOutOfSync, "/PGM/CPU%u/RZ/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
1981	PGM_REG_COUNTER(&pCpuStats->StatRZAccessedPage, "/PGM/CPU%u/RZ/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
1982	PGM_REG_PROFILE(&pCpuStats->StatRZDirtyBitTracking, "/PGM/CPU%u/RZ/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
1983	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPage, "/PGM/CPU%u/RZ/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
1984	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageBig, "/PGM/CPU%u/RZ/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
1985	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageSkipped, "/PGM/CPU%u/RZ/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
1986	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageTrap, "/PGM/CPU%u/RZ/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
1987	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyPageStale, "/PGM/CPU%u/RZ/DirtyPage/Stale", "The number of traps generated for dirty bit tracking (stale tlb entries).");
1988	PGM_REG_COUNTER(&pCpuStats->StatRZDirtiedPage, "/PGM/CPU%u/RZ/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
1989	PGM_REG_COUNTER(&pCpuStats->StatRZDirtyTrackRealPF, "/PGM/CPU%u/RZ/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
1990	PGM_REG_COUNTER(&pCpuStats->StatRZPageAlreadyDirty, "/PGM/CPU%u/RZ/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
1991	PGM_REG_PROFILE(&pCpuStats->StatRZInvalidatePage, "/PGM/CPU%u/RZ/InvalidatePage", "PGMInvalidatePage() profiling.");
1992	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4KBPages, "/PGM/CPU%u/RZ/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
1993	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPages, "/PGM/CPU%u/RZ/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
1994	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePage4MBPagesSkip, "/PGM/CPU%u/RZ/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
1995	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDMappings, "/PGM/CPU%u/RZ/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
1996	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNAs, "/PGM/CPU%u/RZ/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
1997	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDNPs, "/PGM/CPU%u/RZ/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
1998	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePagePDOutOfSync, "/PGM/CPU%u/RZ/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
1999	PGM_REG_COUNTER(&pCpuStats->StatRZInvalidatePageSkipped, "/PGM/CPU%u/RZ/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2000	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisor, "/PGM/CPU%u/RZ/OutOfSync/SuperVisor", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2001	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUser, "/PGM/CPU%u/RZ/OutOfSync/User", "Number of traps due to pages out of sync (P) and times VerifyAccessSyncPage calls SyncPage.");
2002	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncSupervisorWrite,"/PGM/CPU%u/RZ/OutOfSync/SuperVisorWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2003	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncUserWrite, "/PGM/CPU%u/RZ/OutOfSync/UserWrite", "Number of traps due to pages out of sync (RW) and times VerifyAccessSyncPage calls SyncPage.");
2004	PGM_REG_COUNTER(&pCpuStats->StatRZPageOutOfSyncBallloon, "/PGM/CPU%u/RZ/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2005	PGM_REG_PROFILE(&pCpuStats->StatRZPrefetch, "/PGM/CPU%u/RZ/Prefetch", "PGMPrefetchPage profiling.");
2006	PGM_REG_PROFILE(&pCpuStats->StatRZFlushTLB, "/PGM/CPU%u/RZ/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2007	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3, "/PGM/CPU%u/RZ/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2008	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBNewCR3Global, "/PGM/CPU%u/RZ/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2009	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3, "/PGM/CPU%u/RZ/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2010	PGM_REG_COUNTER(&pCpuStats->StatRZFlushTLBSameCR3Global, "/PGM/CPU%u/RZ/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2011	PGM_REG_PROFILE(&pCpuStats->StatRZGstModifyPage, "/PGM/CPU%u/RZ/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2012
2013	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3, "/PGM/CPU%u/R3/SyncCR3", "Profiling of the PGMSyncCR3() body.");
2014	PGM_REG_PROFILE(&pCpuStats->StatR3SyncCR3Handlers, "/PGM/CPU%u/R3/SyncCR3/Handlers", "Profiling of the PGMSyncCR3() update handler section.");
2015	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3Global, "/PGM/CPU%u/R3/SyncCR3/Global", "The number of global CR3 syncs.");
2016	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3NotGlobal, "/PGM/CPU%u/R3/SyncCR3/NotGlobal", "The number of non-global CR3 syncs.");
2017	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstCacheHit, "/PGM/CPU%u/R3/SyncCR3/DstChacheHit", "The number of times we got some kind of a cache hit.");
2018	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreed, "/PGM/CPU%u/R3/SyncCR3/DstFreed", "The number of times we've had to free a shadow entry.");
2019	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstFreedSrcNP, "/PGM/CPU%u/R3/SyncCR3/DstFreedSrcNP", "The number of times we've had to free a shadow entry for which the source entry was not present.");
2020	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstNotPresent, "/PGM/CPU%u/R3/SyncCR3/DstNotPresent", "The number of times we've encountered a not present shadow entry for a present guest entry.");
2021	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPD, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPD", "The number of times a global page directory wasn't flushed.");
2022	PGM_REG_COUNTER(&pCpuStats->StatR3SyncCR3DstSkippedGlobalPT, "/PGM/CPU%u/R3/SyncCR3/DstSkippedGlobalPT", "The number of times a page table with only global entries wasn't flushed.");
2023	PGM_REG_PROFILE(&pCpuStats->StatR3SyncPT, "/PGM/CPU%u/R3/SyncPT", "Profiling of the pfnSyncPT() body.");
2024	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPTFailed, "/PGM/CPU%u/R3/SyncPT/Failed", "The number of times pfnSyncPT() failed.");
2025	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4K, "/PGM/CPU%u/R3/SyncPT/4K", "Nr of 4K PT syncs");
2026	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPT4M, "/PGM/CPU%u/R3/SyncPT/4M", "Nr of 4M PT syncs");
2027	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDNAs, "/PGM/CPU%u/R3/SyncPagePDNAs", "The number of time we've marked a PD not present from SyncPage to virtualize the accessed bit.");
2028	PGM_REG_COUNTER(&pCpuStats->StatR3SyncPagePDOutOfSync, "/PGM/CPU%u/R3/SyncPagePDOutOfSync", "The number of time we've encountered an out-of-sync PD in SyncPage.");
2029	PGM_REG_COUNTER(&pCpuStats->StatR3AccessedPage, "/PGM/CPU%u/R3/AccessedPage", "The number of pages marked not present for accessed bit emulation.");
2030	PGM_REG_PROFILE(&pCpuStats->StatR3DirtyBitTracking, "/PGM/CPU%u/R3/DirtyPage", "Profiling the dirty bit tracking in CheckPageFault().");
2031	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPage, "/PGM/CPU%u/R3/DirtyPage/Mark", "The number of pages marked read-only for dirty bit tracking.");
2032	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageBig, "/PGM/CPU%u/R3/DirtyPage/MarkBig", "The number of 4MB pages marked read-only for dirty bit tracking.");
2033	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageSkipped, "/PGM/CPU%u/R3/DirtyPage/Skipped", "The number of pages already dirty or readonly.");
2034	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyPageTrap, "/PGM/CPU%u/R3/DirtyPage/Trap", "The number of traps generated for dirty bit tracking.");
2035	PGM_REG_COUNTER(&pCpuStats->StatR3DirtiedPage, "/PGM/CPU%u/R3/DirtyPage/SetDirty", "The number of pages marked dirty because of write accesses.");
2036	PGM_REG_COUNTER(&pCpuStats->StatR3DirtyTrackRealPF, "/PGM/CPU%u/R3/DirtyPage/RealPF", "The number of real pages faults during dirty bit tracking.");
2037	PGM_REG_COUNTER(&pCpuStats->StatR3PageAlreadyDirty, "/PGM/CPU%u/R3/DirtyPage/AlreadySet", "The number of pages already marked dirty because of write accesses.");
2038	PGM_REG_PROFILE(&pCpuStats->StatR3InvalidatePage, "/PGM/CPU%u/R3/InvalidatePage", "PGMInvalidatePage() profiling.");
2039	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4KBPages, "/PGM/CPU%u/R3/InvalidatePage/4KBPages", "The number of times PGMInvalidatePage() was called for a 4KB page.");
2040	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPages, "/PGM/CPU%u/R3/InvalidatePage/4MBPages", "The number of times PGMInvalidatePage() was called for a 4MB page.");
2041	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePage4MBPagesSkip, "/PGM/CPU%u/R3/InvalidatePage/4MBPagesSkip","The number of times PGMInvalidatePage() skipped a 4MB page.");
2042	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDMappings, "/PGM/CPU%u/R3/InvalidatePage/PDMappings", "The number of times PGMInvalidatePage() was called for a page directory containing mappings (no conflict).");
2043	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNAs, "/PGM/CPU%u/R3/InvalidatePage/PDNAs", "The number of times PGMInvalidatePage() was called for a not accessed page directory.");
2044	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDNPs, "/PGM/CPU%u/R3/InvalidatePage/PDNPs", "The number of times PGMInvalidatePage() was called for a not present page directory.");
2045	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePagePDOutOfSync, "/PGM/CPU%u/R3/InvalidatePage/PDOutOfSync", "The number of times PGMInvalidatePage() was called for an out of sync page directory.");
2046	PGM_REG_COUNTER(&pCpuStats->StatR3InvalidatePageSkipped, "/PGM/CPU%u/R3/InvalidatePage/Skipped", "The number of times PGMInvalidatePage() was skipped due to not present shw or pending pending SyncCR3.");
2047	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncSupervisor, "/PGM/CPU%u/R3/OutOfSync/SuperVisor", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2048	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncUser, "/PGM/CPU%u/R3/OutOfSync/User", "Number of traps due to pages out of sync and times VerifyAccessSyncPage calls SyncPage.");
2049	PGM_REG_COUNTER(&pCpuStats->StatR3PageOutOfSyncBallloon, "/PGM/CPU%u/R3/OutOfSync/Balloon", "The number of times a ballooned page was accessed (read).");
2050	PGM_REG_PROFILE(&pCpuStats->StatR3Prefetch, "/PGM/CPU%u/R3/Prefetch", "PGMPrefetchPage profiling.");
2051	PGM_REG_PROFILE(&pCpuStats->StatR3FlushTLB, "/PGM/CPU%u/R3/FlushTLB", "Profiling of the PGMFlushTLB() body.");
2052	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3, "/PGM/CPU%u/R3/FlushTLB/NewCR3", "The number of times PGMFlushTLB was called with a new CR3, non-global. (switch)");
2053	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBNewCR3Global, "/PGM/CPU%u/R3/FlushTLB/NewCR3Global", "The number of times PGMFlushTLB was called with a new CR3, global. (switch)");
2054	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3, "/PGM/CPU%u/R3/FlushTLB/SameCR3", "The number of times PGMFlushTLB was called with the same CR3, non-global. (flush)");
2055	PGM_REG_COUNTER(&pCpuStats->StatR3FlushTLBSameCR3Global, "/PGM/CPU%u/R3/FlushTLB/SameCR3Global", "The number of times PGMFlushTLB was called with the same CR3, global. (flush)");
2056	PGM_REG_PROFILE(&pCpuStats->StatR3GstModifyPage, "/PGM/CPU%u/R3/GstModifyPage", "Profiling of the PGMGstModifyPage() body.");
2057	#endif /* VBOX_WITH_STATISTICS */
2058
2059	#undef PGM_REG_PROFILE
2060	#undef PGM_REG_COUNTER
2061
2062	}
2063
2064	return VINF_SUCCESS;
2065	}
2066
2067
2068	/**
2069	* Init the PGM bits that rely on VMMR0 and MM to be fully initialized.
2070	*
2071	* The dynamic mapping area will also be allocated and initialized at this
2072	* time. We could allocate it during PGMR3Init of course, but the mapping
2073	* wouldn't be allocated at that time preventing us from setting up the
2074	* page table entries with the dummy page.
2075	*
2076	* @returns VBox status code.
2077	* @param pVM Pointer to the VM.
2078	*/
2079	VMMR3DECL(int) PGMR3InitDynMap(PVM pVM)
2080	{
2081	RTGCPTR GCPtr;
2082	int rc;
2083
2084	/*
2085	* Reserve space for the dynamic mappings.
2086	*/
2087	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping", &GCPtr);
2088	if (RT_SUCCESS(rc))
2089	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2090
2091	if ( RT_SUCCESS(rc)
2092	&& (pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) != ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT))
2093	{
2094	rc = MMR3HyperReserve(pVM, MM_HYPER_DYNAMIC_SIZE, "Dynamic mapping not crossing", &GCPtr);
2095	if (RT_SUCCESS(rc))
2096	pVM->pgm.s.pbDynPageMapBaseGC = GCPtr;
2097	}
2098	if (RT_SUCCESS(rc))
2099	{
2100	AssertRelease((pVM->pgm.s.pbDynPageMapBaseGC >> X86_PD_PAE_SHIFT) == ((pVM->pgm.s.pbDynPageMapBaseGC + MM_HYPER_DYNAMIC_SIZE - 1) >> X86_PD_PAE_SHIFT));
2101	MMR3HyperReserve(pVM, PAGE_SIZE, "fence", NULL);
2102	}
2103	return rc;
2104	}
2105
2106
2107	/**
2108	* Ring-3 init finalizing.
2109	*
2110	* @returns VBox status code.
2111	* @param pVM Pointer to the VM.
2112	*/
2113	VMMR3DECL(int) PGMR3InitFinalize(PVM pVM)
2114	{
2115	int rc;
2116
2117	/*
2118	* Reserve space for the dynamic mappings.
2119	* Initialize the dynamic mapping pages with dummy pages to simply the cache.
2120	*/
2121	/* get the pointer to the page table entries. */
2122	PPGMMAPPING pMapping = pgmGetMapping(pVM, pVM->pgm.s.pbDynPageMapBaseGC);
2123	AssertRelease(pMapping);
2124	const uintptr_t off = pVM->pgm.s.pbDynPageMapBaseGC - pMapping->GCPtr;
2125	const unsigned iPT = off >> X86_PD_SHIFT;
2126	const unsigned iPG = (off >> X86_PT_SHIFT) & X86_PT_MASK;
2127	pVM->pgm.s.paDynPageMap32BitPTEsGC = pMapping->aPTs[iPT].pPTRC + iPG * sizeof(pMapping->aPTs[0].pPTR3->a[0]);
2128	pVM->pgm.s.paDynPageMapPaePTEsGC = pMapping->aPTs[iPT].paPaePTsRC + iPG * sizeof(pMapping->aPTs[0].paPaePTsR3->a[0]);
2129
2130	/* init cache area */
2131	RTHCPHYS HCPhysDummy = MMR3PageDummyHCPhys(pVM);
2132	for (uint32_t offDynMap = 0; offDynMap < MM_HYPER_DYNAMIC_SIZE; offDynMap += PAGE_SIZE)
2133	{
2134	rc = PGMMap(pVM, pVM->pgm.s.pbDynPageMapBaseGC + offDynMap, HCPhysDummy, PAGE_SIZE, 0);
2135	AssertRCReturn(rc, rc);
2136	}
2137
2138	/*
2139	* Determine the max physical address width (MAXPHYADDR) and apply it to
2140	* all the mask members and stuff.
2141	*/
2142	uint32_t cMaxPhysAddrWidth;
2143	uint32_t uMaxExtLeaf = ASMCpuId_EAX(0x80000000);
2144	if ( uMaxExtLeaf >= 0x80000008
2145	&& uMaxExtLeaf <= 0x80000fff)
2146	{
2147	cMaxPhysAddrWidth = ASMCpuId_EAX(0x80000008) & 0xff;
2148	LogRel(("PGM: The CPU physical address width is %u bits\n", cMaxPhysAddrWidth));
2149	cMaxPhysAddrWidth = RT_MIN(52, cMaxPhysAddrWidth);
2150	pVM->pgm.s.fLessThan52PhysicalAddressBits = cMaxPhysAddrWidth < 52;
2151	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 52; iBit++)
2152	pVM->pgm.s.HCPhysInvMmioPg \|= RT_BIT_64(iBit);
2153	}
2154	else
2155	{
2156	LogRel(("PGM: ASSUMING CPU physical address width of 48 bits (uMaxExtLeaf=%#x)\n", uMaxExtLeaf));
2157	cMaxPhysAddrWidth = 48;
2158	pVM->pgm.s.fLessThan52PhysicalAddressBits = true;
2159	pVM->pgm.s.HCPhysInvMmioPg \|= UINT64_C(0x000f0000000000);
2160	}
2161
2162	pVM->pgm.s.GCPhysInvAddrMask = 0;
2163	for (uint32_t iBit = cMaxPhysAddrWidth; iBit < 64; iBit++)
2164	pVM->pgm.s.GCPhysInvAddrMask \|= RT_BIT_64(iBit);
2165
2166	/*
2167	* Initialize the invalid paging entry masks, assuming NX is disabled.
2168	*/
2169	uint64_t fMbzPageFrameMask = pVM->pgm.s.GCPhysInvAddrMask & UINT64_C(0x000ffffffffff000);
2170	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2171	{
2172	PVMCPU pVCpu = &pVM->aCpus[iCpu];
2173
2174	/** @todo The manuals are not entirely clear whether the physical
2175	* address width is relevant. See table 5-9 in the intel
2176	* manual vs the PDE4M descriptions. Write testcase (NP). */
2177	pVCpu->pgm.s.fGst32BitMbzBigPdeMask = ((uint32_t)(fMbzPageFrameMask >> (32 - 13)) & X86_PDE4M_PG_HIGH_MASK)
2178	\| X86_PDE4M_MBZ_MASK;
2179
2180	pVCpu->pgm.s.fGstPaeMbzPteMask = fMbzPageFrameMask \| X86_PTE_PAE_MBZ_MASK_NO_NX;
2181	pVCpu->pgm.s.fGstPaeMbzPdeMask = fMbzPageFrameMask \| X86_PDE_PAE_MBZ_MASK_NO_NX;
2182	pVCpu->pgm.s.fGstPaeMbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_PAE_MBZ_MASK_NO_NX;
2183	pVCpu->pgm.s.fGstPaeMbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_PAE_MBZ_MASK;
2184
2185	pVCpu->pgm.s.fGstAmd64MbzPteMask = fMbzPageFrameMask \| X86_PTE_LM_MBZ_MASK_NO_NX;
2186	pVCpu->pgm.s.fGstAmd64MbzPdeMask = fMbzPageFrameMask \| X86_PDE_LM_MBZ_MASK_NX;
2187	pVCpu->pgm.s.fGstAmd64MbzBigPdeMask = fMbzPageFrameMask \| X86_PDE2M_LM_MBZ_MASK_NX;
2188	pVCpu->pgm.s.fGstAmd64MbzPdpeMask = fMbzPageFrameMask \| X86_PDPE_LM_MBZ_MASK_NO_NX;
2189	pVCpu->pgm.s.fGstAmd64MbzBigPdpeMask = fMbzPageFrameMask \| X86_PDPE1G_LM_MBZ_MASK_NO_NX;
2190	pVCpu->pgm.s.fGstAmd64MbzPml4eMask = fMbzPageFrameMask \| X86_PML4E_MBZ_MASK_NO_NX;
2191
2192	pVCpu->pgm.s.fGst64ShadowedPteMask = X86_PTE_P \| X86_PTE_RW \| X86_PTE_US \| X86_PTE_G \| X86_PTE_A \| X86_PTE_D;
2193	pVCpu->pgm.s.fGst64ShadowedPdeMask = X86_PDE_P \| X86_PDE_RW \| X86_PDE_US \| X86_PDE_A;
2194	pVCpu->pgm.s.fGst64ShadowedBigPdeMask = X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_A;
2195	pVCpu->pgm.s.fGst64ShadowedBigPde4PteMask =
2196	X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US \| X86_PDE4M_G \| X86_PDE4M_A \| X86_PDE4M_D;
2197	pVCpu->pgm.s.fGstAmd64ShadowedPdpeMask = X86_PDPE_P \| X86_PDPE_RW \| X86_PDPE_US \| X86_PDPE_A;
2198	pVCpu->pgm.s.fGstAmd64ShadowedPml4eMask = X86_PML4E_P \| X86_PML4E_RW \| X86_PML4E_US \| X86_PML4E_A;
2199	}
2200
2201	/*
2202	* Note that AMD uses all the 8 reserved bits for the address (so 40 bits in total);
2203	* Intel only goes up to 36 bits, so we stick to 36 as well.
2204	* Update: More recent intel manuals specifies 40 bits just like AMD.
2205	*/
2206	uint32_t u32Dummy, u32Features;
2207	CPUMGetGuestCpuId(VMMGetCpu(pVM), 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
2208	if (u32Features & X86_CPUID_FEATURE_EDX_PSE36)
2209	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(RT_MAX(36, cMaxPhysAddrWidth)) - 1;
2210	else
2211	pVM->pgm.s.GCPhys4MBPSEMask = RT_BIT_64(32) - 1;
2212
2213	/*
2214	* Allocate memory if we're supposed to do that.
2215	*/
2216	if (pVM->pgm.s.fRamPreAlloc)
2217	rc = pgmR3PhysRamPreAllocate(pVM);
2218
2219	LogRel(("PGMR3InitFinalize: 4 MB PSE mask %RGp\n", pVM->pgm.s.GCPhys4MBPSEMask));
2220	return rc;
2221	}
2222
2223
2224	/**
2225	* Init phase completed callback.
2226	*
2227	* @returns VBox status code.
2228	* @param pVM Pointer to the VM.
2229	* @param enmWhat What has been completed.
2230	* @thread EMT(0)
2231	*/
2232	VMMR3_INT_DECL(int) PGMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
2233	{
2234	switch (enmWhat)
2235	{
2236	case VMINITCOMPLETED_HM:
2237	#ifdef VBOX_WITH_PCI_PASSTHROUGH
2238	if (pVM->pgm.s.fPciPassthrough)
2239	{
2240	AssertLogRelReturn(pVM->pgm.s.fRamPreAlloc, VERR_PCI_PASSTHROUGH_NO_RAM_PREALLOC);
2241	AssertLogRelReturn(HMIsEnabled(pVM), VERR_PCI_PASSTHROUGH_NO_HM);
2242	AssertLogRelReturn(HMIsNestedPagingActive(pVM), VERR_PCI_PASSTHROUGH_NO_NESTED_PAGING);
2243
2244	/*
2245	* Report assignments to the IOMMU (hope that's good enough for now).
2246	*/
2247	if (pVM->pgm.s.fPciPassthrough)
2248	{
2249	int rc = VMMR3CallR0(pVM, VMMR0_DO_PGM_PHYS_SETUP_IOMMU, 0, NULL);
2250	AssertRCReturn(rc, rc);
2251	}
2252	}
2253	#else
2254	AssertLogRelReturn(!pVM->pgm.s.fPciPassthrough, VERR_PGM_PCI_PASSTHRU_MISCONFIG);
2255	#endif
2256	break;
2257
2258	default:
2259	/* shut up gcc */
2260	break;
2261	}
2262
2263	return VINF_SUCCESS;
2264	}
2265
2266
2267	/**
2268	* Applies relocations to data and code managed by this component.
2269	*
2270	* This function will be called at init and whenever the VMM need to relocate it
2271	* self inside the GC.
2272	*
2273	* @param pVM The VM.
2274	* @param offDelta Relocation delta relative to old location.
2275	*/
2276	VMMR3DECL(void) PGMR3Relocate(PVM pVM, RTGCINTPTR offDelta)
2277	{
2278	LogFlow(("PGMR3Relocate %RGv to %RGv\n", pVM->pgm.s.GCPtrCR3Mapping, pVM->pgm.s.GCPtrCR3Mapping + offDelta));
2279
2280	/*
2281	* Paging stuff.
2282	*/
2283	pVM->pgm.s.GCPtrCR3Mapping += offDelta;
2284
2285	pgmR3ModeDataInit(pVM, true /* resolve GC/R0 symbols */);
2286
2287	/* Shadow, guest and both mode switch & relocation for each VCPU. */
2288	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2289	{
2290	PVMCPU pVCpu = &pVM->aCpus[i];
2291
2292	pgmR3ModeDataSwitch(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
2293
2294	PGM_SHW_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2295	PGM_GST_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2296	PGM_BTH_PFN(Relocate, pVCpu)(pVCpu, offDelta);
2297	}
2298
2299	/*
2300	* Trees.
2301	*/
2302	pVM->pgm.s.pTreesRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pTreesR3);
2303
2304	/*
2305	* Ram ranges.
2306	*/
2307	if (pVM->pgm.s.pRamRangesXR3)
2308	{
2309	/* Update the pSelfRC pointers and relink them. */
2310	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2311	if (!(pCur->fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2312	pCur->pSelfRC = MMHyperCCToRC(pVM, pCur);
2313	pgmR3PhysRelinkRamRanges(pVM);
2314
2315	/* Flush the RC TLB. */
2316	for (unsigned i = 0; i < PGM_RAMRANGE_TLB_ENTRIES; i++)
2317	pVM->pgm.s.apRamRangesTlbRC[i] = NIL_RTRCPTR;
2318	}
2319
2320	/*
2321	* Update the pSelfRC pointer of the MMIO2 ram ranges since they might not
2322	* be mapped and thus not included in the above exercise.
2323	*/
2324	for (PPGMMMIO2RANGE pCur = pVM->pgm.s.pMmio2RangesR3; pCur; pCur = pCur->pNextR3)
2325	if (!(pCur->RamRange.fFlags & PGM_RAM_RANGE_FLAGS_FLOATING))
2326	pCur->RamRange.pSelfRC = MMHyperCCToRC(pVM, &pCur->RamRange);
2327
2328	/*
2329	* Update the two page directories with all page table mappings.
2330	* (One or more of them have changed, that's why we're here.)
2331	*/
2332	pVM->pgm.s.pMappingsRC = MMHyperR3ToRC(pVM, pVM->pgm.s.pMappingsR3);
2333	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur->pNextR3; pCur = pCur->pNextR3)
2334	pCur->pNextRC = MMHyperR3ToRC(pVM, pCur->pNextR3);
2335
2336	/* Relocate GC addresses of Page Tables. */
2337	for (PPGMMAPPING pCur = pVM->pgm.s.pMappingsR3; pCur; pCur = pCur->pNextR3)
2338	{
2339	for (RTHCUINT i = 0; i < pCur->cPTs; i++)
2340	{
2341	pCur->aPTs[i].pPTRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].pPTR3);
2342	pCur->aPTs[i].paPaePTsRC = MMHyperR3ToRC(pVM, pCur->aPTs[i].paPaePTsR3);
2343	}
2344	}
2345
2346	/*
2347	* Dynamic page mapping area.
2348	*/
2349	pVM->pgm.s.paDynPageMap32BitPTEsGC += offDelta;
2350	pVM->pgm.s.paDynPageMapPaePTEsGC += offDelta;
2351	pVM->pgm.s.pbDynPageMapBaseGC += offDelta;
2352
2353	if (pVM->pgm.s.pRCDynMap)
2354	{
2355	pVM->pgm.s.pRCDynMap += offDelta;
2356	PPGMRCDYNMAP pDynMap = (PPGMRCDYNMAP)MMHyperRCToCC(pVM, pVM->pgm.s.pRCDynMap);
2357
2358	pDynMap->paPages += offDelta;
2359	PPGMRCDYNMAPENTRY paPages = (PPGMRCDYNMAPENTRY)MMHyperRCToCC(pVM, pDynMap->paPages);
2360
2361	for (uint32_t iPage = 0; iPage < pDynMap->cPages; iPage++)
2362	{
2363	paPages[iPage].pvPage += offDelta;
2364	paPages[iPage].uPte.pLegacy += offDelta;
2365	paPages[iPage].uPte.pPae += offDelta;
2366	}
2367	}
2368
2369	/*
2370	* The Zero page.
2371	*/
2372	pVM->pgm.s.pvZeroPgR0 = MMHyperR3ToR0(pVM, pVM->pgm.s.pvZeroPgR3);
2373	#ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
2374	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
2375	#else
2376	AssertRelease(pVM->pgm.s.pvZeroPgR0 != NIL_RTR0PTR);
2377	#endif
2378
2379	/*
2380	* Physical and virtual handlers.
2381	*/
2382	RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3RelocatePhysHandler, &offDelta);
2383	pVM->pgm.s.pLastPhysHandlerRC = NIL_RTRCPTR;
2384	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3RelocateVirtHandler, &offDelta);
2385	RTAvlroGCPtrDoWithAll(&pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3RelocateHyperVirtHandler, &offDelta);
2386
2387	/*
2388	* The page pool.
2389	*/
2390	pgmR3PoolRelocate(pVM);
2391
2392	#ifdef VBOX_WITH_STATISTICS
2393	/*
2394	* Statistics.
2395	*/
2396	pVM->pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->pgm.s.pStatsR3);
2397	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
2398	pVM->aCpus[iCpu].pgm.s.pStatsRC = MMHyperCCToRC(pVM, pVM->aCpus[iCpu].pgm.s.pStatsR3);
2399	#endif
2400	}
2401
2402
2403	/**
2404	* Callback function for relocating a physical access handler.
2405	*
2406	* @returns 0 (continue enum)
2407	* @param pNode Pointer to a PGMPHYSHANDLER node.
2408	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2409	* not certain the delta will fit in a void pointer for all possible configs.
2410	*/
2411	static DECLCALLBACK(int) pgmR3RelocatePhysHandler(PAVLROGCPHYSNODECORE pNode, void *pvUser)
2412	{
2413	PPGMPHYSHANDLER pHandler = (PPGMPHYSHANDLER)pNode;
2414	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2415	if (pHandler->pfnHandlerRC)
2416	pHandler->pfnHandlerRC += offDelta;
2417	if (pHandler->pvUserRC >= 0x10000)
2418	pHandler->pvUserRC += offDelta;
2419	return 0;
2420	}
2421
2422
2423	/**
2424	* Callback function for relocating a virtual access handler.
2425	*
2426	* @returns 0 (continue enum)
2427	* @param pNode Pointer to a PGMVIRTHANDLER node.
2428	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2429	* not certain the delta will fit in a void pointer for all possible configs.
2430	*/
2431	static DECLCALLBACK(int) pgmR3RelocateVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2432	{
2433	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2434	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2435	Assert( pHandler->enmType == PGMVIRTHANDLERTYPE_ALL
2436	\|\| pHandler->enmType == PGMVIRTHANDLERTYPE_WRITE);
2437	Assert(pHandler->pfnHandlerRC);
2438	pHandler->pfnHandlerRC += offDelta;
2439	return 0;
2440	}
2441
2442
2443	/**
2444	* Callback function for relocating a virtual access handler for the hypervisor mapping.
2445	*
2446	* @returns 0 (continue enum)
2447	* @param pNode Pointer to a PGMVIRTHANDLER node.
2448	* @param pvUser Pointer to the offDelta. This is a pointer to the delta since we're
2449	* not certain the delta will fit in a void pointer for all possible configs.
2450	*/
2451	static DECLCALLBACK(int) pgmR3RelocateHyperVirtHandler(PAVLROGCPTRNODECORE pNode, void *pvUser)
2452	{
2453	PPGMVIRTHANDLER pHandler = (PPGMVIRTHANDLER)pNode;
2454	RTGCINTPTR offDelta = *(PRTGCINTPTR)pvUser;
2455	Assert(pHandler->enmType == PGMVIRTHANDLERTYPE_HYPERVISOR);
2456	Assert(pHandler->pfnHandlerRC);
2457	pHandler->pfnHandlerRC += offDelta;
2458	return 0;
2459	}
2460
2461
2462	/**
2463	* Resets a virtual CPU when unplugged.
2464	*
2465	* @param pVM Pointer to the VM.
2466	* @param pVCpu Pointer to the VMCPU.
2467	*/
2468	VMMR3DECL(void) PGMR3ResetCpu(PVM pVM, PVMCPU pVCpu)
2469	{
2470	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2471	AssertRC(rc);
2472
2473	rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2474	AssertRC(rc);
2475
2476	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2477
2478	pgmR3PoolResetUnpluggedCpu(pVM, pVCpu);
2479
2480	/*
2481	* Re-init other members.
2482	*/
2483	pVCpu->pgm.s.fA20Enabled = true;
2484	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2485
2486	/*
2487	* Clear the FFs PGM owns.
2488	*/
2489	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2490	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2491	}
2492
2493
2494	/**
2495	* The VM is being reset.
2496	*
2497	* For the PGM component this means that any PD write monitors
2498	* needs to be removed.
2499	*
2500	* @param pVM Pointer to the VM.
2501	*/
2502	VMMR3_INT_DECL(void) PGMR3Reset(PVM pVM)
2503	{
2504	LogFlow(("PGMR3Reset:\n"));
2505	VM_ASSERT_EMT(pVM);
2506
2507	pgmLock(pVM);
2508
2509	/*
2510	* Unfix any fixed mappings and disable CR3 monitoring.
2511	*/
2512	pVM->pgm.s.fMappingsFixed = false;
2513	pVM->pgm.s.fMappingsFixedRestored = false;
2514	pVM->pgm.s.GCPtrMappingFixed = NIL_RTGCPTR;
2515	pVM->pgm.s.cbMappingFixed = 0;
2516
2517	/*
2518	* Exit the guest paging mode before the pgm pool gets reset.
2519	* Important to clean up the amd64 case.
2520	*/
2521	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2522	{
2523	PVMCPU pVCpu = &pVM->aCpus[i];
2524	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
2525	AssertReleaseRC(rc);
2526	}
2527
2528	#ifdef DEBUG
2529	DBGFR3_INFO_LOG(pVM, "mappings", NULL);
2530	DBGFR3_INFO_LOG(pVM, "handlers", "all nostat");
2531	#endif
2532
2533	/*
2534	* Switch mode back to real mode. (before resetting the pgm pool!)
2535	*/
2536	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2537	{
2538	PVMCPU pVCpu = &pVM->aCpus[i];
2539
2540	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
2541	AssertReleaseRC(rc);
2542
2543	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cGuestModeChanges);
2544	STAM_REL_COUNTER_RESET(&pVCpu->pgm.s.cA20Changes);
2545	}
2546
2547	/*
2548	* Reset the shadow page pool.
2549	*/
2550	pgmR3PoolReset(pVM);
2551
2552	/*
2553	* Re-init various other members and clear the FFs that PGM owns.
2554	*/
2555	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2556	{
2557	PVMCPU pVCpu = &pVM->aCpus[i];
2558
2559	pVCpu->pgm.s.fGst32BitPageSizeExtension = false;
2560	PGMNotifyNxeChanged(pVCpu, false);
2561
2562	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2563	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
2564
2565	if (!pVCpu->pgm.s.fA20Enabled)
2566	{
2567	pVCpu->pgm.s.fA20Enabled = true;
2568	pVCpu->pgm.s.GCPhysA20Mask = ~((RTGCPHYS)!pVCpu->pgm.s.fA20Enabled << 20);
2569	#ifdef PGM_WITH_A20
2570	pVCpu->pgm.s.fSyncFlags \|= PGM_SYNC_UPDATE_PAGE_BIT_VIRTUAL;
2571	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
2572	pgmR3RefreshShadowModeAfterA20Change(pVCpu);
2573	HMFlushTLB(pVCpu);
2574	#endif
2575	}
2576	}
2577
2578	pgmUnlock(pVM);
2579	}
2580
2581
2582	/**
2583	* Memory setup after VM construction or reset.
2584	*
2585	* @param pVM Pointer to the VM.
2586	* @param fAtReset Indicates the context, after reset if @c true or after
2587	* construction if @c false.
2588	*/
2589	VMMR3_INT_DECL(void) PGMR3MemSetup(PVM pVM, bool fAtReset)
2590	{
2591	if (fAtReset)
2592	{
2593	pgmLock(pVM);
2594
2595	int rc = pgmR3PhysRamZeroAll(pVM);
2596	AssertReleaseRC(rc);
2597
2598	rc = pgmR3PhysRomReset(pVM);
2599	AssertReleaseRC(rc);
2600
2601	pgmUnlock(pVM);
2602	}
2603	}
2604
2605
2606	#ifdef VBOX_STRICT
2607	/**
2608	* VM state change callback for clearing fNoMorePhysWrites after
2609	* a snapshot has been created.
2610	*/
2611	static DECLCALLBACK(void) pgmR3ResetNoMorePhysWritesFlag(PUVM pUVM, VMSTATE enmState, VMSTATE enmOldState, void *pvUser)
2612	{
2613	if ( enmState == VMSTATE_RUNNING
2614	\|\| enmState == VMSTATE_RESUMING)
2615	pUVM->pVM->pgm.s.fNoMorePhysWrites = false;
2616	NOREF(enmOldState); NOREF(pvUser);
2617	}
2618	#endif
2619
2620	/**
2621	* Private API to reset fNoMorePhysWrites.
2622	*/
2623	VMMR3DECL(void) PGMR3ResetNoMorePhysWritesFlag(PVM pVM)
2624	{
2625	pVM->pgm.s.fNoMorePhysWrites = false;
2626	}
2627
2628	/**
2629	* Terminates the PGM.
2630	*
2631	* @returns VBox status code.
2632	* @param pVM Pointer to VM structure.
2633	*/
2634	VMMR3DECL(int) PGMR3Term(PVM pVM)
2635	{
2636	/* Must free shared pages here. */
2637	pgmLock(pVM);
2638	pgmR3PhysRamTerm(pVM);
2639	pgmR3PhysRomTerm(pVM);
2640	pgmUnlock(pVM);
2641
2642	PGMDeregisterStringFormatTypes();
2643	return PDMR3CritSectDelete(&pVM->pgm.s.CritSectX);
2644	}
2645
2646
2647	/**
2648	* Show paging mode.
2649	*
2650	* @param pVM Pointer to the VM.
2651	* @param pHlp The info helpers.
2652	* @param pszArgs "all" (default), "guest", "shadow" or "host".
2653	*/
2654	static DECLCALLBACK(void) pgmR3InfoMode(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2655	{
2656	/* digest argument. */
2657	bool fGuest, fShadow, fHost;
2658	if (pszArgs)
2659	pszArgs = RTStrStripL(pszArgs);
2660	if (!pszArgs \|\| !*pszArgs \|\| strstr(pszArgs, "all"))
2661	fShadow = fHost = fGuest = true;
2662	else
2663	{
2664	fShadow = fHost = fGuest = false;
2665	if (strstr(pszArgs, "guest"))
2666	fGuest = true;
2667	if (strstr(pszArgs, "shadow"))
2668	fShadow = true;
2669	if (strstr(pszArgs, "host"))
2670	fHost = true;
2671	}
2672
2673	/** @todo SMP support! */
2674	/* print info. */
2675	if (fGuest)
2676	pHlp->pfnPrintf(pHlp, "Guest paging mode: %s (changed %RU64 times), A20 %s (changed %RU64 times)\n",
2677	PGMGetModeName(pVM->aCpus[0].pgm.s.enmGuestMode), pVM->aCpus[0].pgm.s.cGuestModeChanges.c,
2678	pVM->aCpus[0].pgm.s.fA20Enabled ? "enabled" : "disabled", pVM->aCpus[0].pgm.s.cA20Changes.c);
2679	if (fShadow)
2680	pHlp->pfnPrintf(pHlp, "Shadow paging mode: %s\n", PGMGetModeName(pVM->aCpus[0].pgm.s.enmShadowMode));
2681	if (fHost)
2682	{
2683	const char *psz;
2684	switch (pVM->pgm.s.enmHostMode)
2685	{
2686	case SUPPAGINGMODE_INVALID: psz = "invalid"; break;
2687	case SUPPAGINGMODE_32_BIT: psz = "32-bit"; break;
2688	case SUPPAGINGMODE_32_BIT_GLOBAL: psz = "32-bit+G"; break;
2689	case SUPPAGINGMODE_PAE: psz = "PAE"; break;
2690	case SUPPAGINGMODE_PAE_GLOBAL: psz = "PAE+G"; break;
2691	case SUPPAGINGMODE_PAE_NX: psz = "PAE+NX"; break;
2692	case SUPPAGINGMODE_PAE_GLOBAL_NX: psz = "PAE+G+NX"; break;
2693	case SUPPAGINGMODE_AMD64: psz = "AMD64"; break;
2694	case SUPPAGINGMODE_AMD64_GLOBAL: psz = "AMD64+G"; break;
2695	case SUPPAGINGMODE_AMD64_NX: psz = "AMD64+NX"; break;
2696	case SUPPAGINGMODE_AMD64_GLOBAL_NX: psz = "AMD64+G+NX"; break;
2697	default: psz = "unknown"; break;
2698	}
2699	pHlp->pfnPrintf(pHlp, "Host paging mode: %s\n", psz);
2700	}
2701	}
2702
2703
2704	/**
2705	* Dump registered MMIO ranges to the log.
2706	*
2707	* @param pVM Pointer to the VM.
2708	* @param pHlp The info helpers.
2709	* @param pszArgs Arguments, ignored.
2710	*/
2711	static DECLCALLBACK(void) pgmR3PhysInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2712	{
2713	NOREF(pszArgs);
2714	pHlp->pfnPrintf(pHlp,
2715	"RAM ranges (pVM=%p)\n"
2716	"%.s %.s\n",
2717	pVM,
2718	sizeof(RTGCPHYS) * 4 + 1, "GC Phys Range ",
2719	sizeof(RTHCPTR) * 2, "pvHC ");
2720
2721	for (PPGMRAMRANGE pCur = pVM->pgm.s.pRamRangesXR3; pCur; pCur = pCur->pNextR3)
2722	pHlp->pfnPrintf(pHlp,
2723	"%RGp-%RGp %RHv %s\n",
2724	pCur->GCPhys,
2725	pCur->GCPhysLast,
2726	pCur->pvR3,
2727	pCur->pszDesc);
2728	}
2729
2730
2731	/**
2732	* Dump the page directory to the log.
2733	*
2734	* @param pVM Pointer to the VM.
2735	* @param pHlp The info helpers.
2736	* @param pszArgs Arguments, ignored.
2737	*/
2738	static DECLCALLBACK(void) pgmR3InfoCr3(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
2739	{
2740	/** @todo SMP support!! */
2741	PVMCPU pVCpu = &pVM->aCpus[0];
2742
2743	/** @todo fix this! Convert the PGMR3DumpHierarchyHC functions to do guest stuff. */
2744	/* Big pages supported? */
2745	const bool fPSE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PSE);
2746
2747	/* Global pages supported? */
2748	const bool fPGE = !!(CPUMGetGuestCR4(pVCpu) & X86_CR4_PGE);
2749
2750	NOREF(pszArgs);
2751
2752	/*
2753	* Get page directory addresses.
2754	*/
2755	pgmLock(pVM);
2756	PX86PD pPDSrc = pgmGstGet32bitPDPtr(pVCpu);
2757	Assert(pPDSrc);
2758
2759	/*
2760	* Iterate the page directory.
2761	*/
2762	for (unsigned iPD = 0; iPD < RT_ELEMENTS(pPDSrc->a); iPD++)
2763	{
2764	X86PDE PdeSrc = pPDSrc->a[iPD];
2765	if (PdeSrc.n.u1Present)
2766	{
2767	if (PdeSrc.b.u1Size && fPSE)
2768	pHlp->pfnPrintf(pHlp,
2769	"%04X - %RGp P=%d U=%d RW=%d G=%d - BIG\n",
2770	iPD,
2771	pgmGstGet4MBPhysPage(pVM, PdeSrc),
2772	PdeSrc.b.u1Present, PdeSrc.b.u1User, PdeSrc.b.u1Write, PdeSrc.b.u1Global && fPGE);
2773	else
2774	pHlp->pfnPrintf(pHlp,
2775	"%04X - %RGp P=%d U=%d RW=%d [G=%d]\n",
2776	iPD,
2777	(RTGCPHYS)(PdeSrc.u & X86_PDE_PG_MASK),
2778	PdeSrc.n.u1Present, PdeSrc.n.u1User, PdeSrc.n.u1Write, PdeSrc.b.u1Global && fPGE);
2779	}
2780	}
2781	pgmUnlock(pVM);
2782	}
2783
2784
2785	/**
2786	* Service a VMMCALLRING3_PGM_LOCK call.
2787	*
2788	* @returns VBox status code.
2789	* @param pVM Pointer to the VM.
2790	*/
2791	VMMR3DECL(int) PGMR3LockCall(PVM pVM)
2792	{
2793	int rc = PDMR3CritSectEnterEx(&pVM->pgm.s.CritSectX, true /* fHostCall */);
2794	AssertRC(rc);
2795	return rc;
2796	}
2797
2798
2799	/**
2800	* Converts a PGMMODE value to a PGM_TYPE_* \#define.
2801	*
2802	* @returns PGM_TYPE_*.
2803	* @param pgmMode The mode value to convert.
2804	*/
2805	DECLINLINE(unsigned) pgmModeToType(PGMMODE pgmMode)
2806	{
2807	switch (pgmMode)
2808	{
2809	case PGMMODE_REAL: return PGM_TYPE_REAL;
2810	case PGMMODE_PROTECTED: return PGM_TYPE_PROT;
2811	case PGMMODE_32_BIT: return PGM_TYPE_32BIT;
2812	case PGMMODE_PAE:
2813	case PGMMODE_PAE_NX: return PGM_TYPE_PAE;
2814	case PGMMODE_AMD64:
2815	case PGMMODE_AMD64_NX: return PGM_TYPE_AMD64;
2816	case PGMMODE_NESTED: return PGM_TYPE_NESTED;
2817	case PGMMODE_EPT: return PGM_TYPE_EPT;
2818	default:
2819	AssertFatalMsgFailed(("pgmMode=%d\n", pgmMode));
2820	}
2821	}
2822
2823
2824	/**
2825	* Gets the index into the paging mode data array of a SHW+GST mode.
2826	*
2827	* @returns PGM::paPagingData index.
2828	* @param uShwType The shadow paging mode type.
2829	* @param uGstType The guest paging mode type.
2830	*/
2831	DECLINLINE(unsigned) pgmModeDataIndex(unsigned uShwType, unsigned uGstType)
2832	{
2833	Assert(uShwType >= PGM_TYPE_32BIT && uShwType <= PGM_TYPE_MAX);
2834	Assert(uGstType >= PGM_TYPE_REAL && uGstType <= PGM_TYPE_AMD64);
2835	return (uShwType - PGM_TYPE_32BIT) * (PGM_TYPE_AMD64 - PGM_TYPE_REAL + 1)
2836	+ (uGstType - PGM_TYPE_REAL);
2837	}
2838
2839
2840	/**
2841	* Gets the index into the paging mode data array of a SHW+GST mode.
2842	*
2843	* @returns PGM::paPagingData index.
2844	* @param enmShw The shadow paging mode.
2845	* @param enmGst The guest paging mode.
2846	*/
2847	DECLINLINE(unsigned) pgmModeDataIndexByMode(PGMMODE enmShw, PGMMODE enmGst)
2848	{
2849	Assert(enmShw >= PGMMODE_32_BIT && enmShw <= PGMMODE_MAX);
2850	Assert(enmGst > PGMMODE_INVALID && enmGst < PGMMODE_MAX);
2851	return pgmModeDataIndex(pgmModeToType(enmShw), pgmModeToType(enmGst));
2852	}
2853
2854
2855	/**
2856	* Calculates the max data index.
2857	* @returns The number of entries in the paging data array.
2858	*/
2859	DECLINLINE(unsigned) pgmModeDataMaxIndex(void)
2860	{
2861	return pgmModeDataIndex(PGM_TYPE_MAX, PGM_TYPE_AMD64) + 1;
2862	}
2863
2864
2865	/**
2866	* Initializes the paging mode data kept in PGM::paModeData.
2867	*
2868	* @param pVM Pointer to the VM.
2869	* @param fResolveGCAndR0 Indicate whether or not GC and Ring-0 symbols can be resolved now.
2870	* This is used early in the init process to avoid trouble with PDM
2871	* not being initialized yet.
2872	*/
2873	static int pgmR3ModeDataInit(PVM pVM, bool fResolveGCAndR0)
2874	{
2875	PPGMMODEDATA pModeData;
2876	int rc;
2877
2878	/*
2879	* Allocate the array on the first call.
2880	*/
2881	if (!pVM->pgm.s.paModeData)
2882	{
2883	pVM->pgm.s.paModeData = (PPGMMODEDATA)MMR3HeapAllocZ(pVM, MM_TAG_PGM, sizeof(PGMMODEDATA) * pgmModeDataMaxIndex());
2884	AssertReturn(pVM->pgm.s.paModeData, VERR_NO_MEMORY);
2885	}
2886
2887	/*
2888	* Initialize the array entries.
2889	*/
2890	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_REAL)];
2891	pModeData->uShwType = PGM_TYPE_32BIT;
2892	pModeData->uGstType = PGM_TYPE_REAL;
2893	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2894	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2895	rc = PGM_BTH_NAME_32BIT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2896
2897	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGMMODE_PROTECTED)];
2898	pModeData->uShwType = PGM_TYPE_32BIT;
2899	pModeData->uGstType = PGM_TYPE_PROT;
2900	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2901	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2902	rc = PGM_BTH_NAME_32BIT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2903
2904	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_32BIT, PGM_TYPE_32BIT)];
2905	pModeData->uShwType = PGM_TYPE_32BIT;
2906	pModeData->uGstType = PGM_TYPE_32BIT;
2907	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2908	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2909	rc = PGM_BTH_NAME_32BIT_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2910
2911	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_REAL)];
2912	pModeData->uShwType = PGM_TYPE_PAE;
2913	pModeData->uGstType = PGM_TYPE_REAL;
2914	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2915	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2916	rc = PGM_BTH_NAME_PAE_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2917
2918	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PROT)];
2919	pModeData->uShwType = PGM_TYPE_PAE;
2920	pModeData->uGstType = PGM_TYPE_PROT;
2921	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2922	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2923	rc = PGM_BTH_NAME_PAE_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2924
2925	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_32BIT)];
2926	pModeData->uShwType = PGM_TYPE_PAE;
2927	pModeData->uGstType = PGM_TYPE_32BIT;
2928	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2929	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2930	rc = PGM_BTH_NAME_PAE_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2931
2932	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_PAE, PGM_TYPE_PAE)];
2933	pModeData->uShwType = PGM_TYPE_PAE;
2934	pModeData->uGstType = PGM_TYPE_PAE;
2935	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2936	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2937	rc = PGM_BTH_NAME_PAE_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2938
2939	#ifdef VBOX_WITH_64_BITS_GUESTS
2940	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_AMD64, PGM_TYPE_AMD64)];
2941	pModeData->uShwType = PGM_TYPE_AMD64;
2942	pModeData->uGstType = PGM_TYPE_AMD64;
2943	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2944	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2945	rc = PGM_BTH_NAME_AMD64_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2946	#endif
2947
2948	/* The nested paging mode. */
2949	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_REAL)];
2950	pModeData->uShwType = PGM_TYPE_NESTED;
2951	pModeData->uGstType = PGM_TYPE_REAL;
2952	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2953	rc = PGM_BTH_NAME_NESTED_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2954
2955	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGMMODE_PROTECTED)];
2956	pModeData->uShwType = PGM_TYPE_NESTED;
2957	pModeData->uGstType = PGM_TYPE_PROT;
2958	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2959	rc = PGM_BTH_NAME_NESTED_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2960
2961	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_32BIT)];
2962	pModeData->uShwType = PGM_TYPE_NESTED;
2963	pModeData->uGstType = PGM_TYPE_32BIT;
2964	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2965	rc = PGM_BTH_NAME_NESTED_32BIT(InitData)(pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2966
2967	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_PAE)];
2968	pModeData->uShwType = PGM_TYPE_NESTED;
2969	pModeData->uGstType = PGM_TYPE_PAE;
2970	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2971	rc = PGM_BTH_NAME_NESTED_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2972
2973	#ifdef VBOX_WITH_64_BITS_GUESTS
2974	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2975	pModeData->uShwType = PGM_TYPE_NESTED;
2976	pModeData->uGstType = PGM_TYPE_AMD64;
2977	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2978	rc = PGM_BTH_NAME_NESTED_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2979	#endif
2980
2981	/* The shadow part of the nested callback mode depends on the host paging mode (AMD-V only). */
2982	switch (pVM->pgm.s.enmHostMode)
2983	{
2984	#if HC_ARCH_BITS == 32
2985	case SUPPAGINGMODE_32_BIT:
2986	case SUPPAGINGMODE_32_BIT_GLOBAL:
2987	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
2988	{
2989	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
2990	rc = PGM_SHW_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2991	}
2992	# ifdef VBOX_WITH_64_BITS_GUESTS
2993	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
2994	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
2995	# endif
2996	break;
2997
2998	case SUPPAGINGMODE_PAE:
2999	case SUPPAGINGMODE_PAE_NX:
3000	case SUPPAGINGMODE_PAE_GLOBAL:
3001	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3002	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3003	{
3004	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3005	rc = PGM_SHW_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3006	}
3007	# ifdef VBOX_WITH_64_BITS_GUESTS
3008	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, PGM_TYPE_AMD64)];
3009	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3010	# endif
3011	break;
3012	#endif /* HC_ARCH_BITS == 32 */
3013
3014	#if HC_ARCH_BITS == 64 \|\| defined(RT_OS_DARWIN)
3015	case SUPPAGINGMODE_AMD64:
3016	case SUPPAGINGMODE_AMD64_GLOBAL:
3017	case SUPPAGINGMODE_AMD64_NX:
3018	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3019	# ifdef VBOX_WITH_64_BITS_GUESTS
3020	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_AMD64; i++)
3021	# else
3022	for (unsigned i = PGM_TYPE_REAL; i <= PGM_TYPE_PAE; i++)
3023	# endif
3024	{
3025	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_NESTED, i)];
3026	rc = PGM_SHW_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3027	}
3028	break;
3029	#endif /* HC_ARCH_BITS == 64 \|\| RT_OS_DARWIN */
3030
3031	default:
3032	AssertFailed();
3033	break;
3034	}
3035
3036	/* Extended paging (EPT) / Intel VT-x */
3037	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_REAL)];
3038	pModeData->uShwType = PGM_TYPE_EPT;
3039	pModeData->uGstType = PGM_TYPE_REAL;
3040	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3041	rc = PGM_GST_NAME_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3042	rc = PGM_BTH_NAME_EPT_REAL(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3043
3044	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PROT)];
3045	pModeData->uShwType = PGM_TYPE_EPT;
3046	pModeData->uGstType = PGM_TYPE_PROT;
3047	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3048	rc = PGM_GST_NAME_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3049	rc = PGM_BTH_NAME_EPT_PROT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3050
3051	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_32BIT)];
3052	pModeData->uShwType = PGM_TYPE_EPT;
3053	pModeData->uGstType = PGM_TYPE_32BIT;
3054	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3055	rc = PGM_GST_NAME_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3056	rc = PGM_BTH_NAME_EPT_32BIT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3057
3058	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_PAE)];
3059	pModeData->uShwType = PGM_TYPE_EPT;
3060	pModeData->uGstType = PGM_TYPE_PAE;
3061	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3062	rc = PGM_GST_NAME_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3063	rc = PGM_BTH_NAME_EPT_PAE(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3064
3065	#ifdef VBOX_WITH_64_BITS_GUESTS
3066	pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndex(PGM_TYPE_EPT, PGM_TYPE_AMD64)];
3067	pModeData->uShwType = PGM_TYPE_EPT;
3068	pModeData->uGstType = PGM_TYPE_AMD64;
3069	rc = PGM_SHW_NAME_EPT(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3070	rc = PGM_GST_NAME_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3071	rc = PGM_BTH_NAME_EPT_AMD64(InitData)( pVM, pModeData, fResolveGCAndR0); AssertRCReturn(rc, rc);
3072	#endif
3073	return VINF_SUCCESS;
3074	}
3075
3076
3077	/**
3078	* Switch to different (or relocated in the relocate case) mode data.
3079	*
3080	* @param pVM Pointer to the VM.
3081	* @param pVCpu Pointer to the VMCPU.
3082	* @param enmShw The shadow paging mode.
3083	* @param enmGst The guest paging mode.
3084	*/
3085	static void pgmR3ModeDataSwitch(PVM pVM, PVMCPU pVCpu, PGMMODE enmShw, PGMMODE enmGst)
3086	{
3087	PPGMMODEDATA pModeData = &pVM->pgm.s.paModeData[pgmModeDataIndexByMode(enmShw, enmGst)];
3088
3089	Assert(pModeData->uGstType == pgmModeToType(enmGst));
3090	Assert(pModeData->uShwType == pgmModeToType(enmShw));
3091
3092	/* shadow */
3093	pVCpu->pgm.s.pfnR3ShwRelocate = pModeData->pfnR3ShwRelocate;
3094	pVCpu->pgm.s.pfnR3ShwExit = pModeData->pfnR3ShwExit;
3095	pVCpu->pgm.s.pfnR3ShwGetPage = pModeData->pfnR3ShwGetPage;
3096	Assert(pVCpu->pgm.s.pfnR3ShwGetPage);
3097	pVCpu->pgm.s.pfnR3ShwModifyPage = pModeData->pfnR3ShwModifyPage;
3098
3099	pVCpu->pgm.s.pfnRCShwGetPage = pModeData->pfnRCShwGetPage;
3100	pVCpu->pgm.s.pfnRCShwModifyPage = pModeData->pfnRCShwModifyPage;
3101
3102	pVCpu->pgm.s.pfnR0ShwGetPage = pModeData->pfnR0ShwGetPage;
3103	pVCpu->pgm.s.pfnR0ShwModifyPage = pModeData->pfnR0ShwModifyPage;
3104
3105
3106	/* guest */
3107	pVCpu->pgm.s.pfnR3GstRelocate = pModeData->pfnR3GstRelocate;
3108	pVCpu->pgm.s.pfnR3GstExit = pModeData->pfnR3GstExit;
3109	pVCpu->pgm.s.pfnR3GstGetPage = pModeData->pfnR3GstGetPage;
3110	Assert(pVCpu->pgm.s.pfnR3GstGetPage);
3111	pVCpu->pgm.s.pfnR3GstModifyPage = pModeData->pfnR3GstModifyPage;
3112	pVCpu->pgm.s.pfnR3GstGetPDE = pModeData->pfnR3GstGetPDE;
3113	pVCpu->pgm.s.pfnRCGstGetPage = pModeData->pfnRCGstGetPage;
3114	pVCpu->pgm.s.pfnRCGstModifyPage = pModeData->pfnRCGstModifyPage;
3115	pVCpu->pgm.s.pfnRCGstGetPDE = pModeData->pfnRCGstGetPDE;
3116	pVCpu->pgm.s.pfnR0GstGetPage = pModeData->pfnR0GstGetPage;
3117	pVCpu->pgm.s.pfnR0GstModifyPage = pModeData->pfnR0GstModifyPage;
3118	pVCpu->pgm.s.pfnR0GstGetPDE = pModeData->pfnR0GstGetPDE;
3119
3120	/* both */
3121	pVCpu->pgm.s.pfnR3BthRelocate = pModeData->pfnR3BthRelocate;
3122	pVCpu->pgm.s.pfnR3BthInvalidatePage = pModeData->pfnR3BthInvalidatePage;
3123	pVCpu->pgm.s.pfnR3BthSyncCR3 = pModeData->pfnR3BthSyncCR3;
3124	Assert(pVCpu->pgm.s.pfnR3BthSyncCR3);
3125	pVCpu->pgm.s.pfnR3BthPrefetchPage = pModeData->pfnR3BthPrefetchPage;
3126	pVCpu->pgm.s.pfnR3BthVerifyAccessSyncPage = pModeData->pfnR3BthVerifyAccessSyncPage;
3127	#ifdef VBOX_STRICT
3128	pVCpu->pgm.s.pfnR3BthAssertCR3 = pModeData->pfnR3BthAssertCR3;
3129	#endif
3130	pVCpu->pgm.s.pfnR3BthMapCR3 = pModeData->pfnR3BthMapCR3;
3131	pVCpu->pgm.s.pfnR3BthUnmapCR3 = pModeData->pfnR3BthUnmapCR3;
3132
3133	pVCpu->pgm.s.pfnRCBthTrap0eHandler = pModeData->pfnRCBthTrap0eHandler;
3134	pVCpu->pgm.s.pfnRCBthInvalidatePage = pModeData->pfnRCBthInvalidatePage;
3135	pVCpu->pgm.s.pfnRCBthSyncCR3 = pModeData->pfnRCBthSyncCR3;
3136	pVCpu->pgm.s.pfnRCBthPrefetchPage = pModeData->pfnRCBthPrefetchPage;
3137	pVCpu->pgm.s.pfnRCBthVerifyAccessSyncPage = pModeData->pfnRCBthVerifyAccessSyncPage;
3138	#ifdef VBOX_STRICT
3139	pVCpu->pgm.s.pfnRCBthAssertCR3 = pModeData->pfnRCBthAssertCR3;
3140	#endif
3141	pVCpu->pgm.s.pfnRCBthMapCR3 = pModeData->pfnRCBthMapCR3;
3142	pVCpu->pgm.s.pfnRCBthUnmapCR3 = pModeData->pfnRCBthUnmapCR3;
3143
3144	pVCpu->pgm.s.pfnR0BthTrap0eHandler = pModeData->pfnR0BthTrap0eHandler;
3145	pVCpu->pgm.s.pfnR0BthInvalidatePage = pModeData->pfnR0BthInvalidatePage;
3146	pVCpu->pgm.s.pfnR0BthSyncCR3 = pModeData->pfnR0BthSyncCR3;
3147	pVCpu->pgm.s.pfnR0BthPrefetchPage = pModeData->pfnR0BthPrefetchPage;
3148	pVCpu->pgm.s.pfnR0BthVerifyAccessSyncPage = pModeData->pfnR0BthVerifyAccessSyncPage;
3149	#ifdef VBOX_STRICT
3150	pVCpu->pgm.s.pfnR0BthAssertCR3 = pModeData->pfnR0BthAssertCR3;
3151	#endif
3152	pVCpu->pgm.s.pfnR0BthMapCR3 = pModeData->pfnR0BthMapCR3;
3153	pVCpu->pgm.s.pfnR0BthUnmapCR3 = pModeData->pfnR0BthUnmapCR3;
3154	}
3155
3156
3157	/**
3158	* Calculates the shadow paging mode.
3159	*
3160	* @returns The shadow paging mode.
3161	* @param pVM Pointer to the VM.
3162	* @param enmGuestMode The guest mode.
3163	* @param enmHostMode The host mode.
3164	* @param enmShadowMode The current shadow mode.
3165	* @param penmSwitcher Where to store the switcher to use.
3166	* VMMSWITCHER_INVALID means no change.
3167	*/
3168	static PGMMODE pgmR3CalcShadowMode(PVM pVM, PGMMODE enmGuestMode, SUPPAGINGMODE enmHostMode, PGMMODE enmShadowMode, VMMSWITCHER *penmSwitcher)
3169	{
3170	VMMSWITCHER enmSwitcher = VMMSWITCHER_INVALID;
3171	switch (enmGuestMode)
3172	{
3173	/*
3174	* When switching to real or protected mode we don't change
3175	* anything since it's likely that we'll switch back pretty soon.
3176	*
3177	* During pgmR3InitPaging we'll end up here with PGMMODE_INVALID
3178	* and is supposed to determine which shadow paging and switcher to
3179	* use during init.
3180	*/
3181	case PGMMODE_REAL:
3182	case PGMMODE_PROTECTED:
3183	if ( enmShadowMode != PGMMODE_INVALID
3184	&& !HMIsEnabled(pVM) /* always switch in hm mode! */)
3185	break; /* (no change) */
3186
3187	switch (enmHostMode)
3188	{
3189	case SUPPAGINGMODE_32_BIT:
3190	case SUPPAGINGMODE_32_BIT_GLOBAL:
3191	enmShadowMode = PGMMODE_32_BIT;
3192	enmSwitcher = VMMSWITCHER_32_TO_32;
3193	break;
3194
3195	case SUPPAGINGMODE_PAE:
3196	case SUPPAGINGMODE_PAE_NX:
3197	case SUPPAGINGMODE_PAE_GLOBAL:
3198	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3199	enmShadowMode = PGMMODE_PAE;
3200	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3201	#ifdef DEBUG_bird
3202	if (RTEnvExist("VBOX_32BIT"))
3203	{
3204	enmShadowMode = PGMMODE_32_BIT;
3205	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3206	}
3207	#endif
3208	break;
3209
3210	case SUPPAGINGMODE_AMD64:
3211	case SUPPAGINGMODE_AMD64_GLOBAL:
3212	case SUPPAGINGMODE_AMD64_NX:
3213	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3214	enmShadowMode = PGMMODE_PAE;
3215	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3216	#ifdef DEBUG_bird
3217	if (RTEnvExist("VBOX_32BIT"))
3218	{
3219	enmShadowMode = PGMMODE_32_BIT;
3220	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3221	}
3222	#endif
3223	break;
3224
3225	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3226	}
3227	break;
3228
3229	case PGMMODE_32_BIT:
3230	switch (enmHostMode)
3231	{
3232	case SUPPAGINGMODE_32_BIT:
3233	case SUPPAGINGMODE_32_BIT_GLOBAL:
3234	enmShadowMode = PGMMODE_32_BIT;
3235	enmSwitcher = VMMSWITCHER_32_TO_32;
3236	break;
3237
3238	case SUPPAGINGMODE_PAE:
3239	case SUPPAGINGMODE_PAE_NX:
3240	case SUPPAGINGMODE_PAE_GLOBAL:
3241	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3242	enmShadowMode = PGMMODE_PAE;
3243	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3244	#ifdef DEBUG_bird
3245	if (RTEnvExist("VBOX_32BIT"))
3246	{
3247	enmShadowMode = PGMMODE_32_BIT;
3248	enmSwitcher = VMMSWITCHER_PAE_TO_32;
3249	}
3250	#endif
3251	break;
3252
3253	case SUPPAGINGMODE_AMD64:
3254	case SUPPAGINGMODE_AMD64_GLOBAL:
3255	case SUPPAGINGMODE_AMD64_NX:
3256	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3257	enmShadowMode = PGMMODE_PAE;
3258	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3259	#ifdef DEBUG_bird
3260	if (RTEnvExist("VBOX_32BIT"))
3261	{
3262	enmShadowMode = PGMMODE_32_BIT;
3263	enmSwitcher = VMMSWITCHER_AMD64_TO_32;
3264	}
3265	#endif
3266	break;
3267
3268	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3269	}
3270	break;
3271
3272	case PGMMODE_PAE:
3273	case PGMMODE_PAE_NX: /** @todo This might require more switchers and guest+both modes. */
3274	switch (enmHostMode)
3275	{
3276	case SUPPAGINGMODE_32_BIT:
3277	case SUPPAGINGMODE_32_BIT_GLOBAL:
3278	enmShadowMode = PGMMODE_PAE;
3279	enmSwitcher = VMMSWITCHER_32_TO_PAE;
3280	break;
3281
3282	case SUPPAGINGMODE_PAE:
3283	case SUPPAGINGMODE_PAE_NX:
3284	case SUPPAGINGMODE_PAE_GLOBAL:
3285	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3286	enmShadowMode = PGMMODE_PAE;
3287	enmSwitcher = VMMSWITCHER_PAE_TO_PAE;
3288	break;
3289
3290	case SUPPAGINGMODE_AMD64:
3291	case SUPPAGINGMODE_AMD64_GLOBAL:
3292	case SUPPAGINGMODE_AMD64_NX:
3293	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3294	enmShadowMode = PGMMODE_PAE;
3295	enmSwitcher = VMMSWITCHER_AMD64_TO_PAE;
3296	break;
3297
3298	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3299	}
3300	break;
3301
3302	case PGMMODE_AMD64:
3303	case PGMMODE_AMD64_NX:
3304	switch (enmHostMode)
3305	{
3306	case SUPPAGINGMODE_32_BIT:
3307	case SUPPAGINGMODE_32_BIT_GLOBAL:
3308	enmShadowMode = PGMMODE_AMD64;
3309	enmSwitcher = VMMSWITCHER_32_TO_AMD64;
3310	break;
3311
3312	case SUPPAGINGMODE_PAE:
3313	case SUPPAGINGMODE_PAE_NX:
3314	case SUPPAGINGMODE_PAE_GLOBAL:
3315	case SUPPAGINGMODE_PAE_GLOBAL_NX:
3316	enmShadowMode = PGMMODE_AMD64;
3317	enmSwitcher = VMMSWITCHER_PAE_TO_AMD64;
3318	break;
3319
3320	case SUPPAGINGMODE_AMD64:
3321	case SUPPAGINGMODE_AMD64_GLOBAL:
3322	case SUPPAGINGMODE_AMD64_NX:
3323	case SUPPAGINGMODE_AMD64_GLOBAL_NX:
3324	enmShadowMode = PGMMODE_AMD64;
3325	enmSwitcher = VMMSWITCHER_AMD64_TO_AMD64;
3326	break;
3327
3328	default: AssertMsgFailed(("enmHostMode=%d\n", enmHostMode)); break;
3329	}
3330	break;
3331
3332
3333	default:
3334	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3335	*penmSwitcher = VMMSWITCHER_INVALID;
3336	return PGMMODE_INVALID;
3337	}
3338	/* Override the shadow mode is nested paging is active. */
3339	pVM->pgm.s.fNestedPaging = HMIsNestedPagingActive(pVM);
3340	if (pVM->pgm.s.fNestedPaging)
3341	enmShadowMode = HMGetShwPagingMode(pVM);
3342
3343	*penmSwitcher = enmSwitcher;
3344	return enmShadowMode;
3345	}
3346
3347
3348	/**
3349	* Performs the actual mode change.
3350	* This is called by PGMChangeMode and pgmR3InitPaging().
3351	*
3352	* @returns VBox status code. May suspend or power off the VM on error, but this
3353	* will trigger using FFs and not status codes.
3354	*
3355	* @param pVM Pointer to the VM.
3356	* @param pVCpu Pointer to the VMCPU.
3357	* @param enmGuestMode The new guest mode. This is assumed to be different from
3358	* the current mode.
3359	*/
3360	VMMR3DECL(int) PGMR3ChangeMode(PVM pVM, PVMCPU pVCpu, PGMMODE enmGuestMode)
3361	{
3362	#if HC_ARCH_BITS == 32
3363	bool fIsOldGuestPagingMode64Bits = (pVCpu->pgm.s.enmGuestMode >= PGMMODE_AMD64);
3364	#endif
3365	bool fIsNewGuestPagingMode64Bits = (enmGuestMode >= PGMMODE_AMD64);
3366
3367	Log(("PGMR3ChangeMode: Guest mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmGuestMode), PGMGetModeName(enmGuestMode)));
3368	STAM_REL_COUNTER_INC(&pVCpu->pgm.s.cGuestModeChanges);
3369
3370	/*
3371	* Calc the shadow mode and switcher.
3372	*/
3373	VMMSWITCHER enmSwitcher;
3374	PGMMODE enmShadowMode;
3375	enmShadowMode = pgmR3CalcShadowMode(pVM, enmGuestMode, pVM->pgm.s.enmHostMode, pVCpu->pgm.s.enmShadowMode, &enmSwitcher);
3376
3377	#ifdef VBOX_WITH_RAW_MODE
3378	if ( enmSwitcher != VMMSWITCHER_INVALID
3379	&& !HMIsEnabled(pVM))
3380	{
3381	/*
3382	* Select new switcher.
3383	*/
3384	int rc = VMMR3SelectSwitcher(pVM, enmSwitcher);
3385	if (RT_FAILURE(rc))
3386	{
3387	AssertReleaseMsgFailed(("VMMR3SelectSwitcher(%d) -> %Rrc\n", enmSwitcher, rc));
3388	return rc;
3389	}
3390	}
3391	#endif
3392
3393	/*
3394	* Exit old mode(s).
3395	*/
3396	#if HC_ARCH_BITS == 32
3397	/* The nested shadow paging mode for AMD-V does change when running 64 bits guests on 32 bits hosts; typically PAE <-> AMD64 */
3398	const bool fForceShwEnterExit = ( fIsOldGuestPagingMode64Bits != fIsNewGuestPagingMode64Bits
3399	&& enmShadowMode == PGMMODE_NESTED);
3400	#else
3401	const bool fForceShwEnterExit = false;
3402	#endif
3403	/* shadow */
3404	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3405	\|\| fForceShwEnterExit)
3406	{
3407	LogFlow(("PGMR3ChangeMode: Shadow mode: %s -> %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode), PGMGetModeName(enmShadowMode)));
3408	if (PGM_SHW_PFN(Exit, pVCpu))
3409	{
3410	int rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3411	if (RT_FAILURE(rc))
3412	{
3413	AssertMsgFailed(("Exit failed for shadow mode %d: %Rrc\n", pVCpu->pgm.s.enmShadowMode, rc));
3414	return rc;
3415	}
3416	}
3417
3418	}
3419	else
3420	LogFlow(("PGMR3ChangeMode: Shadow mode remains: %s\n", PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3421
3422	/* guest */
3423	if (PGM_GST_PFN(Exit, pVCpu))
3424	{
3425	int rc = PGM_GST_PFN(Exit, pVCpu)(pVCpu);
3426	if (RT_FAILURE(rc))
3427	{
3428	AssertMsgFailed(("Exit failed for guest mode %d: %Rrc\n", pVCpu->pgm.s.enmGuestMode, rc));
3429	return rc;
3430	}
3431	}
3432
3433	/*
3434	* Load new paging mode data.
3435	*/
3436	pgmR3ModeDataSwitch(pVM, pVCpu, enmShadowMode, enmGuestMode);
3437
3438	/*
3439	* Enter new shadow mode (if changed).
3440	*/
3441	if ( enmShadowMode != pVCpu->pgm.s.enmShadowMode
3442	\|\| fForceShwEnterExit)
3443	{
3444	int rc;
3445	pVCpu->pgm.s.enmShadowMode = enmShadowMode;
3446	switch (enmShadowMode)
3447	{
3448	case PGMMODE_32_BIT:
3449	rc = PGM_SHW_NAME_32BIT(Enter)(pVCpu, false);
3450	break;
3451	case PGMMODE_PAE:
3452	case PGMMODE_PAE_NX:
3453	rc = PGM_SHW_NAME_PAE(Enter)(pVCpu, false);
3454	break;
3455	case PGMMODE_AMD64:
3456	case PGMMODE_AMD64_NX:
3457	rc = PGM_SHW_NAME_AMD64(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3458	break;
3459	case PGMMODE_NESTED:
3460	rc = PGM_SHW_NAME_NESTED(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3461	break;
3462	case PGMMODE_EPT:
3463	rc = PGM_SHW_NAME_EPT(Enter)(pVCpu, fIsNewGuestPagingMode64Bits);
3464	break;
3465	case PGMMODE_REAL:
3466	case PGMMODE_PROTECTED:
3467	default:
3468	AssertReleaseMsgFailed(("enmShadowMode=%d\n", enmShadowMode));
3469	return VERR_INTERNAL_ERROR;
3470	}
3471	if (RT_FAILURE(rc))
3472	{
3473	AssertReleaseMsgFailed(("Entering enmShadowMode=%d failed: %Rrc\n", enmShadowMode, rc));
3474	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3475	return rc;
3476	}
3477	}
3478
3479	/*
3480	* Always flag the necessary updates
3481	*/
3482	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3483
3484	/*
3485	* Enter the new guest and shadow+guest modes.
3486	*/
3487	int rc = -1;
3488	int rc2 = -1;
3489	RTGCPHYS GCPhysCR3 = NIL_RTGCPHYS;
3490	pVCpu->pgm.s.enmGuestMode = enmGuestMode;
3491	switch (enmGuestMode)
3492	{
3493	case PGMMODE_REAL:
3494	rc = PGM_GST_NAME_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3495	switch (pVCpu->pgm.s.enmShadowMode)
3496	{
3497	case PGMMODE_32_BIT:
3498	rc2 = PGM_BTH_NAME_32BIT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3499	break;
3500	case PGMMODE_PAE:
3501	case PGMMODE_PAE_NX:
3502	rc2 = PGM_BTH_NAME_PAE_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3503	break;
3504	case PGMMODE_NESTED:
3505	rc2 = PGM_BTH_NAME_NESTED_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3506	break;
3507	case PGMMODE_EPT:
3508	rc2 = PGM_BTH_NAME_EPT_REAL(Enter)(pVCpu, NIL_RTGCPHYS);
3509	break;
3510	case PGMMODE_AMD64:
3511	case PGMMODE_AMD64_NX:
3512	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3513	default: AssertFailed(); break;
3514	}
3515	break;
3516
3517	case PGMMODE_PROTECTED:
3518	rc = PGM_GST_NAME_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3519	switch (pVCpu->pgm.s.enmShadowMode)
3520	{
3521	case PGMMODE_32_BIT:
3522	rc2 = PGM_BTH_NAME_32BIT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3523	break;
3524	case PGMMODE_PAE:
3525	case PGMMODE_PAE_NX:
3526	rc2 = PGM_BTH_NAME_PAE_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3527	break;
3528	case PGMMODE_NESTED:
3529	rc2 = PGM_BTH_NAME_NESTED_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3530	break;
3531	case PGMMODE_EPT:
3532	rc2 = PGM_BTH_NAME_EPT_PROT(Enter)(pVCpu, NIL_RTGCPHYS);
3533	break;
3534	case PGMMODE_AMD64:
3535	case PGMMODE_AMD64_NX:
3536	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3537	default: AssertFailed(); break;
3538	}
3539	break;
3540
3541	case PGMMODE_32_BIT:
3542	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAGE_MASK;
3543	rc = PGM_GST_NAME_32BIT(Enter)(pVCpu, GCPhysCR3);
3544	switch (pVCpu->pgm.s.enmShadowMode)
3545	{
3546	case PGMMODE_32_BIT:
3547	rc2 = PGM_BTH_NAME_32BIT_32BIT(Enter)(pVCpu, GCPhysCR3);
3548	break;
3549	case PGMMODE_PAE:
3550	case PGMMODE_PAE_NX:
3551	rc2 = PGM_BTH_NAME_PAE_32BIT(Enter)(pVCpu, GCPhysCR3);
3552	break;
3553	case PGMMODE_NESTED:
3554	rc2 = PGM_BTH_NAME_NESTED_32BIT(Enter)(pVCpu, GCPhysCR3);
3555	break;
3556	case PGMMODE_EPT:
3557	rc2 = PGM_BTH_NAME_EPT_32BIT(Enter)(pVCpu, GCPhysCR3);
3558	break;
3559	case PGMMODE_AMD64:
3560	case PGMMODE_AMD64_NX:
3561	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3562	default: AssertFailed(); break;
3563	}
3564	break;
3565
3566	case PGMMODE_PAE_NX:
3567	case PGMMODE_PAE:
3568	{
3569	uint32_t u32Dummy, u32Features;
3570
3571	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
3572	if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
3573	return VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_FATAL, "PAEmode",
3574	N_("The guest is trying to switch to the PAE mode which is currently disabled by default in VirtualBox. PAE support can be enabled using the VM settings (General/Advanced)"));
3575
3576	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & X86_CR3_PAE_PAGE_MASK;
3577	rc = PGM_GST_NAME_PAE(Enter)(pVCpu, GCPhysCR3);
3578	switch (pVCpu->pgm.s.enmShadowMode)
3579	{
3580	case PGMMODE_PAE:
3581	case PGMMODE_PAE_NX:
3582	rc2 = PGM_BTH_NAME_PAE_PAE(Enter)(pVCpu, GCPhysCR3);
3583	break;
3584	case PGMMODE_NESTED:
3585	rc2 = PGM_BTH_NAME_NESTED_PAE(Enter)(pVCpu, GCPhysCR3);
3586	break;
3587	case PGMMODE_EPT:
3588	rc2 = PGM_BTH_NAME_EPT_PAE(Enter)(pVCpu, GCPhysCR3);
3589	break;
3590	case PGMMODE_32_BIT:
3591	case PGMMODE_AMD64:
3592	case PGMMODE_AMD64_NX:
3593	AssertMsgFailed(("Should use PAE shadow mode!\n"));
3594	default: AssertFailed(); break;
3595	}
3596	break;
3597	}
3598
3599	#ifdef VBOX_WITH_64_BITS_GUESTS
3600	case PGMMODE_AMD64_NX:
3601	case PGMMODE_AMD64:
3602	GCPhysCR3 = CPUMGetGuestCR3(pVCpu) & UINT64_C(0xfffffffffffff000); /** @todo define this mask! */
3603	rc = PGM_GST_NAME_AMD64(Enter)(pVCpu, GCPhysCR3);
3604	switch (pVCpu->pgm.s.enmShadowMode)
3605	{
3606	case PGMMODE_AMD64:
3607	case PGMMODE_AMD64_NX:
3608	rc2 = PGM_BTH_NAME_AMD64_AMD64(Enter)(pVCpu, GCPhysCR3);
3609	break;
3610	case PGMMODE_NESTED:
3611	rc2 = PGM_BTH_NAME_NESTED_AMD64(Enter)(pVCpu, GCPhysCR3);
3612	break;
3613	case PGMMODE_EPT:
3614	rc2 = PGM_BTH_NAME_EPT_AMD64(Enter)(pVCpu, GCPhysCR3);
3615	break;
3616	case PGMMODE_32_BIT:
3617	case PGMMODE_PAE:
3618	case PGMMODE_PAE_NX:
3619	AssertMsgFailed(("Should use AMD64 shadow mode!\n"));
3620	default: AssertFailed(); break;
3621	}
3622	break;
3623	#endif
3624
3625	default:
3626	AssertReleaseMsgFailed(("enmGuestMode=%d\n", enmGuestMode));
3627	rc = VERR_NOT_IMPLEMENTED;
3628	break;
3629	}
3630
3631	/* status codes. */
3632	AssertRC(rc);
3633	AssertRC(rc2);
3634	if (RT_SUCCESS(rc))
3635	{
3636	rc = rc2;
3637	if (RT_SUCCESS(rc)) /* no informational status codes. */
3638	rc = VINF_SUCCESS;
3639	}
3640
3641	/* Notify HM as well. */
3642	HMR3PagingModeChanged(pVM, pVCpu, pVCpu->pgm.s.enmShadowMode, pVCpu->pgm.s.enmGuestMode);
3643	return rc;
3644	}
3645
3646
3647	/**
3648	* Called by pgmPoolFlushAllInt prior to flushing the pool.
3649	*
3650	* @returns VBox status code, fully asserted.
3651	* @param pVCpu Pointer to the VMCPU.
3652	*/
3653	int pgmR3ExitShadowModeBeforePoolFlush(PVMCPU pVCpu)
3654	{
3655	/* Unmap the old CR3 value before flushing everything. */
3656	int rc = PGM_BTH_PFN(UnmapCR3, pVCpu)(pVCpu);
3657	AssertRC(rc);
3658
3659	/* Exit the current shadow paging mode as well; nested paging and EPT use a root CR3 which will get flushed here. */
3660	rc = PGM_SHW_PFN(Exit, pVCpu)(pVCpu);
3661	AssertRC(rc);
3662	Assert(pVCpu->pgm.s.pShwPageCR3R3 == NULL);
3663	return rc;
3664	}
3665
3666
3667	/**
3668	* Called by pgmPoolFlushAllInt after flushing the pool.
3669	*
3670	* @returns VBox status code, fully asserted.
3671	* @param pVM Pointer to the VM.
3672	* @param pVCpu Pointer to the VMCPU.
3673	*/
3674	int pgmR3ReEnterShadowModeAfterPoolFlush(PVM pVM, PVMCPU pVCpu)
3675	{
3676	pVCpu->pgm.s.enmShadowMode = PGMMODE_INVALID;
3677	int rc = PGMR3ChangeMode(pVM, pVCpu, PGMGetGuestMode(pVCpu));
3678	Assert(VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
3679	AssertRCReturn(rc, rc);
3680	AssertRCSuccessReturn(rc, VERR_IPE_UNEXPECTED_INFO_STATUS);
3681
3682	Assert(pVCpu->pgm.s.pShwPageCR3R3 != NULL);
3683	AssertMsg( pVCpu->pgm.s.enmShadowMode >= PGMMODE_NESTED
3684	\|\| CPUMGetHyperCR3(pVCpu) == PGMGetHyperCR3(pVCpu),
3685	("%RHp != %RHp %s\n", (RTHCPHYS)CPUMGetHyperCR3(pVCpu), PGMGetHyperCR3(pVCpu), PGMGetModeName(pVCpu->pgm.s.enmShadowMode)));
3686	return rc;
3687	}
3688
3689
3690	/**
3691	* Called by PGMR3PhysSetA20 after changing the A20 state.
3692	*
3693	* @param pVCpu Pointer to the VMCPU.
3694	*/
3695	void pgmR3RefreshShadowModeAfterA20Change(PVMCPU pVCpu)
3696	{
3697	/** @todo Probably doing a bit too much here. */
3698	int rc = pgmR3ExitShadowModeBeforePoolFlush(pVCpu);
3699	AssertReleaseRC(rc);
3700	rc = pgmR3ReEnterShadowModeAfterPoolFlush(pVCpu->CTX_SUFF(pVM), pVCpu);
3701	AssertReleaseRC(rc);
3702	}
3703
3704
3705	#ifdef VBOX_WITH_DEBUGGER
3706
3707	/**
3708	* @callback_method_impl{FNDBGCCMD, The '.pgmerror' and '.pgmerroroff' commands.}
3709	*/
3710	static DECLCALLBACK(int) pgmR3CmdError(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3711	{
3712	/*
3713	* Validate input.
3714	*/
3715	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3716	PVM pVM = pUVM->pVM;
3717	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 0 \|\| (cArgs == 1 && paArgs[0].enmType == DBGCVAR_TYPE_STRING));
3718
3719	if (!cArgs)
3720	{
3721	/*
3722	* Print the list of error injection locations with status.
3723	*/
3724	DBGCCmdHlpPrintf(pCmdHlp, "PGM error inject locations:\n");
3725	DBGCCmdHlpPrintf(pCmdHlp, " handy - %RTbool\n", pVM->pgm.s.fErrInjHandyPages);
3726	}
3727	else
3728	{
3729	/*
3730	* String switch on where to inject the error.
3731	*/
3732	bool const fNewState = !strcmp(pCmd->pszCmd, "pgmerror");
3733	const char *pszWhere = paArgs[0].u.pszString;
3734	if (!strcmp(pszWhere, "handy"))
3735	ASMAtomicWriteBool(&pVM->pgm.s.fErrInjHandyPages, fNewState);
3736	else
3737	return DBGCCmdHlpPrintf(pCmdHlp, "error: Invalid 'where' value: %s.\n", pszWhere);
3738	DBGCCmdHlpPrintf(pCmdHlp, "done\n");
3739	}
3740	return VINF_SUCCESS;
3741	}
3742
3743
3744	/**
3745	* @callback_method_impl{FNDBGCCMD, The '.pgmsync' command.}
3746	*/
3747	static DECLCALLBACK(int) pgmR3CmdSync(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3748	{
3749	/*
3750	* Validate input.
3751	*/
3752	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3753	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3754	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3755	if (!pVCpu)
3756	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3757
3758	/*
3759	* Force page directory sync.
3760	*/
3761	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3762
3763	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Forcing page directory sync.\n");
3764	if (RT_FAILURE(rc))
3765	return rc;
3766
3767	return VINF_SUCCESS;
3768	}
3769
3770	#ifdef VBOX_STRICT
3771
3772	/**
3773	* EMT callback for pgmR3CmdAssertCR3.
3774	*
3775	* @returns VBox status code.
3776	* @param pUVM The user mode VM handle.
3777	* @param pcErrors Where to return the error count.
3778	*/
3779	static DECLCALLBACK(int) pgmR3CmdAssertCR3EmtWorker(PUVM pUVM, unsigned *pcErrors)
3780	{
3781	PVM pVM = pUVM->pVM;
3782	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
3783	PVMCPU pVCpu = VMMGetCpu(pVM);
3784
3785	*pcErrors = PGMAssertCR3(pVM, pVCpu, CPUMGetGuestCR3(pVCpu), CPUMGetGuestCR4(pVCpu));
3786
3787	return VINF_SUCCESS;
3788	}
3789
3790
3791	/**
3792	* @callback_method_impl{FNDBGCCMD, The '.pgmassertcr3' command.}
3793	*/
3794	static DECLCALLBACK(int) pgmR3CmdAssertCR3(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3795	{
3796	/*
3797	* Validate input.
3798	*/
3799	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3800	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3801
3802	int rc = DBGCCmdHlpPrintf(pCmdHlp, "Checking shadow CR3 page tables for consistency.\n");
3803	if (RT_FAILURE(rc))
3804	return rc;
3805
3806	unsigned cErrors = 0;
3807	rc = VMR3ReqCallWaitU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp), (PFNRT)pgmR3CmdAssertCR3EmtWorker, 2, pUVM, &cErrors);
3808	if (RT_FAILURE(rc))
3809	return DBGCCmdHlpFail(pCmdHlp, pCmd, "VMR3ReqCallWaitU failed: %Rrc", rc);
3810	if (cErrors > 0)
3811	return DBGCCmdHlpFail(pCmdHlp, pCmd, "PGMAssertCR3: %u error(s)", cErrors);
3812	return DBGCCmdHlpPrintf(pCmdHlp, "PGMAssertCR3: OK\n");
3813	}
3814
3815	#endif /* VBOX_STRICT */
3816
3817	/**
3818	* @callback_method_impl{FNDBGCCMD, The '.pgmsyncalways' command.}
3819	*/
3820	static DECLCALLBACK(int) pgmR3CmdSyncAlways(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3821	{
3822	/*
3823	* Validate input.
3824	*/
3825	NOREF(pCmd); NOREF(paArgs); NOREF(cArgs);
3826	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3827	PVMCPU pVCpu = VMMR3GetCpuByIdU(pUVM, DBGCCmdHlpGetCurrentCpu(pCmdHlp));
3828	if (!pVCpu)
3829	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid CPU ID");
3830
3831	/*
3832	* Force page directory sync.
3833	*/
3834	int rc;
3835	if (pVCpu->pgm.s.fSyncFlags & PGM_SYNC_ALWAYS)
3836	{
3837	ASMAtomicAndU32(&pVCpu->pgm.s.fSyncFlags, ~PGM_SYNC_ALWAYS);
3838	rc = DBGCCmdHlpPrintf(pCmdHlp, "Disabled permanent forced page directory syncing.\n");
3839	}
3840	else
3841	{
3842	ASMAtomicOrU32(&pVCpu->pgm.s.fSyncFlags, PGM_SYNC_ALWAYS);
3843	VMCPU_FF_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3);
3844	rc = DBGCCmdHlpPrintf(pCmdHlp, "Enabled permanent forced page directory syncing.\n");
3845	}
3846	return rc;
3847	}
3848
3849
3850	/**
3851	* @callback_method_impl{FNDBGCCMD, The '.pgmphystofile' command.}
3852	*/
3853	static DECLCALLBACK(int) pgmR3CmdPhysToFile(PCDBGCCMD pCmd, PDBGCCMDHLP pCmdHlp, PUVM pUVM, PCDBGCVAR paArgs, unsigned cArgs)
3854	{
3855	/*
3856	* Validate input.
3857	*/
3858	NOREF(pCmd);
3859	DBGC_CMDHLP_REQ_UVM_RET(pCmdHlp, pCmd, pUVM);
3860	PVM pVM = pUVM->pVM;
3861	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, cArgs == 1 \|\| cArgs == 2);
3862	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 0, paArgs[0].enmType != DBGCVAR_TYPE_STRING);
3863	if (cArgs == 2)
3864	{
3865	DBGC_CMDHLP_ASSERT_PARSER_RET(pCmdHlp, pCmd, 1, paArgs[2].enmType != DBGCVAR_TYPE_STRING);
3866	if (strcmp(paArgs[1].u.pszString, "nozero"))
3867	return DBGCCmdHlpFail(pCmdHlp, pCmd, "Invalid 2nd argument '%s', must be 'nozero'.\n", paArgs[1].u.pszString);
3868	}
3869	bool fIncZeroPgs = cArgs < 2;
3870
3871	/*
3872	* Open the output file and get the ram parameters.
3873	*/
3874	RTFILE hFile;
3875	int rc = RTFileOpen(&hFile, paArgs[0].u.pszString, RTFILE_O_WRITE \| RTFILE_O_CREATE_REPLACE \| RTFILE_O_DENY_WRITE);
3876	if (RT_FAILURE(rc))
3877	return DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileOpen(,'%s',) -> %Rrc.\n", paArgs[0].u.pszString, rc);
3878
3879	uint32_t cbRamHole = 0;
3880	CFGMR3QueryU32Def(CFGMR3GetRootU(pUVM), "RamHoleSize", &cbRamHole, MM_RAM_HOLE_SIZE_DEFAULT);
3881	uint64_t cbRam = 0;
3882	CFGMR3QueryU64Def(CFGMR3GetRootU(pUVM), "RamSize", &cbRam, 0);
3883	RTGCPHYS GCPhysEnd = cbRam + cbRamHole;
3884
3885	/*
3886	* Dump the physical memory, page by page.
3887	*/
3888	RTGCPHYS GCPhys = 0;
3889	char abZeroPg[PAGE_SIZE];
3890	RT_ZERO(abZeroPg);
3891
3892	pgmLock(pVM);
3893	for (PPGMRAMRANGE pRam = pVM->pgm.s.pRamRangesXR3;
3894	pRam && pRam->GCPhys < GCPhysEnd && RT_SUCCESS(rc);
3895	pRam = pRam->pNextR3)
3896	{
3897	/* fill the gap */
3898	if (pRam->GCPhys > GCPhys && fIncZeroPgs)
3899	{
3900	while (pRam->GCPhys > GCPhys && RT_SUCCESS(rc))
3901	{
3902	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3903	GCPhys += PAGE_SIZE;
3904	}
3905	}
3906
3907	PCPGMPAGE pPage = &pRam->aPages[0];
3908	while (GCPhys < pRam->GCPhysLast && RT_SUCCESS(rc))
3909	{
3910	if ( PGM_PAGE_IS_ZERO(pPage)
3911	\|\| PGM_PAGE_IS_BALLOONED(pPage))
3912	{
3913	if (fIncZeroPgs)
3914	{
3915	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3916	if (RT_FAILURE(rc))
3917	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3918	}
3919	}
3920	else
3921	{
3922	switch (PGM_PAGE_GET_TYPE(pPage))
3923	{
3924	case PGMPAGETYPE_RAM:
3925	case PGMPAGETYPE_ROM_SHADOW: /* trouble?? */
3926	case PGMPAGETYPE_ROM:
3927	case PGMPAGETYPE_MMIO2:
3928	{
3929	void const *pvPage;
3930	PGMPAGEMAPLOCK Lock;
3931	rc = PGMPhysGCPhys2CCPtrReadOnly(pVM, GCPhys, &pvPage, &Lock);
3932	if (RT_SUCCESS(rc))
3933	{
3934	rc = RTFileWrite(hFile, pvPage, PAGE_SIZE, NULL);
3935	PGMPhysReleasePageMappingLock(pVM, &Lock);
3936	if (RT_FAILURE(rc))
3937	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3938	}
3939	else
3940	DBGCCmdHlpPrintf(pCmdHlp, "error: PGMPhysGCPhys2CCPtrReadOnly -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3941	break;
3942	}
3943
3944	default:
3945	AssertFailed();
3946	case PGMPAGETYPE_MMIO2_ALIAS_MMIO:
3947	case PGMPAGETYPE_MMIO:
3948	if (fIncZeroPgs)
3949	{
3950	rc = RTFileWrite(hFile, abZeroPg, PAGE_SIZE, NULL);
3951	if (RT_FAILURE(rc))
3952	DBGCCmdHlpPrintf(pCmdHlp, "error: RTFileWrite -> %Rrc at GCPhys=%RGp.\n", rc, GCPhys);
3953	}
3954	break;
3955	}
3956	}
3957
3958
3959	/* advance */
3960	GCPhys += PAGE_SIZE;
3961	pPage++;
3962	}
3963	}
3964	pgmUnlock(pVM);
3965
3966	RTFileClose(hFile);
3967	if (RT_SUCCESS(rc))
3968	return DBGCCmdHlpPrintf(pCmdHlp, "Successfully saved physical memory to '%s'.\n", paArgs[0].u.pszString);
3969	return VINF_SUCCESS;
3970	}
3971
3972	#endif /* VBOX_WITH_DEBUGGER */
3973
3974	/**
3975	* pvUser argument of the pgmR3CheckIntegrity*Node callbacks.
3976	*/
3977	typedef struct PGMCHECKINTARGS
3978	{
3979	bool fLeftToRight; /*< true: left-to-right; false: right-to-left. /
3980	PPGMPHYSHANDLER pPrevPhys;
3981	PPGMVIRTHANDLER pPrevVirt;
3982	PPGMPHYS2VIRTHANDLER pPrevPhys2Virt;
3983	PVM pVM;
3984	} PGMCHECKINTARGS, *PPGMCHECKINTARGS;
3985
3986	/**
3987	* Validate a node in the physical handler tree.
3988	*
3989	* @returns 0 on if ok, other wise 1.
3990	* @param pNode The handler node.
3991	* @param pvUser pVM.
3992	*/
3993	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
3994	{
3995	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
3996	PPGMPHYSHANDLER pCur = (PPGMPHYSHANDLER)pNode;
3997	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
3998	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
3999	AssertReleaseMsg( !pArgs->pPrevPhys
4000	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys->Core.KeyLast > pCur->Core.Key),
4001	("pPrevPhys=%p %RGp-%RGp %s\n"
4002	" pCur=%p %RGp-%RGp %s\n",
4003	pArgs->pPrevPhys, pArgs->pPrevPhys->Core.Key, pArgs->pPrevPhys->Core.KeyLast, pArgs->pPrevPhys->pszDesc,
4004	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4005	pArgs->pPrevPhys = pCur;
4006	return 0;
4007	}
4008
4009
4010	/**
4011	* Validate a node in the virtual handler tree.
4012	*
4013	* @returns 0 on if ok, other wise 1.
4014	* @param pNode The handler node.
4015	* @param pvUser pVM.
4016	*/
4017	static DECLCALLBACK(int) pgmR3CheckIntegrityVirtHandlerNode(PAVLROGCPTRNODECORE pNode, void *pvUser)
4018	{
4019	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4020	PPGMVIRTHANDLER pCur = (PPGMVIRTHANDLER)pNode;
4021	AssertReleaseReturn(!((uintptr_t)pCur & 7), 1);
4022	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGv-%RGv %s\n", pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4023	AssertReleaseMsg( !pArgs->pPrevVirt
4024	\|\| (pArgs->fLeftToRight ? pArgs->pPrevVirt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevVirt->Core.KeyLast > pCur->Core.Key),
4025	("pPrevVirt=%p %RGv-%RGv %s\n"
4026	" pCur=%p %RGv-%RGv %s\n",
4027	pArgs->pPrevVirt, pArgs->pPrevVirt->Core.Key, pArgs->pPrevVirt->Core.KeyLast, pArgs->pPrevVirt->pszDesc,
4028	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc));
4029	for (unsigned iPage = 0; iPage < pCur->cPages; iPage++)
4030	{
4031	AssertReleaseMsg(pCur->aPhysToVirt[iPage].offVirtHandler == -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage]),
4032	("pCur=%p %RGv-%RGv %s\n"
4033	"iPage=%d offVirtHandle=%#x expected %#x\n",
4034	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->pszDesc,
4035	iPage, pCur->aPhysToVirt[iPage].offVirtHandler, -RT_OFFSETOF(PGMVIRTHANDLER, aPhysToVirt[iPage])));
4036	}
4037	pArgs->pPrevVirt = pCur;
4038	return 0;
4039	}
4040
4041
4042	/**
4043	* Validate a node in the virtual handler tree.
4044	*
4045	* @returns 0 on if ok, other wise 1.
4046	* @param pNode The handler node.
4047	* @param pvUser pVM.
4048	*/
4049	static DECLCALLBACK(int) pgmR3CheckIntegrityPhysToVirtHandlerNode(PAVLROGCPHYSNODECORE pNode, void *pvUser)
4050	{
4051	PPGMCHECKINTARGS pArgs = (PPGMCHECKINTARGS)pvUser;
4052	PPGMPHYS2VIRTHANDLER pCur = (PPGMPHYS2VIRTHANDLER)pNode;
4053	AssertReleaseMsgReturn(!((uintptr_t)pCur & 3), ("\n"), 1);
4054	AssertReleaseMsgReturn(!(pCur->offVirtHandler & 3), ("\n"), 1);
4055	AssertReleaseMsg(pCur->Core.Key <= pCur->Core.KeyLast,("pCur=%p %RGp-%RGp\n", pCur, pCur->Core.Key, pCur->Core.KeyLast));
4056	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4057	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4058	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4059	" pCur=%p %RGp-%RGp\n",
4060	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4061	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4062	AssertReleaseMsg( !pArgs->pPrevPhys2Virt
4063	\|\| (pArgs->fLeftToRight ? pArgs->pPrevPhys2Virt->Core.KeyLast < pCur->Core.Key : pArgs->pPrevPhys2Virt->Core.KeyLast > pCur->Core.Key),
4064	("pPrevPhys2Virt=%p %RGp-%RGp\n"
4065	" pCur=%p %RGp-%RGp\n",
4066	pArgs->pPrevPhys2Virt, pArgs->pPrevPhys2Virt->Core.Key, pArgs->pPrevPhys2Virt->Core.KeyLast,
4067	pCur, pCur->Core.Key, pCur->Core.KeyLast));
4068	AssertReleaseMsg((pCur->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD),
4069	("pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4070	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4071	if (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK)
4072	{
4073	PPGMPHYS2VIRTHANDLER pCur2 = pCur;
4074	for (;;)
4075	{
4076	pCur2 = (PPGMPHYS2VIRTHANDLER)((intptr_t)pCur + (pCur->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK));
4077	AssertReleaseMsg(pCur2 != pCur,
4078	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4079	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias));
4080	AssertReleaseMsg((pCur2->offNextAlias & (PGMPHYS2VIRTHANDLER_IN_TREE \| PGMPHYS2VIRTHANDLER_IS_HEAD)) == PGMPHYS2VIRTHANDLER_IN_TREE,
4081	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4082	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4083	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4084	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4085	AssertReleaseMsg((pCur2->Core.Key ^ pCur->Core.Key) < PAGE_SIZE,
4086	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4087	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4088	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4089	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4090	AssertReleaseMsg((pCur2->Core.KeyLast ^ pCur->Core.KeyLast) < PAGE_SIZE,
4091	(" pCur=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n"
4092	"pCur2=%p:{.Core.Key=%RGp, .Core.KeyLast=%RGp, .offVirtHandler=%#RX32, .offNextAlias=%#RX32}\n",
4093	pCur, pCur->Core.Key, pCur->Core.KeyLast, pCur->offVirtHandler, pCur->offNextAlias,
4094	pCur2, pCur2->Core.Key, pCur2->Core.KeyLast, pCur2->offVirtHandler, pCur2->offNextAlias));
4095	if (!(pCur2->offNextAlias & PGMPHYS2VIRTHANDLER_OFF_MASK))
4096	break;
4097	}
4098	}
4099
4100	pArgs->pPrevPhys2Virt = pCur;
4101	return 0;
4102	}
4103
4104
4105	/**
4106	* Perform an integrity check on the PGM component.
4107	*
4108	* @returns VINF_SUCCESS if everything is fine.
4109	* @returns VBox error status after asserting on integrity breach.
4110	* @param pVM Pointer to the VM.
4111	*/
4112	VMMR3DECL(int) PGMR3CheckIntegrity(PVM pVM)
4113	{
4114	AssertReleaseReturn(pVM->pgm.s.offVM, VERR_INTERNAL_ERROR);
4115
4116	/*
4117	* Check the trees.
4118	*/
4119	int cErrors = 0;
4120	const static PGMCHECKINTARGS s_LeftToRight = { true, NULL, NULL, NULL, pVM };
4121	const static PGMCHECKINTARGS s_RightToLeft = { false, NULL, NULL, NULL, pVM };
4122	PGMCHECKINTARGS Args = s_LeftToRight;
4123	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, true, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4124	Args = s_RightToLeft;
4125	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysHandlers, false, pgmR3CheckIntegrityPhysHandlerNode, &Args);
4126	Args = s_LeftToRight;
4127	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4128	Args = s_RightToLeft;
4129	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->VirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4130	Args = s_LeftToRight;
4131	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, true, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4132	Args = s_RightToLeft;
4133	cErrors += RTAvlroGCPtrDoWithAll( &pVM->pgm.s.pTreesR3->HyperVirtHandlers, false, pgmR3CheckIntegrityVirtHandlerNode, &Args);
4134	Args = s_LeftToRight;
4135	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, true, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4136	Args = s_RightToLeft;
4137	cErrors += RTAvlroGCPhysDoWithAll(&pVM->pgm.s.pTreesR3->PhysToVirtHandlers, false, pgmR3CheckIntegrityPhysToVirtHandlerNode, &Args);
4138
4139	return !cErrors ? VINF_SUCCESS : VERR_INTERNAL_ERROR;
4140	}
4141

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source: vbox/trunk/src/VBox/VMM/VMMR3/PGM.cpp@ 45744

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